/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mk_dma.h"
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#include "mk_clock.h"
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#include "mk_reset.h"
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#include "mk_trace.h"
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static struct DMA_HANDLE_T dma_handle[DMA_MAX_NUM] = {
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{
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.base = DMA,
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.irq = DMA_IRQn,
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},
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};
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int dma_open(enum DMA_CH_T ch, struct DMA_CH_CFG_T *config)
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{
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if ((ch >= DMA_CH_NUM) || (config == NULL))
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{
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return DRV_ERROR;
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}
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if ((dma_handle[DMA_ID0].base->CTRL0 & DMA_CTRL0_ENABLE_MSK) == 0)
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{
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// enable DMA clock
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clock_enable(CLOCK_DMA);
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reset_module(RESET_MODULE_DMA);
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// enable DMA
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dma_handle[DMA_ID0].base->CTRL0 |= DMA_CTRL0_ENABLE_MSK;
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NVIC_SetPriority(dma_handle[DMA_ID0].irq, IRQ_PRIORITY_HIGH);
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NVIC_ClearPendingIRQ(dma_handle[DMA_ID0].irq);
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NVIC_EnableIRQ(dma_handle[DMA_ID0].irq);
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}
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dma_handle[DMA_ID0].base->CH[ch].CFG = DMA_CH_CFG_DST_REQ_SEL(config->dst_req_sel) | DMA_CH_CFG_SRC_REQ_SEL(config->src_req_sel);
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dma_handle[DMA_ID0].base->CH[ch].CTRL = DMA_CH_CTRL_FIFO_TH(config->fifo_th) | DMA_CH_CTRL_SRC_BURST_SIZE(config->src_burst_size) |
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DMA_CH_CTRL_SRC_DATA_WIDTH(config->src_width) | DMA_CH_CTRL_DST_DATA_WIDTH(config->dst_width) |
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DMA_CH_CTRL_MODE_MSK | DMA_CH_CTRL_SRC_ADDR_CTRL(config->src_addr_ctrl) |
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DMA_CH_CTRL_DST_ADDR_CTRL(config->dst_addr_ctrl);
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return DRV_OK;
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}
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int dma_close(enum DMA_CH_T ch)
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{
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if (ch >= DMA_CH_NUM)
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{
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return DRV_ERROR;
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}
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dma_handle[DMA_ID0].base->CH[ch].CTRL &= ~DMA_CH_CTRL_EN_MSK;
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if ((dma_handle[DMA_ID0].base->STATUS1 & DMA_STATUS1_ENABLE_MSK) == 0)
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{
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// disable DMA
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dma_handle[DMA_ID0].base->CTRL0 &= ~DMA_CTRL0_ENABLE_MSK;
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// disable DMA clock
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clock_disable(CLOCK_DMA);
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NVIC_DisableIRQ(dma_handle[DMA_ID0].irq);
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NVIC_ClearPendingIRQ(dma_handle[DMA_ID0].irq);
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}
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return DRV_OK;
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}
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uint32_t get_uart1_dma_cndtr(void)
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{
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return dma_handle[DMA_ID0].base->CH[6].DATA_SIZE;
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}
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uint32_t get_uart0_dma_cndtr(void)
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{
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return dma_handle[DMA_ID0].base->CH[4].DATA_SIZE;
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}
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int dma_transfer(enum DMA_CH_T ch, void *src_addr, void *dst_addr, uint32_t size, drv_callback_t callback)
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{
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ASSERT(dst_addr, "Invalid transfer dst addr");
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if (dma_handle[DMA_ID0].base->STATUS1 & (1U << (ch + DMA_STATUS1_ENABLE_POS)))
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{
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return DRV_BUSY;
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}
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dma_handle[DMA_ID0].callback[ch] = callback;
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// enable dma channel int
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dma_handle[DMA_ID0].base->CH[ch].CFG &= ~(DMA_CH_CFG_INT_DONE_MSK | DMA_CH_CFG_INT_ERR_MSK | DMA_CH_CFG_INT_ABORT_MSK);
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// source address
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dma_handle[DMA_ID0].base->CH[ch].ADDR_SRC = (uint32_t)src_addr;
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// destination address
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dma_handle[DMA_ID0].base->CH[ch].ADDR_DST = (uint32_t)dst_addr;
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// transfer size
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dma_handle[DMA_ID0].base->CH[ch].DATA_SIZE = size;
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// enable dma channel
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dma_handle[DMA_ID0].base->CH[ch].CTRL |= DMA_CH_CTRL_EN_MSK;
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return DRV_OK;
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}
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int dma_abort(enum DMA_CH_T ch, drv_callback_t callback)
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{
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int ret = DRV_ERROR;
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uint32_t lock = int_lock();
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// Detect whether dma is in a busy state. If it is not in a busy state,
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// abort will not be executed and callback will not be called
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if (REG_IS_BIT_SET(dma_handle[DMA_ID0].base->STATUS1, (1U << (ch + DMA_STATUS1_ENABLE_POS))))
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{
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// disable dma channel done and err int
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dma_handle[DMA_ID0].base->CH[ch].CFG |= (DMA_CH_CFG_INT_DONE_MSK | DMA_CH_CFG_INT_ERR_MSK);
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// Transaction abort
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dma_handle[DMA_ID0].base->CH[ch].CTRL |= DMA_CH_CTRL_ABORT_MSK;
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// Clear Status0 Register
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dma_handle[DMA_ID0].base->INTR_CLR = ((1U << (ch + DMA_INTR_STATUS_DONE_POS)) | (1U << (ch + DMA_INTR_STATUS_ERR_POS)));
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dma_handle[DMA_ID0].abort_callback[ch] = callback;
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ret = DRV_OK;
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}
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int_unlock(lock);
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// LOG_INFO(TRACE_MODULE_DRIVER, "dma_abort %d\r\n", ch);
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return ret;
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}
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void dma_force_abort(enum DMA_CH_T ch, drv_callback_t callback)
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{
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uint32_t lock = int_lock();
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// disable dma channel done/abort/err int
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dma_handle[DMA_ID0].base->CH[ch].CFG |= (DMA_CH_CFG_INT_ABORT_MSK | DMA_CH_CFG_INT_DONE_MSK | DMA_CH_CFG_INT_ERR_MSK);
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if (REG_IS_BIT_SET(dma_handle[DMA_ID0].base->STATUS1, (1U << (ch + DMA_STATUS1_ENABLE_POS))))
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{
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// Transaction abort
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dma_handle[DMA_ID0].base->CH[ch].CTRL |= DMA_CH_CTRL_ABORT_MSK;
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}
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// Clear interrupt penging source
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dma_handle[DMA_ID0].base->INTR_CLR =
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(1U << (ch + DMA_INTR_STATUS_DONE_POS)) | (1U << (ch + DMA_INTR_STATUS_ERR_POS)) | (1U << (ch + DMA_INTR_STATUS_ABORT_POS));
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// Clear interrupt pending
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NVIC_ClearPendingIRQ(dma_handle[DMA_ID0].irq);
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if (callback)
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{
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callback(&ch, DMA_INT_TYPE_FORCE_ABORT);
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}
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int_unlock(lock);
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}
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void DMA_IRQHandler(void)
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{
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uint32_t err_code = 0;
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uint32_t int_status = dma_handle[DMA_ID0].base->INTR_STATUS;
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for (uint8_t i = 0; i < DMA_CH_NUM; i++)
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{
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// abort/error/done interrupt process
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if (int_status & (1U << (i + DMA_INTR_STATUS_ABORT_POS)))
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{
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dma_handle[DMA_ID0].base->INTR_CLR = (1U << (i + DMA_INTR_STATUS_ABORT_POS));
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err_code = DMA_INT_TYPE_ABORT;
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}
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else if (int_status & (1U << (i + DMA_INTR_STATUS_ERR_POS)))
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{
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dma_handle[DMA_ID0].base->INTR_CLR = (1U << (i + DMA_INTR_STATUS_ERR_POS));
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err_code = DMA_INT_TYPE_ERROR;
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}
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else if (int_status & (1U << (i + DMA_INTR_STATUS_DONE_POS)))
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{
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dma_handle[DMA_ID0].base->INTR_CLR = (1U << (i + DMA_INTR_STATUS_DONE_POS));
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err_code = DMA_INT_TYPE_DONE;
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}
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if (err_code == DMA_INT_TYPE_DONE || err_code == DMA_INT_TYPE_ERROR)
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{
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if (dma_handle[DMA_ID0].callback[i])
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{
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dma_handle[DMA_ID0].callback[i](&i, err_code);
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}
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err_code = 0;
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}
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else if (err_code == DMA_INT_TYPE_ABORT)
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{
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if (dma_handle[DMA_ID0].abort_callback[i])
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{
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dma_handle[DMA_ID0].abort_callback[i](&i, err_code);
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}
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err_code = 0;
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}
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}
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}
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