/*
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* Copyright (c) 2019-2023 Mauna Kea Semiconductor Holdings.
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* All rights reserved.
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*
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*/
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#ifndef USER_CONFIG_H_
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#define USER_CONFIG_H_
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/* =========================================================================================================================== */
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/* ================ Silicon configuration ================ */
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/* =========================================================================================================================== */
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/** CPU model */
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#define CPU_MK8000
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/** Enable trace output */
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#define TRACE_EN (0)
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#define BOR_EN (0)
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#define DCDC_EN (0)
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/** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */
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#define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK)
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/** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
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#define AHB_DIV (CLOCK_DIVIDED_BY_1)
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/** APBCLK = AHBCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
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#define APB_DIV (CLOCK_DIVIDED_BY_1)
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/** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */
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#if XTAL32K_EN
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#define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK)
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#define LOW_POWER_CLOCK_PPM (50)
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#else
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#define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK)
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#define LOW_POWER_CLOCK_PPM (1000)
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#endif
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#define SYS_TICK_EN (1)
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#endif /* USER_CONFIG_H_ */
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