/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mk_adc.h"
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#include "mk_clock.h"
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#include "mk_reset.h"
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#include "mk_trace.h"
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#include "mk_misc.h"
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#if ADC_DMA_MODE_EN
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static void adc_dma_callback(void *ch, uint32_t err_code);
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#endif
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static struct ADC_HANDLE_T adc_handle = {
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.base = ADC,
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.irq = ADC_IRQn,
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.dma_ch = DMA_CH1,
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.callback = NULL,
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};
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int adc_open(struct ADC_CFG_T *config)
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{
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if (config == NULL)
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{
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return DRV_ERROR;
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}
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// check if ADC is using by HW or not
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if (adc_handle.base->STATUS & ADC_STATUS_BUSY_MSK)
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{
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return DRV_BUSY;
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}
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else
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{
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// enable ADC clock
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clock_enable(CLOCK_ADC);
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reset_module(RESET_MODULE_ADC);
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}
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adc_handle.mode = config->mode;
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adc_handle.int_en = config->int_en;
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adc_handle.dma_en = config->dma_en;
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adc_handle.base->CTRL0 = ADC_CTRL0_CONV_MODE(adc_handle.mode) | ADC_CTRL0_CLK_SEL(config->clk_sel) | ADC_CTRL0_CHNL_P(config->channel_p) |
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ADC_CTRL0_CHNL_N(config->channel_n) | ADC_CTRL0_ACC_NUM(config->acc_num) | ADC_CTRL0_HIGH_PULSE_WIDTH(config->high_pulse_time) |
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ADC_CTRL0_SETTLE_TIME(config->settle_time);
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uint32_t adc_clk = config->clk_sel ? ADC_CLK_LOW_FREQ : ADC_CLK_HIGH_FREQ;
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/* If the sampling rate setting exceeds the conversion rate threshold, the maximum sampling rate is used by default */
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uint32_t rate = (adc_clk == ADC_CLK_LOW_FREQ) ? ((config->rate < ADC_CLK_L_MAX_SAMPLE_RATE) ? config->rate : ADC_CLK_L_MAX_SAMPLE_RATE)
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: (config->rate < ADC_CLK_H_MAX_SAMPLE_RATE ? config->rate : ADC_CLK_H_MAX_SAMPLE_RATE);
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/* If the sample rate is set to 0, no frequency division */
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uint16_t div = (uint16_t)((adc_clk / ((rate == 0) ? 1 : rate)) - 1);
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adc_handle.base->CTRL1 = ADC_CTRL1_CONV_RATE(div);
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// TS_VS
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uint32_t val = REG_READ(0x4000062C);
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if (config->vref_sel == ADC_SEL_VREF_INT)
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{
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val &= ~(1U << 8);
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val |= (1 << 9) | (7 << 5) | (1 << 4);
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}
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else
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{
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val |= (1 << 8);
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/* If the external reference voltage driving capability is insufficient */
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/* It is recommended to enable this configuration */
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// val |= (9 << 1) | (1 << 4);
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}
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REG_WRITE(0x4000062C, val);
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if (adc_handle.dma_en)
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{
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// enable DMA
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adc_handle.base->DMA_EN = ADC_DMA_EN_MSK;
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}
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else if (adc_handle.int_en)
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{
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NVIC_SetPriority(adc_handle.irq, IRQ_PRIORITY_NORMAL);
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NVIC_ClearPendingIRQ(adc_handle.irq);
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NVIC_EnableIRQ(adc_handle.irq);
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}
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adc_handle.state = ADC_STATE_READY;
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return DRV_OK;
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}
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int adc_close(void)
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{
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// check if ADC is using by HW or not
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if ((adc_handle.base->STATUS & ADC_STATUS_BUSY_MSK) && (adc_handle.state != ADC_STATE_BUSY))
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{
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return DRV_BUSY;
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}
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else
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{
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// disable conversion
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adc_handle.base->CTRL2 &= ~ADC_CTRL2_CONV_EN_MSK;
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}
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if (adc_handle.int_en)
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{
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NVIC_DisableIRQ(adc_handle.irq);
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NVIC_ClearPendingIRQ(adc_handle.irq);
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}
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// disable ADC clock
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clock_disable(CLOCK_ADC);
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// update status
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adc_handle.state = ADC_STATE_RESET;
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return DRV_OK;
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}
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int adc_switch_channel(enum ADC_P_N_SET P, enum ADC_P_N_SET N)
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{
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if (adc_handle.state == ADC_STATE_BUSY)
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{
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return DRV_BUSY;
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}
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adc_handle.base->CTRL0 = (adc_handle.base->CTRL0 & ~(ADC_CTRL0_CHNL_P_MSK | ADC_CTRL0_CHNL_N_MSK)) | ADC_CTRL0_CHNL_P(P) | ADC_CTRL0_CHNL_N(N);
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return DRV_OK;
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}
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#if defined(__GNUC__)
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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int adc_get(uint32_t *data, uint16_t number, drv_callback_t callback)
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{
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uint32_t lock = int_lock();
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// update state
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switch (adc_handle.state)
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{
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case ADC_STATE_READY:
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adc_handle.state = ADC_STATE_BUSY;
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break;
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case ADC_STATE_BUSY:
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int_unlock(lock);
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return DRV_BUSY;
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case ADC_STATE_RESET:
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case ADC_STATE_TIMEOUT:
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case ADC_STATE_ERROR:
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int_unlock(lock);
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return DRV_ERROR;
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}
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adc_handle.data = data;
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adc_handle.number = number;
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adc_handle.count = number;
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adc_handle.callback = callback;
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int_unlock(lock);
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if (adc_handle.dma_en)
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{
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#if ADC_DMA_MODE_EN
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struct DMA_CH_CFG_T adc_dma_cfg = {
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.fifo_th = DMA_FIFO_TH_4,
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.src_burst_size = DMA_SRC_BURST_SIZE_4,
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.src_width = DMA_WIDTH_4B,
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.dst_width = DMA_WIDTH_4B,
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.src_addr_ctrl = DMA_ADDR_FIXED,
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.dst_addr_ctrl = DMA_ADDR_INC,
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.src_req_sel = DMA_REQ_ADC,
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.dst_req_sel = DMA_REQ_MEM,
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};
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dma_open(adc_handle.dma_ch, &adc_dma_cfg);
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dma_transfer(adc_handle.dma_ch, (uint32_t *)&adc_handle.base->DATA, data, number, adc_dma_callback);
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// start conversion
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adc_handle.base->CTRL2 = ADC_CTRL2_CONV_EN_MSK;
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#endif
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}
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else if (adc_handle.int_en)
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{
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#if ADC_INT_MODE_EN
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// enable interrupt
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adc_handle.base->INTR_EN = ADC_INTR_DONE_EN_MSK | ADC_INTR_CONFLICT_EN_MSK | ADC_INTR_OVERWRITE_EN_MSK;
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// start conversion
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adc_handle.base->CTRL2 = ADC_CTRL2_CONV_EN_MSK;
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#endif
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}
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else
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{
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#if ADC_POLL_MODE_EN
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// polling
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while (adc_handle.count > 0)
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{
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if (adc_handle.mode == ADC_MODE_SINGLE)
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{
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// start conversion
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adc_handle.base->CTRL2 = ADC_CTRL2_CONV_EN_MSK;
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}
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else if ((adc_handle.mode == ADC_MODE_CONTINUE) && (adc_handle.count == adc_handle.number))
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{
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// start conversion
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adc_handle.base->CTRL2 = ADC_CTRL2_CONV_EN_MSK;
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}
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while ((adc_handle.base->STATUS & ADC_STATUS_DONE_MSK) == 0)
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{
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}
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*adc_handle.data++ = adc_handle.base->DATA;
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adc_handle.count--;
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}
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if (adc_handle.mode == ADC_MODE_CONTINUE)
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{
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adc_handle.base->CTRL2 &= ~ADC_CTRL2_CONV_EN_MSK;
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}
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// update state
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adc_handle.state = ADC_STATE_READY;
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if (adc_handle.callback)
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{
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adc_handle.callback(adc_handle.data - adc_handle.number, adc_handle.number);
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}
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#endif
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}
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return DRV_OK;
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}
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#if defined(__GNUC__)
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#pragma GCC diagnostic pop
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#endif
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#if ADC_DMA_MODE_EN
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static void adc_dma_callback(void *ch, uint32_t err_code)
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{
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uint8_t ch_num = *(uint8_t *)ch;
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if (ch_num == adc_handle.dma_ch)
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{
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if (adc_handle.mode == ADC_MODE_CONTINUE)
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{
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// stop conversion
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adc_handle.base->CTRL2 &= ~ADC_CTRL2_CONV_EN_MSK;
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}
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if (err_code == DMA_INT_TYPE_DONE)
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{
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// finished - update statue
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adc_handle.state = ADC_STATE_READY;
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}
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else
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{
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adc_handle.state = ADC_STATE_ERROR;
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}
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if (adc_handle.callback)
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{
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adc_handle.callback(adc_handle.data, adc_handle.number);
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}
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}
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else
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{
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ASSERT(0, "Unexpected dma channel\r\n");
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}
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}
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#endif
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void ADC_IRQHandler(void)
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{
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#if ADC_INT_MODE_EN
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uint32_t int_stat = adc_handle.base->INTR_STATUS;
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if (int_stat & ADC_INTR_STATUS_CONFLICT_MSK)
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{
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adc_handle.state = ADC_STATE_ERROR;
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adc_handle.base->INTR_CLR = ADC_INTR_CONFLICT_CLR_MSK;
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}
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else if (int_stat & ADC_INTR_STATUS_OVERWRITE_MSK)
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{
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adc_handle.state = ADC_STATE_ERROR;
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adc_handle.base->INTR_CLR = ADC_INTR_OVERWRITE_CLR_MSK;
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}
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else if (int_stat & ADC_INTR_STATUS_DONE_MSK)
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{
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if (adc_handle.count)
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{
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*adc_handle.data++ = adc_handle.base->DATA;
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adc_handle.count--;
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}
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if (adc_handle.count)
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{
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// continue
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if (adc_handle.mode == ADC_MODE_SINGLE)
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{
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adc_handle.base->CTRL2 = ADC_CTRL2_CONV_EN_MSK;
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}
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}
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else
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{
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// done
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if (adc_handle.mode == ADC_MODE_CONTINUE)
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{
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// stop conversion
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adc_handle.base->CTRL2 &= ~ADC_CTRL2_CONV_EN_MSK;
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adc_handle.base->INTR_CLR = ADC_INTR_DONE_CLR_MSK;
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// clear pending interrupt
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NVIC_ClearPendingIRQ(adc_handle.irq);
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}
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// finished - update status
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adc_handle.state = ADC_STATE_READY;
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if (adc_handle.callback)
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{
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adc_handle.callback(adc_handle.data - adc_handle.number, adc_handle.number);
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}
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}
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}
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else
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{
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ASSERT(0, "Unexpected ADC interrupt\r\n");
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}
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#endif
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}
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int16_t adc_code_to_mv(int16_t adc_val, int16_t vref_mv)
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{
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int16_t val = adc_val;
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if (adc_val >= 0x800)
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{
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val = adc_val - 0x1000;
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}
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float vol = val * vref_mv / (2048);
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return (int16_t)vol;
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}
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/* BATTM (battery monitor == voltage sensor) */
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void battery_monitor_open(void)
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{
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// enable ADC
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struct ADC_CFG_T vs_adc_cfg;
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vs_adc_cfg.mode = ADC_MODE_CONTINUE; /* Selected single conversion mode */
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vs_adc_cfg.clk_sel = ADC_CLK_HIGH; /* Selected 62.4M high speed clock */
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vs_adc_cfg.vref_sel = ADC_SEL_VREF_INT; /* Using internal reference voltage (1.2V)*/
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vs_adc_cfg.rate = 1000; /* ADC works at high frequency system clock, the maximum sampling rate is 2M */
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vs_adc_cfg.channel_p = 7; /* ADC positive channel --> VDD/4 */
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vs_adc_cfg.channel_n = 2; /* ADC negative channel --> GND */
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vs_adc_cfg.int_en = false;
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vs_adc_cfg.dma_en = false; /* DMA support only in continue mode */
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vs_adc_cfg.acc_num = 0;
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vs_adc_cfg.high_pulse_time = 4;
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vs_adc_cfg.settle_time = 1;
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adc_open(&vs_adc_cfg);
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// enable BATTM
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adc_handle.base->CTRL1 |= ADC_CTRL1_VS_EN_MSK;
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}
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void battery_monitor_close(void)
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{
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// disable BATTM
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adc_handle.base->CTRL1 &= ~ADC_CTRL1_VS_EN_MSK;
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adc_close();
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}
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static void adc_continue_callback(void *data, uint32_t number)
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{
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LOG_INFO(TRACE_MODULE_APP, "Chip adc callback %d degree\r\n", data);
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}
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int16_t battery_monitor_get(void)
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{
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#define NUM_SAMPLES (3)
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uint32_t sample[NUM_SAMPLES];
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adc_get(&sample[0], NUM_SAMPLES, adc_continue_callback);
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int32_t sum = 0;
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for (int i = 0; i < NUM_SAMPLES; i++)
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{
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sum += adc_code_to_mv((int16_t)sample[i], ADC_INTERNAL_VREF_MV);
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}
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return (int16_t)(4 * sum / NUM_SAMPLES);
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}
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/* TEMP (temperature sensor)*/
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void temp_sensor_open(void)
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{
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// enable ADC
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struct ADC_CFG_T ts_adc_cfg;
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ts_adc_cfg.mode = ADC_MODE_SINGLE; /* Selected single conversion mode */
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ts_adc_cfg.clk_sel = ADC_CLK_HIGH; /* Selected 62.4M high speed clock */
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ts_adc_cfg.vref_sel = ADC_SEL_VREF_INT; /* Using internal reference voltage (1.2V)*/
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ts_adc_cfg.rate = 1000; /* ADC works at high frequency system clock, the maximum sampling rate is 2M */
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ts_adc_cfg.channel_p = 3; /* ADC positive channel --> Vref */
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ts_adc_cfg.channel_n = 4; /* ADC negative channel --> Temp sensor */
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ts_adc_cfg.int_en = false;
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ts_adc_cfg.dma_en = false; /* DMA support only in continue mode */
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ts_adc_cfg.acc_num = 0;
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ts_adc_cfg.high_pulse_time = 4;
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ts_adc_cfg.settle_time = 1;
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adc_open(&ts_adc_cfg);
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// enable TEMP
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adc_handle.base->CTRL1 |= ADC_CTRL1_TS_EN_MSK;
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delay_us(100);
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}
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void temp_sensor_close(void)
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{
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// disable TEMP
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adc_handle.base->CTRL1 &= ~ADC_CTRL1_TS_EN_MSK;
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adc_close();
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}
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int8_t temp_sensor_get(int16_t *p_adc_value)
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{
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#define NUM_SAMPLES (3)
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uint32_t sample[NUM_SAMPLES];
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adc_get(&sample[0], NUM_SAMPLES, NULL);
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uint32_t reg_value = REG_READ(0x40000300);
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int16_t temp_ref_code = reg_value & 0xfff;
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int8_t temp_ref_val = (int8_t)((reg_value >> 12) & 0xFF);
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float temp_ref_val_f = temp_ref_val == 0 ? 25 : (float)(temp_ref_val >> 2) + (float)(temp_ref_val & 0x03) * 0.25f;
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int32_t sum = 0;
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for (int i = 0; i < NUM_SAMPLES; i++)
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{
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sum += sample[i];
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}
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int16_t temp_code = (int16_t)(sum / NUM_SAMPLES);
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int8_t temp_val = 0;
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if ((temp_ref_code > 600) && (temp_ref_code < 1400))
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{
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temp_val = (int8_t)(ADC_TEMP_K_FACTOR * (temp_code - temp_ref_code) + 0.5 + temp_ref_val_f);
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}
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else
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{
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// y = 0.3449x - 299.92
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temp_val = (int8_t)(ADC_TEMP_K_FACTOR * temp_code - 299.42);
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}
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if (p_adc_value)
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*p_adc_value = temp_code;
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return temp_val;
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}
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