/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mk_clock.h"
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static void clock_32K_clk_config(uint8_t choice)
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{
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// 0 - 32KHz RCO
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// 1 - 32KHz XTAL oscillator
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// 2 - External sine wave
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// 3 - External square wave
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if (choice)
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{
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if ((choice == 2) || (choice == 3))
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{
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clock_xtal32k_injection_set(choice == 3 ? CLOCK_XTAL_INJECTION_SQUARE : CLOCK_XTAL_INJECTION_SINE);
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}
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// XTAL, wait for ready
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while (!(SYSCON->CLK_STATUS & SYSCON_CLK_STATUS_XTAL_32K_REDAY_MSK))
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{
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}
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SYSCON->SYS_CMU |= SYSCON_SYS_CMU_32K_CLK_SEL_MSK;
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}
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else
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{
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SYSCON->SYS_CMU &= ~SYSCON_SYS_CMU_32K_CLK_SEL_MSK;
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}
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}
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static void clock_sys_clk_config(uint8_t choice)
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{
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// 0 - 32KHz
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// 1 - 48MHz RO
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// 2 - 62.4MHz Clock XTAL38.4M
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// 3 - 62.4MHz Clock External 38.4M sine wave
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// 4 - 62.4MHz Clock External 38.4M square wave
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uint32_t sys_cmu = SYSCON->SYS_CMU;
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if (choice == 0)
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{
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sys_cmu = (sys_cmu & ~SYSCON_SYS_CMU_SYS_CLK_SEL_MSK);
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}
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else if (choice == 1)
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{
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sys_cmu = (sys_cmu | SYSCON_SYS_CMU_SYS_CLK_SEL_MSK);
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sys_cmu = (sys_cmu & ~SYSCON_SYS_CMU_HS_CLK_SEL_MSK);
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}
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else
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{
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if ((choice == 3) || (choice == 4))
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{
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clock_xtal38m4_injection_set(choice == 4 ? CLOCK_XTAL_INJECTION_SQUARE : CLOCK_XTAL_INJECTION_SINE);
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}
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// XTAL, wait for REFPLL ready
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while (!(SYSCON->CLK_STATUS & SYSCON_CLK_STATUS_REFPLL_REDAY_MSK))
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{
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}
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sys_cmu = (sys_cmu | SYSCON_SYS_CMU_SYS_CLK_SEL_MSK | SYSCON_SYS_CMU_HS_CLK_SEL_MSK);
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}
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SYSCON->SYS_CMU = sys_cmu;
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}
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static void clock_wdt_clk_config(uint8_t choice)
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{
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if (choice)
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{
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SYSCON->CLK_DIV |= SYSCON_CLK_DIV_WDT_CLK_SEL_MSK;
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}
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else
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{
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SYSCON->CLK_DIV &= ~SYSCON_CLK_DIV_WDT_CLK_SEL_MSK;
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}
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}
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static uint32_t clock_get_sys_clk_freq(void)
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{
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uint32_t freq;
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if (SYSCON->SYS_CMU & SYSCON_SYS_CMU_SYS_CLK_SEL_MSK)
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{
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freq = (SYSCON->SYS_CMU & SYSCON_SYS_CMU_HS_CLK_SEL_MSK) ? CLOCK_XTAL38P4M : CLOCK_RO_48M;
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}
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else
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{
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freq = (SYSCON->SYS_CMU & SYSCON_SYS_CMU_32K_CLK_SEL_MSK) ? CLOCK_XTAL_32K : CLOCK_RCO_32K;
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}
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return (freq);
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}
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static uint32_t clock_get_ahb_clk_freq(void)
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{
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return (clock_get_sys_clk_freq() / (1 << GET_BIT_FIELD(SYSCON->CLK_DIV, SYSCON_CLK_DIV_HCLK_DIV_MSK, SYSCON_CLK_DIV_HCLK_DIV_POS)));
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}
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static uint32_t clock_get_apb_clk_freq(void)
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{
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return (clock_get_ahb_clk_freq() / (1 << GET_BIT_FIELD(SYSCON->CLK_DIV, SYSCON_CLK_DIV_PCLK_DIV_MSK, SYSCON_CLK_DIV_PCLK_DIV_POS)));
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}
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static uint32_t clock_get_32k_clk_freq(void)
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{
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return ((SYSCON->SYS_CMU & SYSCON_SYS_CMU_32K_CLK_SEL_MSK) ? CLOCK_XTAL_32K : CLOCK_RCO_32K);
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}
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static uint32_t clock_get_wdt_clk_freq(void)
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{
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return ((SYSCON->CLK_DIV & SYSCON_CLK_DIV_WDT_CLK_SEL_MSK) ? clock_get_apb_clk_freq() : clock_get_32k_clk_freq());
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}
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static uint32_t clock_get_flash_clk_freq(void)
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{
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return (clock_get_sys_clk_freq() / (1 << GET_BIT_FIELD(SYSCON->CLK_DIV, SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK, SYSCON_CLK_DIV_FLASH_CTRL_DIV_POS)));
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}
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void clock_enable(enum CLOCK_GATE_T clk)
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{
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SYSCON->SYS_CMU |= (1U << clk);
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}
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void clock_disable(enum CLOCK_GATE_T clk)
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{
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SYSCON->SYS_CMU &= ~(1U << clk);
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}
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void clock_attach(enum CLOCK_ATTACH_TYPE_T connection)
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{
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uint8_t mux, choice;
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mux = (uint8_t)connection;
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choice = (uint8_t)(connection >> 8);
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switch (mux)
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{
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case CLOCK_32K_CLK_SEL:
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clock_32K_clk_config(choice);
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break;
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case CLOCK_SYS_CLK_SEL:
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clock_sys_clk_config(choice);
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break;
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case CLOCK_WDT_CLK_SEL:
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clock_wdt_clk_config(choice);
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break;
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default:
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break;
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}
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}
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void clock_set_divider(enum CLOCK_DIVIDER_T div_name, uint8_t div_value)
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{
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switch (div_name)
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{
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case CLOCK_AHB_DIV:
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SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_HCLK_DIV_MSK) | SYSCON_CLK_DIV_HCLK_DIV(div_value);
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break;
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case CLOCK_APB_DIV:
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SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_PCLK_DIV_MSK) | SYSCON_CLK_DIV_PCLK_DIV(div_value);
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break;
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case CLOCK_FLASH_CTRL_DIV:
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SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK) | SYSCON_CLK_DIV_FLASH_CTRL_DIV(div_value);
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break;
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case CLOCK_UART1_FDIV:
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SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART1_FDIV_MSK) | SYSCON_CLK_DIV_UART1_FDIV(div_value);
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break;
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case CLOCK_UART0_FDIV:
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SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART0_FDIV_MSK) | SYSCON_CLK_DIV_UART0_FDIV(div_value);
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break;
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}
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}
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uint32_t clock_get_frequency(enum CLOCK_TYPE_T clk_name)
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{
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uint32_t freq = 0;
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switch (clk_name)
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{
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case CLOCK_SYS_CLK:
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freq = clock_get_sys_clk_freq();
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break;
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case CLOCK_AHB_CLK:
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freq = clock_get_ahb_clk_freq();
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break;
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case CLOCK_APB_CLK:
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freq = clock_get_apb_clk_freq();
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break;
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case CLOCK_WDT_CLK:
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freq = clock_get_wdt_clk_freq();
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break;
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case CLOCK_32K_CLK:
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freq = clock_get_32k_clk_freq();
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break;
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case CLOCK_FLASH_CLK:
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freq = clock_get_flash_clk_freq();
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break;
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}
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return freq;
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}
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void clock_xtal38m4_injection_set(enum CLOCK_XTAL_INJECTION_TYPE_T type)
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{
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uint32_t tmp_val = REG_READ(0x40000048);
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tmp_val &= ~((0x3U << 16) | 0x7fU);
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REG_WRITE(0x40000048, tmp_val | (type << 16));
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REG_WRITE(0x40000210, 0x0);
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REG_WRITE(0x40000104, 0x0FFF);
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tmp_val = REG_READ(0x40000214);
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REG_WRITE(0x40000214, tmp_val | (1 << 12) | (2 << 10) | (2 << 8));
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}
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void clock_xtal32k_injection_set(enum CLOCK_XTAL_INJECTION_TYPE_T type)
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{
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uint32_t tmp_val = REG_READ(0x4000004C);
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tmp_val &= ~(0x3U << 16);
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REG_WRITE(0x4000004C, tmp_val | (type << 16));
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}
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