/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "wsf_queue.h"
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#include "wsf_buf.h"
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#include "mk_spi.h"
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#include "mk_power.h"
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#include "mk_misc.h"
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#include "uwb_api.h"
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#include "uci_tl_comm.h"
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#include "uci_tl_task.h"
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#include "board.h"
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#if UCI_INTF_PORT == 1
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#define UCI_PORT SPI_ID0
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#define UCI_SEND_RETRY_MAX (2)
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static void uci_tl_up_req(void);
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static void uci_tl_timer_notify(void);
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static void uci_tl_setup(void);
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static bool uci_tl_up_is_active(void);
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static void rx_over_callback(void *dev, uint32_t err_code);
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static void tx_over_callback(void *dev, uint32_t err_code);
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extern int uci_validate(uint8_t *buf);
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uci_tl_dev_t g_uci_tl_dev = {
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.uci_tl_setup = &uci_tl_setup,
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.uci_tl_resume = &uci_tl_setup,
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.uci_tl_up_is_active = &uci_tl_up_is_active,
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.uci_tl_up_req = &uci_tl_up_req,
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.uci_tl_timer_notify = &uci_tl_timer_notify,
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};
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static struct SPI_CFG_T uci_spi_cfg = {
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.bit_rate = UCI_INTF_SPI_SPEED,
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.data_bits = 8,
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.slave = 1,
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.clk_polarity = 0,
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.clk_phase = 1,
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.ti_mode = 0,
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.dma_rx = true,
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.dma_tx = true,
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.int_rx = false,
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.int_tx = false,
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};
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static uint8_t recv_buff[UCI_RX_BUFF_SIZE] = {0};
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static uint8_t send_buff[UCI_TX_BUFF_SIZE] = {0};
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static struct UCI_TL_MSG_T *tl_up_msg = NULL;
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static bool tx_idle = true;
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static bool rx_idle = true;
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static uint8_t retry_cnt = 0;
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static void host2slave_gpio_callback(enum IO_PIN_T pin);
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static void uci_tl_setup(void)
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{
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/*SCK of SPI pin pull-down.*/
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io_pull_set(IO_PIN_13, IO_PULL_DOWN, IO_PULL_UP_NONE);
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/*Host to slave pin pull-up. */
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io_pull_set(HOST2SLAVE_HS_GPIO, IO_PULL_UP, IO_PULL_UP_LEVEL0);
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/*Host to salve pin wake-up enalbe by low level.*/
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power_wakeup_enable((enum POWER_WAKEUP_SOURCE_T)HOST2SLAVE_HS_GPIO, POWER_WAKEUP_LEVEL_LOW);
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gpio_pin_set_dir(SLAVE2HOST_HS_GPIO, GPIO_DIR_OUT, 1);
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gpio_pin_set_dir(HOST2SLAVE_HS_GPIO, GPIO_DIR_IN, 0);
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback);
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spi_open(UCI_PORT, &uci_spi_cfg);
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}
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static void rx_over_callback(void *dev, uint32_t err_code)
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{
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if (uci_validate(recv_buff))
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{
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uint16_t frame_len = (uint16_t)((recv_buff[2] << 8) + recv_buff[3] + UCI_HEADER_SIZE);
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if (WsfQueueCount(&g_uci_tl_dev.tl_down_queue) < UCI_MAX_DL_ITEMS)
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{
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struct UCI_TL_MSG_T *p;
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if ((p = WsfBufAlloc((uint16_t)(frame_len + sizeof(struct UCI_TL_MSG_T)))) != NULL)
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{
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memcpy(p->msg, recv_buff, frame_len);
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p->msg_length = frame_len;
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WsfQueueEnq(&g_uci_tl_dev.tl_down_queue, p);
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}
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else
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{
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LOG_INFO(TRACE_MODULE_UCI, "No buff to queue cmd\r\n");
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}
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}
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/* Set UCI receive event */
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if (g_uci_tl_dev.uci_tl_down_notify != NULL)
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{
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g_uci_tl_dev.uci_tl_down_notify();
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}
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}
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}
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static void tx_over_callback(void *dev, uint32_t err_code)
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{
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WsfTimerStop(&g_uci_tl_dev.tl_timer);
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if (tl_up_msg)
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{
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WsfBufFree(tl_up_msg);
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tl_up_msg = NULL;
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}
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retry_cnt = 0;
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g_uci_tl_dev.uci_tl_up_done_notify();
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}
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#if !(UCI_INTF_SPI_FD_HS)
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static void host2slave_gpio_callback(enum IO_PIN_T pin)
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{
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if (0 == gpio_pin_get_val(pin))
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{
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if (!tx_idle)
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{
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gpio_pin_set(SLAVE2HOST_HS_GPIO);
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spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL);
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if (tl_up_msg != NULL)
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{
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WsfQueuePush(&g_uci_tl_dev.tl_up_queue, tl_up_msg);
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tl_up_msg = NULL;
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g_uci_tl_dev.uci_tl_up_done_notify();
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}
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tx_idle = true;
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}
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memset(recv_buff, 0, UCI_RX_BUFF_SIZE);
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memset(send_buff, 0, UCI_TX_BUFF_SIZE);
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spi_open(UCI_PORT, &uci_spi_cfg);
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spi_transfer(UCI_PORT, send_buff, recv_buff, UCI_RX_BUFF_SIZE, NULL);
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WsfTimerStartMs(&g_uci_tl_dev.tl_timer, UCI_HS_TIMEOUT_MS, WSF_TIMER_ONE_SHOT);
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback);
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gpio_pin_clr(SLAVE2HOST_HS_GPIO);
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rx_idle = false;
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power_mode_request(POWER_UNIT_UCI_RX, POWER_MODE_SLEEP);
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}
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else
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{
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WsfTimerStop(&g_uci_tl_dev.tl_timer);
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spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL);
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rx_over_callback(NULL, 0);
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memset(recv_buff, 0, UCI_RX_BUFF_SIZE);
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memset(send_buff, 0, UCI_TX_BUFF_SIZE);
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback);
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gpio_pin_set(SLAVE2HOST_HS_GPIO);
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rx_idle = true;
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power_mode_clear(POWER_UNIT_UCI_RX);
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}
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}
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#endif
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#if (UCI_INTF_SPI_FD_HS)
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static void host2slave_gpio_callback(enum IO_PIN_T pin)
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{
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if (0 == gpio_pin_get_val(pin))
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{
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if (tx_idle)
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{
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memset(recv_buff, 0, UCI_RX_BUFF_SIZE);
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memset(send_buff, 0, UCI_TX_BUFF_SIZE);
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tl_up_msg = WsfQueueDeq(&g_uci_tl_dev.tl_up_queue);
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if (tl_up_msg != NULL)
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{
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memcpy(send_buff, tl_up_msg->msg, tl_up_msg->msg_length);
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tx_idle = false;
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power_mode_request(POWER_UNIT_UCI_TX, POWER_MODE_SLEEP);
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}
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spi_open(UCI_PORT, &uci_spi_cfg);
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spi_transfer(UCI_PORT, send_buff, recv_buff, UCI_RX_BUFF_SIZE, NULL);
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WsfTimerStartMs(&g_uci_tl_dev.tl_timer, UCI_HS_TIMEOUT_MS, WSF_TIMER_ONE_SHOT);
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback);
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gpio_pin_clr(SLAVE2HOST_HS_GPIO);
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}
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rx_idle = false;
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power_mode_request(POWER_UNIT_UCI_RX, POWER_MODE_SLEEP);
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}
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else
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{
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WsfTimerStop(&g_uci_tl_dev.tl_timer);
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spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL);
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rx_over_callback(NULL, 0);
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if (!tx_idle)
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{
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tx_over_callback(NULL, 0);
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tx_idle = true;
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}
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memset(recv_buff, 0, UCI_RX_BUFF_SIZE);
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memset(send_buff, 0, UCI_TX_BUFF_SIZE);
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback);
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gpio_pin_set(SLAVE2HOST_HS_GPIO);
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rx_idle = true;
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power_mode_clear(POWER_UNIT_UCI_RX);
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power_mode_clear(POWER_UNIT_UCI_TX);
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}
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}
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#endif
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static void uci_tl_up_req(void)
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{
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if (!tx_idle || !rx_idle)
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{
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return;
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}
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if (0 == gpio_pin_get_val(HOST2SLAVE_HS_GPIO))
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{
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return;
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}
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uint32_t lock = int_lock();
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/* Get messages from the up queue */
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tl_up_msg = WsfQueueDeq(&g_uci_tl_dev.tl_up_queue);
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if (tl_up_msg != NULL)
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{
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if (tl_up_msg->msg_length == 0)
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{
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WsfBufFree(tl_up_msg);
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tl_up_msg = NULL;
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g_uci_tl_dev.uci_tl_up_done_notify();
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}
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else
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{
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#if !(UCI_INTF_SPI_FD_HS)
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if (!rx_idle || (0 == gpio_pin_get_val(HOST2SLAVE_HS_GPIO)))
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{
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WsfQueuePush(&g_uci_tl_dev.tl_up_queue, tl_up_msg);
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tl_up_msg = NULL;
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g_uci_tl_dev.uci_tl_up_done_notify();
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}
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else
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#endif
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{
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tx_idle = false;
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memset(recv_buff, 0, UCI_RX_BUFF_SIZE);
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memset(send_buff, 0, UCI_TX_BUFF_SIZE);
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memcpy(send_buff, tl_up_msg->msg, tl_up_msg->msg_length);
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spi_open(UCI_PORT, &uci_spi_cfg);
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#if !(UCI_INTF_SPI_FD_HS)
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spi_transfer(UCI_PORT, send_buff, recv_buff, tl_up_msg->msg_length, tx_over_callback);
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#else
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spi_transfer(UCI_PORT, send_buff, recv_buff, UCI_RX_BUFF_SIZE, NULL);
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback);
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#endif
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gpio_pin_clr(SLAVE2HOST_HS_GPIO);
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WsfTimerStartMs(&g_uci_tl_dev.tl_timer, UCI_HS_TIMEOUT_MS, WSF_TIMER_ONE_SHOT);
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power_mode_request(POWER_UNIT_UCI_TX, POWER_MODE_SLEEP);
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}
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}
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}
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else
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{
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LOG_INFO(TRACE_MODULE_UCI, "Up queue is empty\r\n");
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g_uci_tl_dev.uci_tl_up_done_notify();
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}
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int_unlock(lock);
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}
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static bool uci_tl_up_is_active(void)
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{
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if (!spi_is_busy(UCI_PORT) && !tx_idle && rx_idle)
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{
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gpio_pin_set(SLAVE2HOST_HS_GPIO);
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tx_idle = true;
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power_mode_clear(POWER_UNIT_UCI_TX);
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}
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return !tx_idle;
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}
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static void uci_tl_timer_notify(void)
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{
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uint32_t lock = int_lock();
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gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback);
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gpio_pin_set(SLAVE2HOST_HS_GPIO);
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if (!tx_idle)
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{
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if (rx_idle)
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{
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LOG_INFO(TRACE_MODULE_UCI, "UCI Host did not ACK in time\n");
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spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL);
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}
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if (++retry_cnt > UCI_SEND_RETRY_MAX)
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{
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if (tl_up_msg)
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{
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WsfBufFree(tl_up_msg);
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tl_up_msg = NULL;
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}
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retry_cnt = 0;
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}
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else
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{
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if (tl_up_msg != NULL)
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{
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WsfQueuePush(&g_uci_tl_dev.tl_up_queue, tl_up_msg);
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tl_up_msg = NULL;
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}
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}
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g_uci_tl_dev.uci_tl_up_done_notify();
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tx_idle = true;
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power_mode_clear(POWER_UNIT_UCI_TX);
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}
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if (!rx_idle)
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{
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LOG_INFO(TRACE_MODULE_UCI, "UCI Host did not send CMD in time after CMD pin has gone low\n");
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spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL);
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rx_idle = true;
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power_mode_clear(POWER_UNIT_UCI_RX);
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}
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int_unlock(lock);
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}
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#endif
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