/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef USER_CONFIG_H_
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#define USER_CONFIG_H_
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/* =========================================================================================================================== */
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/* ================ Silicon configuration ================ */
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/* =========================================================================================================================== */
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/** CPU model */
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#define CPU_MK8000
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/* =========================================================================================================================== */
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/* ================ Board configuration ================ */
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/* =========================================================================================================================== */
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/* =========================================================================================================================== */
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/* ================ Debug/TRACE configuration ================ */
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/* =========================================================================================================================== */
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/** Enable trace output */
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#define TRACE_EN (1)
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/** Enable exception reboot */
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#ifndef TRACE_REBOOT_EN
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#define TRACE_REBOOT_EN (1)
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#endif
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/** Enable standard format output */
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#define TRACE_STD_LIB_EN (0)
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/** Configure trace level for modules: BOOT | TEST | UCI | UWB | APP | DRIVER | PHY | MAC */
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#define TRACE_LVL_CONFIG_0 (0x44444004)
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/** Configure trace level for modules: CCC | FIRA | OS */
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#define TRACE_LVL_CONFIG_1 (0x00000444)
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/* =========================================================================================================================== */
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/* ================ Power configuration ================ */
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/* =========================================================================================================================== */
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/** Enable low power mode */
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#ifndef LOW_POWER_EN
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#define LOW_POWER_EN (1)
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#endif
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/** Enable 32.768K crystal as low power mode clock source */
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#ifndef XTAL32K_EN
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#define XTAL32K_EN (1)
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#endif
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/** Enable DC-DC */
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#ifndef DCDC_EN
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#define DCDC_EN (1)
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#endif
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/** Enable BOR */
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#ifndef BOR_EN
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#define BOR_EN (0)
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#endif
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/** Enable BOD */
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#ifndef BOD_EN
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#define BOD_EN (0)
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#endif
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/** Enable UWB high performance mode, it will increase power consumption */
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#ifndef HIGH_PERFORMANCE_MODE_EN
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#define HIGH_PERFORMANCE_MODE_EN (0)
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#endif
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/* =========================================================================================================================== */
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/* ================ Clock configuration ================ */
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/* =========================================================================================================================== */
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/** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */
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#define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK)
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/** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
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#define AHB_DIV (CLOCK_DIVIDED_BY_1)
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/** APBCLK = AHBCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
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#define APB_DIV (CLOCK_DIVIDED_BY_1)
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/** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */
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#if XTAL32K_EN
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#define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK)
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#define LOW_POWER_CLOCK_PPM (50)
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#else
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#define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK)
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#define LOW_POWER_CLOCK_PPM (1000)
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#endif
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/** Enable system tick timer (period = 10ms), needed by OS */
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#define SYS_TICK_EN (1)
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/* =========================================================================================================================== */
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/* ================ UWB configuration ================ */
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/* =========================================================================================================================== */
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/** TX power level: 0 ~ 60 */
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#define TX_POWER_LEVEL (55)
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/** Antenna port number for AoA, 2~4 */
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#define RX_AOA_ANT_PORTS_NUM (4)
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/** Antenna ports combination for AoA, @ref enum RX_ANTENNA_MODE_T */
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#define RX_AOA_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2)
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/** Antenna ports combination, @ref macro definition RX_xPORTS_ANT_xxx */
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#define RX_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2)
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/** Antenna pattern: Linear or Square */
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#define SQUARE_4ANTS (0)
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#define RANGING_CORR (0)
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/** Velocity of propagation (%) */
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#define VP_VAL (100)
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/** Maximum PHY payload length */
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#define PHY_PAYLOAD_LEN_MAX (127)
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/* =========================================================================================================================== */
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/* ================ Simple Selection ================ */
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/* =========================================================================================================================== */
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//#define MK_SIMPLE_TX
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//#define MK_SIMPLE_RX
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//#define MK_DS_TWR_INIT
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//#define MK_DS_TWR_RESP
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//#define MK_DS_TWR_INIT_STS
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//#define MK_DS_TWR_RESP_STS
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//#define MK_SS_TWR_DW_INIT
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#define MK_SS_TWR_DW_RESP
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#define INPUT_5V_Pin IO_PIN_11
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#define RSSI_EN (1)
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#define WS2812_PIN IO_PIN_7
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#define _4G_USART_RX_Pin IO_PIN_17
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#define ACCLERATE_DETECT_Pin IO_PIN_2
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#define SDA_PIN IO_PIN_3
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#define SER_PIN IO_PIN_3
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#define SCL_PIN IO_PIN_4
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#define SRCLK_PIN IO_PIN_8
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#define RCLK_PIN IO_PIN_7
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#define ADC_GND_ENABLE IO_PIN_12
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#define PCA_INPUT_DETECT IO_PIN_17
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#define GET_USERKEY gpio_pin_get_val(SCL_PIN)
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//#define STS_MODE
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/* =========================================================================================================================== */
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/* ================ End ================ */
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/* =========================================================================================================================== */
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#endif /* USER_CONFIG_H_ */
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