/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mk_spi.h"
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#include "mk_trace.h"
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#include "mk_clock.h"
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#include "mk_reset.h"
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#include "string.h"
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static struct SPI_HANDLE_T spi_handle[SPI_MAX_NUM] = {
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{
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.base = SPI0,
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.irq = SPI0_IRQn,
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.dma_rx_ch = DMA_CH0,
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.dma_tx_ch = DMA_CH1,
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.tx_dummy = 0,
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},
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{
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.base = SPI1,
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.irq = SPI1_IRQn,
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.dma_rx_ch = DMA_CH4,
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.dma_tx_ch = DMA_CH5,
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.tx_dummy = 0,
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},
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};
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#if SPI_DMA_MODE_EN
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static void spi_dma_callback(void *ch, uint32_t err_code);
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static void spi_dma_abort_callback(void *ch, uint32_t err_code);
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#endif
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static uint8_t spi_get_frame_size(enum SPI_DEV_T id)
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{
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uint8_t bits, cnt;
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bits = GET_BIT_FIELD(spi_handle[id].base->CTRL0, SPI_CTRL0_DSS_MSK, SPI_CTRL0_DSS_POS);
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if (bits < 8)
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{
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cnt = 1;
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}
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else
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{
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cnt = 2;
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}
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return cnt;
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}
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static int spi_state_set(enum SPI_DEV_T id, enum SPI_STATE_T state)
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{
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int ret = DRV_OK;
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uint32_t lock = int_lock();
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// update state
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switch (spi_handle[id].state)
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{
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case SPI_STATE_READY:
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spi_handle[id].state = state;
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break;
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case SPI_STATE_BUSY_RX:
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if (state == SPI_STATE_BUSY_TX)
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{
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spi_handle[id].state = SPI_STATE_BUSY_TX_RX;
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}
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else
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{
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ret = DRV_BUSY;
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}
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break;
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case SPI_STATE_BUSY_TX:
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if (state == SPI_STATE_BUSY_RX)
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{
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spi_handle[id].state = SPI_STATE_BUSY_TX_RX;
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}
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else
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{
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ret = DRV_BUSY;
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}
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break;
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case SPI_STATE_BUSY_TX_RX:
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ret = DRV_BUSY;
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break;
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case SPI_STATE_RESET:
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case SPI_STATE_TIMEOUT:
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case SPI_STATE_ERROR:
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ret = DRV_ERROR;
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break;
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}
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int_unlock(lock);
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return ret;
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}
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static void spi_state_clear(enum SPI_DEV_T id, enum SPI_STATE_T state)
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{
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uint32_t lock = int_lock();
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// update state
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spi_handle[id].state &= ~state;
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if (spi_handle[id].state == 0)
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{
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spi_handle[id].state = SPI_STATE_READY;
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}
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int_unlock(lock);
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}
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enum SPI_STATE_T spi_state_get(enum SPI_DEV_T id)
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{
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return spi_handle[id].state;
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}
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bool spi_is_busy(enum SPI_DEV_T id)
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{
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return ((spi_handle[id].state != SPI_STATE_RESET) && (spi_handle[id].base->CTRL1 & SPI_CTRL1_SSE_MSK) &&
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(spi_handle[id].base->STATUS0 & SPI_STATUS0_BSY_MSK));
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}
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int spi_open(enum SPI_DEV_T id, struct SPI_CFG_T *config)
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{
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if ((id >= SPI_MAX_NUM) && (config == NULL))
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{
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return DRV_ERROR;
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}
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else if (id == SPI_ID0)
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{
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// enable SPI0 clock
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clock_enable(CLOCK_SPI0);
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reset_module(RESET_MODULE_SPI0);
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}
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else if (id == SPI_ID1)
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{
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// enable SPI1 clock
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clock_enable(CLOCK_SPI1);
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reset_module(RESET_MODULE_SPI1);
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}
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uint32_t val;
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uint32_t cpsdvsr, scr;
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uint32_t spi_clk = clock_get_frequency(CLOCK_AHB_CLK);
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ASSERT(config->bit_rate <= spi_clk / (SPI_CPSDVSR_MIN * (1 + SPI_SCR_MIN)), "SPI rate too large: %d", config->bit_rate);
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ASSERT(config->bit_rate >= spi_clk / (SPI_CPSDVSR_MAX * (1 + SPI_SCR_MAX)), "SPI rate too small: %d", config->bit_rate);
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ASSERT(config->data_bits <= SPI_DATA_BITS_MAX && config->data_bits >= SPI_DATA_BITS_MIN, "Invalid SPI data bits: %d", config->data_bits);
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// reset device handle
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spi_handle[id].tx_buff = NULL;
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spi_handle[id].tx_callback = NULL;
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spi_handle[id].tx_count = 0;
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spi_handle[id].tx_size = 0;
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spi_handle[id].rx_buff = NULL;
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spi_handle[id].rx_callback = NULL;
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spi_handle[id].rx_count = 0;
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spi_handle[id].rx_size = 0;
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spi_handle[id].slave = config->slave;
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spi_handle[id].dma_rx = config->dma_rx;
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spi_handle[id].dma_tx = config->dma_tx;
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spi_handle[id].int_rx = config->int_rx;
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spi_handle[id].int_tx = config->int_tx;
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// caculate divisor
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val = (spi_clk + config->bit_rate - 1) / config->bit_rate;
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cpsdvsr = (val + SPI_SCR_MAX) / (SPI_SCR_MAX + 1);
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if (cpsdvsr < SPI_CPSDVSR_MIN)
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{
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cpsdvsr = SPI_CPSDVSR_MIN;
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}
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else
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{
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if (cpsdvsr & 0x1)
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{
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cpsdvsr += 1;
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}
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if (cpsdvsr > SPI_CPSDVSR_MAX)
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{
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cpsdvsr = SPI_CPSDVSR_MAX;
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}
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}
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scr = (val + cpsdvsr - 1) / cpsdvsr;
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if (scr > SPI_SCR_MIN)
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{
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scr -= 1;
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}
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if (scr > SPI_SCR_MAX)
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{
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scr = SPI_SCR_MAX;
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}
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val = SPI_CTRL0_SCR(scr) | (config->clk_phase ? SPI_CTRL0_SPH_MSK : 0) | (config->clk_polarity ? SPI_CTRL0_SPO_MSK : 0) |
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(config->ti_mode ? SPI_CTRL0_FRF(1) : 0) | SPI_CTRL0_DSS(config->data_bits - 1);
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spi_handle[id].base->CTRL0 = val;
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// enable SPI
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val = (config->slave ? SPI_CTRL1_MS_MSK : 0) | SPI_CTRL1_SSE_MSK;
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spi_handle[id].base->CTRL1 = val;
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spi_handle[id].base->PRESCALER = SPI_PRESCALER(cpsdvsr);
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#if SPI_INT_MODE_EN
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if (spi_handle[id].int_rx || spi_handle[id].int_tx)
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{
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NVIC_SetPriority(spi_handle[id].irq, IRQ_PRIORITY_NORMAL);
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NVIC_ClearPendingIRQ(spi_handle[id].irq);
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NVIC_EnableIRQ(spi_handle[id].irq);
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}
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#endif
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spi_handle[id].state = SPI_STATE_READY;
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return DRV_OK;
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}
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int spi_close(enum SPI_DEV_T id)
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{
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if (id >= SPI_MAX_NUM)
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{
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return DRV_ERROR;
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}
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#if SPI_INT_MODE_EN
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if (spi_handle[id].int_rx || spi_handle[id].int_tx)
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{
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NVIC_DisableIRQ(spi_handle[id].irq);
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NVIC_ClearPendingIRQ(spi_handle[id].irq);
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}
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#endif
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// disable SPI
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spi_handle[id].base->CTRL1 &= ~SPI_CTRL1_SSE_MSK;
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if (id == SPI_ID0)
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{
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// disable SPI0 clock
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clock_disable(CLOCK_SPI0);
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}
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else if (id == SPI_ID1)
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{
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// disable SPI1 clock
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clock_disable(CLOCK_SPI1);
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}
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spi_handle[id].state = SPI_STATE_RESET;
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return DRV_OK;
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}
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#if defined(__GNUC__)
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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/*
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* TX
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*/
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int spi_send(enum SPI_DEV_T id, uint8_t *tx_buf, uint32_t len, drv_callback_t callback)
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{
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uint8_t frame_size = spi_get_frame_size(id);
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if ((tx_buf == 0) || (len == 0) || (len % frame_size))
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{
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LOG_INFO(TRACE_MODULE_DRIVER, "Invalid SPI send parameters\r\n");
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return DRV_ERROR;
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}
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int ret = spi_state_set(id, SPI_STATE_BUSY_TX);
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if (ret != DRV_OK)
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{
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return ret;
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}
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spi_handle[id].tx_buff = tx_buf;
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spi_handle[id].tx_count = 0;
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spi_handle[id].tx_size = len;
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spi_handle[id].tx_callback = callback;
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uint32_t frame_data = 0U;
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if (spi_handle[id].dma_tx)
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{
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#if SPI_DMA_MODE_EN
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struct DMA_CH_CFG_T spi_tx_dma_cfg = {
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.fifo_th = (frame_size == 2 ? DMA_FIFO_TH_2 : DMA_FIFO_TH_1),
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.src_burst_size = DMA_SRC_BURST_SIZE_1,
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.src_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
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.dst_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
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.src_addr_ctrl = DMA_ADDR_INC,
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.dst_addr_ctrl = DMA_ADDR_FIXED,
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.src_req_sel = DMA_REQ_MEM,
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.dst_req_sel = (id == SPI_ID1 ? DMA_REQ_SPI1_TX : DMA_REQ_SPI0_TX),
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};
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spi_handle[id].base->DMA_EN = SPI_DMA_EN_TX_MSK;
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dma_open(spi_handle[id].dma_tx_ch, &spi_tx_dma_cfg);
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dma_transfer(spi_handle[id].dma_tx_ch, tx_buf, (uint8_t *)&spi_handle[id].base->DATA, len / frame_size, spi_dma_callback);
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#endif
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}
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else if (spi_handle[id].int_tx)
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{
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#if SPI_INT_MODE_EN
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// write data to FIFO
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while ((spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK) && (spi_handle[id].tx_count < spi_handle[id].tx_size))
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{
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frame_data = 0;
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memcpy(&frame_data, &spi_handle[id].tx_buff[spi_handle[id].tx_count], frame_size);
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spi_handle[id].base->DATA = frame_data;
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spi_handle[id].tx_count += frame_size;
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}
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// enable interrupts
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spi_handle[id].base->INTR_EN |= SPI_INTR_EN_TX_MSK;
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#endif
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}
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else
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{
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#if SPI_POLL_MODE_EN
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// polling
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while (spi_handle[id].tx_count < spi_handle[id].tx_size)
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{
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if ((spi_handle[id].base->CTRL1 & SPI_CTRL1_SSE_MSK) == 0)
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{
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ret = DRV_ERROR;
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break;
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}
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if (spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK)
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{
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frame_data = 0;
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memcpy(&frame_data, &spi_handle[id].tx_buff[spi_handle[id].tx_count], frame_size);
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spi_handle[id].base->DATA = frame_data;
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spi_handle[id].tx_count += frame_size;
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}
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}
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while (spi_is_busy(id))
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{
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}
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spi_state_clear(id, SPI_STATE_BUSY_TX);
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if (spi_handle[id].tx_callback)
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{
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spi_handle[id].tx_callback(&id, 0);
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}
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#endif
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}
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return ret;
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}
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/*
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* RX
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* Master RX DMA mode need to enable TX DMA to send dummy data
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*/
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int spi_receive(enum SPI_DEV_T id, uint8_t *rx_buf, uint32_t len, drv_callback_t callback)
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{
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uint8_t frame_size = spi_get_frame_size(id);
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if ((rx_buf == 0) || (len == 0) || (len % frame_size))
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{
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LOG_INFO(TRACE_MODULE_DRIVER, "Invalid SPI recv parameters\r\n");
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return DRV_ERROR;
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}
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int ret = spi_state_set(id, SPI_STATE_BUSY_RX);
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if (ret != DRV_OK)
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{
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return ret;
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}
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spi_handle[id].rx_buff = rx_buf;
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spi_handle[id].rx_count = 0;
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spi_handle[id].rx_size = len;
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spi_handle[id].rx_callback = callback;
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uint32_t frame_data = 0U;
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uint32_t dummy_cnt = 0;
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// clear FIFO
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while (spi_handle[id].base->STATUS0 & SPI_STATUS0_RNE_MSK)
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{
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spi_handle[id].base->DATA;
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}
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spi_handle[id].base->INTR_CLR = ~0UL;
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if (spi_handle[id].dma_rx)
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{
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#if SPI_DMA_MODE_EN
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struct DMA_CH_CFG_T spi_rx_dma_cfg = {
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.fifo_th = (frame_size == 2 ? DMA_FIFO_TH_2 : DMA_FIFO_TH_1),
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.src_burst_size = DMA_SRC_BURST_SIZE_1,
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.src_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
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.dst_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
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.src_addr_ctrl = DMA_ADDR_FIXED,
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.dst_addr_ctrl = DMA_ADDR_INC,
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.src_req_sel = (id == SPI_ID1 ? DMA_REQ_SPI1_RX : DMA_REQ_SPI0_RX),
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.dst_req_sel = DMA_REQ_MEM,
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};
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spi_handle[id].base->DMA_EN = (spi_handle[id].slave == 0) ? (SPI_DMA_EN_RX_MSK | SPI_DMA_EN_TX_MSK) : SPI_DMA_EN_RX_MSK;
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dma_open(spi_handle[id].dma_rx_ch, &spi_rx_dma_cfg);
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dma_transfer(spi_handle[id].dma_rx_ch, (uint8_t *)&spi_handle[id].base->DATA, rx_buf, len / frame_size, spi_dma_callback);
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if (spi_handle[id].slave == false)
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{
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struct DMA_CH_CFG_T spi_tx_dma_cfg = {
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.fifo_th = (frame_size == 2 ? DMA_FIFO_TH_2 : DMA_FIFO_TH_1),
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.src_burst_size = DMA_SRC_BURST_SIZE_1,
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.src_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
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.dst_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
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.src_addr_ctrl = DMA_ADDR_FIXED,
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.dst_addr_ctrl = DMA_ADDR_FIXED,
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.src_req_sel = DMA_REQ_MEM,
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.dst_req_sel = (id == SPI_ID1 ? DMA_REQ_SPI1_TX : DMA_REQ_SPI0_TX),
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};
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dma_open(spi_handle[id].dma_tx_ch, &spi_tx_dma_cfg);
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dma_transfer(spi_handle[id].dma_tx_ch, &spi_handle[id].tx_dummy, (uint8_t *)&spi_handle[id].base->DATA, len / frame_size, NULL);
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}
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#endif
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}
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else if (spi_handle[id].int_rx)
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{
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#if SPI_INT_MODE_EN
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// enable interrupts
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spi_handle[id].base->INTR_EN |= SPI_INTR_EN_RX_MSK | SPI_INTR_EN_RT_MSK | SPI_INTR_EN_ROR_MSK;
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if ((spi_handle[id].slave == 0) && (((spi_handle[id].state & SPI_STATE_BUSY_TX) == 0) && (spi_handle[id].base->STATUS0 & SPI_STATUS0_TFE_MSK)))
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{
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// send dummy data as many as possible
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dummy_cnt = spi_handle[id].rx_size - spi_handle[id].rx_count;
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while ((dummy_cnt >= frame_size) && (spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK))
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{
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spi_handle[id].base->DATA = spi_handle[id].tx_dummy;
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dummy_cnt -= frame_size;
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}
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}
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#endif
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}
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else
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{
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#if SPI_POLL_MODE_EN
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// polling
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while (spi_handle[id].rx_count < spi_handle[id].rx_size)
|
{
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if ((spi_handle[id].base->CTRL1 & SPI_CTRL1_SSE_MSK) == 0)
|
{
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ret = DRV_ERROR;
|
break;
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}
|
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if (spi_handle[id].base->STATUS0 & SPI_STATUS0_RNE_MSK)
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{
|
frame_data = spi_handle[id].base->DATA;
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memcpy(&spi_handle[id].rx_buff[spi_handle[id].rx_count], &frame_data, frame_size);
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spi_handle[id].rx_count += frame_size;
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}
|
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if ((spi_handle[id].slave == 0) && (((spi_handle[id].state & SPI_STATE_BUSY_TX) == 0) && (spi_handle[id].base->STATUS0 & SPI_STATUS0_TFE_MSK)))
|
{
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if (dummy_cnt < spi_handle[id].rx_size)
|
{
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// send dummy data
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spi_handle[id].base->DATA = spi_handle[id].tx_dummy;
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dummy_cnt++;
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}
|
}
|
}
|
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// update state
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spi_state_clear(id, SPI_STATE_BUSY_RX);
|
|
if (spi_handle[id].rx_callback)
|
{
|
spi_handle[id].rx_callback(&id, 0);
|
}
|
#endif
|
}
|
|
return ret;
|
}
|
|
/*
|
* Full duplex
|
* limitation: int_tx == int_rx, dma_tx == dma_rx
|
*/
|
int spi_transfer(enum SPI_DEV_T id, uint8_t *tx_buf, uint8_t *rx_buf, uint32_t len, drv_callback_t callback)
|
{
|
uint8_t frame_size = spi_get_frame_size(id);
|
if ((rx_buf == 0) || (len == 0) || (len % frame_size))
|
{
|
LOG_INFO(TRACE_MODULE_DRIVER, "Invalid SPI transfer parameters\r\n");
|
return DRV_ERROR;
|
}
|
if ((spi_handle[id].dma_rx != spi_handle[id].dma_tx) || (spi_handle[id].int_rx != spi_handle[id].int_tx))
|
{
|
LOG_INFO(TRACE_MODULE_DRIVER, "Invalid SPI configuration\r\n");
|
return DRV_ERROR;
|
}
|
|
int ret = spi_state_set(id, SPI_STATE_BUSY_TX_RX);
|
if (ret != DRV_OK)
|
{
|
return ret;
|
}
|
|
spi_handle[id].tx_buff = tx_buf;
|
spi_handle[id].tx_count = 0;
|
spi_handle[id].tx_size = len;
|
spi_handle[id].tx_callback = NULL;
|
|
spi_handle[id].rx_buff = rx_buf;
|
spi_handle[id].rx_count = 0;
|
spi_handle[id].rx_size = len;
|
spi_handle[id].rx_callback = callback;
|
|
// clear FIFO
|
while (spi_handle[id].base->STATUS0 & SPI_STATUS0_RNE_MSK)
|
{
|
spi_handle[id].base->DATA;
|
}
|
spi_handle[id].base->INTR_CLR = ~0UL;
|
|
uint32_t frame_data = 0U;
|
|
if (spi_handle[id].dma_tx)
|
{
|
#if SPI_DMA_MODE_EN
|
struct DMA_CH_CFG_T spi_rx_dma_cfg = {
|
.fifo_th = (frame_size == 2 ? DMA_FIFO_TH_2 : DMA_FIFO_TH_1),
|
.src_burst_size = DMA_SRC_BURST_SIZE_1,
|
.src_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
|
.dst_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
|
.src_addr_ctrl = DMA_ADDR_FIXED,
|
.dst_addr_ctrl = DMA_ADDR_INC,
|
.src_req_sel = (id == SPI_ID1 ? DMA_REQ_SPI1_RX : DMA_REQ_SPI0_RX),
|
.dst_req_sel = DMA_REQ_MEM,
|
};
|
|
spi_handle[id].base->DMA_EN = SPI_DMA_EN_TX_MSK | SPI_DMA_EN_RX_MSK;
|
dma_open(spi_handle[id].dma_rx_ch, &spi_rx_dma_cfg);
|
dma_transfer(spi_handle[id].dma_rx_ch, (uint8_t *)&spi_handle[id].base->DATA, rx_buf, len / frame_size, spi_dma_callback);
|
|
struct DMA_CH_CFG_T spi_tx_dma_cfg = {
|
.fifo_th = (frame_size == 2 ? DMA_FIFO_TH_2 : DMA_FIFO_TH_1),
|
.src_burst_size = DMA_SRC_BURST_SIZE_1,
|
.src_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
|
.dst_width = (frame_size == 2 ? DMA_WIDTH_2B : DMA_WIDTH_1B),
|
.src_addr_ctrl = DMA_ADDR_INC,
|
.dst_addr_ctrl = DMA_ADDR_FIXED,
|
.src_req_sel = DMA_REQ_MEM,
|
.dst_req_sel = (id == SPI_ID1 ? DMA_REQ_SPI1_TX : DMA_REQ_SPI0_TX),
|
};
|
|
dma_open(spi_handle[id].dma_tx_ch, &spi_tx_dma_cfg);
|
dma_transfer(spi_handle[id].dma_tx_ch, tx_buf, (uint8_t *)&spi_handle[id].base->DATA, len / frame_size, spi_dma_callback);
|
#endif
|
}
|
else if (spi_handle[id].int_tx)
|
{
|
#if SPI_INT_MODE_EN
|
// write data to FIFO
|
while ((spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK) && (spi_handle[id].tx_count < spi_handle[id].tx_size))
|
{
|
frame_data = 0;
|
memcpy(&frame_data, &spi_handle[id].tx_buff[spi_handle[id].tx_count], frame_size);
|
spi_handle[id].base->DATA = frame_data;
|
spi_handle[id].tx_count += frame_size;
|
}
|
// enable interrupts
|
spi_handle[id].base->INTR_EN |= SPI_INTR_EN_TX_MSK | SPI_INTR_EN_RX_MSK | SPI_INTR_EN_RT_MSK | SPI_INTR_EN_ROR_MSK;
|
#endif
|
}
|
else
|
{
|
#if SPI_POLL_MODE_EN
|
// polling
|
while (spi_handle[id].rx_count < spi_handle[id].rx_size)
|
{
|
if ((spi_handle[id].base->CTRL1 & SPI_CTRL1_SSE_MSK) == 0)
|
{
|
ret = DRV_ERROR;
|
break;
|
}
|
|
if ((spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK) && (spi_handle[id].tx_count < spi_handle[id].tx_size))
|
{
|
frame_data = 0;
|
memcpy(&frame_data, &spi_handle[id].tx_buff[spi_handle[id].tx_count], frame_size);
|
spi_handle[id].base->DATA = frame_data;
|
spi_handle[id].tx_count += frame_size;
|
}
|
|
if (spi_handle[id].base->STATUS0 & SPI_STATUS0_RNE_MSK)
|
{
|
frame_data = spi_handle[id].base->DATA;
|
memcpy(&spi_handle[id].rx_buff[spi_handle[id].rx_count], &frame_data, frame_size);
|
spi_handle[id].rx_count += frame_size;
|
}
|
}
|
|
// update state
|
spi_state_clear(id, SPI_STATE_BUSY_TX_RX);
|
|
if (spi_handle[id].rx_callback)
|
{
|
spi_handle[id].rx_callback(&id, 0);
|
}
|
#endif
|
}
|
|
return ret;
|
}
|
|
int spi_abort_dma(enum SPI_DEV_T id, uint32_t abort_direction, drv_callback_t abort_tx_callback, drv_callback_t abort_rx_callback)
|
{
|
#if SPI_DMA_MODE_EN
|
/*
|
* disable the SPI DMA rx request if enabled
|
* if (REG_IS_BIT_SET(spi_handle[id].base->DMA_EN, SPI_DMA_EN_RX_MSK))
|
* if (spi_handle[id].state & SPI_STATE_BUSY_RX)
|
*/
|
if (SPI_DMA_ABORT_RX & abort_direction)
|
{
|
spi_handle[id].rx_abort_callback = abort_rx_callback;
|
spi_handle[id].base->DMA_EN &= ~SPI_DMA_EN_RX_MSK;
|
// dma_abort(spi_handle[id].dma_rx_ch, spi_dma_abort_callback);
|
dma_force_abort(spi_handle[id].dma_rx_ch, spi_dma_abort_callback);
|
}
|
|
/*
|
* disable the SPI DMA tx request if enabled
|
* if (REG_IS_BIT_SET(spi_handle[id].base->DMA_EN, SPI_DMA_EN_TX_MSK))
|
* if (spi_handle[id].state & SPI_STATE_BUSY_TX)
|
*/
|
if (SPI_DMA_ABORT_TX & abort_direction)
|
{
|
spi_handle[id].tx_abort_callback = abort_tx_callback;
|
spi_handle[id].base->DMA_EN &= ~SPI_DMA_EN_TX_MSK;
|
// dma_abort(spi_handle[id].dma_tx_ch, spi_dma_abort_callback);
|
dma_force_abort(spi_handle[id].dma_tx_ch, spi_dma_abort_callback);
|
}
|
#endif
|
|
return DRV_OK;
|
}
|
|
#if defined(__GNUC__)
|
#pragma GCC diagnostic pop
|
#endif
|
|
#if SPI_DMA_MODE_EN
|
static void spi_dma_abort_callback(void *ch, uint32_t err_code)
|
{
|
uint8_t ch_num = *(uint8_t *)ch;
|
drv_callback_t usr_callback = NULL;
|
enum SPI_DEV_T id;
|
|
if ((ch_num == spi_handle[SPI_ID0].dma_tx_ch) || (ch_num == spi_handle[SPI_ID1].dma_tx_ch))
|
{
|
id = (ch_num == spi_handle[SPI_ID0].dma_tx_ch ? SPI_ID0 : SPI_ID1);
|
|
// TX dma abort
|
usr_callback = spi_handle[id].tx_abort_callback;
|
|
// update state
|
spi_handle[id].state = SPI_STATE_READY;
|
|
spi_handle[id].tx_buff = NULL;
|
spi_handle[id].tx_abort_callback = NULL;
|
spi_handle[id].tx_callback = NULL;
|
spi_handle[id].tx_count = 0;
|
spi_handle[id].tx_size = 0;
|
}
|
else if ((ch_num == spi_handle[SPI_ID0].dma_rx_ch) || (ch_num == spi_handle[SPI_ID1].dma_rx_ch))
|
{
|
id = (ch_num == spi_handle[SPI_ID0].dma_rx_ch ? SPI_ID0 : SPI_ID1);
|
|
// RX dma abort
|
usr_callback = spi_handle[id].rx_abort_callback;
|
|
spi_handle[id].state = SPI_STATE_READY;
|
|
spi_handle[id].rx_buff = NULL;
|
spi_handle[id].rx_abort_callback = NULL;
|
spi_handle[id].rx_callback = NULL;
|
spi_handle[id].rx_count = 0;
|
spi_handle[id].rx_size = 0;
|
}
|
else
|
{
|
ASSERT(0, "Unexpected dma channel\r\n");
|
}
|
|
if (usr_callback)
|
{
|
usr_callback(&id, err_code);
|
}
|
}
|
|
static void spi_dma_callback(void *ch, uint32_t err_code)
|
{
|
uint8_t ch_num = *(uint8_t *)ch;
|
drv_callback_t usr_callback = NULL;
|
enum SPI_DEV_T id;
|
|
if ((ch_num == spi_handle[SPI_ID0].dma_tx_ch) || (ch_num == spi_handle[SPI_ID1].dma_tx_ch))
|
{
|
id = (ch_num == spi_handle[SPI_ID0].dma_tx_ch ? SPI_ID0 : SPI_ID1);
|
|
if (err_code == DMA_INT_TYPE_DONE)
|
{
|
spi_handle[id].base->DMA_EN &= ~SPI_DMA_EN_TX_MSK;
|
|
// TX done
|
usr_callback = spi_handle[id].tx_callback;
|
|
// update state
|
spi_state_clear(id, SPI_STATE_BUSY_TX);
|
}
|
else
|
{
|
// update state
|
if ((spi_handle[id].state == SPI_STATE_BUSY_TX_RX) || (spi_handle[id].state == SPI_STATE_BUSY_TX))
|
{
|
spi_handle[id].state = SPI_STATE_ERROR;
|
}
|
else
|
{
|
ASSERT(0, "Unexpected spi state\r\n");
|
}
|
}
|
spi_handle[id].tx_buff = NULL;
|
spi_handle[id].tx_callback = NULL;
|
spi_handle[id].tx_count = 0;
|
spi_handle[id].tx_size = 0;
|
}
|
else if ((ch_num == spi_handle[SPI_ID0].dma_rx_ch) || (ch_num == spi_handle[SPI_ID1].dma_rx_ch))
|
{
|
id = (ch_num == spi_handle[SPI_ID0].dma_rx_ch ? SPI_ID0 : SPI_ID1);
|
|
if (err_code == DMA_INT_TYPE_DONE)
|
{
|
spi_handle[id].base->DMA_EN &= ~SPI_DMA_EN_RX_MSK;
|
// RX done
|
usr_callback = spi_handle[id].rx_callback;
|
|
// update state
|
spi_state_clear(id, SPI_STATE_BUSY_RX);
|
}
|
else
|
{
|
// update state
|
if ((spi_handle[id].state == SPI_STATE_BUSY_TX_RX) || (spi_handle[id].state == SPI_STATE_BUSY_RX))
|
{
|
spi_handle[id].state = SPI_STATE_ERROR;
|
}
|
else
|
{
|
ASSERT(0, "Unexpected spi state\r\n");
|
}
|
}
|
spi_handle[id].rx_buff = NULL;
|
spi_handle[id].rx_callback = NULL;
|
spi_handle[id].rx_count = 0;
|
spi_handle[id].rx_size = 0;
|
}
|
else
|
{
|
ASSERT(0, "Unexpected dma channel\r\n");
|
}
|
|
if (usr_callback)
|
{
|
usr_callback(&id, err_code);
|
}
|
}
|
#endif
|
|
#if SPI_INT_MODE_EN
|
static void spi_irq_handler(enum SPI_DEV_T id)
|
{
|
drv_callback_t usr_callback = NULL;
|
// what caused the interrupt?
|
uint32_t int_stat = spi_handle[id].base->INTR_STATUS;
|
|
uint32_t frame_data = 0U;
|
uint8_t frame_size = spi_get_frame_size(id);
|
|
if (int_stat & (SPI_INTR_STATUS_RX_MSK | SPI_INTR_STATUS_ROR_MSK | SPI_INTR_STATUS_RT_MSK))
|
{
|
if (int_stat & SPI_INTR_STATUS_ROR_MSK)
|
{
|
spi_handle[id].base->INTR_CLR = SPI_INTR_CLR_ROR_MSK;
|
LOG_INFO(TRACE_MODULE_DRIVER, "SPI receive overrun\r\n");
|
}
|
else if (int_stat & SPI_INTR_STATUS_RT_MSK)
|
{
|
// rx timeout interrupt happens to fetch less than 4 bytes data in FIFO
|
spi_handle[id].base->INTR_CLR = SPI_INTR_CLR_RT_MSK;
|
}
|
|
// received data - read FIFO
|
if (spi_handle[id].state & SPI_STATE_BUSY_RX)
|
{
|
while ((spi_handle[id].base->STATUS0 & SPI_STATUS0_RNE_MSK) && (spi_handle[id].rx_count < spi_handle[id].rx_size))
|
{
|
frame_data = spi_handle[id].base->DATA;
|
memcpy(&spi_handle[id].rx_buff[spi_handle[id].rx_count], &frame_data, frame_size);
|
spi_handle[id].rx_count += frame_size;
|
}
|
|
if (spi_handle[id].rx_count == spi_handle[id].rx_size)
|
{
|
// RX done - disable interrupts
|
spi_handle[id].base->INTR_EN &= ~(SPI_INTR_EN_RX_MSK | SPI_INTR_EN_RT_MSK | SPI_INTR_EN_ROR_MSK);
|
usr_callback = spi_handle[id].rx_callback;
|
|
// update state
|
spi_state_clear(id, SPI_STATE_BUSY_RX);
|
|
spi_handle[id].rx_buff = NULL;
|
spi_handle[id].rx_callback = NULL;
|
spi_handle[id].rx_count = 0;
|
spi_handle[id].rx_size = 0;
|
}
|
else if ((spi_handle[id].slave == 0) && (((spi_handle[id].state & SPI_STATE_BUSY_TX) == 0) && (spi_handle[id].base->STATUS0 & SPI_STATUS0_TFE_MSK)))
|
{
|
// send dummy data as many as possible
|
uint32_t dummy_cnt = spi_handle[id].rx_size - spi_handle[id].rx_count;
|
while ((dummy_cnt >= frame_size) && (spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK))
|
{
|
spi_handle[id].base->DATA = spi_handle[id].tx_dummy;
|
dummy_cnt -= frame_size;
|
}
|
}
|
}
|
}
|
else if (int_stat & SPI_INTR_STATUS_TX_MSK)
|
{
|
if (spi_handle[id].state & SPI_STATE_BUSY_TX)
|
{
|
if (spi_handle[id].tx_count == spi_handle[id].tx_size)
|
{
|
// TX done - disable interrupt
|
spi_handle[id].base->INTR_EN &= ~SPI_INTR_EN_TX_MSK;
|
usr_callback = spi_handle[id].tx_callback;
|
|
// update state
|
spi_state_clear(id, SPI_STATE_BUSY_TX);
|
|
spi_handle[id].tx_buff = NULL;
|
spi_handle[id].tx_callback = NULL;
|
spi_handle[id].tx_count = 0;
|
spi_handle[id].tx_size = 0;
|
}
|
else
|
{
|
// TX continue - write FIFO
|
while ((spi_handle[id].base->STATUS0 & SPI_STATUS0_TNF_MSK) && (spi_handle[id].tx_count < spi_handle[id].tx_size))
|
{
|
frame_data = 0;
|
memcpy(&frame_data, &spi_handle[id].tx_buff[spi_handle[id].tx_count], frame_size);
|
spi_handle[id].base->DATA = frame_data;
|
spi_handle[id].tx_count += frame_size;
|
}
|
}
|
}
|
}
|
else
|
{
|
// it will reach here since FIFO was read empty by last interrupt
|
}
|
|
if (usr_callback)
|
{
|
usr_callback(&id, int_stat);
|
}
|
}
|
#endif
|
|
void SPI0_IRQHandler(void)
|
{
|
#if SPI_INT_MODE_EN
|
spi_irq_handler(SPI_ID0);
|
#endif
|
}
|
|
void SPI1_IRQHandler(void)
|
{
|
#if SPI_INT_MODE_EN
|
spi_irq_handler(SPI_ID1);
|
#endif
|
}
|
