/*
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* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: Exception handlers (C functions)
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*
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* -----------------------------------------------------------------------------
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*/
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#include "RTE_Components.h"
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#include CMSIS_device_header
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//Fault Status Register (IFSR/DFSR) definitions
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#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
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#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
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#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
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#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
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#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
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#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
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#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
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#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
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#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
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#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
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#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
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#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
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#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal
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#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal
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#define FSR_DEBUG_EVENT 0x02 //internal
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#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
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#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
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#define FSR_LOCKDOWN 0x14 //internal
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#define FSR_COPROCESSOR_ABORT 0x1a //internal
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#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
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#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
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#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
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void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
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uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
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switch(FS) {
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//Synchronous parity errors - retry
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case FSR_SYNC_PARITY_ERROR:
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case FSR_SYNC_PARITY_TTB_WALK_FIRST:
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case FSR_SYNC_PARITY_TTB_WALK_SECOND:
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return;
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//Your code here. Value in DFAR is invalid for some fault statuses.
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case FSR_ALIGNMENT_FAULT:
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case FSR_INSTRUCTION_CACHE_MAINTENANCE:
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case FSR_SYNC_EXT_TTB_WALK_FIRST:
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case FSR_SYNC_EXT_TTB_WALK_SECOND:
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case FSR_TRANSLATION_FAULT_FIRST:
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case FSR_TRANSLATION_FAULT_SECOND:
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case FSR_ACCESS_FLAG_FAULT_FIRST:
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case FSR_ACCESS_FLAG_FAULT_SECOND:
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case FSR_DOMAIN_FAULT_FIRST:
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case FSR_DOMAIN_FAULT_SECOND:
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case FSR_PERMISSION_FAULT_FIRST:
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case FSR_PERMISSION_FAULT_SECOND:
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case FSR_DEBUG_EVENT:
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case FSR_SYNC_EXT_ABORT:
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case FSR_TLB_CONFLICT_ABORT:
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case FSR_LOCKDOWN:
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case FSR_COPROCESSOR_ABORT:
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case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
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case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
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default:
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while(1);
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}
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}
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void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
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uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
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switch(FS) {
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//Synchronous parity errors - retry
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case FSR_SYNC_PARITY_ERROR:
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case FSR_SYNC_PARITY_TTB_WALK_FIRST:
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case FSR_SYNC_PARITY_TTB_WALK_SECOND:
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return;
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//Your code here. Value in IFAR is invalid for some fault statuses.
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case FSR_SYNC_EXT_TTB_WALK_FIRST:
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case FSR_SYNC_EXT_TTB_WALK_SECOND:
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case FSR_TRANSLATION_FAULT_FIRST:
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case FSR_TRANSLATION_FAULT_SECOND:
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case FSR_ACCESS_FLAG_FAULT_FIRST:
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case FSR_ACCESS_FLAG_FAULT_SECOND:
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case FSR_DOMAIN_FAULT_FIRST:
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case FSR_DOMAIN_FAULT_SECOND:
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case FSR_PERMISSION_FAULT_FIRST:
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case FSR_PERMISSION_FAULT_SECOND:
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case FSR_DEBUG_EVENT: //IFAR invalid
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case FSR_SYNC_EXT_ABORT:
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case FSR_TLB_CONFLICT_ABORT:
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case FSR_LOCKDOWN:
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case FSR_COPROCESSOR_ABORT:
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default:
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while(1);
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}
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}
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//returns amount to decrement lr by
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//this will be 0 when we have emulated the instruction and want to execute the next instruction
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//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
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//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
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uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
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const int THUMB = 2;
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const int ARM = 4;
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//Lazy VFP/NEON initialisation and switching
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// (ARM ARM section A7.5) VFP data processing instruction?
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// (ARM ARM section A7.6) VFP/NEON register load/store instruction?
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// (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
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// (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
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if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
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(state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
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if (((opcode & 0x00000E00) >> 9) == 5) {
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__FPU_Enable();
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return state;
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}
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}
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// (ARM ARM section A7.4) NEON data processing instruction?
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if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
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(state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
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// (ARM ARM section A7.7) NEON load/store instruction?
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(state == ARM && ((opcode >> 24) == 0xF4)) ||
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(state == THUMB && ((opcode >> 24) == 0xF9))) {
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__FPU_Enable();
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return state;
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}
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//Add code here for other Undef cases
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while(1);
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}
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