/******************************************************************************
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* @file startup_ARMCA5.c
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* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
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* @version V1.00
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* @date 10. January 2018
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <ARMCA5.h>
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/*----------------------------------------------------------------------------
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Definitions
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*----------------------------------------------------------------------------*/
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#define USR_MODE 0x10 // User mode
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#define FIQ_MODE 0x11 // Fast Interrupt Request mode
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#define IRQ_MODE 0x12 // Interrupt Request mode
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#define SVC_MODE 0x13 // Supervisor mode
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#define ABT_MODE 0x17 // Abort mode
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#define UND_MODE 0x1B // Undefined Instruction mode
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#define SYS_MODE 0x1F // System mode
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/*----------------------------------------------------------------------------
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Internal References
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*----------------------------------------------------------------------------*/
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void Vectors (void) __attribute__ ((naked, section("RESET")));
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void Reset_Handler (void) __attribute__ ((naked));
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/*----------------------------------------------------------------------------
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Exception / Interrupt Handler
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*----------------------------------------------------------------------------*/
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void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector Table
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*----------------------------------------------------------------------------*/
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void Vectors(void) {
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__ASM volatile(
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"LDR PC, =Reset_Handler \n"
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"LDR PC, =Undef_Handler \n"
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"LDR PC, =SVC_Handler \n"
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"LDR PC, =PAbt_Handler \n"
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"LDR PC, =DAbt_Handler \n"
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"NOP \n"
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"LDR PC, =IRQ_Handler \n"
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"LDR PC, =FIQ_Handler \n"
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);
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}
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/*----------------------------------------------------------------------------
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Reset Handler called on controller reset
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*----------------------------------------------------------------------------*/
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void Reset_Handler(void) {
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__ASM volatile(
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// Mask interrupts
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"CPSID if \n"
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// Put any cores other than 0 to sleep
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"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
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"ANDS R0, R0, #3 \n"
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"goToSleep: \n"
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"WFINE \n"
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"BNE goToSleep \n"
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// Reset SCTLR Settings
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"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
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"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
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"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
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"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
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"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
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"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
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"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
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"ISB \n"
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// Configure ACTLR
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"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
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"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
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"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
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// Set Vector Base Address Register (VBAR) to point to this application's vector table
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"LDR R0, =Vectors \n"
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"MCR p15, 0, R0, c12, c0, 0 \n"
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// Setup Stack for each exceptional mode
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"CPS #0x11 \n"
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"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
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"CPS #0x12 \n"
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"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
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"CPS #0x13 \n"
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"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
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"CPS #0x17 \n"
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"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
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"CPS #0x1B \n"
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"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
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"CPS #0x1F \n"
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"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
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// Call SystemInit
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"BL SystemInit \n"
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// Unmask interrupts
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"CPSIE if \n"
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// Call __main
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"BL __main \n"
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);
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}
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/*----------------------------------------------------------------------------
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Default Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
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void Default_Handler(void) {
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while(1);
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}
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