/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file stm32h7xx_it.c
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* @brief Interrupt Service Routines.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2025 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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#include "stm32h7xx_it.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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#include "bluetooth.h"
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN TD */
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/* USER CODE END TD */
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/* Private define ------------------------------------------------------------*/
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/* USER CODE BEGIN PD */
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/* USER CODE END PD */
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/* Private macro -------------------------------------------------------------*/
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/* USER CODE BEGIN PM */
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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/* USER CODE BEGIN PV */
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/* USER CODE END PV */
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/* Private function prototypes -----------------------------------------------*/
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/* USER CODE BEGIN PFP */
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/* USER CODE END PFP */
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/* Private user code ---------------------------------------------------------*/
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/* External variables --------------------------------------------------------*/
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extern TIM_HandleTypeDef htim2;
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extern TIM_HandleTypeDef htim3;
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extern TIM_HandleTypeDef htim4;
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extern DMA_HandleTypeDef hdma_uart4_rx;
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extern DMA_HandleTypeDef hdma_usart1_rx;
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extern DMA_HandleTypeDef hdma_usart1_tx;
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extern DMA_HandleTypeDef hdma_usart2_rx;
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extern DMA_HandleTypeDef hdma_usart2_tx;
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extern DMA_HandleTypeDef hdma_usart3_rx;
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extern DMA_HandleTypeDef hdma_usart3_tx;
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extern DMA_HandleTypeDef hdma_usart6_rx;
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extern DMA_HandleTypeDef hdma_usart6_tx;
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extern UART_HandleTypeDef huart4;
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extern UART_HandleTypeDef huart1;
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extern UART_HandleTypeDef huart2;
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extern UART_HandleTypeDef huart3;
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extern UART_HandleTypeDef huart6;
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extern TIM_HandleTypeDef htim17;
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/* USER CODE BEGIN EV */
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/* USER CODE END EV */
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/******************************************************************************/
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/* Cortex Processor Interruption and Exception Handlers */
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/******************************************************************************/
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/**
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* @brief This function handles Non maskable interrupt.
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
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/* USER CODE END NonMaskableInt_IRQn 0 */
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/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
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while (1)
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{
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}
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/* USER CODE END NonMaskableInt_IRQn 1 */
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}
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/**
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* @brief This function handles Hard fault interrupt.
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*/
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void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn 0 */
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/* USER CODE END HardFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_HardFault_IRQn 0 */
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/* USER CODE END W1_HardFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Memory management fault.
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN MemoryManagement_IRQn 0 */
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/* USER CODE END MemoryManagement_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
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/* USER CODE END W1_MemoryManagement_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Pre-fetch fault, memory access fault.
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN BusFault_IRQn 0 */
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/* USER CODE END BusFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_BusFault_IRQn 0 */
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/* USER CODE END W1_BusFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Undefined instruction or illegal state.
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN UsageFault_IRQn 0 */
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/* USER CODE END UsageFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
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/* USER CODE END W1_UsageFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Debug monitor.
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*/
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void DebugMon_Handler(void)
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{
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/* USER CODE BEGIN DebugMonitor_IRQn 0 */
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/* USER CODE END DebugMonitor_IRQn 0 */
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/* USER CODE BEGIN DebugMonitor_IRQn 1 */
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/* USER CODE END DebugMonitor_IRQn 1 */
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}
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/******************************************************************************/
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/* STM32H7xx Peripheral Interrupt Handlers */
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/* Add here the Interrupt Handlers for the used peripherals. */
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/* For the available peripheral interrupt handler names, */
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/* please refer to the startup file (startup_stm32h7xx.s). */
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/******************************************************************************/
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/**
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* @brief This function handles DMA1 stream0 global interrupt.
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*/
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void DMA1_Stream0_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
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/* USER CODE END DMA1_Stream0_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart1_rx);
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/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
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/* USER CODE END DMA1_Stream0_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream1 global interrupt.
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*/
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void DMA1_Stream1_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
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/* USER CODE END DMA1_Stream1_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart1_tx);
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/* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
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/* USER CODE END DMA1_Stream1_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream2 global interrupt.
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*/
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void DMA1_Stream2_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
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/* USER CODE END DMA1_Stream2_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart2_rx);
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/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
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/* USER CODE END DMA1_Stream2_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream3 global interrupt.
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*/
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void DMA1_Stream3_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
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/* USER CODE END DMA1_Stream3_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart2_tx);
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/* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
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/* USER CODE END DMA1_Stream3_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream4 global interrupt.
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*/
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void DMA1_Stream4_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
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/* USER CODE END DMA1_Stream4_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart3_rx);
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/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
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/* USER CODE END DMA1_Stream4_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream5 global interrupt.
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*/
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void DMA1_Stream5_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
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/* USER CODE END DMA1_Stream5_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart3_tx);
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/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
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/* USER CODE END DMA1_Stream5_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream6 global interrupt.
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*/
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void DMA1_Stream6_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
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/* USER CODE END DMA1_Stream6_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart6_rx);
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/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
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/* USER CODE END DMA1_Stream6_IRQn 1 */
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}
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/**
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* @brief This function handles TIM2 global interrupt.
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*/
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void TIM2_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM2_IRQn 0 */
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/* USER CODE END TIM2_IRQn 0 */
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HAL_TIM_IRQHandler(&htim2);
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/* USER CODE BEGIN TIM2_IRQn 1 */
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/* USER CODE END TIM2_IRQn 1 */
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}
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/**
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* @brief This function handles TIM3 global interrupt.
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*/
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void TIM3_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM3_IRQn 0 */
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/* USER CODE END TIM3_IRQn 0 */
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HAL_TIM_IRQHandler(&htim3);
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/* USER CODE BEGIN TIM3_IRQn 1 */
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/* USER CODE END TIM3_IRQn 1 */
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}
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/**
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* @brief This function handles TIM4 global interrupt.
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*/
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void TIM4_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM4_IRQn 0 */
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/* USER CODE END TIM4_IRQn 0 */
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HAL_TIM_IRQHandler(&htim4);
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/* USER CODE BEGIN TIM4_IRQn 1 */
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/* USER CODE END TIM4_IRQn 1 */
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}
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/**
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* @brief This function handles USART1 global interrupt.
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*/
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void USART1_IRQHandler(void)
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{
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/* USER CODE BEGIN USART1_IRQn 0 */
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/* USER CODE END USART1_IRQn 0 */
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HAL_UART_IRQHandler(&huart1);
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/* USER CODE BEGIN USART1_IRQn 1 */
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/* USER CODE END USART1_IRQn 1 */
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}
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/**
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* @brief This function handles USART2 global interrupt.
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*/
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void USART2_IRQHandler(void)
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{
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/* USER CODE BEGIN USART2_IRQn 0 */
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/* USER CODE END USART2_IRQn 0 */
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HAL_UART_IRQHandler(&huart2);
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/* USER CODE BEGIN USART2_IRQn 1 */
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/* USER CODE END USART2_IRQn 1 */
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}
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/**
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* @brief This function handles USART3 global interrupt.
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*/
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void USART3_IRQHandler(void)
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{
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/* USER CODE BEGIN USART3_IRQn 0 */
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/* USER CODE END USART3_IRQn 0 */
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HAL_UART_IRQHandler(&huart3);
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/* USER CODE BEGIN USART3_IRQn 1 */
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/* USER CODE END USART3_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream7 global interrupt.
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*/
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void DMA1_Stream7_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
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/* USER CODE END DMA1_Stream7_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart6_tx);
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/* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
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/* USER CODE END DMA1_Stream7_IRQn 1 */
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}
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/**
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* @brief This function handles UART4 global interrupt.
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*/
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void UART4_IRQHandler(void)
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{
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/* USER CODE BEGIN UART4_IRQn 0 */
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/* USER CODE END UART4_IRQn 0 */
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HAL_UART_IRQHandler(&huart4);
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/* USER CODE BEGIN UART4_IRQn 1 */
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/* USER CODE END UART4_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream0 global interrupt.
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*/
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void DMA2_Stream0_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
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/* USER CODE END DMA2_Stream0_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_uart4_rx);
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/* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
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/* USER CODE END DMA2_Stream0_IRQn 1 */
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}
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/**
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* @brief This function handles USART6 global interrupt.
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*/
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void USART6_IRQHandler(void)
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{
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/* USER CODE BEGIN USART6_IRQn 0 */
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uint32_t tmp_flag = 0;
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uint32_t temp;
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tmp_flag = __HAL_UART_GET_FLAG(&huart6, UART_FLAG_IDLE);
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if ((tmp_flag != RESET))
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{
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__HAL_UART_CLEAR_IDLEFLAG(&huart6);
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HAL_UART_DMAStop(&huart6); //
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temp = __HAL_DMA_GET_COUNTER(&hdma_usart6_rx);
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uart6_dma_recv_len = UART6_DMA_RX_BUF_SIZE - temp;
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uart6_dma_recv_end_flag = 1;
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HAL_UART_Receive_DMA(&huart6, uart6_dma_rxbuf, UART6_DMA_RX_BUF_SIZE);
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}
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/* USER CODE END USART6_IRQn 0 */
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HAL_UART_IRQHandler(&huart6);
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/* USER CODE BEGIN USART6_IRQn 1 */
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/* USER CODE END USART6_IRQn 1 */
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}
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/**
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* @brief This function handles TIM17 global interrupt.
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*/
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void TIM17_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM17_IRQn 0 */
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/* USER CODE END TIM17_IRQn 0 */
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HAL_TIM_IRQHandler(&htim17);
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/* USER CODE BEGIN TIM17_IRQn 1 */
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/* USER CODE END TIM17_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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