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Pdà dà Ðdà eà Pe à e à PddÐdePeeà# ¿ à# ¿ ø< ¿FÂçÐé#ChÚ`Ðé#CÃiCjCCjCÃjCkC[ BêBhChaBh²ñOÑhiBð@Bha "hZaBk * ÚhRiBô"hZaBkQB²hbà²hbk *ÚhRiBô "hZakQBhjBêBhbàhjCêBhbBh²ñOÐyhbà "hb "hZbpGðµ Fhvicóh~ao hvigó Vh~a &h~`hòah´aðA±ñ _ Ð1¹h¶jFô6h¾bàh¶j&ô6h¾bðA±ñ _ Ð1¹h¶jFô 6h¾bàh¶j&ô 6h¾bhÆm~bð½ ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM __asm___20_stm32h7xx_hal_mdma_c_49e2804d____REV16 X > ..\Drivers\CMSIS\Include\ cmsis_armcc.h í ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM __asm___20_stm32h7xx_hal_mdma_c_49e2804d____REVSH X > ..\Drivers\CMSIS\Include\ cmsis_armcc.h ü ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM __asm___20_stm32h7xx_hal_mdma_c_49e2804d____RRX X > ..\Drivers\CMSIS\Include\ cmsis_armcc.h ·& ` ÿÿÿÿarmcc+ |
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../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM Ä ? MDMA_Init Ä ihmdma ? Yblockoffset Y Q ( ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM l >¨ÚHAL_MDMA_Init ú l ihmdma ? F ___result ú Ztickstart Y 3 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ^ >¦HAL_MDMA_DeInit ú ^ ihmdma ? * ___result ú ` ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM n >ßÛHAL_MDMA_ConfigPostRequestMask ú n ihmdma ? n iMaskAddress Y [ iMaskData Y H ___result ú " Zstatus ú 5 d ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM d >æHAL_MDMA_RegisterCallback ú d ihmdma ? n iCallbackID p [ ipCallback <H O¼%? "2___result ú " Zstatus ú 5 H ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM >ÈÚHAL_MDMA_UnRegisterCallback ú ihmdma ? N iCallbackID p ; ___result ú Zstatus ú ( h ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM
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ipNode Ò n ipNodeConfig E [ ___result ú 5 ZaddressMask Y " Zblockoffset Y H ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ä >ÇHAL_MDMA_LinkedList_AddNode ú ä ihmdma ? ² ipNewNode Ò ipPrevNode Q ___result ú " ZpNode Ò n Zcounter Y [ ZnodeInserted Y H Zhal_status ú 5 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM Ø >
ÌHAL_MDMA_LinkedList_RemoveNode ú Ø ihmdma ? ipNode Ò ___result ú ZptmpNode Ò l Zcounter Y Y ZnodeDeleted Y F Zhal_status ú 3 @ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM X >½HAL_MDMA_LinkedList_EnableCircularMode ú X ihmdma ? : ___result ú Zhal_status ú ' D ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM X >ÃéHAL_MDMA_LinkedList_DisableCircularMode ú X ihmdma ? : ___result ú Zhal_status ú ' h ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ?êà MDMA_SetConfig ihmdma ? y iSrcAddress Y [ iDstAddress Y H iBlockDataLength Y 5 iBlockCount Y " XaddressMask Y Q2 l ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM >î°HAL_MDMA_Start ú ihmdma ? ¢ iSrcAddress Y iDstAddress Y f iBlockDataLength Y H iBlockCount Y 5 ___result ú " p ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM Ì >ñìHAL_MDMA_Start_IT ú Ì ihmdma ? ¢ iSrcAddress Y iDstAddress Y f iBlockDataLength Y H iBlockCount Y 5 ___result ú " ( ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM >©¿ HAL_MDMA_Abort ú ihmdma ? F ___result ú Ztickstart Y 3 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM . >
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HAL_MDMA_Abort_IT ú . ihmdma ? * ___result ú ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM " >
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HAL_MDMA_PollForTransfer ú " ihmdma ? ª iCompleteLevel J iTimeout Y n ___result ú [ ZlevelFlag Y H ZerrorFlag Y " Ztickstart Y 5 8 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM H >¸¶ HAL_MDMA_GenerateSWRequest ú H ihmdma ? : ___result ú ' Zrequest_mode Y P ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM Ü ?Ïà HAL_MDMA_IRQHandler Ü ihmdma ? Z Ycount U hZtimeout Y 4 ZgeneralIntFlag Y ! ZerrorFlag Y G ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM >º HAL_MDMA_GetState , ihmdma a ^__result , P ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM >Å
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U P T . } P P , Q } " } R ¬ V B X < Y P R W Q U P T H } F R P P F Q } Ü } $ Ø W Ø V Ø U P Ø T } P Q } P Q __DATE__ "Nov 12 2025" __TIME__ "10:32:11" __STDC__ 1 __STDC_VERSION__ 199901L __STDC_HOSTED__ 1 __STDC_ISO_10646__ 200607 __EDG__ 1 __EDG_VERSION__ 407 __EDG_SIZE_TYPE__ unsigned int __EDG_PTRDIFF_TYPE__ int __GNUC__ 4 __GNUC_STDC_INLINE__ 1 __GNUC_MINOR__ 7 __GNUC_PATCHLEVEL__ 0 __VERSION__ "4.7 (EDG gcc mode)" __CHAR16_TYPE__ unsigned short __CHAR32_TYPE__ unsigned int __USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1 __WCHAR_UNSIGNED__ 1 __SIZE_TYPE__ unsigned int __PTRDIFF_TYPE__ int __WCHAR_TYPE__ unsigned short __WINT_TYPE__ unsigned short __INTMAX_TYPE__ long long __UINTMAX_TYPE__ unsigned long long __sizeof_int 4 __sizeof_long 4 __sizeof_ptr 4 __ARMCC_VERSION 5060750 __TARGET_CPU_CORTEX_M7_FP_DP 1 __TARGET_FPU_FPV5_D16 1 __UVISION_VERSION 530 _RTE_ 1 STM32H743xx 1 _RTE_ 1 USE_PWR_LDO_SUPPLY 1 USE_HAL_DRIVER 1 STM32H743xx 1 _USE_OS_ 1 _RTK_MODE_ 1 __EC600S__ 1 __APP_CODE__ 1 __USE_UWB__ 1 __USE_NTRIP__ 1 __CC_ARM 1 __arm 1 __arm__ 1 __TARGET_ARCH_7E_M 1 __TARGET_ARCH_ARM 0 __TARGET_ARCH_THUMB 4 __TARGET_ARCH_A64 0 __TARGET_ARCH_AARCH32 1 __TARGET_PROFILE_M 1 __TARGET_FEATURE_HALFWORD 1 __TARGET_FEATURE_THUMB 1 __TARGET_FEATURE_MULTIPLY 1 __TARGET_FEATURE_DSPMUL 1 __TARGET_FEATURE_DOUBLEWORD 1 __TARGET_FEATURE_DIVIDE 1 __TARGET_FEATURE_UNALIGNED 1 __TARGET_FEATURE_CLZ 1 __TARGET_FEATURE_DMB 1 __TARGET_FPU_VFPV5 1 __TARGET_FPU_VFP 1 __TARGET_FPU_VFP_SINGLE 1 __TARGET_FPU_VFP_DOUBLE 1 __TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16 __APCS_INTERWORK 1 __FP_FAST_FMAF 1 __FP_FAST_FMA 1 __FP_FAST_FMAL 1 __thumb 1 __thumb__ 1 __t32__ 1 __OPTIMISE_SPACE 1 __OPTIMIZE_SIZE__ 1 __OPTIMISE_LEVEL 0 , È HAL_MDMA_Init " È HAL_MDMA_DeInit 1 d È HAL_MDMA_ConfigPostRequestMask , h È HAL_MDMA_RegisterCallback . L È HAL_MDMA_UnRegisterCallback 1 l È HAL_MDMA_LinkedList_CreateNode . È HAL_MDMA_LinkedList_AddNode 1 È HAL_MDMA_LinkedList_RemoveNode 9 D È HAL_MDMA_LinkedList_EnableCircularMode : H È HAL_MDMA_LinkedList_DisableCircularMode ! p È HAL_MDMA_Start $ t È HAL_MDMA_Start_IT ! , È HAL_MDMA_Abort $ È HAL_MDMA_Abort_IT + È HAL_MDMA_PollForTransfer - < È HAL_MDMA_GenerateSWRequest & T È HAL_MDMA_IRQHandler $ È HAL_MDMA_GetState $ È HAL_MDMA_GetError % . __stdint_h __ARMCLIB_VERSION 5060037 __INT64 __int64 __INT64_C_SUFFIX__ ll __PASTE2(x,y) x ## y __PASTE(x,y) __PASTE2(x, y) __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) __LONGLONG long long #__STDINT_DECLS %__CLIBNS ,__CLIBNS sINT8_MIN -128 tINT16_MIN -32768 uINT32_MIN (~0x7fffffff) vINT64_MIN __INT64_C(~0x7fffffffffffffff) yINT8_MAX 127 zINT16_MAX 32767 {INT32_MAX 2147483647 |INT64_MAX __INT64_C(9223372036854775807) UINT8_MAX 255 UINT16_MAX 65535 UINT32_MAX 4294967295u UINT64_MAX __UINT64_C(18446744073709551615) INT_LEAST8_MIN -128 INT_LEAST16_MIN -32768 INT_LEAST32_MIN (~0x7fffffff) INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) INT_LEAST8_MAX 127 INT_LEAST16_MAX 32767 INT_LEAST32_MAX 2147483647 INT_LEAST64_MAX __INT64_C(9223372036854775807) UINT_LEAST8_MAX 255 UINT_LEAST16_MAX 65535 UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __UINT64_C(18446744073709551615) INT_FAST8_MIN (~0x7fffffff) INT_FAST16_MIN (~0x7fffffff) INT_FAST32_MIN (~0x7fffffff) INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) ¡INT_FAST8_MAX 2147483647 ¢INT_FAST16_MAX 2147483647 £INT_FAST32_MAX 2147483647 ¤INT_FAST64_MAX __INT64_C(9223372036854775807) §UINT_FAST8_MAX 4294967295u ¨UINT_FAST16_MAX 4294967295u ©UINT_FAST32_MAX 4294967295u ªUINT_FAST64_MAX __UINT64_C(18446744073709551615) ²INTPTR_MIN INT32_MIN ¹INTPTR_MAX INT32_MAX ÀUINTPTR_MAX UINT32_MAX ÆINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ÉINTMAX_MAX __ESCAPE__(9223372036854775807ll) ÌUINTMAX_MAX __ESCAPE__(18446744073709551615ull) ÕPTRDIFF_MIN INT32_MIN ÖPTRDIFF_MAX INT32_MAX ÚSIG_ATOMIC_MIN (~0x7fffffff) ÛSIG_ATOMIC_MAX 2147483647 áSIZE_MAX UINT32_MAX çWCHAR_MIN èWCHAR_MAX îWCHAR_MIN 0 ïWCHAR_MAX 65535 óWINT_MIN (~0x7fffffff) ôWINT_MAX 2147483647 ûINT8_C(x) (x) üINT16_C(x) (x) ýINT32_C(x) (x) þINT64_C(x) __INT64_C(x) UINT8_C(x) (x ## u) UINT16_C(x) (x ## u) UINT32_C(x) (x ## u) UINT64_C(x) __UINT64_C(x) INTMAX_C(x) __ESCAPE__(x ## ll) UINTMAX_C(x) __ESCAPE__(x ## ull) ²__INT64 ³__LONGLONG P D C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stdint.h C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] signed char short int long long unsigned char unsigned short unsigned int unsigned long long Pint8_t 8 Pint16_t 9 Pint32_t ¢ : Pint64_t © ; Puint8_t ¶ > Puint16_t Ç ? Puint32_t Ù @ Puint64_t é A Pint_least8_t G Pint_least16_t H Pint_least32_t ¢ I Pint_least64_t © J Puint_least8_t ¶ M Puint_least16_t Ç N Puint_least32_t Ù O Puint_least64_t é P Pint_fast8_t ¢ U Pint_fast16_t ¢ V Pint_fast32_t ¢ W Pint_fast64_t © X Puint_fast8_t Ù [ Puint_fast16_t Ù \ Puint_fast32_t Ù ] Puint_fast64_t é ^ Pintptr_t ¢ e Puintptr_t Ù f Pintmax_t © j!Puintmax_t é k! __CMSIS_VERSION_H #__CM_CMSIS_VERSION_MAIN ( 5U) $__CM_CMSIS_VERSION_SUB ( 3U) %__CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB ) L @ ../Drivers/CMSIS/Include/ cmsis_version.h ´
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../Drivers/CMSIS/Include/cmsis_version.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM __CMSIS_ARMCC_H ,__ARM_ARCH_7EM__ 1 4__ARM_FEATURE_DSP 1 9__ASM __asm <__INLINE __inline ?__STATIC_INLINE static __inline B__STATIC_FORCEINLINE static __forceinline E__NO_RETURN __declspec(noreturn) H__USED __attribute__((used)) K__WEAK __attribute__((weak)) N__PACKED __attribute__((packed)) Q__PACKED_STRUCT __packed struct T__PACKED_UNION __packed union W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) Z__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val)) ]__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) `__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val)) c__UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) f__ALIGNED(x) __attribute__((aligned(x))) i__RESTRICT __restrict l__COMPILER_BARRIER() __memory_changed() r__PROGRAM_START __main v__INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit z__STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base ~__VECTOR_TABLE __Vectors __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) ¦__enable_fault_irq __enable_fiq ®__disable_fault_irq __disable_fiq __NOP __nop §__WFI __wfi ¯__WFE __wfe ¶__SEV __sev ¿__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) Ê__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) Õ__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) â__REV __rev __ROR __ror __BKPT(value) __breakpoint(value) __RBIT __rbit ¹__CLZ __clz È__LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") Õ__LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") â__LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") ñ__STREXB(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") __STREXH(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") __STREXW(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") __CLREX __clrex ¡__SSAT __ssat «__USAT __usat Ä__LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) Í__LDRHT(ptr) ((uint16_t) __ldrt(ptr)) Ö__LDRT(ptr) ((uint32_t ) __ldrt(ptr)) ß__STRBT(value,ptr) __strt(value, ptr) è__STRHT(value,ptr) __strt(value, ptr) ñ__STRT(value,ptr) __strt(value, ptr) µ__SADD8 __sadd8 ¶__QADD8 __qadd8 ·__SHADD8 __shadd8 ¸__UADD8 __uadd8 ¹__UQADD8 __uqadd8 º__UHADD8 __uhadd8 »__SSUB8 __ssub8 ¼__QSUB8 __qsub8 ½__SHSUB8 __shsub8 ¾__USUB8 __usub8 ¿__UQSUB8 __uqsub8 À__UHSUB8 __uhsub8 Á__SADD16 __sadd16 Â__QADD16 __qadd16 Ã__SHADD16 __shadd16 Ä__UADD16 __uadd16 Å__UQADD16 __uqadd16 Æ__UHADD16 __uhadd16 Ç__SSUB16 __ssub16 È__QSUB16 __qsub16 É__SHSUB16 __shsub16 Ê__USUB16 __usub16 Ë__UQSUB16 __uqsub16 Ì__UHSUB16 __uhsub16 Í__SASX __sasx Î__QASX __qasx Ï__SHASX __shasx Ð__UASX __uasx Ñ__UQASX __uqasx Ò__UHASX __uhasx Ó__SSAX __ssax Ô__QSAX __qsax Õ__SHSAX __shsax Ö__USAX __usax ×__UQSAX __uqsax Ø__UHSAX __uhsax Ù__USAD8 __usad8 Ú__USADA8 __usada8 Û__SSAT16 __ssat16 Ü__USAT16 __usat16 Ý__UXTB16 __uxtb16 Þ__UXTAB16 __uxtab16 ß__SXTB16 __sxtb16 à__SXTAB16 __sxtab16 á__SMUAD __smuad â__SMUADX __smuadx ã__SMLAD __smlad ä__SMLADX __smladx å__SMLALD __smlald æ__SMLALDX __smlaldx ç__SMUSD __smusd è__SMUSDX __smusdx é__SMLSD __smlsd ê__SMLSDX __smlsdx ë__SMLSLD __smlsld ì__SMLSLDX __smlsldx í__SEL __sel î__QADD __qadd ï__QSUB __qsub ñ__PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) ô__PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) ÷__SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U)) H > ../Drivers/CMSIS/Include/ cmsis_armcc.h (
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../Drivers/CMSIS/Include/cmsis_armcc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ;ó__get_CONTROL Y a__result Y Y__regControl Y P <«__set_CONTROL $Y control Y__regControl Y P ;è·__get_IPSR Y a__result Y Y__regIPSR Y P ;£Ã__get_APSR Y a__result Y Y__regAPSR Y P ;ÞÏ__get_xPSR Y a__result Y Y__regXPSR Y P ;§Û__get_PSP Y a__result Y Y__regProcessStackPointer Y P <ðç__set_PSP $Y topOfProcStack Y__regProcessStackPointer Y P ;¶ó__get_MSP Y a__result Y Y__regMainStackPointer Y P <üÿ__set_MSP $Y topOfMainStack Y__regMainStackPointer Y P ;½__get_PRIMASK Y a__result Y Y__regPriMask Y P <÷__set_PRIMASK $Y priMask Y__regPriMask Y P ;¸¶__get_BASEPRI Y a__result Y Y__regBasePri Y P <òÂ__set_BASEPRI $Y basePri Y__regBasePri Y P <³Ï__set_BASEPRI_MAX $Y basePri Y__regBasePriMax Y P ;øÛ__get_FAULTMASK Y a__result Y Y__regFaultMask Y P <¸ ç__set_FAULTMASK $Y faultMask Y__regFaultMask Y P ;õ ö__get_FPSCR Y a__result Y Y__regfpscr Y P <©
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__set_FPSCR $Y fpscr Y__regfpscr Y P __CMSIS_COMPILER_H " ../Drivers/CMSIS/Include/ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ cmsis_compiler.h stdint.h cmsis_armcc.h ´
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../Drivers/CMSIS/Include/cmsis_compiler.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ¡ ARM_MPU_ARMV7_H "ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) #ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) $ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) %ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) &ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) 'ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) (ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) )ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) *ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ,ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) .ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) 0ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) 1ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) 2ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) 3ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) 4ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) 5ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) 6ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) 7ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) 8ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) 9ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) :ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ;ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) <ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) =ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ?ARM_MPU_AP_NONE 0U @ARM_MPU_AP_PRIV 1U AARM_MPU_AP_URO 2U BARM_MPU_AP_FULL 3U CARM_MPU_AP_PRO 5U DARM_MPU_AP_RO 6U KARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk)) XARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) gARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | (((MPU_RASR_ENABLE_Msk)))) {ARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) ¢ARM_MPU_CACHEP_NOCACHE 0U §ARM_MPU_CACHEP_WB_WRA 1U ¬ARM_MPU_CACHEP_WT_NWA 2U ±ARM_MPU_CACHEP_WB_NWA 3U H < ../Drivers/CMSIS/Include/ mpu_armv7.h \
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../Drivers/CMSIS/Include/mpu_armv7.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *Ñ RBAR Y # RASR Y # PARM_MPU_Region_t ° º<¿ARM_MPU_Enable $Y MPU_Control <ËARM_MPU_Disable <Ò×ARM_MPU_ClrRegion $Y rnr <áARM_MPU_SetRegion $Y rbar $Y rasr <ÀìARM_MPU_SetRegionEx $Y rnr $Y rbar $Y rasr <øARM_MPU_OrderedMemcpy $dst $src $Y len \i Y tY "Y " #<Õ
ARM_MPU_Load $Ytable $Y cnt srowWordSize Ñ "U £ ¤ ¥ ¦ __CORE_CM7_H_GENERIC "?B__CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) C__CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) D__CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB ) G__CORTEX_M (7U) O__FPU_USED 1U ¢®__CORE_CM7_H_DEPENDANT ê__I volatile const ì__O volatile í__IO volatile ð__IM volatile const ñ__OM volatile ò__IOM volatile £APSR_N_Pos 31U ¤APSR_N_Msk (1UL << APSR_N_Pos) ¦APSR_Z_Pos 30U §APSR_Z_Msk (1UL << APSR_Z_Pos) ©APSR_C_Pos 29U ªAPSR_C_Msk (1UL << APSR_C_Pos) ¬APSR_V_Pos 28U APSR_V_Msk (1UL << APSR_V_Pos) ¯APSR_Q_Pos 27U °APSR_Q_Msk (1UL << APSR_Q_Pos) ²APSR_GE_Pos 16U ³APSR_GE_Msk (0xFUL << APSR_GE_Pos) ÄIPSR_ISR_Pos 0U ÅIPSR_ISR_Msk (0x1FFUL ) àxPSR_N_Pos 31U áxPSR_N_Msk (1UL << xPSR_N_Pos) ãxPSR_Z_Pos 30U äxPSR_Z_Msk (1UL << xPSR_Z_Pos) æxPSR_C_Pos 29U çxPSR_C_Msk (1UL << xPSR_C_Pos) éxPSR_V_Pos 28U êxPSR_V_Msk (1UL << xPSR_V_Pos) ìxPSR_Q_Pos 27U íxPSR_Q_Msk (1UL << xPSR_Q_Pos) ïxPSR_ICI_IT_2_Pos 25U ðxPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) òxPSR_T_Pos 24U óxPSR_T_Msk (1UL << xPSR_T_Pos) õxPSR_GE_Pos 16U öxPSR_GE_Msk (0xFUL << xPSR_GE_Pos) øxPSR_ICI_IT_1_Pos 10U ùxPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) ûxPSR_ISR_Pos 0U üxPSR_ISR_Msk (0x1FFUL ) CONTROL_FPCA_Pos 2U CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) CONTROL_SPSEL_Pos 1U CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) CONTROL_nPRIV_Pos 0U CONTROL_nPRIV_Msk (1UL ) ·NVIC_STIR_INTID_Pos 0U ¸NVIC_STIR_INTID_Msk (0x1FFUL ) þSCB_CPUID_IMPLEMENTER_Pos 24U ÿSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) SCB_CPUID_VARIANT_Pos 20U SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) SCB_CPUID_ARCHITECTURE_Pos 16U
SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) SCB_CPUID_PARTNO_Pos 4U SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) SCB_CPUID_REVISION_Pos 0U SCB_CPUID_REVISION_Msk (0xFUL ) SCB_ICSR_NMIPENDSET_Pos 31U SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) SCB_ICSR_PENDSVSET_Pos 28U SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) SCB_ICSR_PENDSVCLR_Pos 27U SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) SCB_ICSR_PENDSTSET_Pos 26U SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) SCB_ICSR_PENDSTCLR_Pos 25U SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) SCB_ICSR_ISRPREEMPT_Pos 23U SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) SCB_ICSR_ISRPENDING_Pos 22U ¡SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) £SCB_ICSR_VECTPENDING_Pos 12U ¤SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) ¦SCB_ICSR_RETTOBASE_Pos 11U §SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) ©SCB_ICSR_VECTACTIVE_Pos 0U ªSCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) SCB_VTOR_TBLOFF_Pos 7U ®SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) ±SCB_AIRCR_VECTKEY_Pos 16U ²SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) ´SCB_AIRCR_VECTKEYSTAT_Pos 16U µSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) ·SCB_AIRCR_ENDIANESS_Pos 15U ¸SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) ºSCB_AIRCR_PRIGROUP_Pos 8U »SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) ½SCB_AIRCR_SYSRESETREQ_Pos 2U ¾SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) ÀSCB_AIRCR_VECTCLRACTIVE_Pos 1U ÁSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) ÃSCB_AIRCR_VECTRESET_Pos 0U ÄSCB_AIRCR_VECTRESET_Msk (1UL ) ÇSCB_SCR_SEVONPEND_Pos 4U ÈSCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) ÊSCB_SCR_SLEEPDEEP_Pos 2U ËSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) ÍSCB_SCR_SLEEPONEXIT_Pos 1U ÎSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) ÑSCB_CCR_BP_Pos 18U ÒSCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) ÔSCB_CCR_IC_Pos 17U ÕSCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) ×SCB_CCR_DC_Pos 16U ØSCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) ÚSCB_CCR_STKALIGN_Pos 9U ÛSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) ÝSCB_CCR_BFHFNMIGN_Pos 8U ÞSCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) àSCB_CCR_DIV_0_TRP_Pos 4U áSCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) ãSCB_CCR_UNALIGN_TRP_Pos 3U äSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) æSCB_CCR_USERSETMPEND_Pos 1U çSCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) éSCB_CCR_NONBASETHRDENA_Pos 0U êSCB_CCR_NONBASETHRDENA_Msk (1UL ) íSCB_SHCSR_USGFAULTENA_Pos 18U îSCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) ðSCB_SHCSR_BUSFAULTENA_Pos 17U ñSCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) óSCB_SHCSR_MEMFAULTENA_Pos 16U ôSCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) öSCB_SHCSR_SVCALLPENDED_Pos 15U ÷SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) ùSCB_SHCSR_BUSFAULTPENDED_Pos 14U úSCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) üSCB_SHCSR_MEMFAULTPENDED_Pos 13U ýSCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) ÿSCB_SHCSR_USGFAULTPENDED_Pos 12U SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) SCB_SHCSR_SYSTICKACT_Pos 11U SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
SCB_SHCSR_PENDSVACT_Pos 10U SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) SCB_SHCSR_MONITORACT_Pos 8U SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) SCB_SHCSR_SVCALLACT_Pos 7U SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) SCB_SHCSR_USGFAULTACT_Pos 3U SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) SCB_SHCSR_BUSFAULTACT_Pos 1U SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) SCB_SHCSR_MEMFAULTACT_Pos 0U SCB_SHCSR_MEMFAULTACT_Msk (1UL ) SCB_CFSR_USGFAULTSR_Pos 16U SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) SCB_CFSR_BUSFAULTSR_Pos 8U SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) SCB_CFSR_MEMFAULTSR_Pos 0U SCB_CFSR_MEMFAULTSR_Msk (0xFFUL ) ¢SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) £SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) ¥SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) ¦SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) ¨SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) ©SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) «SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) ¬SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) ®SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) ¯SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) ±SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) ²SCB_CFSR_IACCVIOL_Msk (1UL ) µSCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) ¶SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) ¸SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) ¹SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) »SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) ¼SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) ¾SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) ¿SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) ÁSCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) ÂSCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) ÄSCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) ÅSCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) ÇSCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) ÈSCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) ËSCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) ÌSCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) ÎSCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) ÏSCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) ÑSCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) ÒSCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) ÔSCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) ÕSCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) ×SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) ØSCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) ÚSCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) ÛSCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) ÞSCB_HFSR_DEBUGEVT_Pos 31U ßSCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) áSCB_HFSR_FORCED_Pos 30U âSCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) äSCB_HFSR_VECTTBL_Pos 1U åSCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) èSCB_DFSR_EXTERNAL_Pos 4U éSCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) ëSCB_DFSR_VCATCH_Pos 3U ìSCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) îSCB_DFSR_DWTTRAP_Pos 2U ïSCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) ñSCB_DFSR_BKPT_Pos 1U òSCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) ôSCB_DFSR_HALTED_Pos 0U õSCB_DFSR_HALTED_Msk (1UL ) øSCB_CLIDR_LOUU_Pos 27U ùSCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) ûSCB_CLIDR_LOC_Pos 24U üSCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) ÿSCB_CTR_FORMAT_Pos 29U SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) SCB_CTR_CWG_Pos 24U SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
SCB_CTR_ERG_Pos 20U SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) SCB_CTR_DMINLINE_Pos 16U SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) SCB_CTR_IMINLINE_Pos 0U SCB_CTR_IMINLINE_Msk (0xFUL ) SCB_CCSIDR_WT_Pos 31U SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) SCB_CCSIDR_WB_Pos 30U SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) SCB_CCSIDR_RA_Pos 29U SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) SCB_CCSIDR_WA_Pos 28U SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) SCB_CCSIDR_NUMSETS_Pos 13U SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) SCB_CCSIDR_ASSOCIATIVITY_Pos 3U SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) ¡SCB_CCSIDR_LINESIZE_Pos 0U ¢SCB_CCSIDR_LINESIZE_Msk (7UL ) ¥SCB_CSSELR_LEVEL_Pos 1U ¦SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) ¨SCB_CSSELR_IND_Pos 0U ©SCB_CSSELR_IND_Msk (1UL ) ¬SCB_STIR_INTID_Pos 0U SCB_STIR_INTID_Msk (0x1FFUL ) °SCB_DCISW_WAY_Pos 30U ±SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) ³SCB_DCISW_SET_Pos 5U ´SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) ·SCB_DCCSW_WAY_Pos 30U ¸SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) ºSCB_DCCSW_SET_Pos 5U »SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) ¾SCB_DCCISW_WAY_Pos 30U ¿SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) ÁSCB_DCCISW_SET_Pos 5U ÂSCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) ÅSCB_ITCMCR_SZ_Pos 3U ÆSCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) ÈSCB_ITCMCR_RETEN_Pos 2U ÉSCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) ËSCB_ITCMCR_RMW_Pos 1U ÌSCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) ÎSCB_ITCMCR_EN_Pos 0U ÏSCB_ITCMCR_EN_Msk (1UL ) ÒSCB_DTCMCR_SZ_Pos 3U ÓSCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) ÕSCB_DTCMCR_RETEN_Pos 2U ÖSCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) ØSCB_DTCMCR_RMW_Pos 1U ÙSCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) ÛSCB_DTCMCR_EN_Pos 0U ÜSCB_DTCMCR_EN_Msk (1UL ) ßSCB_AHBPCR_SZ_Pos 1U àSCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) âSCB_AHBPCR_EN_Pos 0U ãSCB_AHBPCR_EN_Msk (1UL ) æSCB_CACR_FORCEWT_Pos 2U çSCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) éSCB_CACR_ECCEN_Pos 1U êSCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) ìSCB_CACR_SIWT_Pos 0U íSCB_CACR_SIWT_Msk (1UL ) ðSCB_AHBSCR_INITCOUNT_Pos 11U ñSCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) óSCB_AHBSCR_TPRI_Pos 2U ôSCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) öSCB_AHBSCR_CTL_Pos 0U ÷SCB_AHBSCR_CTL_Msk (3UL ) úSCB_ABFSR_AXIMTYPE_Pos 8U ûSCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) ýSCB_ABFSR_EPPB_Pos 4U þSCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) SCB_ABFSR_AXIM_Pos 3U SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) SCB_ABFSR_AHBP_Pos 2U SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) SCB_ABFSR_DTCM_Pos 1U SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) SCB_ABFSR_ITCM_Pos 0U SCB_ABFSR_ITCM_Msk (1UL ) ¡SCnSCB_ICTR_INTLINESNUM_Pos 0U ¢SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL ) ¥SCnSCB_ACTLR_DISDYNADD_Pos 26U ¦SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) ¨SCnSCB_ACTLR_DISISSCH1_Pos 21U ©SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) «SCnSCB_ACTLR_DISDI_Pos 16U ¬SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) ®SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U ¯SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) ±SCnSCB_ACTLR_DISBTACALLOC_Pos 14U ²SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) ´SCnSCB_ACTLR_DISBTACREAD_Pos 13U µSCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) ·SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U ¸SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) ºSCnSCB_ACTLR_DISRAMODE_Pos 11U »SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) ½SCnSCB_ACTLR_FPEXCODIS_Pos 10U ¾SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) ÀSCnSCB_ACTLR_DISFOLD_Pos 2U ÁSCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) ÃSCnSCB_ACTLR_DISMCYCINT_Pos 0U ÄSCnSCB_ACTLR_DISMCYCINT_Msk (1UL ) ÜSysTick_CTRL_COUNTFLAG_Pos 16U ÝSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) ßSysTick_CTRL_CLKSOURCE_Pos 2U àSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) âSysTick_CTRL_TICKINT_Pos 1U ãSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) åSysTick_CTRL_ENABLE_Pos 0U æSysTick_CTRL_ENABLE_Msk (1UL ) éSysTick_LOAD_RELOAD_Pos 0U êSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) íSysTick_VAL_CURRENT_Pos 0U îSysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) ñSysTick_CALIB_NOREF_Pos 31U òSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) ôSysTick_CALIB_SKEW_Pos 30U õSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) ÷SysTick_CALIB_TENMS_Pos 0U øSysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) ©ITM_TPR_PRIVMASK_Pos 0U ªITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL ) ITM_TCR_BUSY_Pos 23U ®ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) °ITM_TCR_TraceBusID_Pos 16U ±ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) ³ITM_TCR_GTSFREQ_Pos 10U ´ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) ¶ITM_TCR_TSPrescale_Pos 8U ·ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) ¹ITM_TCR_SWOENA_Pos 4U ºITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) ¼ITM_TCR_DWTENA_Pos 3U ½ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) ¿ITM_TCR_SYNCENA_Pos 2U ÀITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) ÂITM_TCR_TSENA_Pos 1U ÃITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) ÅITM_TCR_ITMENA_Pos 0U ÆITM_TCR_ITMENA_Msk (1UL ) ÉITM_LSR_ByteAcc_Pos 2U ÊITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) ÌITM_LSR_Access_Pos 1U ÍITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) ÏITM_LSR_Present_Pos 0U ÐITM_LSR_Present_Msk (1UL ) þDWT_CTRL_NUMCOMP_Pos 28U ÿDWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) DWT_CTRL_NOTRCPKT_Pos 27U DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) DWT_CTRL_NOEXTTRIG_Pos 26U
DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) DWT_CTRL_NOCYCCNT_Pos 25U DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) DWT_CTRL_NOPRFCNT_Pos 24U DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) DWT_CTRL_CYCEVTENA_Pos 22U DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) DWT_CTRL_FOLDEVTENA_Pos 21U DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) DWT_CTRL_LSUEVTENA_Pos 20U DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) DWT_CTRL_SLEEPEVTENA_Pos 19U DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) DWT_CTRL_EXCEVTENA_Pos 18U DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) DWT_CTRL_CPIEVTENA_Pos 17U DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) DWT_CTRL_EXCTRCENA_Pos 16U DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) ¢ DWT_CTRL_PCSAMPLENA_Pos 12U £ DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) ¥ DWT_CTRL_SYNCTAP_Pos 10U ¦ DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) ¨ DWT_CTRL_CYCTAP_Pos 9U © DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) « DWT_CTRL_POSTINIT_Pos 5U ¬ DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) ® DWT_CTRL_POSTPRESET_Pos 1U ¯ DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) ± DWT_CTRL_CYCCNTENA_Pos 0U ² DWT_CTRL_CYCCNTENA_Msk (0x1UL ) µ DWT_CPICNT_CPICNT_Pos 0U ¶ DWT_CPICNT_CPICNT_Msk (0xFFUL ) ¹ DWT_EXCCNT_EXCCNT_Pos 0U º DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) ½ DWT_SLEEPCNT_SLEEPCNT_Pos 0U ¾ DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) Á DWT_LSUCNT_LSUCNT_Pos 0U Â DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) Å DWT_FOLDCNT_FOLDCNT_Pos 0U Æ DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) É DWT_MASK_MASK_Pos 0U Ê DWT_MASK_MASK_Msk (0x1FUL ) Í DWT_FUNCTION_MATCHED_Pos 24U Î DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) Ð DWT_FUNCTION_DATAVADDR1_Pos 16U Ñ DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) Ó DWT_FUNCTION_DATAVADDR0_Pos 12U Ô DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) Ö DWT_FUNCTION_DATAVSIZE_Pos 10U × DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) Ù DWT_FUNCTION_LNK1ENA_Pos 9U Ú DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) Ü DWT_FUNCTION_DATAVMATCH_Pos 8U Ý DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) ß DWT_FUNCTION_CYCMATCH_Pos 7U à DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) â DWT_FUNCTION_EMITRANGE_Pos 5U ã DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) å DWT_FUNCTION_FUNCTION_Pos 0U æ DWT_FUNCTION_FUNCTION_Msk (0xFUL )
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TPI_ACPR_PRESCALER_Pos 0U
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TPI_ACPR_PRESCALER_Msk (0x1FFFUL )
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TPI_SPPR_TXMODE_Pos 0U
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TPI_SPPR_TXMODE_Msk (0x3UL )
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TPI_FFSR_FtNonStop_Pos 3U
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TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
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TPI_FFSR_TCPresent_Pos 2U
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TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
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TPI_FFSR_FtStopped_Pos 1U ¡
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TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) £
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TPI_FFSR_FlInProg_Pos 0U ¤
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TPI_FFSR_FlInProg_Msk (0x1UL ) §
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TPI_FFCR_TrigIn_Pos 8U ¨
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TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) ª
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TPI_FFCR_EnFCont_Pos 1U «
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TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) ®
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TPI_TRIGGER_TRIGGER_Pos 0U ¯
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TPI_TRIGGER_TRIGGER_Msk (0x1UL ) ²
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TPI_FIFO0_ITM_ATVALID_Pos 29U ³
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TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) µ
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TPI_FIFO0_ITM_bytecount_Pos 27U ¶
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TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) ¸
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TPI_FIFO0_ETM_ATVALID_Pos 26U ¹
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TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) »
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TPI_FIFO0_ETM_bytecount_Pos 24U ¼
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TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) ¾
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TPI_FIFO0_ETM2_Pos 16U ¿
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TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) Á
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TPI_FIFO0_ETM1_Pos 8U Â
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TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) Ä
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TPI_FIFO0_ETM0_Pos 0U Å
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TPI_FIFO0_ETM0_Msk (0xFFUL ) È
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TPI_ITATBCTR2_ATREADY2_Pos 0U É
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TPI_ITATBCTR2_ATREADY2_Msk (0x1UL ) Ë
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TPI_ITATBCTR2_ATREADY1_Pos 0U Ì
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TPI_ITATBCTR2_ATREADY1_Msk (0x1UL ) Ï
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TPI_FIFO1_ITM_ATVALID_Pos 29U Ð
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TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) Ò
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TPI_FIFO1_ITM_bytecount_Pos 27U Ó
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TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) Õ
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TPI_FIFO1_ETM_ATVALID_Pos 26U Ö
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TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) Ø
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TPI_FIFO1_ETM_bytecount_Pos 24U Ù
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TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) Û
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TPI_FIFO1_ITM2_Pos 16U Ü
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TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) Þ
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TPI_FIFO1_ITM1_Pos 8U ß
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TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) á
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TPI_FIFO1_ITM0_Pos 0U â
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TPI_FIFO1_ITM0_Msk (0xFFUL ) å
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TPI_ITATBCTR0_ATREADY2_Pos 0U æ
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TPI_ITATBCTR0_ATREADY2_Msk (0x1UL ) è
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TPI_ITATBCTR0_ATREADY1_Pos 0U é
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TPI_ITATBCTR0_ATREADY1_Msk (0x1UL ) ì
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TPI_ITCTRL_Mode_Pos 0U í
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TPI_ITCTRL_Mode_Msk (0x3UL ) ð
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TPI_DEVID_NRZVALID_Pos 11U ñ
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TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) ó
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TPI_DEVID_MANCVALID_Pos 10U ô
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TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) ö
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TPI_DEVID_PTINVALID_Pos 9U ÷
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TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) ù
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TPI_DEVID_MinBufSz_Pos 6U ú
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TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) ü
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TPI_DEVID_AsynClkIn_Pos 5U ý
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TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) ÿ
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TPI_DEVID_NrTraceInput_Pos 0U TPI_DEVID_NrTraceInput_Msk (0x1FUL ) TPI_DEVTYPE_SubType_Pos 4U TPI_DEVTYPE_SubType_Msk (0xFUL ) TPI_DEVTYPE_MajorType_Pos 0U TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) ¦ MPU_TYPE_RALIASES 4U © MPU_TYPE_IREGION_Pos 16U ª MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) ¬ MPU_TYPE_DREGION_Pos 8U MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) ¯ MPU_TYPE_SEPARATE_Pos 0U ° MPU_TYPE_SEPARATE_Msk (1UL ) ³ MPU_CTRL_PRIVDEFENA_Pos 2U ´ MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) ¶ MPU_CTRL_HFNMIENA_Pos 1U · MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) ¹ MPU_CTRL_ENABLE_Pos 0U º MPU_CTRL_ENABLE_Msk (1UL ) ½ MPU_RNR_REGION_Pos 0U ¾ MPU_RNR_REGION_Msk (0xFFUL ) Á MPU_RBAR_ADDR_Pos 5U Â MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) Ä MPU_RBAR_VALID_Pos 4U Å MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) Ç MPU_RBAR_REGION_Pos 0U È MPU_RBAR_REGION_Msk (0xFUL ) Ë MPU_RASR_ATTRS_Pos 16U Ì MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) Î MPU_RASR_XN_Pos 28U Ï MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) Ñ MPU_RASR_AP_Pos 24U Ò MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) Ô MPU_RASR_TEX_Pos 19U Õ MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) × MPU_RASR_S_Pos 18U Ø MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) Ú MPU_RASR_C_Pos 17U Û MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) Ý MPU_RASR_B_Pos 16U Þ MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) à MPU_RASR_SRD_Pos 8U á MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) ã MPU_RASR_SIZE_Pos 1U ä MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) æ MPU_RASR_ENABLE_Pos 0U ç MPU_RASR_ENABLE_Msk (1UL ) FPU_FPCCR_ASPEN_Pos 31U FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) FPU_FPCCR_LSPEN_Pos 30U FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) FPU_FPCCR_MONRDY_Pos 8U FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) FPU_FPCCR_BFRDY_Pos 6U FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) FPU_FPCCR_MMRDY_Pos 5U FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) FPU_FPCCR_HFRDY_Pos 4U FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) FPU_FPCCR_THREAD_Pos 3U FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) FPU_FPCCR_USER_Pos 1U FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) FPU_FPCCR_LSPACT_Pos 0U FPU_FPCCR_LSPACT_Msk (1UL ) FPU_FPCAR_ADDRESS_Pos 3U FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) £ FPU_FPDSCR_AHP_Pos 26U ¤ FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) ¦ FPU_FPDSCR_DN_Pos 25U § FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) © FPU_FPDSCR_FZ_Pos 24U ª FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) ¬ FPU_FPDSCR_RMode_Pos 22U FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) ° FPU_MVFR0_FP_rounding_modes_Pos 28U ± FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) ³ FPU_MVFR0_Short_vectors_Pos 24U ´ FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) ¶ FPU_MVFR0_Square_root_Pos 20U · FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) ¹ FPU_MVFR0_Divide_Pos 16U º FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) ¼ FPU_MVFR0_FP_excep_trapping_Pos 12U ½ FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) ¿ FPU_MVFR0_Double_precision_Pos 8U À FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) Â FPU_MVFR0_Single_precision_Pos 4U Ã FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) Å FPU_MVFR0_A_SIMD_registers_Pos 0U Æ FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) É FPU_MVFR1_FP_fused_MAC_Pos 28U Ê FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) Ì FPU_MVFR1_FP_HPFP_Pos 24U Í FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) Ï FPU_MVFR1_D_NaN_mode_Pos 4U Ð FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) Ò FPU_MVFR1_FtZ_mode_Pos 0U Ó FPU_MVFR1_FtZ_mode_Msk (0xFUL ) × FPU_MVFR2_VFP_Misc_Pos 4U Ø FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) ð CoreDebug_DHCSR_DBGKEY_Pos 16U ñ CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) ó CoreDebug_DHCSR_S_RESET_ST_Pos 25U ô CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) ö CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U ÷ CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) ù CoreDebug_DHCSR_S_LOCKUP_Pos 19U ú CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) ü CoreDebug_DHCSR_S_SLEEP_Pos 18U ý CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) ÿ CoreDebug_DHCSR_S_HALT_Pos 17U CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) CoreDebug_DHCSR_S_REGRDY_Pos 16U CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) CoreDebug_DHCSR_C_MASKINTS_Pos 3U CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) CoreDebug_DHCSR_C_STEP_Pos 2U CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) CoreDebug_DHCSR_C_HALT_Pos 1U CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) CoreDebug_DHCSR_C_DEBUGEN_Pos 0U CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) CoreDebug_DCRSR_REGWnR_Pos 16U CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) CoreDebug_DCRSR_REGSEL_Pos 0U CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) CoreDebug_DEMCR_TRCENA_Pos 24U CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) CoreDebug_DEMCR_MON_REQ_Pos 19U CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) ¢ CoreDebug_DEMCR_MON_STEP_Pos 18U £ CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) ¥ CoreDebug_DEMCR_MON_PEND_Pos 17U ¦ CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) ¨ CoreDebug_DEMCR_MON_EN_Pos 16U © CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) « CoreDebug_DEMCR_VC_HARDERR_Pos 10U ¬ CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) ® CoreDebug_DEMCR_VC_INTERR_Pos 9U ¯ CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) ± CoreDebug_DEMCR_VC_BUSERR_Pos 8U ² CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) ´ CoreDebug_DEMCR_VC_STATERR_Pos 7U µ CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) · CoreDebug_DEMCR_VC_CHKERR_Pos 6U ¸ CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) º CoreDebug_DEMCR_VC_NOCPERR_Pos 5U » CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) ½ CoreDebug_DEMCR_VC_MMERR_Pos 4U ¾ CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) À CoreDebug_DEMCR_VC_CORERESET_Pos 0U Á CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) Ó _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) Û _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) è SCS_BASE (0xE000E000UL) é ITM_BASE (0xE0000000UL) ê DWT_BASE (0xE0001000UL) ë TPI_BASE (0xE0040000UL) ì CoreDebug_BASE (0xE000EDF0UL) í SysTick_BASE (SCS_BASE + 0x0010UL) î NVIC_BASE (SCS_BASE + 0x0100UL) ï SCB_BASE (SCS_BASE + 0x0D00UL) ñ SCnSCB ((SCnSCB_Type *) SCS_BASE ) ò SCB ((SCB_Type *) SCB_BASE ) ó SysTick ((SysTick_Type *) SysTick_BASE ) ô NVIC ((NVIC_Type *) NVIC_BASE ) õ ITM ((ITM_Type *) ITM_BASE ) ö DWT ((DWT_Type *) DWT_BASE ) ÷ TPI ((TPI_Type *) TPI_BASE ) ø CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) û MPU_BASE (SCS_BASE + 0x0D90UL) ü MPU ((MPU_Type *) MPU_BASE ) ÿ FPU_BASE (SCS_BASE + 0x0F30UL) FPU ((FPU_Type *) FPU_BASE ) ¢NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping £NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping ¤NVIC_EnableIRQ __NVIC_EnableIRQ ¥NVIC_GetEnableIRQ __NVIC_GetEnableIRQ ¦NVIC_DisableIRQ __NVIC_DisableIRQ §NVIC_GetPendingIRQ __NVIC_GetPendingIRQ ¨NVIC_SetPendingIRQ __NVIC_SetPendingIRQ ©NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ ªNVIC_GetActive __NVIC_GetActive «NVIC_SetPriority __NVIC_SetPriority ¬NVIC_GetPriority __NVIC_GetPriority NVIC_SystemReset __NVIC_SystemReset ¶NVIC_SetVector __NVIC_SetVector ·NVIC_GetVector __NVIC_GetVector ºNVIC_USER_IRQ_OFFSET 16 ¾EXC_RETURN_HANDLER (0xFFFFFFF1UL) ¿EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) ÀEXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) ÁEXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) ÂEXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) ÃEXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) ·CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) ¸CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) º__SCB_DCACHE_LINE_SIZE 32U »__SCB_ICACHE_LINE_SIZE 32U ÙITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) ¬ ¢ ../Drivers/CMSIS/Include/ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ core_cm7.h stdint.h cmsis_version.h cmsis_compiler.h mpu_armv7.h ô
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../Drivers/CMSIS/Include/core_cm7.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM uvoid "¯ <öSCB_EnableDCache \ccsidr Y \sets Y \ways Y <´½SCB_DisableDCache \ccsidr Y \sets Y \ways Y <õãSCB_InvalidateDCache \ccsidr Y \sets Y \ways Y <±SCB_CleanDCache \ccsidr Y \sets Y \ways Y <÷©SCB_CleanInvalidateDCache \ccsidr Y \sets Y \ways Y <ÒÐSCB_InvalidateDCache_by_Addr $µ addr $ dsize Ñ\op_size \op_addr Y <¨îSCB_CleanDCache_by_Addr $_addr $ dsize §\op_size \op_addr Y <SCB_CleanInvalidateDCache_by_Addr $_addr $ dsize \op_size \op_addr Y ;ÁºSysTick_Config Y $Y ticks a__result Y ;õäITM_SendChar Y $Y ch a__result Y ;¬ùITM_ReceiveChar a__result \ch ;ØITM_CheckChar a__result *à!_reserved0 Y # !GE Y # !_reserved1 Y # !Q Y # !V Y # !C Y # !Z Y # !N Y # Só b Ø w Y PAPSR_Type ` *± !ISR Y # !_reserved0 Y # SÄ b
w Y PIPSR_Type ±Á*¦ !ISR Y # !_reserved0 Y # !ICI_IT_1 Y # !GE Y # !_reserved1 Y # !T Y # !ICI_IT_2 Y # !Q Y # !V Y # !C Y # !Z Y # !N Y # S¹ b Ö w Y PxPSR_Type ¦Ý* !nPRIV Y # !SPSEL Y # !FPCA Y # !_reserved0 Y # S¯ b Ë w Y PCONTROL_Type * Ò ISER I# é Y RESERVED0 ^# ICER z# Y RESERVED1 # ¶ ISPR #Î Y RESERVED2 Ã# é ICPR à#Y RESERVED3 ö# IABR #´Y 7 RESERVED4 )# Ðï IP F#çY RESERVED5 [#ð STIR # tY t: PNVIC_Type D´*è¬ CPUID î
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# ICSR # VTOR # AIRCR # SCR # CCR #û SHPR ò# SHCSR #$ CFSR #( HFSR #, DFSR #0 MMFAR #4 BFAR #8 AFSR #<æî
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ID_PFR ]#@ ID_DFR î
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#H ID_AFR î
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#Lî
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ID_MFR #P°î
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ID_ISAR §#`ÊY RESERVED0 ¿#t CLIDR î
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#x CTR î
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#| CCSIDR î
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# CSSELR # CPACR #ªY \ RESERVED3 # STIR #ÔY RESERVED4 I # MVFR0 î
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#À MVFR1 î
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#Ä MVFR2 î
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#ÈY RESERVED5 #Ì ICIALLU #ÐÈY RESERVED6 ½ #Ô ICIMVAU #Ø DCIMVAC #Ü DCISW #à DCCMVAU #ä DCCMVAC #è DCCSW #ì DCCIMVAC #ð DCCISW #ôáY RESERVED7 V
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#ø ITCMCR # DTCMCR # AHBPCR # CACR # AHBSCR # ÇY RESERVED8 ¼
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#¤ ABFSR #¨ Y tè
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PSCB_Type ¥û*½ Y RESERVED0 # ICTR î
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# ACTLR # PSCnSCB_Type * CTRL # LOAD # VAL # CALIB î
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# PSysTick_Type Q ÙS· u8 u16 · u32 tI *ß Ë_ PORT Â # ãY ß RESERVED0 × # TER # Y RESERVED1 # TPR #À µY RESERVED2 * #Ä TCR # ÞY RESERVED3 S # ûY * RESERVED4 p # LAR #° LSR î
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#´ °Y RESERVED5 ¥ #¸ PID4 î
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#Ð PID5 î
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#Ô PID6 î
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#Ø PID7 î
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#Ü PID0 î
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#à PID1 î
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#ä PID2 î
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#è PID3 î
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#ì CID0 î
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#ð CID1 î
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#ô CID2 î
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#ø CID3 î
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#ü t PITM_Type ½ ¦* ¸ CTRL # CYCCNT # CPICNT # EXCCNT # SLEEPCNT # LSUCNT # FOLDCNT # PCSR î
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# COMP0 # MASK0 #$ FUNCTION0 #( Y RESERVED0 #, COMP1 #0 MASK1 #4 FUNCTION1 #8å Y RESERVED1 Z#< COMP2 #@ MASK2 #D FUNCTION2 #H¬ Y RESERVED2 ¡#L COMP3 #P MASK3 #T FUNCTION3 #Xô Y Ô RESERVED3 è#\ LAR #° LSR î
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#´ PDWT_Type t û*ù!Ð SSPSR î
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# CSPSR #Ù Y RESERVED0 N# ACPR # Y 6 RESERVED1 v# SPPR #ð« Y RESERVED2 #ô FFSR î
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# FFCR # FSCR î
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#ð Y ö RESERVED3 ä# TRIGGER î
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#è FIFO0 î
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#ì ITATBCTR2 î
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#ð ½ Y RESERVED4 2#ô ITATBCTR0 î
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#ø FIFO1 î
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#ü ITCTRL # !Y & RESERVED5 ~# CLAIMSET # CLAIMCLR #¤ È!Y RESERVED7 ½#¨ DEVID î
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#È DEVTYPE î
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#Ì PTPI_Type /
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*¤#, TYPE î
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# CTRL # RNR # RBAR # RASR # RBAR_A1 # RASR_A1 # RBAR_A2 # RASR_A2 # RBAR_A3 #$ RASR_A3 #( PMPU_Type
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¤ *¥$ Ä#Y RESERVED0 ¹# FPCCR # FPCAR # FPDSCR # MVFR0 î
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# MVFR1 î
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# MVFR2 î
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# PFPU_Type µ *ï$ DHCSR # DCRSR # DCRDR # DEMCR # PCoreDebug_Type 6í t qITM_RxBuffer <þ%Ï__NVIC_SetPriorityGrouping $Y PriorityGroup \reg_value Y \PriorityGroupTmp Y ;·&â__NVIC_GetPriorityGrouping Y a__result Y <Ü&î__NVIC_EnableIRQ $\
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IRQn ;'__NVIC_GetEnableIRQ Y $\
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IRQn a__result Y <¿'__NVIC_DisableIRQ $\
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IRQn ;ý'§__NVIC_GetPendingIRQ Y $\
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IRQn a__result Y <¦(º__NVIC_SetPendingIRQ $\
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IRQn <Ñ(É__NVIC_ClearPendingIRQ $\
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IRQn ;)Ú__NVIC_GetActive Y $\
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IRQn a__result Y <Á)ð__NVIC_SetPriority $\
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IRQn $Y priority ;ý)__NVIC_GetPriority Y $\
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IRQn a__result Y ;²+NVIC_EncodePriority Y $Y PriorityGroup $Y PreemptPriority $Y SubPriority a__result Y \PriorityGroupTmp Y \PreemptPriorityBits Y \SubPriorityBits Y <ß,ºNVIC_DecodePriority $Y Priority $Y PriorityGroup $epPreemptPriority $epSubPriority \PriorityGroupTmp Y \PreemptPriorityBits Y \SubPriorityBits Y "Y _<©-Ñ__NVIC_SetVector $\
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IRQn $Y vector \vectors Y ;ñ-á__NVIC_GetVector Y $\
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IRQn a__result Y \vectors Y <.ì"__NVIC_SystemReset ;Æ.SCB_GetFPUType Y a__result Y \mvfr0 Y <à.ÁSCB_EnableICache <û.ÖSCB_DisableICache </çSCB_InvalidateICache <ô/ûSCB_InvalidateICache_by_Addr $µ addr $ isize ó/\op_size \op_addr Y ø ITM_RxBuffer ¨ © ª « SYSTEM_STM32H7XX_H ` W ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/ system_stm32h7xx.h
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../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM qSystemCoreClock Y qSystemD2Clock Y : ù qD1CorePrescTable ÿ I $ Ë SystemCoreClock ã SystemD2Clock D1CorePrescTable ® ¯ "STM32H743xx_H Ø__CM7_REV 0x0101U Ù__MPU_PRESENT 1U Ú__NVIC_PRIO_BITS 4U Û__Vendor_SysTickConfig 0U Ü__FPU_PRESENT 1U Ý__ICACHE_PRESENT 1U Þ__DCACHE_PRESENT 1U ßçèD1_ITCMRAM_BASE (0x00000000UL) D1_ITCMICP_BASE (0x00100000UL) D1_DTCMRAM_BASE (0x20000000UL) D1_AXIFLASH_BASE (0x08000000UL) D1_AXIICP_BASE (0x1FF00000UL) D1_AXISRAM_BASE (0x24000000UL) D2_AXISRAM_BASE (0x10000000UL) D2_AHBSRAM_BASE (0x30000000UL) D3_BKPSRAM_BASE (0x38800000UL) D3_SRAM_BASE (0x38000000UL) PERIPH_BASE (0x40000000UL) QSPI_BASE (0x90000000UL) FLASH_BANK1_BASE (0x08000000UL) FLASH_BANK2_BASE (0x08100000UL) FLASH_END (0x081FFFFFUL) ¡FLASH_BASE FLASH_BANK1_BASE ¤UID_BASE (0x1FF1E800UL) ¥FLASHSIZE_BASE (0x1FF1E880UL) ©D2_APB1PERIPH_BASE PERIPH_BASE ªD2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) «D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) ¬D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) ®D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) ¯D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) ±D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) ²D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) µAPB1PERIPH_BASE PERIPH_BASE ¶APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) ·AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) ¸AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) ½MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) ¾DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) ¿JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL) ÀFLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) ÁFMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) ÂQSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) ÃDLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) ÄSDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) ÅDLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) ÆRAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) ÊDMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) ËDMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) ÌDMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) ÍADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) ÎADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) ÏADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) ÐETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) ÑETH_MAC_BASE (ETH_BASE) ÔUSB1_OTG_HS_PERIPH_BASE (0x40040000UL) ÕUSB2_OTG_FS_PERIPH_BASE (0x40080000UL) ÖUSB_OTG_GLOBAL_BASE (0x000UL) ×USB_OTG_DEVICE_BASE (0x800UL) ØUSB_OTG_IN_ENDPOINT_BASE (0x900UL) ÙUSB_OTG_OUT_ENDPOINT_BASE (0xB00UL) ÚUSB_OTG_EP_REG_SIZE (0x20UL) ÛUSB_OTG_HOST_BASE (0x400UL) ÜUSB_OTG_HOST_PORT_BASE (0x440UL) ÝUSB_OTG_HOST_CHANNEL_BASE (0x500UL) ÞUSB_OTG_HOST_CHANNEL_SIZE (0x20UL) ßUSB_OTG_PCGCCTL_BASE (0xE00UL) àUSB_OTG_FIFO_BASE (0x1000UL) áUSB_OTG_FIFO_SIZE (0x1000UL) åDCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) æRNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) çSDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) èDLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) éRAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) ìGPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) íGPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) îGPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) ïGPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) ðGPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) ñGPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) òGPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) óGPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) ôGPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) õGPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) öGPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) ÷RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) øPWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) ùCRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) úBDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) ûDMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) üADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) ýADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) þHSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) ÿRAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) ¡UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) ¢CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) £SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) ¤OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) ¥OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) ¦OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) §MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) ¨FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) ©FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) ªFDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) «SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) ¯TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) °TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) ±USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) ²USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) ³SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) ´SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) µTIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) ¶TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) ·TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) ¸SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) ¹SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) ºSAI1_Block_A_BASE (SAI1_BASE + 0x004UL) »SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) ¼SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) ½SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) ¾SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) ¿SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) ÀSAI3_Block_A_BASE (SAI3_BASE + 0x004UL) ÁSAI3_Block_B_BASE (SAI3_BASE + 0x024UL) ÂDFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) ÃDFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) ÄDFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) ÅDFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) ÆDFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) ÇDFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) ÈDFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) ÉDFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) ÊDFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) ËDFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) ÌDFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) ÍDFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) ÎDFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) ÏHRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) ÐHRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) ÑHRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) ÒHRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) ÓHRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) ÔHRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) ÕHRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) ÙEXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) ÚEXTI_D1_BASE (EXTI_BASE + 0x0080UL) ÛEXTI_D2_BASE (EXTI_BASE + 0x00C0UL) ÜSYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) ÝLPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) ÞSPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) ßI2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) àLPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) áLPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) âLPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) ãLPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) äCOMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) åCOMP1_BASE (COMP12_BASE + 0x0CUL) æCOMP2_BASE (COMP12_BASE + 0x10UL) çVREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) èRTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) éIWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) ìSAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) íSAI4_Block_A_BASE (SAI4_BASE + 0x004UL) îSAI4_Block_B_BASE (SAI4_BASE + 0x024UL) óBDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) ôBDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) õBDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) öBDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) ÷BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) øBDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) ùBDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) úBDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) üDMAMUX2_Channel0_BASE (DMAMUX2_BASE) ýDMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) þDMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) ÿDMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) ¡DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) £DMAMUX1_Channel0_BASE (DMAMUX1_BASE) ¤DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) ¥DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) ¦DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) §DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) ¨DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) ©DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) ªDMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) «DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) ¬DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) ®DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) ¯DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) °DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) ±DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) ²DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) ´DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) µDMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) ¶DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) ·DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) ¸DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) ¹DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) ºDMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) »DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) ½DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) ¾DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) ÁFMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) ÂFMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) ÃFMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) ÄFMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) ÅFMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) ÈDBGMCU_BASE (0x5C001000UL) ÊMDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) ËMDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) ÌMDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) ÍMDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) ÎMDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) ÏMDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) ÐMDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) ÑMDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) ÒMDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) ÓMDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) ÔMDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) ÕMDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) ÖMDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) ×MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) ØMDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) ÙMDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) ÛRAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) ÜRAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) ÝRAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) ÞRAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) ßRAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) áRAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) âRAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) ãRAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) äRAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) åRAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) çRAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) èRAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) ìGPV_BASE (PERIPH_BASE + 0x11000000UL) õTIM2 ((TIM_TypeDef *) TIM2_BASE) öTIM3 ((TIM_TypeDef *) TIM3_BASE) ÷TIM4 ((TIM_TypeDef *) TIM4_BASE) øTIM5 ((TIM_TypeDef *) TIM5_BASE) ùTIM6 ((TIM_TypeDef *) TIM6_BASE) úTIM7 ((TIM_TypeDef *) TIM7_BASE) ûTIM13 ((TIM_TypeDef *) TIM13_BASE) üTIM14 ((TIM_TypeDef *) TIM14_BASE) ýVREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) þRTC ((RTC_TypeDef *) RTC_BASE) ÿWWDG1 ((WWDG_TypeDef *) WWDG1_BASE) IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) SPI2 ((SPI_TypeDef *) SPI2_BASE) SPI3 ((SPI_TypeDef *) SPI3_BASE)
SPI4 ((SPI_TypeDef *) SPI4_BASE) SPI5 ((SPI_TypeDef *) SPI5_BASE) SPI6 ((SPI_TypeDef *) SPI6_BASE) USART2 ((USART_TypeDef *) USART2_BASE) USART3 ((USART_TypeDef *) USART3_BASE) USART6 ((USART_TypeDef *) USART6_BASE) UART7 ((USART_TypeDef *) UART7_BASE) UART8 ((USART_TypeDef *) UART8_BASE) CRS ((CRS_TypeDef *) CRS_BASE) UART4 ((USART_TypeDef *) UART4_BASE) UART5 ((USART_TypeDef *) UART5_BASE) I2C1 ((I2C_TypeDef *) I2C1_BASE) I2C2 ((I2C_TypeDef *) I2C2_BASE) I2C3 ((I2C_TypeDef *) I2C3_BASE) I2C4 ((I2C_TypeDef *) I2C4_BASE) FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) CEC ((CEC_TypeDef *) CEC_BASE) LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) PWR ((PWR_TypeDef *) PWR_BASE) DAC1 ((DAC_TypeDef *) DAC1_BASE) LPUART1 ((USART_TypeDef *) LPUART1_BASE) SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) ¢SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) £COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) ¤COMP1 ((COMP_TypeDef *) COMP1_BASE) ¥COMP2 ((COMP_TypeDef *) COMP2_BASE) ¦COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) §OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) ¨OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) ©OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) ¬EXTI ((EXTI_TypeDef *) EXTI_BASE) EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) ®EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) ¯TIM1 ((TIM_TypeDef *) TIM1_BASE) °SPI1 ((SPI_TypeDef *) SPI1_BASE) ±TIM8 ((TIM_TypeDef *) TIM8_BASE) ²USART1 ((USART_TypeDef *) USART1_BASE) ³TIM12 ((TIM_TypeDef *) TIM12_BASE) ´TIM15 ((TIM_TypeDef *) TIM15_BASE) µTIM16 ((TIM_TypeDef *) TIM16_BASE) ¶TIM17 ((TIM_TypeDef *) TIM17_BASE) ·HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) ¸HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) ¹HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) ºHRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) »HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) ¼HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) ½HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) ¾SAI1 ((SAI_TypeDef *) SAI1_BASE) ¿SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) ÀSAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) ÁSAI2 ((SAI_TypeDef *) SAI2_BASE) ÂSAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) ÃSAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) ÄSAI3 ((SAI_TypeDef *) SAI3_BASE) ÅSAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) ÆSAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) ÇSAI4 ((SAI_TypeDef *) SAI4_BASE) ÈSAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) ÉSAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) ËSPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) ÌDFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) ÍDFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) ÎDFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) ÏDFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) ÐDFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) ÑDFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) ÒDFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) ÓDFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) ÔDFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) ÕDFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) ÖDFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) ×DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) ØDMA2D ((DMA2D_TypeDef *) DMA2D_BASE) ÙDCMI ((DCMI_TypeDef *) DCMI_BASE) ÚRCC ((RCC_TypeDef *) RCC_BASE) ÛFLASH ((FLASH_TypeDef *) FLASH_R_BASE) ÜCRC ((CRC_TypeDef *) CRC_BASE) ÞGPIOA ((GPIO_TypeDef *) GPIOA_BASE) ßGPIOB ((GPIO_TypeDef *) GPIOB_BASE) àGPIOC ((GPIO_TypeDef *) GPIOC_BASE) áGPIOD ((GPIO_TypeDef *) GPIOD_BASE) âGPIOE ((GPIO_TypeDef *) GPIOE_BASE) ãGPIOF ((GPIO_TypeDef *) GPIOF_BASE) äGPIOG ((GPIO_TypeDef *) GPIOG_BASE) åGPIOH ((GPIO_TypeDef *) GPIOH_BASE) æGPIOI ((GPIO_TypeDef *) GPIOI_BASE) çGPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) èGPIOK ((GPIO_TypeDef *) GPIOK_BASE) êADC1 ((ADC_TypeDef *) ADC1_BASE) ëADC2 ((ADC_TypeDef *) ADC2_BASE) ìADC3 ((ADC_TypeDef *) ADC3_BASE) íADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) îADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) ðRNG ((RNG_TypeDef *) RNG_BASE) ñSDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) òDLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) ôBDMA ((BDMA_TypeDef *) BDMA_BASE) õBDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) öBDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) ÷BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) øBDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) ùBDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) úBDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) ûBDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) üBDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) þRAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) ÿRAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) ¡DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) ¢DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) ¤DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) ¥DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) §DMA2 ((DMA_TypeDef *) DMA2_BASE) ¨DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) ©DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) ªDMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) «DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) ¬DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) ®DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) ¯DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) ±DMA1 ((DMA_TypeDef *) DMA1_BASE) ²DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) ³DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) ´DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) µDMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) ¶DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) ·DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) ¸DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) ¹DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) ¼DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) ½DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) ¾DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) ¿DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) ÀDMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) ÁDMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) ÂDMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) ÃDMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) ÄDMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) ÅDMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) ÆDMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) ÇDMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) ÈDMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) ÉDMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) ÊDMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) ËDMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) ÌDMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) ÎDMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) ÏDMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) ÐDMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) ÑDMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) ÒDMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) ÓDMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) ÔDMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) ÕDMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) ×DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) ØDMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) ÛFMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) ÜFMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) ÝFMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) ÞFMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) ßFMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) âQUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) ãDLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) äSDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) åDLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) çDBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) éJPEG ((JPEG_TypeDef *) JPGDEC_BASE) êHSEM ((HSEM_TypeDef *) HSEM_BASE) ëHSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) íLTDC ((LTDC_TypeDef *)LTDC_BASE) îLTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) ïLTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) ñMDIOS ((MDIOS_TypeDef *) MDIOS_BASE) óETH ((ETH_TypeDef *)ETH_BASE) ôMDMA ((MDMA_TypeDef *)MDMA_BASE) õMDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) öMDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) ÷MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) øMDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) ùMDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) úMDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) ûMDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) üMDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) ýMDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) þMDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) ÿMDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) USB_OTG_HS USB1_OTG_HS USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE USB_OTG_FS USB2_OTG_FS USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE GPV ((GPV_TypeDef *) GPV_BASE) LSI_STARTUP_TIME 130U ±ADC_VER_V5_X ³ADC_ISR_ADRDY_Pos (0U) ´ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) µADC_ISR_ADRDY ADC_ISR_ADRDY_Msk ¶ADC_ISR_EOSMP_Pos (1U) ·ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) ¸ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk ¹ADC_ISR_EOC_Pos (2U) ºADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) »ADC_ISR_EOC ADC_ISR_EOC_Msk ¼ADC_ISR_EOS_Pos (3U) ½ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) ¾ADC_ISR_EOS ADC_ISR_EOS_Msk ¿ADC_ISR_OVR_Pos (4U) ÀADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) ÁADC_ISR_OVR ADC_ISR_OVR_Msk ÂADC_ISR_JEOC_Pos (5U) ÃADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) ÄADC_ISR_JEOC ADC_ISR_JEOC_Msk ÅADC_ISR_JEOS_Pos (6U) ÆADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) ÇADC_ISR_JEOS ADC_ISR_JEOS_Msk ÈADC_ISR_AWD1_Pos (7U) ÉADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) ÊADC_ISR_AWD1 ADC_ISR_AWD1_Msk ËADC_ISR_AWD2_Pos (8U) ÌADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) ÍADC_ISR_AWD2 ADC_ISR_AWD2_Msk ÎADC_ISR_AWD3_Pos (9U) ÏADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) ÐADC_ISR_AWD3 ADC_ISR_AWD3_Msk ÑADC_ISR_JQOVF_Pos (10U) ÒADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) ÓADC_ISR_JQOVF ADC_ISR_JQOVF_Msk ÔADC_ISR_LDORDY_Pos (12U) ÕADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) ÖADC_ISR_LDORDY ADC_ISR_LDORDY_Msk ÙADC_IER_ADRDYIE_Pos (0U) ÚADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) ÛADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk ÜADC_IER_EOSMPIE_Pos (1U) ÝADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) ÞADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk ßADC_IER_EOCIE_Pos (2U) àADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) áADC_IER_EOCIE ADC_IER_EOCIE_Msk âADC_IER_EOSIE_Pos (3U) ãADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) äADC_IER_EOSIE ADC_IER_EOSIE_Msk åADC_IER_OVRIE_Pos (4U) æADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) çADC_IER_OVRIE ADC_IER_OVRIE_Msk èADC_IER_JEOCIE_Pos (5U) éADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) êADC_IER_JEOCIE ADC_IER_JEOCIE_Msk ëADC_IER_JEOSIE_Pos (6U) ìADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) íADC_IER_JEOSIE ADC_IER_JEOSIE_Msk îADC_IER_AWD1IE_Pos (7U) ïADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) ðADC_IER_AWD1IE ADC_IER_AWD1IE_Msk ñADC_IER_AWD2IE_Pos (8U) òADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) óADC_IER_AWD2IE ADC_IER_AWD2IE_Msk ôADC_IER_AWD3IE_Pos (9U) õADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) öADC_IER_AWD3IE ADC_IER_AWD3IE_Msk ÷ADC_IER_JQOVFIE_Pos (10U) øADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) ùADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk üADC_CR_ADEN_Pos (0U) ýADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) þADC_CR_ADEN ADC_CR_ADEN_Msk ÿADC_CR_ADDIS_Pos (1U) ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) ADC_CR_ADDIS ADC_CR_ADDIS_Msk ADC_CR_ADSTART_Pos (2U) ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) ADC_CR_ADSTART ADC_CR_ADSTART_Msk
ADC_CR_JADSTART_Pos (3U) ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) ADC_CR_JADSTART ADC_CR_JADSTART_Msk ADC_CR_ADSTP_Pos (4U) ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) ADC_CR_ADSTP ADC_CR_ADSTP_Msk ADC_CR_JADSTP_Pos (5U) ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) ADC_CR_JADSTP ADC_CR_JADSTP_Msk ADC_CR_BOOST_Pos (8U) ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) ADC_CR_BOOST ADC_CR_BOOST_Msk ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) ADC_CR_ADCALLIN_Pos (16U) ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk ADC_CR_LINCALRDYW1_Pos (22U) ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk ADC_CR_LINCALRDYW2_Pos (23U) ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk ADC_CR_LINCALRDYW3_Pos (24U) ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk ADC_CR_LINCALRDYW4_Pos (25U) ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) ¡ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk ¢ADC_CR_LINCALRDYW5_Pos (26U) £ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) ¤ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk ¥ADC_CR_LINCALRDYW6_Pos (27U) ¦ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) §ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk ¨ADC_CR_ADVREGEN_Pos (28U) ©ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) ªADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk «ADC_CR_DEEPPWD_Pos (29U) ¬ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk ®ADC_CR_ADCALDIF_Pos (30U) ¯ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) °ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk ±ADC_CR_ADCAL_Pos (31U) ²ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) ³ADC_CR_ADCAL ADC_CR_ADCAL_Msk ¶ADC_CFGR_DMNGT_Pos (0U) ·ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) ¸ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk ¹ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) ºADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) ¼ADC_CFGR_RES_Pos (2U) ½ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) ¾ADC_CFGR_RES ADC_CFGR_RES_Msk ¿ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) ÀADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) ÁADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) ÃADC_CFGR_EXTSEL_Pos (5U) ÄADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) ÅADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk ÆADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) ÇADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) ÈADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) ÉADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) ÊADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) ÌADC_CFGR_EXTEN_Pos (10U) ÍADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) ÎADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk ÏADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) ÐADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) ÒADC_CFGR_OVRMOD_Pos (12U) ÓADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) ÔADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk ÕADC_CFGR_CONT_Pos (13U) ÖADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) ×ADC_CFGR_CONT ADC_CFGR_CONT_Msk ØADC_CFGR_AUTDLY_Pos (14U) ÙADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) ÚADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk ÜADC_CFGR_DISCEN_Pos (16U) ÝADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) ÞADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk àADC_CFGR_DISCNUM_Pos (17U) áADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) âADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk ãADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) äADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) åADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) çADC_CFGR_JDISCEN_Pos (20U) èADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) éADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk êADC_CFGR_JQM_Pos (21U) ëADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) ìADC_CFGR_JQM ADC_CFGR_JQM_Msk íADC_CFGR_AWD1SGL_Pos (22U) îADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) ïADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk ðADC_CFGR_AWD1EN_Pos (23U) ñADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) òADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk óADC_CFGR_JAWD1EN_Pos (24U) ôADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) õADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk öADC_CFGR_JAUTO_Pos (25U) ÷ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) øADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk úADC_CFGR_AWD1CH_Pos (26U) ûADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) üADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk ýADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) þADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) ÿADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) ADC_CFGR_JQDIS_Pos (31U) ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk ADC_CFGR2_ROVSE_Pos (0U) ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk ADC_CFGR2_JOVSE_Pos (1U) ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk ADC_CFGR2_OVSS_Pos (5U) ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) ADC_CFGR2_TROVS_Pos (9U) ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk ADC_CFGR2_ROVSM_Pos (10U) ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk ADC_CFGR2_RSHIFT1_Pos (11U) ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk ¡ADC_CFGR2_RSHIFT2_Pos (12U) ¢ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) £ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk ¤ADC_CFGR2_RSHIFT3_Pos (13U) ¥ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) ¦ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk §ADC_CFGR2_RSHIFT4_Pos (14U) ¨ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) ©ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk «ADC_CFGR2_OVSR_Pos (16U) ¬ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk ®ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) ¯ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) °ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) ±ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) ²ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) ³ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) ´ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) µADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) ¶ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) ·ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) ¹ADC_CFGR2_LSHIFT_Pos (28U) ºADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) »ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk ¼ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) ½ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) ¾ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) ¿ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) ÂADC_SMPR1_SMP0_Pos (0U) ÃADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) ÄADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk ÅADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) ÆADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) ÇADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) ÉADC_SMPR1_SMP1_Pos (3U) ÊADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) ËADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk ÌADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) ÍADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) ÎADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) ÐADC_SMPR1_SMP2_Pos (6U) ÑADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) ÒADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk ÓADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) ÔADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) ÕADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) ×ADC_SMPR1_SMP3_Pos (9U) ØADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) ÙADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk ÚADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) ÛADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) ÜADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) ÞADC_SMPR1_SMP4_Pos (12U) ßADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) àADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk áADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) âADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) ãADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) åADC_SMPR1_SMP5_Pos (15U) æADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) çADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk èADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) éADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) êADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) ìADC_SMPR1_SMP6_Pos (18U) íADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) îADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk ïADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) ðADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) ñADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) óADC_SMPR1_SMP7_Pos (21U) ôADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) õADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk öADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) ÷ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) øADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) úADC_SMPR1_SMP8_Pos (24U) ûADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) üADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk ýADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) þADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) ÿADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) ADC_SMPR1_SMP9_Pos (27U) ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) ADC_SMPR2_SMP10_Pos (0U) ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) ADC_SMPR2_SMP11_Pos (3U) ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) ADC_SMPR2_SMP12_Pos (6U) ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) ADC_SMPR2_SMP13_Pos (9U) ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk ¡ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) ¢ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) £ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) ¥ADC_SMPR2_SMP14_Pos (12U) ¦ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) §ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk ¨ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) ©ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) ªADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) ¬ADC_SMPR2_SMP15_Pos (15U) ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) ®ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk ¯ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) °ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) ±ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) ³ADC_SMPR2_SMP16_Pos (18U) ´ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) µADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk ¶ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) ·ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) ¸ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) ºADC_SMPR2_SMP17_Pos (21U) »ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) ¼ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk ½ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) ¾ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) ¿ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) ÁADC_SMPR2_SMP18_Pos (24U) ÂADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) ÃADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk ÄADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) ÅADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) ÆADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) ÈADC_SMPR2_SMP19_Pos (27U) ÉADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) ÊADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk ËADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) ÌADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) ÍADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) ÐADC_PCSEL_PCSEL_Pos (0U) ÑADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) ÒADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk ÓADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) ÔADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) ÕADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) ÖADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) ×ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) ØADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) ÙADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) ÚADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) ÛADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) ÜADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) ÝADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) ÞADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) ßADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) àADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) áADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) âADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) ãADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) äADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) åADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) æADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) éADC_LTR_LT_Pos (0U) êADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) ëADC_LTR_LT ADC_LTR_LT_Msk îADC_HTR_HT_Pos (0U) ïADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) ðADC_HTR_HT ADC_HTR_HT_Msk ôADC_SQR1_L_Pos (0U) õADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) öADC_SQR1_L ADC_SQR1_L_Msk ÷ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) øADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) ùADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) úADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) üADC_SQR1_SQ1_Pos (6U) ýADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) þADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk ÿADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
ADC_SQR1_SQ2_Pos (12U) ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) ADC_SQR1_SQ3_Pos (18U) ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) ADC_SQR1_SQ4_Pos (24U) ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) ¡ADC_SQR2_SQ5_Pos (0U) ¢ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) £ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk ¤ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) ¥ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) ¦ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) §ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) ¨ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) ªADC_SQR2_SQ6_Pos (6U) «ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) ¬ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) ®ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) ¯ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) °ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) ±ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) ³ADC_SQR2_SQ7_Pos (12U) ´ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) µADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk ¶ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) ·ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) ¸ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) ¹ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) ºADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) ¼ADC_SQR2_SQ8_Pos (18U) ½ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) ¾ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk ¿ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) ÀADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) ÁADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) ÂADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) ÃADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) ÅADC_SQR2_SQ9_Pos (24U) ÆADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) ÇADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk ÈADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) ÉADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) ÊADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) ËADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) ÌADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) ÏADC_SQR3_SQ10_Pos (0U) ÐADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) ÑADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk ÒADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) ÓADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) ÔADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) ÕADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) ÖADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) ØADC_SQR3_SQ11_Pos (6U) ÙADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) ÚADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk ÛADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) ÜADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) ÝADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) ÞADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) ßADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) áADC_SQR3_SQ12_Pos (12U) âADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) ãADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk äADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) åADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) æADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) çADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) èADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) êADC_SQR3_SQ13_Pos (18U) ëADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) ìADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk íADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) îADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) ïADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) ðADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) ñADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) óADC_SQR3_SQ14_Pos (24U) ôADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) õADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk öADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) ÷ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) øADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) ùADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) úADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) ýADC_SQR4_SQ15_Pos (0U) þADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) ÿADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) ADC_SQR4_SQ16_Pos (6U) ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) ADC_DR_RDATA_Pos (0U) ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) ADC_DR_RDATA ADC_DR_RDATA_Msk ADC_JSQR_JL_Pos (0U) ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) ADC_JSQR_JL ADC_JSQR_JL_Msk ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) ADC_JSQR_JEXTSEL_Pos (2U) ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) ¡ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) £ADC_JSQR_JEXTEN_Pos (7U) ¤ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) ¥ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk ¦ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) §ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) ©ADC_JSQR_JSQ1_Pos (9U) ªADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) «ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk ¬ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) ®ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) ¯ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) °ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) ²ADC_JSQR_JSQ2_Pos (15U) ³ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) ´ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk µADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) ¶ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) ·ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) ¸ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) ¹ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) »ADC_JSQR_JSQ3_Pos (21U) ¼ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) ½ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk ¾ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) ¿ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) ÀADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) ÁADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) ÂADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) ÄADC_JSQR_JSQ4_Pos (27U) ÅADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) ÆADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk ÇADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) ÈADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) ÉADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) ÊADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) ËADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) ÎADC_OFR1_OFFSET1_Pos (0U) ÏADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) ÐADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk ÑADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) ÒADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) ÓADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) ÔADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) ÕADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) ÖADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) ×ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) ØADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) ÙADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) ÚADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) ÛADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) ÜADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) ÝADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) ÞADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) ßADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) àADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) áADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) âADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) ãADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) äADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) åADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) æADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) çADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) èADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) éADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) êADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) ìADC_OFR1_OFFSET1_CH_Pos (26U) íADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) îADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk ïADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) ðADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) ñADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) òADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) óADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) õADC_OFR1_SSATE_Pos (31U) öADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) ÷ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk ûADC_OFR2_OFFSET2_Pos (0U) üADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) ýADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk þADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) ÿADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) ADC_OFR2_OFFSET2_CH_Pos (26U) ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) ¢ADC_OFR2_SSATE_Pos (31U) £ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) ¤ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk ¨ADC_OFR3_OFFSET3_Pos (0U) ©ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) ªADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk «ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) ¬ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) ®ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) ¯ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) °ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) ±ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) ²ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) ³ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) ´ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) µADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) ¶ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) ·ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) ¸ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) ¹ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) ºADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) »ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) ¼ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) ½ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) ¾ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) ¿ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) ÀADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) ÁADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) ÂADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) ÃADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) ÄADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) ÆADC_OFR3_OFFSET3_CH_Pos (26U) ÇADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) ÈADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk ÉADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) ÊADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) ËADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) ÌADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) ÍADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) ÏADC_OFR3_SSATE_Pos (31U) ÐADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) ÑADC_OFR3_SSATE ADC_OFR3_SSATE_Msk ÕADC_OFR4_OFFSET4_Pos (0U) ÖADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) ×ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk ØADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) ÙADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) ÚADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) ÛADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) ÜADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) ÝADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) ÞADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) ßADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) àADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) áADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) âADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) ãADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) äADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) åADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) æADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) çADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) èADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) éADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) êADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) ëADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) ìADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) íADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) îADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) ïADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) ðADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) ñADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) óADC_OFR4_OFFSET4_CH_Pos (26U) ôADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) õADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk öADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) ÷ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) øADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) ùADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) úADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) üADC_OFR4_SSATE_Pos (31U) ýADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) þADC_OFR4_SSATE ADC_OFR4_SSATE_Msk ADC_JDR1_JDATA_Pos (0U) ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) ¡ ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) ¢ ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) £ ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) ¤ ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) § ADC_JDR2_JDATA_Pos (0U) ¨ ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) © ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk ª ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) « ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) ¬ ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) ® ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) ¯ ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) ° ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) ± ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) ² ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) ³ ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) ´ ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) µ ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) ¶ ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) · ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) ¸ ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) ¹ ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) º ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) » ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) ¼ ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) ½ ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) ¾ ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) ¿ ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) À ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) Á ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) Â ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) Ã ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) Ä ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) Å ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) Æ ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) Ç ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) È ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) É ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) Ì ADC_JDR3_JDATA_Pos (0U) Í ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) Î ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk Ï ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) Ð ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) Ñ ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) Ò ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) Ó ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) Ô ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) Õ ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) Ö ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) × ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) Ø ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) Ù ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) Ú ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) Û ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) Ü ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) Ý ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) Þ ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) ß ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) à ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) á ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) â ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) ã ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) ä ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) å ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) æ ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) ç ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) è ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) é ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) ê ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) ë ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) ì ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) í ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) î ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) ñ ADC_JDR4_JDATA_Pos (0U) ò ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) ó ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk ô ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) õ ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) ö ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) ÷ ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) ø ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) ù ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) ú ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) û ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) ü ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) ý ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) þ ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) ÿ ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) ADC_AWD2CR_AWD2CH_Pos (0U) ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) ¡ ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) ¢ ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) £ ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) ¤ ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) ¥ ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) ¦ ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) § ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) ¨ ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) © ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) ª ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) « ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) ¬ ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) ¯ ADC_AWD3CR_AWD3CH_Pos (0U) ° ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) ± ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk ² ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) ³ ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) ´ ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) µ ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) ¶ ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) · ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) ¸ ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) ¹ ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) º ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) » ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) ¼ ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) ½ ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) ¾ ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) ¿ ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) À ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) Á ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) Â ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) Ã ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) Ä ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) Å ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) È ADC_DIFSEL_DIFSEL_Pos (0U) É ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) Ê ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk Ë ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) Ì ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) Í ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) Î ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) Ï ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) Ð ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) Ñ ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) Ò ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) Ó ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) Ô ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) Õ ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) Ö ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) × ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) Ø ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) Ù ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) Ú ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) Û ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) Ü ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) Ý ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) Þ ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) á ADC_CALFACT_CALFACT_S_Pos (0U) â ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) ã ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk ä ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) å ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) æ ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) ç ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) è ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) é ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) ê ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) ë ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) ì ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) í ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) î ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) ï ADC_CALFACT_CALFACT_D_Pos (16U) ð ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) ñ ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk ò ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) ó ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) ô ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) õ ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) ö ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) ÷ ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) ø ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) ù ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) ú ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) û ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) ü ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) ÿ ADC_CALFACT2_LINCALFACT_Pos (0U) ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) £ ADC_CSR_ADRDY_MST_Pos (0U) ¤ ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) ¥ ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk ¦ ADC_CSR_EOSMP_MST_Pos (1U) § ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) ¨ ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk © ADC_CSR_EOC_MST_Pos (2U) ª ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) « ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk ¬ ADC_CSR_EOS_MST_Pos (3U) ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) ® ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk ¯ ADC_CSR_OVR_MST_Pos (4U) ° ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) ± ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk ² ADC_CSR_JEOC_MST_Pos (5U) ³ ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) ´ ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk µ ADC_CSR_JEOS_MST_Pos (6U) ¶ ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) · ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk ¸ ADC_CSR_AWD1_MST_Pos (7U) ¹ ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) º ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk » ADC_CSR_AWD2_MST_Pos (8U) ¼ ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) ½ ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk ¾ ADC_CSR_AWD3_MST_Pos (9U) ¿ ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) À ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk Á ADC_CSR_JQOVF_MST_Pos (10U) Â ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) Ã ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk Ä ADC_CSR_ADRDY_SLV_Pos (16U) Å ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) Æ ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk Ç ADC_CSR_EOSMP_SLV_Pos (17U) È ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) É ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk Ê ADC_CSR_EOC_SLV_Pos (18U) Ë ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) Ì ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk Í ADC_CSR_EOS_SLV_Pos (19U) Î ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) Ï ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk Ð ADC_CSR_OVR_SLV_Pos (20U) Ñ ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) Ò ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk Ó ADC_CSR_JEOC_SLV_Pos (21U) Ô ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) Õ ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk Ö ADC_CSR_JEOS_SLV_Pos (22U) × ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) Ø ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk Ù ADC_CSR_AWD1_SLV_Pos (23U) Ú ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) Û ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk Ü ADC_CSR_AWD2_SLV_Pos (24U) Ý ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) Þ ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk ß ADC_CSR_AWD3_SLV_Pos (25U) à ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) á ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk â ADC_CSR_JQOVF_SLV_Pos (26U) ã ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) ä ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk ç ADC_CCR_DUAL_Pos (0U) è ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) é ADC_CCR_DUAL ADC_CCR_DUAL_Msk ê ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) ë ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) ì ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) í ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) î ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) ð ADC_CCR_DELAY_Pos (8U) ñ ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) ò ADC_CCR_DELAY ADC_CCR_DELAY_Msk ó ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) ô ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) õ ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) ö ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) ù ADC_CCR_DAMDF_Pos (14U) ú ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) û ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk ü ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) ý ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) ÿ ADC_CCR_CKMODE_Pos (16U) ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
ADC_CCR_PRESC_Pos (18U) ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) ADC_CCR_PRESC ADC_CCR_PRESC_Msk ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) ADC_CCR_VREFEN_Pos (22U) ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk ADC_CCR_TSEN_Pos (23U) ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) ADC_CCR_TSEN ADC_CCR_TSEN_Msk ADC_CCR_VBATEN_Pos (24U) ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk ADC_CDR_RDATA_MST_Pos (0U) ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk ADC_CDR_RDATA_SLV_Pos (16U) ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk ¡ ADC_CDR2_RDATA_ALT_Pos (0U) ¢ ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) £ ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk ¬ VREFBUF_CSR_ENVR_Pos (0U) VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) ® VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk ¯ VREFBUF_CSR_HIZ_Pos (1U) ° VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) ± VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk ² VREFBUF_CSR_VRR_Pos (3U) ³ VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) ´ VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk µ VREFBUF_CSR_VRS_Pos (4U) ¶ VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) · VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk ¹ VREFBUF_CSR_VRS_OUT1 (0U) º VREFBUF_CSR_VRS_OUT2_Pos (4U) » VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) ¼ VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk ½ VREFBUF_CSR_VRS_OUT3_Pos (5U) ¾ VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) ¿ VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk À VREFBUF_CSR_VRS_OUT4_Pos (4U) Á VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) Â VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk Å VREFBUF_CCR_TRIM_Pos (0U) Æ VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) Ç VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk Ð FDCAN_CREL_DAY_Pos (0U) Ñ FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) Ò FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk Ó FDCAN_CREL_MON_Pos (8U) Ô FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) Õ FDCAN_CREL_MON FDCAN_CREL_MON_Msk Ö FDCAN_CREL_YEAR_Pos (16U) × FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) Ø FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk Ù FDCAN_CREL_SUBSTEP_Pos (20U) Ú FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) Û FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk Ü FDCAN_CREL_STEP_Pos (24U) Ý FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) Þ FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk ß FDCAN_CREL_REL_Pos (28U) à FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) á FDCAN_CREL_REL FDCAN_CREL_REL_Msk ä FDCAN_ENDN_ETV_Pos (0U) å FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) æ FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk é FDCAN_DBTP_DSJW_Pos (0U) ê FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) ë FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk ì FDCAN_DBTP_DTSEG2_Pos (4U) í FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) î FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk ï FDCAN_DBTP_DTSEG1_Pos (8U) ð FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) ñ FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk ò FDCAN_DBTP_DBRP_Pos (16U) ó FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) ô FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk õ FDCAN_DBTP_TDC_Pos (23U) ö FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) ÷ FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk ú FDCAN_TEST_LBCK_Pos (4U) û FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) ü FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk ý FDCAN_TEST_TX_Pos (5U) þ FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) ÿ FDCAN_TEST_TX FDCAN_TEST_TX_Msk FDCAN_TEST_RX_Pos (7U) FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) FDCAN_TEST_RX FDCAN_TEST_RX_Msk
FDCAN_RWD_WDC_Pos (0U) FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk FDCAN_RWD_WDV_Pos (8U) FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk FDCAN_CCCR_INIT_Pos (0U) FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk FDCAN_CCCR_CCE_Pos (1U) FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk FDCAN_CCCR_ASM_Pos (2U) FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk FDCAN_CCCR_CSA_Pos (3U) FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk FDCAN_CCCR_CSR_Pos (4U) FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk FDCAN_CCCR_MON_Pos (5U) FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk FDCAN_CCCR_DAR_Pos (6U) FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) ¡ FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk ¢ FDCAN_CCCR_TEST_Pos (7U) £ FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) ¤ FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk ¥ FDCAN_CCCR_FDOE_Pos (8U) ¦ FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) § FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk ¨ FDCAN_CCCR_BRSE_Pos (9U) © FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) ª FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk « FDCAN_CCCR_PXHD_Pos (12U) ¬ FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk ® FDCAN_CCCR_EFBI_Pos (13U) ¯ FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) ° FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk ± FDCAN_CCCR_TXP_Pos (14U) ² FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) ³ FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk ´ FDCAN_CCCR_NISO_Pos (15U) µ FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) ¶ FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk ¹ FDCAN_NBTP_NTSEG2_Pos (0U) º FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) » FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk ¼ FDCAN_NBTP_NTSEG1_Pos (8U) ½ FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) ¾ FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk ¿ FDCAN_NBTP_NBRP_Pos (16U) À FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) Á FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk  FDCAN_NBTP_NSJW_Pos (25U) à FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) Ä FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk Ç FDCAN_TSCC_TSS_Pos (0U) È FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) É FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk Ê FDCAN_TSCC_TCP_Pos (16U) Ë FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) Ì FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk Ï FDCAN_TSCV_TSC_Pos (0U) Ð FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) Ñ FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk Ô FDCAN_TOCC_ETOC_Pos (0U) Õ FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) Ö FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk × FDCAN_TOCC_TOS_Pos (1U) Ø FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) Ù FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk Ú FDCAN_TOCC_TOP_Pos (16U) Û FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) Ü FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk ß FDCAN_TOCV_TOC_Pos (0U) à FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) á FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk ä FDCAN_ECR_TEC_Pos (0U) å FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) æ FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk ç FDCAN_ECR_REC_Pos (8U) è FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) é FDCAN_ECR_REC FDCAN_ECR_REC_Msk ê FDCAN_ECR_RP_Pos (15U) ë FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) ì FDCAN_ECR_RP FDCAN_ECR_RP_Msk í FDCAN_ECR_CEL_Pos (16U) î FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) ï FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk ò FDCAN_PSR_LEC_Pos (0U) ó FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) ô FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk õ FDCAN_PSR_ACT_Pos (3U) ö FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) ÷ FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk ø FDCAN_PSR_EP_Pos (5U) ù FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) ú FDCAN_PSR_EP FDCAN_PSR_EP_Msk û FDCAN_PSR_EW_Pos (6U) ü FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) ý FDCAN_PSR_EW FDCAN_PSR_EW_Msk þ FDCAN_PSR_BO_Pos (7U) ÿ FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) !FDCAN_PSR_BO FDCAN_PSR_BO_Msk !FDCAN_PSR_DLEC_Pos (8U) !FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) !FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk !FDCAN_PSR_RESI_Pos (11U)
!FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) !FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk !FDCAN_PSR_RBRS_Pos (12U) !FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) !FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk !FDCAN_PSR_REDL_Pos (13U) !FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) !FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk !FDCAN_PSR_PXE_Pos (14U) !FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) !FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk !FDCAN_PSR_TDCV_Pos (16U) !FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) !FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk !FDCAN_TDCR_TDCF_Pos (0U) !FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) !FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk !FDCAN_TDCR_TDCO_Pos (8U) !FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) !FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk !FDCAN_IR_RF0N_Pos (0U) !FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) !FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk !FDCAN_IR_RF0W_Pos (1U) ¡!FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) ¢!FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk £!FDCAN_IR_RF0F_Pos (2U) ¤!FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) ¥!FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk ¦!FDCAN_IR_RF0L_Pos (3U) §!FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) ¨!FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk ©!FDCAN_IR_RF1N_Pos (4U) ª!FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) «!FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk ¬!FDCAN_IR_RF1W_Pos (5U) !FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) ®!FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk ¯!FDCAN_IR_RF1F_Pos (6U) °!FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) ±!FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk ²!FDCAN_IR_RF1L_Pos (7U) ³!FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) ´!FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk µ!FDCAN_IR_HPM_Pos (8U) ¶!FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) ·!FDCAN_IR_HPM FDCAN_IR_HPM_Msk ¸!FDCAN_IR_TC_Pos (9U) ¹!FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) º!FDCAN_IR_TC FDCAN_IR_TC_Msk »!FDCAN_IR_TCF_Pos (10U) ¼!FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) ½!FDCAN_IR_TCF FDCAN_IR_TCF_Msk ¾!FDCAN_IR_TFE_Pos (11U) ¿!FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) À!FDCAN_IR_TFE FDCAN_IR_TFE_Msk Á!FDCAN_IR_TEFN_Pos (12U) Â!FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) Ã!FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk Ä!FDCAN_IR_TEFW_Pos (13U) Å!FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) Æ!FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk Ç!FDCAN_IR_TEFF_Pos (14U) È!FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) É!FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk Ê!FDCAN_IR_TEFL_Pos (15U) Ë!FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) Ì!FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk Í!FDCAN_IR_TSW_Pos (16U) Î!FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) Ï!FDCAN_IR_TSW FDCAN_IR_TSW_Msk Ð!FDCAN_IR_MRAF_Pos (17U) Ñ!FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) Ò!FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk Ó!FDCAN_IR_TOO_Pos (18U) Ô!FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) Õ!FDCAN_IR_TOO FDCAN_IR_TOO_Msk Ö!FDCAN_IR_DRX_Pos (19U) ×!FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) Ø!FDCAN_IR_DRX FDCAN_IR_DRX_Msk Ù!FDCAN_IR_ELO_Pos (22U) Ú!FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) Û!FDCAN_IR_ELO FDCAN_IR_ELO_Msk Ü!FDCAN_IR_EP_Pos (23U) Ý!FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) Þ!FDCAN_IR_EP FDCAN_IR_EP_Msk ß!FDCAN_IR_EW_Pos (24U) à!FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) á!FDCAN_IR_EW FDCAN_IR_EW_Msk â!FDCAN_IR_BO_Pos (25U) ã!FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) ä!FDCAN_IR_BO FDCAN_IR_BO_Msk å!FDCAN_IR_WDI_Pos (26U) æ!FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) ç!FDCAN_IR_WDI FDCAN_IR_WDI_Msk è!FDCAN_IR_PEA_Pos (27U) é!FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) ê!FDCAN_IR_PEA FDCAN_IR_PEA_Msk ë!FDCAN_IR_PED_Pos (28U) ì!FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) í!FDCAN_IR_PED FDCAN_IR_PED_Msk î!FDCAN_IR_ARA_Pos (29U) ï!FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) ð!FDCAN_IR_ARA FDCAN_IR_ARA_Msk ó!FDCAN_IE_RF0NE_Pos (0U) ô!FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) õ!FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk ö!FDCAN_IE_RF0WE_Pos (1U) ÷!FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) ø!FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk ù!FDCAN_IE_RF0FE_Pos (2U) ú!FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) û!FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk ü!FDCAN_IE_RF0LE_Pos (3U) ý!FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) þ!FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk ÿ!FDCAN_IE_RF1NE_Pos (4U) "FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) "FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk "FDCAN_IE_RF1WE_Pos (5U) "FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) "FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
"FDCAN_IE_RF1FE_Pos (6U) "FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) "FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk "FDCAN_IE_RF1LE_Pos (7U) "FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) "FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk "FDCAN_IE_HPME_Pos (8U) "FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) "FDCAN_IE_HPME FDCAN_IE_HPME_Msk "FDCAN_IE_TCE_Pos (9U) "FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) "FDCAN_IE_TCE FDCAN_IE_TCE_Msk "FDCAN_IE_TCFE_Pos (10U) "FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) "FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk "FDCAN_IE_TFEE_Pos (11U) "FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) "FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk "FDCAN_IE_TEFNE_Pos (12U) "FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) "FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk "FDCAN_IE_TEFWE_Pos (13U) "FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) "FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk "FDCAN_IE_TEFFE_Pos (14U) "FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) "FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk "FDCAN_IE_TEFLE_Pos (15U) ¡"FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) ¢"FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk £"FDCAN_IE_TSWE_Pos (16U) ¤"FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) ¥"FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk ¦"FDCAN_IE_MRAFE_Pos (17U) §"FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) ¨"FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk ©"FDCAN_IE_TOOE_Pos (18U) ª"FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) «"FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk ¬"FDCAN_IE_DRXE_Pos (19U) "FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) ®"FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk ¯"FDCAN_IE_BECE_Pos (20U) °"FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) ±"FDCAN_IE_BECE FDCAN_IE_BECE_Msk ²"FDCAN_IE_BEUE_Pos (21U) ³"FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) ´"FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk µ"FDCAN_IE_ELOE_Pos (22U) ¶"FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) ·"FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk ¸"FDCAN_IE_EPE_Pos (23U) ¹"FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) º"FDCAN_IE_EPE FDCAN_IE_EPE_Msk »"FDCAN_IE_EWE_Pos (24U) ¼"FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) ½"FDCAN_IE_EWE FDCAN_IE_EWE_Msk ¾"FDCAN_IE_BOE_Pos (25U) ¿"FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) À"FDCAN_IE_BOE FDCAN_IE_BOE_Msk Á"FDCAN_IE_WDIE_Pos (26U) Â"FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) Ã"FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk Ä"FDCAN_IE_PEAE_Pos (27U) Å"FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) Æ"FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk Ç"FDCAN_IE_PEDE_Pos (28U) È"FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) É"FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk Ê"FDCAN_IE_ARAE_Pos (29U) Ë"FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) Ì"FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk Ï"FDCAN_ILS_RF0NL_Pos (0U) Ð"FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) Ñ"FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk Ò"FDCAN_ILS_RF0WL_Pos (1U) Ó"FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) Ô"FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk Õ"FDCAN_ILS_RF0FL_Pos (2U) Ö"FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) ×"FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk Ø"FDCAN_ILS_RF0LL_Pos (3U) Ù"FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) Ú"FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk Û"FDCAN_ILS_RF1NL_Pos (4U) Ü"FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) Ý"FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk Þ"FDCAN_ILS_RF1WL_Pos (5U) ß"FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) à"FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk á"FDCAN_ILS_RF1FL_Pos (6U) â"FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) ã"FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk ä"FDCAN_ILS_RF1LL_Pos (7U) å"FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) æ"FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk ç"FDCAN_ILS_HPML_Pos (8U) è"FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) é"FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk ê"FDCAN_ILS_TCL_Pos (9U) ë"FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) ì"FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk í"FDCAN_ILS_TCFL_Pos (10U) î"FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) ï"FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk ð"FDCAN_ILS_TFEL_Pos (11U) ñ"FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) ò"FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk ó"FDCAN_ILS_TEFNL_Pos (12U) ô"FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) õ"FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk ö"FDCAN_ILS_TEFWL_Pos (13U) ÷"FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) ø"FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk ù"FDCAN_ILS_TEFFL_Pos (14U) ú"FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) û"FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk ü"FDCAN_ILS_TEFLL_Pos (15U) ý"FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) þ"FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk ÿ"FDCAN_ILS_TSWL_Pos (16U) #FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) #FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk #FDCAN_ILS_MRAFE_Pos (17U) #FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) #FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
#FDCAN_ILS_TOOE_Pos (18U) #FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) #FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk #FDCAN_ILS_DRXE_Pos (19U) #FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) #FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk #FDCAN_ILS_BECE_Pos (20U) #FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) #FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk #FDCAN_ILS_BEUE_Pos (21U) #FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) #FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk #FDCAN_ILS_ELOE_Pos (22U) #FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) #FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk #FDCAN_ILS_EPE_Pos (23U) #FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) #FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk #FDCAN_ILS_EWE_Pos (24U) #FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) #FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk #FDCAN_ILS_BOE_Pos (25U) #FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) #FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk #FDCAN_ILS_WDIE_Pos (26U) #FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) #FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk #FDCAN_ILS_PEAE_Pos (27U) ¡#FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) ¢#FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk £#FDCAN_ILS_PEDE_Pos (28U) ¤#FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) ¥#FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk ¦#FDCAN_ILS_ARAE_Pos (29U) §#FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) ¨#FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk «#FDCAN_ILE_EINT0_Pos (0U) ¬#FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) #FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk ®#FDCAN_ILE_EINT1_Pos (1U) ¯#FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) °#FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk ³#FDCAN_GFC_RRFE_Pos (0U) ´#FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) µ#FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk ¶#FDCAN_GFC_RRFS_Pos (1U) ·#FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) ¸#FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk ¹#FDCAN_GFC_ANFE_Pos (2U) º#FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) »#FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk ¼#FDCAN_GFC_ANFS_Pos (4U) ½#FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) ¾#FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk Á#FDCAN_SIDFC_FLSSA_Pos (2U) Â#FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) Ã#FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk Ä#FDCAN_SIDFC_LSS_Pos (16U) Å#FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) Æ#FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk É#FDCAN_XIDFC_FLESA_Pos (2U) Ê#FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) Ë#FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk Ì#FDCAN_XIDFC_LSE_Pos (16U) Í#FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) Î#FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk Ñ#FDCAN_XIDAM_EIDM_Pos (0U) Ò#FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) Ó#FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk Ö#FDCAN_HPMS_BIDX_Pos (0U) ×#FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) Ø#FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk Ù#FDCAN_HPMS_MSI_Pos (6U) Ú#FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) Û#FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk Ü#FDCAN_HPMS_FIDX_Pos (8U) Ý#FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) Þ#FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk ß#FDCAN_HPMS_FLST_Pos (15U) à#FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) á#FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk ä#FDCAN_NDAT1_ND0_Pos (0U) å#FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) æ#FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk ç#FDCAN_NDAT1_ND1_Pos (1U) è#FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) é#FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk ê#FDCAN_NDAT1_ND2_Pos (2U) ë#FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) ì#FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk í#FDCAN_NDAT1_ND3_Pos (3U) î#FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) ï#FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk ð#FDCAN_NDAT1_ND4_Pos (4U) ñ#FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) ò#FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk ó#FDCAN_NDAT1_ND5_Pos (5U) ô#FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) õ#FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk ö#FDCAN_NDAT1_ND6_Pos (6U) ÷#FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) ø#FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk ù#FDCAN_NDAT1_ND7_Pos (7U) ú#FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) û#FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk ü#FDCAN_NDAT1_ND8_Pos (8U) ý#FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) þ#FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk ÿ#FDCAN_NDAT1_ND9_Pos (9U) $FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) $FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk $FDCAN_NDAT1_ND10_Pos (10U) $FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) $FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
$FDCAN_NDAT1_ND11_Pos (11U) $FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) $FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk $FDCAN_NDAT1_ND12_Pos (12U) $FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) $FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk $FDCAN_NDAT1_ND13_Pos (13U) $FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) $FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk $FDCAN_NDAT1_ND14_Pos (14U) $FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) $FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk $FDCAN_NDAT1_ND15_Pos (15U) $FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) $FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk $FDCAN_NDAT1_ND16_Pos (16U) $FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) $FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk $FDCAN_NDAT1_ND17_Pos (17U) $FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) $FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk $FDCAN_NDAT1_ND18_Pos (18U) $FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) $FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk $FDCAN_NDAT1_ND19_Pos (19U) $FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) $FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk $FDCAN_NDAT1_ND20_Pos (20U) ¡$FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) ¢$FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk £$FDCAN_NDAT1_ND21_Pos (21U) ¤$FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) ¥$FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk ¦$FDCAN_NDAT1_ND22_Pos (22U) §$FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) ¨$FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk ©$FDCAN_NDAT1_ND23_Pos (23U) ª$FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) «$FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk ¬$FDCAN_NDAT1_ND24_Pos (24U) $FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) ®$FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk ¯$FDCAN_NDAT1_ND25_Pos (25U) °$FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) ±$FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk ²$FDCAN_NDAT1_ND26_Pos (26U) ³$FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) ´$FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk µ$FDCAN_NDAT1_ND27_Pos (27U) ¶$FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) ·$FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk ¸$FDCAN_NDAT1_ND28_Pos (28U) ¹$FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) º$FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk »$FDCAN_NDAT1_ND29_Pos (29U) ¼$FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) ½$FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk ¾$FDCAN_NDAT1_ND30_Pos (30U) ¿$FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) À$FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk Á$FDCAN_NDAT1_ND31_Pos (31U) Â$FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) Ã$FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk Æ$FDCAN_NDAT2_ND32_Pos (0U) Ç$FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) È$FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk É$FDCAN_NDAT2_ND33_Pos (1U) Ê$FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) Ë$FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk Ì$FDCAN_NDAT2_ND34_Pos (2U) Í$FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) Î$FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk Ï$FDCAN_NDAT2_ND35_Pos (3U) Ð$FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) Ñ$FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk Ò$FDCAN_NDAT2_ND36_Pos (4U) Ó$FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) Ô$FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk Õ$FDCAN_NDAT2_ND37_Pos (5U) Ö$FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) ×$FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk Ø$FDCAN_NDAT2_ND38_Pos (6U) Ù$FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) Ú$FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk Û$FDCAN_NDAT2_ND39_Pos (7U) Ü$FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) Ý$FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk Þ$FDCAN_NDAT2_ND40_Pos (8U) ß$FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) à$FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk á$FDCAN_NDAT2_ND41_Pos (9U) â$FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) ã$FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk ä$FDCAN_NDAT2_ND42_Pos (10U) å$FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) æ$FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk ç$FDCAN_NDAT2_ND43_Pos (11U) è$FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) é$FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk ê$FDCAN_NDAT2_ND44_Pos (12U) ë$FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) ì$FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk í$FDCAN_NDAT2_ND45_Pos (13U) î$FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) ï$FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk ð$FDCAN_NDAT2_ND46_Pos (14U) ñ$FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) ò$FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk ó$FDCAN_NDAT2_ND47_Pos (15U) ô$FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) õ$FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk ö$FDCAN_NDAT2_ND48_Pos (16U) ÷$FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) ø$FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk ù$FDCAN_NDAT2_ND49_Pos (17U) ú$FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) û$FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk ü$FDCAN_NDAT2_ND50_Pos (18U) ý$FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) þ$FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk ÿ$FDCAN_NDAT2_ND51_Pos (19U) %FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) %FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk %FDCAN_NDAT2_ND52_Pos (20U) %FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) %FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
%FDCAN_NDAT2_ND53_Pos (21U) %FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) %FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk %FDCAN_NDAT2_ND54_Pos (22U) %FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) %FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk %FDCAN_NDAT2_ND55_Pos (23U) %FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) %FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk %FDCAN_NDAT2_ND56_Pos (24U) %FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) %FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk %FDCAN_NDAT2_ND57_Pos (25U) %FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) %FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk %FDCAN_NDAT2_ND58_Pos (26U) %FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) %FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk %FDCAN_NDAT2_ND59_Pos (27U) %FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) %FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk %FDCAN_NDAT2_ND60_Pos (28U) %FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) %FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk %FDCAN_NDAT2_ND61_Pos (29U) %FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) %FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk %FDCAN_NDAT2_ND62_Pos (30U) ¡%FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) ¢%FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk £%FDCAN_NDAT2_ND63_Pos (31U) ¤%FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) ¥%FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk ¨%FDCAN_RXF0C_F0SA_Pos (2U) ©%FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) ª%FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk «%FDCAN_RXF0C_F0S_Pos (16U) ¬%FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) %FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk ®%FDCAN_RXF0C_F0WM_Pos (24U) ¯%FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) °%FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk ±%FDCAN_RXF0C_F0OM_Pos (31U) ²%FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) ³%FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk ¶%FDCAN_RXF0S_F0FL_Pos (0U) ·%FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) ¸%FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk ¹%FDCAN_RXF0S_F0GI_Pos (8U) º%FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) »%FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk ¼%FDCAN_RXF0S_F0PI_Pos (16U) ½%FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) ¾%FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk ¿%FDCAN_RXF0S_F0F_Pos (24U) À%FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) Á%FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk Â%FDCAN_RXF0S_RF0L_Pos (25U) Ã%FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) Ä%FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk Ç%FDCAN_RXF0A_F0AI_Pos (0U) È%FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) É%FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk Ì%FDCAN_RXBC_RBSA_Pos (2U) Í%FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) Î%FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk Ñ%FDCAN_RXF1C_F1SA_Pos (2U) Ò%FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) Ó%FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk Ô%FDCAN_RXF1C_F1S_Pos (16U) Õ%FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) Ö%FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk ×%FDCAN_RXF1C_F1WM_Pos (24U) Ø%FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) Ù%FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk Ú%FDCAN_RXF1C_F1OM_Pos (31U) Û%FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) Ü%FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk ß%FDCAN_RXF1S_F1FL_Pos (0U) à%FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) á%FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk â%FDCAN_RXF1S_F1GI_Pos (8U) ã%FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) ä%FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk å%FDCAN_RXF1S_F1PI_Pos (16U) æ%FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) ç%FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk è%FDCAN_RXF1S_F1F_Pos (24U) é%FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) ê%FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk ë%FDCAN_RXF1S_RF1L_Pos (25U) ì%FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) í%FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk ð%FDCAN_RXF1A_F1AI_Pos (0U) ñ%FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) ò%FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk õ%FDCAN_RXESC_F0DS_Pos (0U) ö%FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) ÷%FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk ø%FDCAN_RXESC_F1DS_Pos (4U) ù%FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) ú%FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk û%FDCAN_RXESC_RBDS_Pos (8U) ü%FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) ý%FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk &FDCAN_TXBC_TBSA_Pos (2U) &FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) &FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk &FDCAN_TXBC_NDTB_Pos (16U) &FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
&FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk &FDCAN_TXBC_TFQS_Pos (24U) &FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) &FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk &FDCAN_TXBC_TFQM_Pos (30U) &FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) &FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk &FDCAN_TXFQS_TFFL_Pos (0U) &FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) &FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk &FDCAN_TXFQS_TFGI_Pos (8U) &FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) &FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk &FDCAN_TXFQS_TFQPI_Pos (16U) &FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) &FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk &FDCAN_TXFQS_TFQF_Pos (21U) &FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) &FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk &FDCAN_TXESC_TBDS_Pos (0U) &FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) &FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk ¡&FDCAN_TXBRP_TRP_Pos (0U) ¢&FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) £&FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk ¦&FDCAN_TXBAR_AR_Pos (0U) §&FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) ¨&FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk «&FDCAN_TXBCR_CR_Pos (0U) ¬&FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) &FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk °&FDCAN_TXBTO_TO_Pos (0U) ±&FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) ²&FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk µ&FDCAN_TXBCF_CF_Pos (0U) ¶&FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) ·&FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk º&FDCAN_TXBTIE_TIE_Pos (0U) »&FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) ¼&FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk ¿&FDCAN_TXBCIE_CFIE_Pos (0U) À&FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) Á&FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk Ä&FDCAN_TXEFC_EFSA_Pos (2U) Å&FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) Æ&FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk Ç&FDCAN_TXEFC_EFS_Pos (16U) È&FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) É&FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk Ê&FDCAN_TXEFC_EFWM_Pos (24U) Ë&FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) Ì&FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk Ï&FDCAN_TXEFS_EFFL_Pos (0U) Ð&FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) Ñ&FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk Ò&FDCAN_TXEFS_EFGI_Pos (8U) Ó&FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) Ô&FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk Õ&FDCAN_TXEFS_EFPI_Pos (16U) Ö&FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) ×&FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk Ø&FDCAN_TXEFS_EFF_Pos (24U) Ù&FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) Ú&FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk Û&FDCAN_TXEFS_TEFL_Pos (25U) Ü&FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) Ý&FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk à&FDCAN_TXEFA_EFAI_Pos (0U) á&FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) â&FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk å&FDCAN_TTTMC_TMSA_Pos (2U) æ&FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) ç&FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk è&FDCAN_TTTMC_TME_Pos (16U) é&FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) ê&FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk í&FDCAN_TTRMC_RID_Pos (0U) î&FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) ï&FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk ð&FDCAN_TTRMC_XTD_Pos (30U) ñ&FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) ò&FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk ó&FDCAN_TTRMC_RMPS_Pos (31U) ô&FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) õ&FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk ø&FDCAN_TTOCF_OM_Pos (0U) ù&FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) ú&FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk û&FDCAN_TTOCF_GEN_Pos (3U) ü&FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) ý&FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk þ&FDCAN_TTOCF_TM_Pos (4U) ÿ&FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) 'FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk 'FDCAN_TTOCF_LDSDL_Pos (5U) 'FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) 'FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk 'FDCAN_TTOCF_IRTO_Pos (8U)
'FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) 'FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk 'FDCAN_TTOCF_EECS_Pos (15U) 'FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) 'FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk 'FDCAN_TTOCF_AWL_Pos (16U) 'FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) 'FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk 'FDCAN_TTOCF_EGTF_Pos (24U) 'FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) 'FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk 'FDCAN_TTOCF_ECC_Pos (25U) 'FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) 'FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk 'FDCAN_TTOCF_EVTP_Pos (26U) 'FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) 'FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk 'FDCAN_TTMLM_CCM_Pos (0U) 'FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) 'FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk 'FDCAN_TTMLM_CSS_Pos (6U) 'FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) 'FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk 'FDCAN_TTMLM_TXEW_Pos (8U) 'FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) 'FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk ¡'FDCAN_TTMLM_ENTT_Pos (16U) ¢'FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) £'FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk ¦'FDCAN_TURCF_NCL_Pos (0U) §'FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) ¨'FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk ©'FDCAN_TURCF_DC_Pos (16U) ª'FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) «'FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk ¬'FDCAN_TURCF_ELT_Pos (31U) 'FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) ®'FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk ±'FDCAN_TTOCN_SGT_Pos (0U) ²'FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) ³'FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk ´'FDCAN_TTOCN_ECS_Pos (1U) µ'FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) ¶'FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk ·'FDCAN_TTOCN_SWP_Pos (2U) ¸'FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) ¹'FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk º'FDCAN_TTOCN_SWS_Pos (3U) »'FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) ¼'FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk ½'FDCAN_TTOCN_RTIE_Pos (5U) ¾'FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) ¿'FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk À'FDCAN_TTOCN_TMC_Pos (6U) Á'FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) Â'FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk Ã'FDCAN_TTOCN_TTIE_Pos (8U) Ä'FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) Å'FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk Æ'FDCAN_TTOCN_GCS_Pos (9U) Ç'FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) È'FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk É'FDCAN_TTOCN_FGP_Pos (10U) Ê'FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) Ë'FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk Ì'FDCAN_TTOCN_TMG_Pos (11U) Í'FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) Î'FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk Ï'FDCAN_TTOCN_NIG_Pos (12U) Ð'FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) Ñ'FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk Ò'FDCAN_TTOCN_ESCN_Pos (13U) Ó'FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) Ô'FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk Õ'FDCAN_TTOCN_LCKC_Pos (15U) Ö'FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) ×'FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk Ú'FDCAN_TTGTP_TP_Pos (0U) Û'FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) Ü'FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk Ý'FDCAN_TTGTP_CTP_Pos (16U) Þ'FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) ß'FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk â'FDCAN_TTTMK_TM_Pos (0U) ã'FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) ä'FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk å'FDCAN_TTTMK_TICC_Pos (16U) æ'FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) ç'FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk è'FDCAN_TTTMK_LCKM_Pos (31U) é'FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) ê'FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk í'FDCAN_TTIR_SBC_Pos (0U) î'FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) ï'FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk ð'FDCAN_TTIR_SMC_Pos (1U) ñ'FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) ò'FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk ó'FDCAN_TTIR_CSM_Pos (2U) ô'FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) õ'FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk ö'FDCAN_TTIR_SOG_Pos (3U) ÷'FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) ø'FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk ù'FDCAN_TTIR_RTMI_Pos (4U) ú'FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) û'FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk ü'FDCAN_TTIR_TTMI_Pos (5U) ý'FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) þ'FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk ÿ'FDCAN_TTIR_SWE_Pos (6U) (FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) (FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk (FDCAN_TTIR_GTW_Pos (7U) (FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) (FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
(FDCAN_TTIR_GTD_Pos (8U) (FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) (FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk (FDCAN_TTIR_GTE_Pos (9U) (FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) (FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk (FDCAN_TTIR_TXU_Pos (10U) (FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) (FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk (FDCAN_TTIR_TXO_Pos (11U) (FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) (FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk (FDCAN_TTIR_SE1_Pos (12U) (FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) (FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk (FDCAN_TTIR_SE2_Pos (13U) (FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) (FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk (FDCAN_TTIR_ELC_Pos (14U) (FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) (FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk (FDCAN_TTIR_IWT_Pos (15U) (FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) (FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk (FDCAN_TTIR_WT_Pos (16U) (FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) (FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk (FDCAN_TTIR_AW_Pos (17U) ¡(FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) ¢(FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk £(FDCAN_TTIR_CER_Pos (18U) ¤(FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) ¥(FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk ¨(FDCAN_TTIE_SBCE_Pos (0U) ©(FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) ª(FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk «(FDCAN_TTIE_SMCE_Pos (1U) ¬(FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) (FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk ®(FDCAN_TTIE_CSME_Pos (2U) ¯(FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) °(FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk ±(FDCAN_TTIE_SOGE_Pos (3U) ²(FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) ³(FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk ´(FDCAN_TTIE_RTMIE_Pos (4U) µ(FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) ¶(FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk ·(FDCAN_TTIE_TTMIE_Pos (5U) ¸(FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) ¹(FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk º(FDCAN_TTIE_SWEE_Pos (6U) »(FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) ¼(FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk ½(FDCAN_TTIE_GTWE_Pos (7U) ¾(FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) ¿(FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk À(FDCAN_TTIE_GTDE_Pos (8U) Á(FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) Â(FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk Ã(FDCAN_TTIE_GTEE_Pos (9U) Ä(FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) Å(FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk Æ(FDCAN_TTIE_TXUE_Pos (10U) Ç(FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) È(FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk É(FDCAN_TTIE_TXOE_Pos (11U) Ê(FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) Ë(FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk Ì(FDCAN_TTIE_SE1E_Pos (12U) Í(FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) Î(FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk Ï(FDCAN_TTIE_SE2E_Pos (13U) Ð(FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) Ñ(FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk Ò(FDCAN_TTIE_ELCE_Pos (14U) Ó(FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) Ô(FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk Õ(FDCAN_TTIE_IWTE_Pos (15U) Ö(FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) ×(FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk Ø(FDCAN_TTIE_WTE_Pos (16U) Ù(FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) Ú(FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk Û(FDCAN_TTIE_AWE_Pos (17U) Ü(FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) Ý(FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk Þ(FDCAN_TTIE_CERE_Pos (18U) ß(FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) à(FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk ã(FDCAN_TTILS_SBCS_Pos (0U) ä(FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) å(FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk æ(FDCAN_TTILS_SMCS_Pos (1U) ç(FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) è(FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk é(FDCAN_TTILS_CSMS_Pos (2U) ê(FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) ë(FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk ì(FDCAN_TTILS_SOGS_Pos (3U) í(FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) î(FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk ï(FDCAN_TTILS_RTMIS_Pos (4U) ð(FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) ñ(FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk ò(FDCAN_TTILS_TTMIS_Pos (5U) ó(FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) ô(FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk õ(FDCAN_TTILS_SWES_Pos (6U) ö(FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) ÷(FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk ø(FDCAN_TTILS_GTWS_Pos (7U) ù(FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) ú(FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk û(FDCAN_TTILS_GTDS_Pos (8U) ü(FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) ý(FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk þ(FDCAN_TTILS_GTES_Pos (9U) ÿ(FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) )FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk )FDCAN_TTILS_TXUS_Pos (10U) )FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) )FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk )FDCAN_TTILS_TXOS_Pos (11U)
)FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) )FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk )FDCAN_TTILS_SE1S_Pos (12U) )FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) )FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk )FDCAN_TTILS_SE2S_Pos (13U) )FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) )FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk )FDCAN_TTILS_ELCS_Pos (14U) )FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) )FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk )FDCAN_TTILS_IWTS_Pos (15U) )FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) )FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk )FDCAN_TTILS_WTS_Pos (16U) )FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) )FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk )FDCAN_TTILS_AWS_Pos (17U) )FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) )FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk )FDCAN_TTILS_CERS_Pos (18U) )FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) )FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk )FDCAN_TTOST_EL_Pos (0U) )FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) )FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk ¡)FDCAN_TTOST_MS_Pos (2U) ¢)FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) £)FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk ¤)FDCAN_TTOST_SYS_Pos (4U) ¥)FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) ¦)FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk §)FDCAN_TTOST_QGTP_Pos (6U) ¨)FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) ©)FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk ª)FDCAN_TTOST_QCS_Pos (7U) «)FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) ¬)FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk )FDCAN_TTOST_RTO_Pos (8U) ®)FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) ¯)FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk °)FDCAN_TTOST_WGTD_Pos (22U) ±)FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) ²)FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk ³)FDCAN_TTOST_GFI_Pos (23U) ´)FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) µ)FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk ¶)FDCAN_TTOST_TMP_Pos (24U) ·)FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) ¸)FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk ¹)FDCAN_TTOST_GSI_Pos (27U) º)FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) »)FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk ¼)FDCAN_TTOST_WFE_Pos (28U) ½)FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) ¾)FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk ¿)FDCAN_TTOST_AWE_Pos (29U) À)FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) Á)FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk Â)FDCAN_TTOST_WECS_Pos (30U) Ã)FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) Ä)FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk Å)FDCAN_TTOST_SPL_Pos (31U) Æ)FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) Ç)FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk Ê)FDCAN_TURNA_NAV_Pos (0U) Ë)FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) Ì)FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk Ï)FDCAN_TTLGT_LT_Pos (0U) Ð)FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) Ñ)FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk Ò)FDCAN_TTLGT_GT_Pos (16U) Ó)FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) Ô)FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk ×)FDCAN_TTCTC_CT_Pos (0U) Ø)FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) Ù)FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk Ú)FDCAN_TTCTC_CC_Pos (16U) Û)FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) Ü)FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk ß)FDCAN_TTCPT_CCV_Pos (0U) à)FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) á)FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk â)FDCAN_TTCPT_SWV_Pos (16U) ã)FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) ä)FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk ç)FDCAN_TTCSM_CSM_Pos (0U) è)FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) é)FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk ì)FDCAN_TTTS_SWTSEL_Pos (0U) í)FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) î)FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk ï)FDCAN_TTTS_EVTSEL_Pos (4U) ð)FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) ñ)FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk ú)FDCANCCU_CREL_DAY_Pos (0U) û)FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) ü)FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk ý)FDCANCCU_CREL_MON_Pos (8U) þ)FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) ÿ)FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk *FDCANCCU_CREL_YEAR_Pos (16U) *FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) *FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk *FDCANCCU_CREL_SUBSTEP_Pos (20U) *FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
*FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk *FDCANCCU_CREL_STEP_Pos (24U) *FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) *FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk *FDCANCCU_CREL_REL_Pos (28U) *FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) *FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk *FDCANCCU_CCFG_TQBT_Pos (0U) *FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) *FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk *FDCANCCU_CCFG_BCC_Pos (6U) *FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) *FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk *FDCANCCU_CCFG_CFL_Pos (7U) *FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) *FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk *FDCANCCU_CCFG_OCPM_Pos (8U) *FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) *FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk *FDCANCCU_CCFG_CDIV_Pos (16U) *FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) *FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk *FDCANCCU_CCFG_SWR_Pos (31U) *FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) *FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk ¢*FDCANCCU_CSTAT_OCPC_Pos (0U) £*FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) ¤*FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk ¥*FDCANCCU_CSTAT_TQC_Pos (18U) ¦*FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) §*FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk ¨*FDCANCCU_CSTAT_CALS_Pos (30U) ©*FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) ª*FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk *FDCANCCU_CWD_WDC_Pos (0U) ®*FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) ¯*FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk °*FDCANCCU_CWD_WDV_Pos (16U) ±*FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) ²*FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk µ*FDCANCCU_IR_CWE_Pos (0U) ¶*FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) ·*FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk ¸*FDCANCCU_IR_CSC_Pos (1U) ¹*FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) º*FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk ½*FDCANCCU_IE_CWEE_Pos (0U) ¾*FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) ¿*FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk À*FDCANCCU_IE_CSCE_Pos (1U) Á*FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) Â*FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk Ë*CEC_CR_CECEN_Pos (0U) Ì*CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) Í*CEC_CR_CECEN CEC_CR_CECEN_Msk Î*CEC_CR_TXSOM_Pos (1U) Ï*CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) Ð*CEC_CR_TXSOM CEC_CR_TXSOM_Msk Ñ*CEC_CR_TXEOM_Pos (2U) Ò*CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) Ó*CEC_CR_TXEOM CEC_CR_TXEOM_Msk Ö*CEC_CFGR_SFT_Pos (0U) ×*CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) Ø*CEC_CFGR_SFT CEC_CFGR_SFT_Msk Ù*CEC_CFGR_RXTOL_Pos (3U) Ú*CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) Û*CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk Ü*CEC_CFGR_BRESTP_Pos (4U) Ý*CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) Þ*CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk ß*CEC_CFGR_BREGEN_Pos (5U) à*CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) á*CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk â*CEC_CFGR_LBPEGEN_Pos (6U) ã*CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) ä*CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk å*CEC_CFGR_SFTOPT_Pos (8U) æ*CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) ç*CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk è*CEC_CFGR_BRDNOGEN_Pos (7U) é*CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) ê*CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk ë*CEC_CFGR_OAR_Pos (16U) ì*CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) í*CEC_CFGR_OAR CEC_CFGR_OAR_Msk î*CEC_CFGR_LSTN_Pos (31U) ï*CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) ð*CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk ó*CEC_TXDR_TXD_Pos (0U) ô*CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) õ*CEC_TXDR_TXD CEC_TXDR_TXD_Msk ø*CEC_RXDR_RXD_Pos (0U) ù*CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) ú*CEC_RXDR_RXD CEC_RXDR_RXD_Msk ý*CEC_ISR_RXBR_Pos (0U) þ*CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) ÿ*CEC_ISR_RXBR CEC_ISR_RXBR_Msk +CEC_ISR_RXEND_Pos (1U) +CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) +CEC_ISR_RXEND CEC_ISR_RXEND_Msk +CEC_ISR_RXOVR_Pos (2U) +CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
+CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk +CEC_ISR_BRE_Pos (3U) +CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) +CEC_ISR_BRE CEC_ISR_BRE_Msk +CEC_ISR_SBPE_Pos (4U) +CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) +CEC_ISR_SBPE CEC_ISR_SBPE_Msk +CEC_ISR_LBPE_Pos (5U) +CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) +CEC_ISR_LBPE CEC_ISR_LBPE_Msk +CEC_ISR_RXACKE_Pos (6U) +CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) +CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk +CEC_ISR_ARBLST_Pos (7U) +CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) +CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk +CEC_ISR_TXBR_Pos (8U) +CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) +CEC_ISR_TXBR CEC_ISR_TXBR_Msk +CEC_ISR_TXEND_Pos (9U) +CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) +CEC_ISR_TXEND CEC_ISR_TXEND_Msk +CEC_ISR_TXUDR_Pos (10U) +CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) +CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk +CEC_ISR_TXERR_Pos (11U) +CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) +CEC_ISR_TXERR CEC_ISR_TXERR_Msk ¡+CEC_ISR_TXACKE_Pos (12U) ¢+CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) £+CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk ¦+CEC_IER_RXBRIE_Pos (0U) §+CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) ¨+CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk ©+CEC_IER_RXENDIE_Pos (1U) ª+CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) «+CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk ¬+CEC_IER_RXOVRIE_Pos (2U) +CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) ®+CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk ¯+CEC_IER_BREIE_Pos (3U) °+CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) ±+CEC_IER_BREIE CEC_IER_BREIE_Msk ²+CEC_IER_SBPEIE_Pos (4U) ³+CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) ´+CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk µ+CEC_IER_LBPEIE_Pos (5U) ¶+CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) ·+CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk ¸+CEC_IER_RXACKEIE_Pos (6U) ¹+CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) º+CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk »+CEC_IER_ARBLSTIE_Pos (7U) ¼+CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) ½+CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk ¾+CEC_IER_TXBRIE_Pos (8U) ¿+CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) À+CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk Á+CEC_IER_TXENDIE_Pos (9U) Â+CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) Ã+CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk Ä+CEC_IER_TXUDRIE_Pos (10U) Å+CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) Æ+CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk Ç+CEC_IER_TXERRIE_Pos (11U) È+CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) É+CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk Ê+CEC_IER_TXACKEIE_Pos (12U) Ë+CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) Ì+CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk Ô+CRC_DR_DR_Pos (0U) Õ+CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) Ö+CRC_DR_DR CRC_DR_DR_Msk Ù+CRC_IDR_IDR_Pos (0U) Ú+CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) Û+CRC_IDR_IDR CRC_IDR_IDR_Msk Þ+CRC_CR_RESET_Pos (0U) ß+CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) à+CRC_CR_RESET CRC_CR_RESET_Msk á+CRC_CR_POLYSIZE_Pos (3U) â+CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) ã+CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk ä+CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) å+CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) æ+CRC_CR_REV_IN_Pos (5U) ç+CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) è+CRC_CR_REV_IN CRC_CR_REV_IN_Msk é+CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) ê+CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) ë+CRC_CR_REV_OUT_Pos (7U) ì+CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) í+CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk ð+CRC_INIT_INIT_Pos (0U) ñ+CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) ò+CRC_INIT_INIT CRC_INIT_INIT_Msk õ+CRC_POL_POL_Pos (0U) ö+CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) ÷+CRC_POL_POL CRC_POL_POL_Msk ÿ+CRS_CR_SYNCOKIE_Pos (0U) ,CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) ,CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk ,CRS_CR_SYNCWARNIE_Pos (1U) ,CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) ,CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
,CRS_CR_ERRIE_Pos (2U) ,CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) ,CRS_CR_ERRIE CRS_CR_ERRIE_Msk ,CRS_CR_ESYNCIE_Pos (3U) ,CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) ,CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk ,CRS_CR_CEN_Pos (5U) ,CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) ,CRS_CR_CEN CRS_CR_CEN_Msk ,CRS_CR_AUTOTRIMEN_Pos (6U) ,CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) ,CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk ,CRS_CR_SWSYNC_Pos (7U) ,CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) ,CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk ,CRS_CR_TRIM_Pos (8U) ,CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) ,CRS_CR_TRIM CRS_CR_TRIM_Msk ,CRS_CFGR_RELOAD_Pos (0U) ,CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) ,CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk ,CRS_CFGR_FELIM_Pos (16U) ,CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) ,CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk ,CRS_CFGR_SYNCDIV_Pos (24U) ¡,CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) ¢,CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk £,CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) ¤,CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) ¥,CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) §,CRS_CFGR_SYNCSRC_Pos (28U) ¨,CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) ©,CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk ª,CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) «,CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) ,CRS_CFGR_SYNCPOL_Pos (31U) ®,CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) ¯,CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk ²,CRS_ISR_SYNCOKF_Pos (0U) ³,CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) ´,CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk µ,CRS_ISR_SYNCWARNF_Pos (1U) ¶,CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) ·,CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk ¸,CRS_ISR_ERRF_Pos (2U) ¹,CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) º,CRS_ISR_ERRF CRS_ISR_ERRF_Msk »,CRS_ISR_ESYNCF_Pos (3U) ¼,CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) ½,CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk ¾,CRS_ISR_SYNCERR_Pos (8U) ¿,CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) À,CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk Á,CRS_ISR_SYNCMISS_Pos (9U) Â,CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) Ã,CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk Ä,CRS_ISR_TRIMOVF_Pos (10U) Å,CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) Æ,CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk Ç,CRS_ISR_FEDIR_Pos (15U) È,CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) É,CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk Ê,CRS_ISR_FECAP_Pos (16U) Ë,CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) Ì,CRS_ISR_FECAP CRS_ISR_FECAP_Msk Ï,CRS_ICR_SYNCOKC_Pos (0U) Ð,CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) Ñ,CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk Ò,CRS_ICR_SYNCWARNC_Pos (1U) Ó,CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) Ô,CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk Õ,CRS_ICR_ERRC_Pos (2U) Ö,CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) ×,CRS_ICR_ERRC CRS_ICR_ERRC_Msk Ø,CRS_ICR_ESYNCC_Pos (3U) Ù,CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) Ú,CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk â,DAC_CR_EN1_Pos (0U) ã,DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) ä,DAC_CR_EN1 DAC_CR_EN1_Msk å,DAC_CR_TEN1_Pos (1U) æ,DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) ç,DAC_CR_TEN1 DAC_CR_TEN1_Msk é,DAC_CR_TSEL1_Pos (2U) ê,DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) ë,DAC_CR_TSEL1 DAC_CR_TSEL1_Msk ì,DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) í,DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) î,DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) ï,DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) ò,DAC_CR_WAVE1_Pos (6U) ó,DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) ô,DAC_CR_WAVE1 DAC_CR_WAVE1_Msk õ,DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) ö,DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) ø,DAC_CR_MAMP1_Pos (8U) ù,DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) ú,DAC_CR_MAMP1 DAC_CR_MAMP1_Msk û,DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) ü,DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) ý,DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) þ,DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) -DAC_CR_DMAEN1_Pos (12U) -DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) -DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk -DAC_CR_DMAUDRIE1_Pos (13U) -DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
-DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk -DAC_CR_CEN1_Pos (14U) -DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) -DAC_CR_CEN1 DAC_CR_CEN1_Msk -DAC_CR_EN2_Pos (16U) -DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) -DAC_CR_EN2 DAC_CR_EN2_Msk -DAC_CR_TEN2_Pos (17U) -DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) -DAC_CR_TEN2 DAC_CR_TEN2_Msk -DAC_CR_TSEL2_Pos (18U) -DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) -DAC_CR_TSEL2 DAC_CR_TSEL2_Msk -DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) -DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) -DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) -DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) -DAC_CR_WAVE2_Pos (22U) -DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) -DAC_CR_WAVE2 DAC_CR_WAVE2_Msk -DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) -DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) -DAC_CR_MAMP2_Pos (24U) ¡-DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) ¢-DAC_CR_MAMP2 DAC_CR_MAMP2_Msk £-DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) ¤-DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) ¥-DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) ¦-DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) ¨-DAC_CR_DMAEN2_Pos (28U) ©-DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) ª-DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk «-DAC_CR_DMAUDRIE2_Pos (29U) ¬-DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) -DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk ®-DAC_CR_CEN2_Pos (30U) ¯-DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) °-DAC_CR_CEN2 DAC_CR_CEN2_Msk ³-DAC_SWTRIGR_SWTRIG1_Pos (0U) ´-DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) µ-DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk ¶-DAC_SWTRIGR_SWTRIG2_Pos (1U) ·-DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) ¸-DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk »-DAC_DHR12R1_DACC1DHR_Pos (0U) ¼-DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) ½-DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk À-DAC_DHR12L1_DACC1DHR_Pos (4U) Á-DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) Â-DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk Å-DAC_DHR8R1_DACC1DHR_Pos (0U) Æ-DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) Ç-DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk Ê-DAC_DHR12R2_DACC2DHR_Pos (0U) Ë-DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) Ì-DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk Ï-DAC_DHR12L2_DACC2DHR_Pos (4U) Ð-DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) Ñ-DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk Ô-DAC_DHR8R2_DACC2DHR_Pos (0U) Õ-DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) Ö-DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk Ù-DAC_DHR12RD_DACC1DHR_Pos (0U) Ú-DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) Û-DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk Ü-DAC_DHR12RD_DACC2DHR_Pos (16U) Ý-DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) Þ-DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk á-DAC_DHR12LD_DACC1DHR_Pos (4U) â-DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) ã-DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk ä-DAC_DHR12LD_DACC2DHR_Pos (20U) å-DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) æ-DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk é-DAC_DHR8RD_DACC1DHR_Pos (0U) ê-DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) ë-DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk ì-DAC_DHR8RD_DACC2DHR_Pos (8U) í-DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) î-DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk ñ-DAC_DOR1_DACC1DOR_Pos (0U) ò-DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) ó-DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk ö-DAC_DOR2_DACC2DOR_Pos (0U) ÷-DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) ø-DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk û-DAC_SR_DMAUDR1_Pos (13U) ü-DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) ý-DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk þ-DAC_SR_CAL_FLAG1_Pos (14U) ÿ-DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) .DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk .DAC_SR_BWST1_Pos (15U) .DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) .DAC_SR_BWST1 DAC_SR_BWST1_Msk
.DAC_SR_DMAUDR2_Pos (29U) .DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) .DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk .DAC_SR_CAL_FLAG2_Pos (30U) .DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) .DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk .DAC_SR_BWST2_Pos (31U) .DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) .DAC_SR_BWST2 DAC_SR_BWST2_Msk .DAC_CCR_OTRIM1_Pos (0U) .DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) .DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk .DAC_CCR_OTRIM2_Pos (16U) .DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) .DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk .DAC_MCR_MODE1_Pos (0U) .DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) .DAC_MCR_MODE1 DAC_MCR_MODE1_Msk .DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) .DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) .DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) .DAC_MCR_MODE2_Pos (16U) .DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) ¡.DAC_MCR_MODE2 DAC_MCR_MODE2_Msk ¢.DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) £.DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) ¤.DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) §.DAC_SHSR1_TSAMPLE1_Pos (0U) ¨.DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) ©.DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk ¬.DAC_SHSR2_TSAMPLE2_Pos (0U) .DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) ®.DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk ±.DAC_SHHR_THOLD1_Pos (0U) ².DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) ³.DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk ´.DAC_SHHR_THOLD2_Pos (16U) µ.DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) ¶.DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk ¹.DAC_SHRR_TREFRESH1_Pos (0U) º.DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) ».DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk ¼.DAC_SHRR_TREFRESH2_Pos (16U) ½.DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) ¾.DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk Æ.DCMI_CR_CAPTURE_Pos (0U) Ç.DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) È.DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk É.DCMI_CR_CM_Pos (1U) Ê.DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) Ë.DCMI_CR_CM DCMI_CR_CM_Msk Ì.DCMI_CR_CROP_Pos (2U) Í.DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) Î.DCMI_CR_CROP DCMI_CR_CROP_Msk Ï.DCMI_CR_JPEG_Pos (3U) Ð.DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) Ñ.DCMI_CR_JPEG DCMI_CR_JPEG_Msk Ò.DCMI_CR_ESS_Pos (4U) Ó.DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) Ô.DCMI_CR_ESS DCMI_CR_ESS_Msk Õ.DCMI_CR_PCKPOL_Pos (5U) Ö.DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) ×.DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk Ø.DCMI_CR_HSPOL_Pos (6U) Ù.DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) Ú.DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk Û.DCMI_CR_VSPOL_Pos (7U) Ü.DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) Ý.DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk Þ.DCMI_CR_FCRC_0 (0x00000100U) ß.DCMI_CR_FCRC_1 (0x00000200U) à.DCMI_CR_EDM_0 (0x00000400U) á.DCMI_CR_EDM_1 (0x00000800U) â.DCMI_CR_CRE_Pos (12U) ã.DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) ä.DCMI_CR_CRE DCMI_CR_CRE_Msk å.DCMI_CR_ENABLE_Pos (14U) æ.DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) ç.DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk è.DCMI_CR_BSM_Pos (16U) é.DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) ê.DCMI_CR_BSM DCMI_CR_BSM_Msk ë.DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) ì.DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) í.DCMI_CR_OEBS_Pos (18U) î.DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) ï.DCMI_CR_OEBS DCMI_CR_OEBS_Msk ð.DCMI_CR_LSM_Pos (19U) ñ.DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) ò.DCMI_CR_LSM DCMI_CR_LSM_Msk ó.DCMI_CR_OELS_Pos (20U) ô.DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) õ.DCMI_CR_OELS DCMI_CR_OELS_Msk ø.DCMI_SR_HSYNC_Pos (0U) ù.DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) ú.DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk û.DCMI_SR_VSYNC_Pos (1U) ü.DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) ý.DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk þ.DCMI_SR_FNE_Pos (2U) ÿ.DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /DCMI_SR_FNE DCMI_SR_FNE_Msk /DCMI_RIS_FRAME_RIS_Pos (0U) /DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
/DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk /DCMI_RIS_OVR_RIS_Pos (1U) /DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk /DCMI_RIS_ERR_RIS_Pos (2U) /DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk /DCMI_RIS_VSYNC_RIS_Pos (3U) /DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk /DCMI_RIS_LINE_RIS_Pos (4U) /DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /DCMI_IER_FRAME_IE_Pos (0U) /DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk /DCMI_IER_OVR_IE_Pos (1U) /DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk /DCMI_IER_ERR_IE_Pos (2U) /DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk /DCMI_IER_VSYNC_IE_Pos (3U) /DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk /DCMI_IER_LINE_IE_Pos (4U) ¡/DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) ¢/DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk ¦/DCMI_MIS_FRAME_MIS_Pos (0U) §/DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) ¨/DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk ©/DCMI_MIS_OVR_MIS_Pos (1U) ª/DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) «/DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk ¬/DCMI_MIS_ERR_MIS_Pos (2U) /DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) ®/DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk ¯/DCMI_MIS_VSYNC_MIS_Pos (3U) °/DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) ±/DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk ²/DCMI_MIS_LINE_MIS_Pos (4U) ³/DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) ´/DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk ¸/DCMI_ICR_FRAME_ISC_Pos (0U) ¹/DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) º/DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk »/DCMI_ICR_OVR_ISC_Pos (1U) ¼/DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) ½/DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk ¾/DCMI_ICR_ERR_ISC_Pos (2U) ¿/DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) À/DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk Á/DCMI_ICR_VSYNC_ISC_Pos (3U) Â/DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) Ã/DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk Ä/DCMI_ICR_LINE_ISC_Pos (4U) Å/DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) Æ/DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk Ê/DCMI_ESCR_FSC_Pos (0U) Ë/DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) Ì/DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk Í/DCMI_ESCR_LSC_Pos (8U) Î/DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) Ï/DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk Ð/DCMI_ESCR_LEC_Pos (16U) Ñ/DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) Ò/DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk Ó/DCMI_ESCR_FEC_Pos (24U) Ô/DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) Õ/DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk Ø/DCMI_ESUR_FSU_Pos (0U) Ù/DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) Ú/DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk Û/DCMI_ESUR_LSU_Pos (8U) Ü/DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) Ý/DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk Þ/DCMI_ESUR_LEU_Pos (16U) ß/DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) à/DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk á/DCMI_ESUR_FEU_Pos (24U) â/DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) ã/DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk æ/DCMI_CWSTRT_HOFFCNT_Pos (0U) ç/DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) è/DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk é/DCMI_CWSTRT_VST_Pos (16U) ê/DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) ë/DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk î/DCMI_CWSIZE_CAPCNT_Pos (0U) ï/DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) ð/DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk ñ/DCMI_CWSIZE_VLINE_Pos (16U) ò/DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) ó/DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk ö/DCMI_DR_BYTE0_Pos (0U) ÷/DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) ø/DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk ù/DCMI_DR_BYTE1_Pos (8U) ú/DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) û/DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk ü/DCMI_DR_BYTE2_Pos (16U) ý/DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) þ/DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk ÿ/DCMI_DR_BYTE3_Pos (24U) 0DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) 0DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk 0DFSDM_CHCFGR1_DFSDMEN_Pos (31U) 0DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) 0DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk 0DFSDM_CHCFGR1_CKOUTSRC_Pos (30U) 0DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) 0DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk 0DFSDM_CHCFGR1_CKOUTDIV_Pos (16U) 0DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) 0DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk 0DFSDM_CHCFGR1_DATPACK_Pos (14U) 0DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) 0DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk 0DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) 0DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) 0DFSDM_CHCFGR1_DATMPX_Pos (12U) 0DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) 0DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk 0DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) 0DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) 0DFSDM_CHCFGR1_CHINSEL_Pos (8U) 0DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) ¡0DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk ¢0DFSDM_CHCFGR1_CHEN_Pos (7U) £0DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) ¤0DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk ¥0DFSDM_CHCFGR1_CKABEN_Pos (6U) ¦0DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) §0DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk ¨0DFSDM_CHCFGR1_SCDEN_Pos (5U) ©0DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) ª0DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk «0DFSDM_CHCFGR1_SPICKSEL_Pos (2U) ¬0DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) 0DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk ®0DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) ¯0DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) °0DFSDM_CHCFGR1_SITP_Pos (0U) ±0DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) ²0DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk ³0DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) ´0DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) ·0DFSDM_CHCFGR2_OFFSET_Pos (8U) ¸0DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) ¹0DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk º0DFSDM_CHCFGR2_DTRBS_Pos (3U) »0DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) ¼0DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk ¿0DFSDM_CHAWSCDR_AWFORD_Pos (22U) À0DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) Á0DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk Â0DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) Ã0DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) Ä0DFSDM_CHAWSCDR_AWFOSR_Pos (16U) Å0DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) Æ0DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk Ç0DFSDM_CHAWSCDR_BKSCD_Pos (12U) È0DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) É0DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk Ê0DFSDM_CHAWSCDR_SCDT_Pos (0U) Ë0DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) Ì0DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk Ï0DFSDM_CHWDATR_WDATA_Pos (0U) Ð0DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) Ñ0DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk Ô0DFSDM_CHDATINR_INDAT0_Pos (0U) Õ0DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) Ö0DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk ×0DFSDM_CHDATINR_INDAT1_Pos (16U) Ø0DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) Ù0DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk Þ0DFSDM_FLTCR1_AWFSEL_Pos (30U) ß0DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) à0DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk á0DFSDM_FLTCR1_FAST_Pos (29U) â0DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) ã0DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk ä0DFSDM_FLTCR1_RCH_Pos (24U) å0DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) æ0DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk ç0DFSDM_FLTCR1_RDMAEN_Pos (21U) è0DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) é0DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk ê0DFSDM_FLTCR1_RSYNC_Pos (19U) ë0DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) ì0DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk í0DFSDM_FLTCR1_RCONT_Pos (18U) î0DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) ï0DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk ð0DFSDM_FLTCR1_RSWSTART_Pos (17U) ñ0DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) ò0DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk ó0DFSDM_FLTCR1_JEXTEN_Pos (13U) ô0DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) õ0DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk ö0DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) ÷0DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) ø0DFSDM_FLTCR1_JEXTSEL_Pos (8U) ù0DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) ú0DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk û0DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) ü0DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) ý0DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) þ0DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) ÿ0DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) 1DFSDM_FLTCR1_JDMAEN_Pos (5U) 1DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) 1DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk 1DFSDM_FLTCR1_JSCAN_Pos (4U)
1DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) 1DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk 1DFSDM_FLTCR1_JSYNC_Pos (3U) 1DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) 1DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk 1DFSDM_FLTCR1_JSWSTART_Pos (1U) 1DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) 1DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk 1DFSDM_FLTCR1_DFEN_Pos (0U) 1DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) 1DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk 1DFSDM_FLTCR2_AWDCH_Pos (16U) 1DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) 1DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk 1DFSDM_FLTCR2_EXCH_Pos (8U) 1DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) 1DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk 1DFSDM_FLTCR2_CKABIE_Pos (6U) 1DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) 1DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk 1DFSDM_FLTCR2_SCDIE_Pos (5U) 1DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) 1DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk 1DFSDM_FLTCR2_AWDIE_Pos (4U) 1DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) 1DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk ¡1DFSDM_FLTCR2_ROVRIE_Pos (3U) ¢1DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) £1DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk ¤1DFSDM_FLTCR2_JOVRIE_Pos (2U) ¥1DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) ¦1DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk §1DFSDM_FLTCR2_REOCIE_Pos (1U) ¨1DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) ©1DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk ª1DFSDM_FLTCR2_JEOCIE_Pos (0U) «1DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) ¬1DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk ¯1DFSDM_FLTISR_SCDF_Pos (24U) °1DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) ±1DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk ²1DFSDM_FLTISR_CKABF_Pos (16U) ³1DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) ´1DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk µ1DFSDM_FLTISR_RCIP_Pos (14U) ¶1DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) ·1DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk ¸1DFSDM_FLTISR_JCIP_Pos (13U) ¹1DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) º1DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk »1DFSDM_FLTISR_AWDF_Pos (4U) ¼1DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) ½1DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk ¾1DFSDM_FLTISR_ROVRF_Pos (3U) ¿1DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) À1DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk Á1DFSDM_FLTISR_JOVRF_Pos (2U) Â1DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) Ã1DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk Ä1DFSDM_FLTISR_REOCF_Pos (1U) Å1DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) Æ1DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk Ç1DFSDM_FLTISR_JEOCF_Pos (0U) È1DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) É1DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk Ì1DFSDM_FLTICR_CLRSCDF_Pos (24U) Í1DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) Î1DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk Ï1DFSDM_FLTICR_CLRCKABF_Pos (16U) Ð1DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) Ñ1DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk Ò1DFSDM_FLTICR_CLRROVRF_Pos (3U) Ó1DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) Ô1DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk Õ1DFSDM_FLTICR_CLRJOVRF_Pos (2U) Ö1DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) ×1DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk Ú1DFSDM_FLTJCHGR_JCHG_Pos (0U) Û1DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) Ü1DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk ß1DFSDM_FLTFCR_FORD_Pos (29U) à1DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) á1DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk â1DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) ã1DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) ä1DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) å1DFSDM_FLTFCR_FOSR_Pos (16U) æ1DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) ç1DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk è1DFSDM_FLTFCR_IOSR_Pos (0U) é1DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) ê1DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk í1DFSDM_FLTJDATAR_JDATA_Pos (8U) î1DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) ï1DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk ð1DFSDM_FLTJDATAR_JDATACH_Pos (0U) ñ1DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) ò1DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk õ1DFSDM_FLTRDATAR_RDATA_Pos (8U) ö1DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) ÷1DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk ø1DFSDM_FLTRDATAR_RPEND_Pos (4U) ù1DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) ú1DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk û1DFSDM_FLTRDATAR_RDATACH_Pos (0U) ü1DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) ý1DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk 2DFSDM_FLTAWHTR_AWHT_Pos (8U) 2DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) 2DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk 2DFSDM_FLTAWHTR_BKAWH_Pos (0U) 2DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
2DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk 2DFSDM_FLTAWLTR_AWLT_Pos (8U) 2DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) 2DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk 2DFSDM_FLTAWLTR_BKAWL_Pos (0U) 2DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) 2DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk 2DFSDM_FLTAWSR_AWHTF_Pos (8U) 2DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) 2DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk 2DFSDM_FLTAWSR_AWLTF_Pos (0U) 2DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) 2DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk 2DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U) 2DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) 2DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk 2DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U) 2DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) 2DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk 2DFSDM_FLTEXMAX_EXMAX_Pos (8U) ¡2DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) ¢2DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk £2DFSDM_FLTEXMAX_EXMAXCH_Pos (0U) ¤2DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) ¥2DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk ¨2DFSDM_FLTEXMIN_EXMIN_Pos (8U) ©2DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) ª2DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk «2DFSDM_FLTEXMIN_EXMINCH_Pos (0U) ¬2DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) 2DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk °2DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U) ±2DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) ²2DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk »2BDMA_ISR_GIF0_Pos (0U) ¼2BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) ½2BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk ¾2BDMA_ISR_TCIF0_Pos (1U) ¿2BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) À2BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk Á2BDMA_ISR_HTIF0_Pos (2U) Â2BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) Ã2BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk Ä2BDMA_ISR_TEIF0_Pos (3U) Å2BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) Æ2BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk Ç2BDMA_ISR_GIF1_Pos (4U) È2BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) É2BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk Ê2BDMA_ISR_TCIF1_Pos (5U) Ë2BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) Ì2BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk Í2BDMA_ISR_HTIF1_Pos (6U) Î2BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) Ï2BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk Ð2BDMA_ISR_TEIF1_Pos (7U) Ñ2BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) Ò2BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk Ó2BDMA_ISR_GIF2_Pos (8U) Ô2BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) Õ2BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk Ö2BDMA_ISR_TCIF2_Pos (9U) ×2BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) Ø2BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk Ù2BDMA_ISR_HTIF2_Pos (10U) Ú2BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) Û2BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk Ü2BDMA_ISR_TEIF2_Pos (11U) Ý2BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) Þ2BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk ß2BDMA_ISR_GIF3_Pos (12U) à2BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) á2BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk â2BDMA_ISR_TCIF3_Pos (13U) ã2BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) ä2BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk å2BDMA_ISR_HTIF3_Pos (14U) æ2BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) ç2BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk è2BDMA_ISR_TEIF3_Pos (15U) é2BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) ê2BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk ë2BDMA_ISR_GIF4_Pos (16U) ì2BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) í2BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk î2BDMA_ISR_TCIF4_Pos (17U) ï2BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) ð2BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk ñ2BDMA_ISR_HTIF4_Pos (18U) ò2BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) ó2BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk ô2BDMA_ISR_TEIF4_Pos (19U) õ2BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) ö2BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk ÷2BDMA_ISR_GIF5_Pos (20U) ø2BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) ù2BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk ú2BDMA_ISR_TCIF5_Pos (21U) û2BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) ü2BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk ý2BDMA_ISR_HTIF5_Pos (22U) þ2BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) ÿ2BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk 3BDMA_ISR_TEIF5_Pos (23U) 3BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) 3BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk 3BDMA_ISR_GIF6_Pos (24U) 3BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
3BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk 3BDMA_ISR_TCIF6_Pos (25U) 3BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) 3BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk 3BDMA_ISR_HTIF6_Pos (26U) 3BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) 3BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk 3BDMA_ISR_TEIF6_Pos (27U) 3BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) 3BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk 3BDMA_ISR_GIF7_Pos (28U) 3BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) 3BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk 3BDMA_ISR_TCIF7_Pos (29U) 3BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) 3BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk 3BDMA_ISR_HTIF7_Pos (30U) 3BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) 3BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk 3BDMA_ISR_TEIF7_Pos (31U) 3BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) 3BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk 3BDMA_IFCR_CGIF0_Pos (0U) 3BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) 3BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk 3BDMA_IFCR_CTCIF0_Pos (1U) ¡3BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) ¢3BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk £3BDMA_IFCR_CHTIF0_Pos (2U) ¤3BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) ¥3BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk ¦3BDMA_IFCR_CTEIF0_Pos (3U) §3BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) ¨3BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk ©3BDMA_IFCR_CGIF1_Pos (4U) ª3BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) «3BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk ¬3BDMA_IFCR_CTCIF1_Pos (5U) 3BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) ®3BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk ¯3BDMA_IFCR_CHTIF1_Pos (6U) °3BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) ±3BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk ²3BDMA_IFCR_CTEIF1_Pos (7U) ³3BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) ´3BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk µ3BDMA_IFCR_CGIF2_Pos (8U) ¶3BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) ·3BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk ¸3BDMA_IFCR_CTCIF2_Pos (9U) ¹3BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) º3BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk »3BDMA_IFCR_CHTIF2_Pos (10U) ¼3BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) ½3BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk ¾3BDMA_IFCR_CTEIF2_Pos (11U) ¿3BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) À3BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk Á3BDMA_IFCR_CGIF3_Pos (12U) Â3BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) Ã3BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk Ä3BDMA_IFCR_CTCIF3_Pos (13U) Å3BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) Æ3BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk Ç3BDMA_IFCR_CHTIF3_Pos (14U) È3BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) É3BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk Ê3BDMA_IFCR_CTEIF3_Pos (15U) Ë3BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) Ì3BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk Í3BDMA_IFCR_CGIF4_Pos (16U) Î3BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) Ï3BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk Ð3BDMA_IFCR_CTCIF4_Pos (17U) Ñ3BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) Ò3BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk Ó3BDMA_IFCR_CHTIF4_Pos (18U) Ô3BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) Õ3BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk Ö3BDMA_IFCR_CTEIF4_Pos (19U) ×3BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) Ø3BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk Ù3BDMA_IFCR_CGIF5_Pos (20U) Ú3BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) Û3BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk Ü3BDMA_IFCR_CTCIF5_Pos (21U) Ý3BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) Þ3BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk ß3BDMA_IFCR_CHTIF5_Pos (22U) à3BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) á3BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk â3BDMA_IFCR_CTEIF5_Pos (23U) ã3BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) ä3BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk å3BDMA_IFCR_CGIF6_Pos (24U) æ3BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) ç3BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk è3BDMA_IFCR_CTCIF6_Pos (25U) é3BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) ê3BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk ë3BDMA_IFCR_CHTIF6_Pos (26U) ì3BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) í3BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk î3BDMA_IFCR_CTEIF6_Pos (27U) ï3BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) ð3BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk ñ3BDMA_IFCR_CGIF7_Pos (28U) ò3BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) ó3BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk ô3BDMA_IFCR_CTCIF7_Pos (29U) õ3BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) ö3BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk ÷3BDMA_IFCR_CHTIF7_Pos (30U) ø3BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) ù3BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk ú3BDMA_IFCR_CTEIF7_Pos (31U) û3BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) ü3BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk ÿ3BDMA_CCR_EN_Pos (0U) 4BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) 4BDMA_CCR_EN BDMA_CCR_EN_Msk 4BDMA_CCR_TCIE_Pos (1U) 4BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) 4BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
4BDMA_CCR_HTIE_Pos (2U) 4BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) 4BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk 4BDMA_CCR_TEIE_Pos (3U) 4BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) 4BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk 4BDMA_CCR_DIR_Pos (4U) 4BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) 4BDMA_CCR_DIR BDMA_CCR_DIR_Msk 4BDMA_CCR_CIRC_Pos (5U) 4BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) 4BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk 4BDMA_CCR_PINC_Pos (6U) 4BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) 4BDMA_CCR_PINC BDMA_CCR_PINC_Msk 4BDMA_CCR_MINC_Pos (7U) 4BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) 4BDMA_CCR_MINC BDMA_CCR_MINC_Msk 4BDMA_CCR_PSIZE_Pos (8U) 4BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) 4BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk 4BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) 4BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) 4BDMA_CCR_MSIZE_Pos (10U) 4BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) 4BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk ¡4BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) ¢4BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) ¤4BDMA_CCR_PL_Pos (12U) ¥4BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) ¦4BDMA_CCR_PL BDMA_CCR_PL_Msk §4BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) ¨4BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) ª4BDMA_CCR_MEM2MEM_Pos (14U) «4BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) ¬4BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk 4BDMA_CCR_DBM_Pos (15U) ®4BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) ¯4BDMA_CCR_DBM BDMA_CCR_DBM_Msk °4BDMA_CCR_CT_Pos (16U) ±4BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) ²4BDMA_CCR_CT BDMA_CCR_CT_Msk µ4BDMA_CNDTR_NDT_Pos (0U) ¶4BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) ·4BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk º4BDMA_CPAR_PA_Pos (0U) »4BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) ¼4BDMA_CPAR_PA BDMA_CPAR_PA_Msk ¿4BDMA_CM0AR_MA_Pos (0U) À4BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) Á4BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk Ä4BDMA_CM1AR_MA_Pos (0U) Å4BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) Æ4BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk Î4ETH_MACCR_ARP_Pos (31U) Ï4ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) Ð4ETH_MACCR_ARP ETH_MACCR_ARP_Msk Ñ4ETH_MACCR_SARC_Pos (28U) Ò4ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) Ó4ETH_MACCR_SARC ETH_MACCR_SARC_Msk Ô4ETH_MACCR_SARC_MTIATI (0U) Õ4ETH_MACCR_SARC_INSADDR0_Pos (29U) Ö4ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) ×4ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk Ø4ETH_MACCR_SARC_INSADDR1_Pos (29U) Ù4ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) Ú4ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk Û4ETH_MACCR_SARC_REPADDR0_Pos (28U) Ü4ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) Ý4ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk Þ4ETH_MACCR_SARC_REPADDR1_Pos (28U) ß4ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) à4ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk á4ETH_MACCR_IPC_Pos (27U) â4ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) ã4ETH_MACCR_IPC ETH_MACCR_IPC_Msk ä4ETH_MACCR_IPG_Pos (24U) å4ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) æ4ETH_MACCR_IPG ETH_MACCR_IPG_Msk ç4ETH_MACCR_IPG_96BIT (0U) è4ETH_MACCR_IPG_88BIT (0x01000000U) é4ETH_MACCR_IPG_80BIT (0x02000000U) ê4ETH_MACCR_IPG_72BIT (0x03000000U) ë4ETH_MACCR_IPG_64BIT (0x04000000U) ì4ETH_MACCR_IPG_56BIT (0x05000000U) í4ETH_MACCR_IPG_48BIT (0x06000000U) î4ETH_MACCR_IPG_40BIT (0x07000000U) ï4ETH_MACCR_GPSLCE_Pos (23U) ð4ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) ñ4ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk ò4ETH_MACCR_S2KP_Pos (22U) ó4ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) ô4ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk õ4ETH_MACCR_CST_Pos (21U) ö4ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) ÷4ETH_MACCR_CST ETH_MACCR_CST_Msk ø4ETH_MACCR_ACS_Pos (20U) ù4ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) ú4ETH_MACCR_ACS ETH_MACCR_ACS_Msk û4ETH_MACCR_WD_Pos (19U) ü4ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) ý4ETH_MACCR_WD ETH_MACCR_WD_Msk þ4ETH_MACCR_JD_Pos (17U) ÿ4ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) 5ETH_MACCR_JD ETH_MACCR_JD_Msk 5ETH_MACCR_JE_Pos (16U) 5ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) 5ETH_MACCR_JE ETH_MACCR_JE_Msk 5ETH_MACCR_FES_Pos (14U)
5ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) 5ETH_MACCR_FES ETH_MACCR_FES_Msk 5ETH_MACCR_DM_Pos (13U) 5ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) 5ETH_MACCR_DM ETH_MACCR_DM_Msk 5ETH_MACCR_LM_Pos (12U) 5ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) 5ETH_MACCR_LM ETH_MACCR_LM_Msk 5ETH_MACCR_ECRSFD_Pos (11U) 5ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) 5ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk 5ETH_MACCR_DO_Pos (10U) 5ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) 5ETH_MACCR_DO ETH_MACCR_DO_Msk 5ETH_MACCR_DCRS_Pos (9U) 5ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) 5ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk 5ETH_MACCR_DR_Pos (8U) 5ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) 5ETH_MACCR_DR ETH_MACCR_DR_Msk 5ETH_MACCR_BL_Pos (5U) 5ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) 5ETH_MACCR_BL ETH_MACCR_BL_Msk 5ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) 5ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) 5ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) 5ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) 5ETH_MACCR_DC_Pos (4U) ¡5ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) ¢5ETH_MACCR_DC ETH_MACCR_DC_Msk £5ETH_MACCR_PRELEN_Pos (2U) ¤5ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) ¥5ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk ¦5ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) §5ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) ¨5ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) ©5ETH_MACCR_TE_Pos (1U) ª5ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) «5ETH_MACCR_TE ETH_MACCR_TE_Msk ¬5ETH_MACCR_RE_Pos (0U) 5ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) ®5ETH_MACCR_RE ETH_MACCR_RE_Msk ±5ETH_MACECR_EIPG_Pos (25U) ²5ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) ³5ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk ´5ETH_MACECR_EIPGEN_Pos (24U) µ5ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) ¶5ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk ·5ETH_MACECR_USP_Pos (18U) ¸5ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) ¹5ETH_MACECR_USP ETH_MACECR_USP_Msk º5ETH_MACECR_SPEN_Pos (17U) »5ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) ¼5ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk ½5ETH_MACECR_DCRCC_Pos (16U) ¾5ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) ¿5ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk À5ETH_MACECR_GPSL_Pos (0U) Á5ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) Â5ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk Å5ETH_MACPFR_RA_Pos (31U) Æ5ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) Ç5ETH_MACPFR_RA ETH_MACPFR_RA_Msk È5ETH_MACPFR_DNTU_Pos (21U) É5ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) Ê5ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk Ë5ETH_MACPFR_IPFE_Pos (20U) Ì5ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) Í5ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk Î5ETH_MACPFR_VTFE_Pos (16U) Ï5ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) Ð5ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk Ñ5ETH_MACPFR_HPF_Pos (10U) Ò5ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) Ó5ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk Ô5ETH_MACPFR_SAF_Pos (9U) Õ5ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) Ö5ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk ×5ETH_MACPFR_SAIF_Pos (8U) Ø5ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) Ù5ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk Ú5ETH_MACPFR_PCF_Pos (6U) Û5ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) Ü5ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk Ý5ETH_MACPFR_PCF_BLOCKALL (0U) Þ5ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) ß5ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) à5ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk á5ETH_MACPFR_PCF_FORWARDALL_Pos (7U) â5ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) ã5ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk ä5ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U) å5ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) æ5ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk ç5ETH_MACPFR_DBF_Pos (5U) è5ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) é5ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk ê5ETH_MACPFR_PM_Pos (4U) ë5ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) ì5ETH_MACPFR_PM ETH_MACPFR_PM_Msk í5ETH_MACPFR_DAIF_Pos (3U) î5ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) ï5ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk ð5ETH_MACPFR_HMC_Pos (2U) ñ5ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) ò5ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk ó5ETH_MACPFR_HUC_Pos (1U) ô5ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) õ5ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk ö5ETH_MACPFR_PR_Pos (0U) ÷5ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) ø5ETH_MACPFR_PR ETH_MACPFR_PR_Msk û5ETH_MACWTR_PWE_Pos (8U) ü5ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) ý5ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk þ5ETH_MACWTR_WTO_Pos (0U) ÿ5ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) 6ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk 6ETH_MACWTR_WTO_2KB (0U) 6ETH_MACWTR_WTO_3KB (0x00000001U) 6ETH_MACWTR_WTO_4KB (0x00000002U) 6ETH_MACWTR_WTO_5KB (0x00000003U)
6ETH_MACWTR_WTO_6KB (0x00000004U) 6ETH_MACWTR_WTO_7KB (0x00000005U) 6ETH_MACWTR_WTO_8KB (0x00000006U) 6ETH_MACWTR_WTO_9KB (0x00000007U) 6ETH_MACWTR_WTO_10KB (0x00000008U) 6ETH_MACWTR_WTO_11KB (0x00000009U) 6ETH_MACWTR_WTO_12KB (0x0000000AU) 6ETH_MACWTR_WTO_13KB (0x0000000BU) 6ETH_MACWTR_WTO_14KB (0x0000000CU) 6ETH_MACWTR_WTO_15KB (0x0000000DU) 6ETH_MACWTR_WTO_16KB (0x0000000EU) 6ETH_MACHTHR_HTH_Pos (0U) 6ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) 6ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk 6ETH_MACHTLR_HTL_Pos (0U) 6ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) 6ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk 6ETH_MACVTR_EIVLRXS_Pos (31U) 6ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) 6ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk 6ETH_MACVTR_EIVLS_Pos (28U) 6ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) ¡6ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk ¢6ETH_MACVTR_EIVLS_DONOTSTRIP (0U) £6ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) ¤6ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) ¥6ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk ¦6ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) §6ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) ¨6ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk ©6ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) ª6ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) «6ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk ¬6ETH_MACVTR_ERIVLT_Pos (27U) 6ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) ®6ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk ¯6ETH_MACVTR_EDVLP_Pos (26U) °6ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) ±6ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk ²6ETH_MACVTR_VTHM_Pos (25U) ³6ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) ´6ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk µ6ETH_MACVTR_EVLRXS_Pos (24U) ¶6ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) ·6ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk ¸6ETH_MACVTR_EVLS_Pos (21U) ¹6ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) º6ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk »6ETH_MACVTR_EVLS_DONOTSTRIP (0U) ¼6ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) ½6ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) ¾6ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk ¿6ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) À6ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) Á6ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk Â6ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) Ã6ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) Ä6ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk Å6ETH_MACVTR_DOVLTC_Pos (20U) Æ6ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) Ç6ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk È6ETH_MACVTR_ERSVLM_Pos (19U) É6ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) Ê6ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk Ë6ETH_MACVTR_ESVL_Pos (18U) Ì6ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) Í6ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk Î6ETH_MACVTR_VTIM_Pos (17U) Ï6ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) Ð6ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk Ñ6ETH_MACVTR_ETV_Pos (16U) Ò6ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) Ó6ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk Ô6ETH_MACVTR_VL_Pos (0U) Õ6ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) Ö6ETH_MACVTR_VL ETH_MACVTR_VL_Msk ×6ETH_MACVTR_VL_UP_Pos (13U) Ø6ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) Ù6ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk Ú6ETH_MACVTR_VL_CFIDEI_Pos (12U) Û6ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) Ü6ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk Ý6ETH_MACVTR_VL_VID_Pos (0U) Þ6ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) ß6ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk â6ETH_MACVHTR_VLHT_Pos (0U) ã6ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) ä6ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk ç6ETH_MACVIR_VLTI_Pos (20U) è6ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) é6ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk ê6ETH_MACVIR_CSVL_Pos (19U) ë6ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) ì6ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk í6ETH_MACVIR_VLP_Pos (18U) î6ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) ï6ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk ð6ETH_MACVIR_VLC_Pos (16U) ñ6ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) ò6ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk ó6ETH_MACVIR_VLC_NOVLANTAG (0U) ô6ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) õ6ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) ö6ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk ÷6ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) ø6ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) ù6ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk ú6ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) û6ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) ü6ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk ý6ETH_MACVIR_VLT_Pos (0U) þ6ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) ÿ6ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk 7ETH_MACVIR_VLT_UP_Pos (13U) 7ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) 7ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk 7ETH_MACVIR_VLT_CFIDEI_Pos (12U) 7ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
7ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk 7ETH_MACVIR_VLT_VID_Pos (0U) 7ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) 7ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk 7ETH_MACIVIR_VLTI_Pos (20U) 7ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) 7ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk 7ETH_MACIVIR_CSVL_Pos (19U) 7ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) 7ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk 7ETH_MACIVIR_VLP_Pos (18U) 7ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) 7ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk 7ETH_MACIVIR_VLC_Pos (16U) 7ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) 7ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk 7ETH_MACIVIR_VLC_NOVLANTAG (0U) 7ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) 7ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) 7ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk 7ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U) 7ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) 7ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk 7ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U) 7ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) 7ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk ¡7ETH_MACIVIR_VLT_Pos (0U) ¢7ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) £7ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk ¤7ETH_MACIVIR_VLT_UP_Pos (13U) ¥7ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) ¦7ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk §7ETH_MACIVIR_VLT_CFIDEI_Pos (12U) ¨7ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) ©7ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk ª7ETH_MACIVIR_VLT_VID_Pos (0U) «7ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) ¬7ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk ¯7ETH_MACTFCR_PT_Pos (16U) °7ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) ±7ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk ²7ETH_MACTFCR_DZPQ_Pos (7U) ³7ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) ´7ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk µ7ETH_MACTFCR_PLT_Pos (4U) ¶7ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) ·7ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk ¸7ETH_MACTFCR_PLT_MINUS4 (0U) ¹7ETH_MACTFCR_PLT_MINUS28_Pos (4U) º7ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) »7ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk ¼7ETH_MACTFCR_PLT_MINUS36_Pos (5U) ½7ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) ¾7ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk ¿7ETH_MACTFCR_PLT_MINUS144_Pos (4U) À7ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) Á7ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk Â7ETH_MACTFCR_PLT_MINUS256_Pos (6U) Ã7ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) Ä7ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk Å7ETH_MACTFCR_PLT_MINUS512_Pos (4U) Æ7ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) Ç7ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk È7ETH_MACTFCR_TFE_Pos (1U) É7ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) Ê7ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk Ë7ETH_MACTFCR_FCB_Pos (0U) Ì7ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) Í7ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk Ð7ETH_MACRFCR_UP_Pos (1U) Ñ7ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) Ò7ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk Ó7ETH_MACRFCR_RFE_Pos (0U) Ô7ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) Õ7ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk Ø7ETH_MACISR_RXSTSIS_Pos (14U) Ù7ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) Ú7ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk Û7ETH_MACISR_TXSTSIS_Pos (13U) Ü7ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) Ý7ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk Þ7ETH_MACISR_TSIS_Pos (12U) ß7ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) à7ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk á7ETH_MACISR_MMCTXIS_Pos (10U) â7ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) ã7ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk ä7ETH_MACISR_MMCRXIS_Pos (9U) å7ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) æ7ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk ç7ETH_MACISR_MMCIS_Pos (8U) è7ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) é7ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk ê7ETH_MACISR_LPIIS_Pos (5U) ë7ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) ì7ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk í7ETH_MACISR_PMTIS_Pos (4U) î7ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) ï7ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk ð7ETH_MACISR_PHYIS_Pos (3U) ñ7ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) ò7ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk õ7ETH_MACIER_RXSTSIE_Pos (14U) ö7ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) ÷7ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk ø7ETH_MACIER_TXSTSIE_Pos (13U) ù7ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) ú7ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk û7ETH_MACIER_TSIE_Pos (12U) ü7ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) ý7ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk þ7ETH_MACIER_LPIIE_Pos (5U) ÿ7ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) 8ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk 8ETH_MACIER_PMTIE_Pos (4U) 8ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) 8ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk 8ETH_MACIER_PHYIE_Pos (3U)
8ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) 8ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk 8ETH_MACRXTXSR_RWT_Pos (8U) 8ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) 8ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk 8ETH_MACRXTXSR_EXCOL_Pos (5U) 8ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) 8ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk 8ETH_MACRXTXSR_LCOL_Pos (4U) 8ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) 8ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk 8ETH_MACRXTXSR_EXDEF_Pos (3U) 8ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) 8ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk 8ETH_MACRXTXSR_LCARR_Pos (2U) 8ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) 8ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk 8ETH_MACRXTXSR_NCARR_Pos (1U) 8ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) 8ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk 8ETH_MACRXTXSR_TJT_Pos (0U) 8ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) 8ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk 8ETH_MACPCSR_RWKFILTRST_Pos (31U) ¡8ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) ¢8ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk £8ETH_MACPCSR_RWKPTR_Pos (24U) ¤8ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) ¥8ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk ¦8ETH_MACPCSR_RWKPFE_Pos (10U) §8ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) ¨8ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk ©8ETH_MACPCSR_GLBLUCAST_Pos (9U) ª8ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) «8ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk ¬8ETH_MACPCSR_RWKPRCVD_Pos (6U) 8ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) ®8ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk ¯8ETH_MACPCSR_MGKPRCVD_Pos (5U) °8ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) ±8ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk ²8ETH_MACPCSR_RWKPKTEN_Pos (2U) ³8ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) ´8ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk µ8ETH_MACPCSR_MGKPKTEN_Pos (1U) ¶8ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) ·8ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk ¸8ETH_MACPCSR_PWRDWN_Pos (0U) ¹8ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) º8ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk ½8ETH_MACRWUPFR_D_Pos (0U) ¾8ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) ¿8ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk Â8ETH_MACLCSR_LPITCSE_Pos (21U) Ã8ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) Ä8ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk Å8ETH_MACLCSR_LPITE_Pos (20U) Æ8ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) Ç8ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk È8ETH_MACLCSR_LPITXA_Pos (19U) É8ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) Ê8ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk Ë8ETH_MACLCSR_PLS_Pos (17U) Ì8ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) Í8ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk Î8ETH_MACLCSR_LPIEN_Pos (16U) Ï8ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) Ð8ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk Ñ8ETH_MACLCSR_RLPIST_Pos (9U) Ò8ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) Ó8ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk Ô8ETH_MACLCSR_TLPIST_Pos (8U) Õ8ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) Ö8ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk ×8ETH_MACLCSR_RLPIEX_Pos (3U) Ø8ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) Ù8ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk Ú8ETH_MACLCSR_RLPIEN_Pos (2U) Û8ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) Ü8ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk Ý8ETH_MACLCSR_TLPIEX_Pos (1U) Þ8ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) ß8ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk à8ETH_MACLCSR_TLPIEN_Pos (0U) á8ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) â8ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk å8ETH_MACLTCR_LST_Pos (16U) æ8ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) ç8ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk è8ETH_MACLTCR_TWT_Pos (0U) é8ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) ê8ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk í8ETH_MACLETR_LPIET_Pos (0U) î8ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) ï8ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk ò8ETH_MAC1USTCR_TIC1USCNTR_Pos (0U) ó8ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) ô8ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk ÷8ETH_MACVR_USERVER_Pos (8U) ø8ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) ù8ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk ú8ETH_MACVR_SNPSVER_Pos (0U) û8ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) ü8ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk ÿ8ETH_MACDR_TFCSTS_Pos (17U) 9ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) 9ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk 9ETH_MACDR_TFCSTS_IDLE (0U) 9ETH_MACDR_TFCSTS_WAIT_Pos (17U) 9ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
9ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk 9ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U) 9ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) 9ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk 9ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U) 9ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) 9ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk 9ETH_MACDR_TPESTS_Pos (16U) 9ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) 9ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk 9ETH_MACDR_RFCFCSTS_Pos (1U) 9ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) 9ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk 9ETH_MACDR_RPESTS_Pos (0U) 9ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) 9ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk 9ETH_MACHWF0R_ACTPHYSEL_Pos (28U) 9ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) 9ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk 9ETH_MACHWF0R_ACTPHYSEL_MII (0U) 9ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) 9ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) 9ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk 9ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U) 9ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) 9ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk ¡9ETH_MACHWF0R_SAVLANINS_Pos (27U) ¢9ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) £9ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk ¤9ETH_MACHWF0R_TSSTSSEL_Pos (25U) ¥9ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) ¦9ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk §9ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U) ¨9ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) ©9ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk ª9ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U) «9ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) ¬9ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk 9ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U) ®9ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) ¯9ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk °9ETH_MACHWF0R_MACADR64SEL_Pos (24U) ±9ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) ²9ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk ³9ETH_MACHWF0R_MACADR32SEL_Pos (23U) ´9ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) µ9ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk ¶9ETH_MACHWF0R_ADDMACADRSEL_Pos (18U) ·9ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) ¸9ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk ¹9ETH_MACHWF0R_RXCOESEL_Pos (16U) º9ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) »9ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk ¼9ETH_MACHWF0R_TXCOESEL_Pos (14U) ½9ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) ¾9ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk ¿9ETH_MACHWF0R_EEESEL_Pos (13U) À9ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) Á9ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk Â9ETH_MACHWF0R_TSSEL_Pos (12U) Ã9ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) Ä9ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk Å9ETH_MACHWF0R_ARPOFFSEL_Pos (9U) Æ9ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) Ç9ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk È9ETH_MACHWF0R_MMCSEL_Pos (8U) É9ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) Ê9ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk Ë9ETH_MACHWF0R_MGKSEL_Pos (7U) Ì9ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) Í9ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk Î9ETH_MACHWF0R_RWKSEL_Pos (6U) Ï9ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) Ð9ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk Ñ9ETH_MACHWF0R_SMASEL_Pos (5U) Ò9ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) Ó9ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk Ô9ETH_MACHWF0R_VLHASH_Pos (4U) Õ9ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) Ö9ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk ×9ETH_MACHWF0R_PCSSEL_Pos (3U) Ø9ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) Ù9ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk Ú9ETH_MACHWF0R_HDSEL_Pos (2U) Û9ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) Ü9ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk Ý9ETH_MACHWF0R_GMIISEL_Pos (1U) Þ9ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) ß9ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk à9ETH_MACHWF0R_MIISEL_Pos (0U) á9ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) â9ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk å9ETH_MACHWF1R_L3L4FNUM_Pos (27U) æ9ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) ç9ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk è9ETH_MACHWF1R_HASHTBLSZ_Pos (24U) é9ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) ê9ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk ë9ETH_MACHWF1R_AVSEL_Pos (20U) ì9ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) í9ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk î9ETH_MACHWF1R_DBGMEMA_Pos (19U) ï9ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) ð9ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk ñ9ETH_MACHWF1R_TSOEN_Pos (18U) ò9ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) ó9ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk ô9ETH_MACHWF1R_SPHEN_Pos (17U) õ9ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) ö9ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk ÷9ETH_MACHWF1R_DCBEN_Pos (16U) ø9ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) ù9ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk ú9ETH_MACHWF1R_ADDR64_Pos (14U) û9ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) ü9ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk ý9ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) þ9ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) ÿ9ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) :ETH_MACHWF1R_ADVTHWORD_Pos (13U) :ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) :ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk :ETH_MACHWF1R_PTOEN_Pos (12U) :ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
:ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk :ETH_MACHWF1R_OSTEN_Pos (11U) :ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) :ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk :ETH_MACHWF1R_TXFIFOSIZE_Pos (6U) :ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) :ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk :ETH_MACHWF1R_RXFIFOSIZE_Pos (0U) :ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) :ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk :ETH_MACHWF2R_AUXSNAPNUM_Pos (28U) :ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) :ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk :ETH_MACHWF2R_PPSOUTNUM_Pos (24U) :ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) :ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk :ETH_MACHWF2R_TXCHCNT_Pos (18U) :ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) :ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk :ETH_MACHWF2R_RXCHCNT_Pos (13U) :ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) :ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk :ETH_MACHWF2R_TXQCNT_Pos (6U) :ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) :ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk :ETH_MACHWF2R_RXQCNT_Pos (0U) ¡:ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) ¢:ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk ¥:ETH_MACMDIOAR_PSE_Pos (27U) ¦:ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) §:ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk ¨:ETH_MACMDIOAR_BTB_Pos (26U) ©:ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) ª:ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk «:ETH_MACMDIOAR_PA_Pos (21U) ¬:ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) :ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk ®:ETH_MACMDIOAR_RDA_Pos (16U) ¯:ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) °:ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk ±:ETH_MACMDIOAR_NTC_Pos (12U) ²:ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) ³:ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk ´:ETH_MACMDIOAR_CR_Pos (8U) µ:ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) ¶:ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk ·:ETH_MACMDIOAR_CR_DIV42 (0U) ¸:ETH_MACMDIOAR_CR_DIV62_Pos (8U) ¹:ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) º:ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk »:ETH_MACMDIOAR_CR_DIV16_Pos (9U) ¼:ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) ½:ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk ¾:ETH_MACMDIOAR_CR_DIV26_Pos (8U) ¿:ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) À:ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk Á:ETH_MACMDIOAR_CR_DIV102_Pos (10U) Â:ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) Ã:ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk Ä:ETH_MACMDIOAR_CR_DIV124_Pos (8U) Å:ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) Æ:ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk Ç:ETH_MACMDIOAR_CR_DIV4AR_Pos (11U) È:ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) É:ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk Ê:ETH_MACMDIOAR_CR_DIV6AR_Pos (8U) Ë:ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) Ì:ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk Í:ETH_MACMDIOAR_CR_DIV8AR_Pos (9U) Î:ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) Ï:ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk Ð:ETH_MACMDIOAR_CR_DIV10AR_Pos (8U) Ñ:ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) Ò:ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk Ó:ETH_MACMDIOAR_CR_DIV12AR_Pos (10U) Ô:ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) Õ:ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk Ö:ETH_MACMDIOAR_CR_DIV14AR_Pos (8U) ×:ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) Ø:ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk Ù:ETH_MACMDIOAR_CR_DIV16AR_Pos (9U) Ú:ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) Û:ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk Ü:ETH_MACMDIOAR_CR_DIV18AR_Pos (8U) Ý:ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) Þ:ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk ß:ETH_MACMDIOAR_SKAP_Pos (4U) à:ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) á:ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk â:ETH_MACMDIOAR_MOC_Pos (2U) ã:ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) ä:ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk å:ETH_MACMDIOAR_MOC_WR_Pos (2U) æ:ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) ç:ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk è:ETH_MACMDIOAR_MOC_PRDIA_Pos (3U) é:ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) ê:ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk ë:ETH_MACMDIOAR_MOC_RD_Pos (2U) ì:ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) í:ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk î:ETH_MACMDIOAR_C45E_Pos (1U) ï:ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) ð:ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk ñ:ETH_MACMDIOAR_MB_Pos (0U) ò:ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) ó:ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk ö:ETH_MACMDIODR_RA_Pos (16U) ÷:ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) ø:ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk ù:ETH_MACMDIODR_MD_Pos (0U) ú:ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) û:ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk þ:ETH_MACARPAR_ARPPA_Pos (0U) ÿ:ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) ;ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk ;ETH_MACA0HR_AE_Pos (31U) ;ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos)
;ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk ;ETH_MACA0HR_ADDRHI_Pos (0U) ;ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) ;ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk ;ETH_MACA0LR_ADDRLO_Pos (0U) ;ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) ;ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk ;ETH_MACA1HR_AE_Pos (31U) ;ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) ;ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk ;ETH_MACA1HR_SA_Pos (30U) ;ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) ;ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk ;ETH_MACA1HR_MBC_Pos (24U) ;ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) ;ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk ;ETH_MACA1HR_ADDRHI_Pos (0U) ;ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) ;ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk ;ETH_MACA1LR_ADDRLO_Pos (0U) ;ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) ;ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk £;ETH_MACA2HR_AE_Pos (31U) ¤;ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) ¥;ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk ¦;ETH_MACA2HR_SA_Pos (30U) §;ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) ¨;ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk ©;ETH_MACA2HR_MBC_Pos (24U) ª;ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) «;ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk ¬;ETH_MACA2HR_ADDRHI_Pos (0U) ;ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) ®;ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk ±;ETH_MACA2LR_ADDRLO_Pos (0U) ²;ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) ³;ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk ¶;ETH_MACA3HR_AE_Pos (31U) ·;ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) ¸;ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk ¹;ETH_MACA3HR_SA_Pos (30U) º;ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) »;ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk ¼;ETH_MACA3HR_MBC_Pos (24U) ½;ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) ¾;ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk ¿;ETH_MACA3HR_ADDRHI_Pos (0U) À;ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) Á;ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk Ä;ETH_MACA3LR_ADDRLO_Pos (0U) Å;ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) Æ;ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk É;ETH_MACAHR_AE_Pos (31U) Ê;ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) Ë;ETH_MACAHR_AE ETH_MACAHR_AE_Msk Ì;ETH_MACAHR_SA_Pos (30U) Í;ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) Î;ETH_MACAHR_SA ETH_MACAHR_SA_Msk Ï;ETH_MACAHR_MBC_Pos (24U) Ð;ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) Ñ;ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk Ò;ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) Ó;ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) Ô;ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) Õ;ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) Ö;ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) ×;ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) Ø;ETH_MACAHR_MACAH_Pos (0U) Ù;ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) Ú;ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk Ý;ETH_MACALR_MACAL_Pos (0U) Þ;ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) ß;ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk â;ETH_MMCCR_UCDBC_Pos (8U) ã;ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) ä;ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk å;ETH_MMCCR_CNTPRSTLVL_Pos (5U) æ;ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) ç;ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk è;ETH_MMCCR_CNTPRST_Pos (4U) é;ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) ê;ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk ë;ETH_MMCCR_CNTFREEZ_Pos (3U) ì;ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) í;ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk î;ETH_MMCCR_RSTONRD_Pos (2U) ï;ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) ð;ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk ñ;ETH_MMCCR_CNTSTOPRO_Pos (1U) ò;ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) ó;ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk ô;ETH_MMCCR_CNTRST_Pos (0U) õ;ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) ö;ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk ù;ETH_MMCRIR_RXLPITRCIS_Pos (27U) ú;ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) û;ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk ü;ETH_MMCRIR_RXLPIUSCIS_Pos (26U) ý;ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) þ;ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk ÿ;ETH_MMCRIR_RXUCGPIS_Pos (17U) <ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) <ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk <ETH_MMCRIR_RXALGNERPIS_Pos (6U) <ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) <ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk
<ETH_MMCRIR_RXCRCERPIS_Pos (5U) <ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) <ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk <ETH_MMCTIR_TXLPITRCIS_Pos (27U) <ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) <ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk <ETH_MMCTIR_TXLPIUSCIS_Pos (26U) <ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) <ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk <ETH_MMCTIR_TXGPKTIS_Pos (21U) <ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) <ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk <ETH_MMCTIR_TXMCOLGPIS_Pos (15U) <ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) <ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk <ETH_MMCTIR_TXSCOLGPIS_Pos (14U) <ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) <ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk <ETH_MMCRIMR_RXLPITRCIM_Pos (27U) <ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) <ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk <ETH_MMCRIMR_RXLPIUSCIM_Pos (26U) <ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) <ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk ¡<ETH_MMCRIMR_RXUCGPIM_Pos (17U) ¢<ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) £<ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk ¤<ETH_MMCRIMR_RXALGNERPIM_Pos (6U) ¥<ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) ¦<ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk §<ETH_MMCRIMR_RXCRCERPIM_Pos (5U) ¨<ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) ©<ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk ¬<ETH_MMCTIMR_TXLPITRCIM_Pos (27U) <ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) ®<ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk ¯<ETH_MMCTIMR_TXLPIUSCIM_Pos (26U) °<ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) ±<ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk ²<ETH_MMCTIMR_TXGPKTIM_Pos (21U) ³<ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) ´<ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk µ<ETH_MMCTIMR_TXMCOLGPIM_Pos (15U) ¶<ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) ·<ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk ¸<ETH_MMCTIMR_TXSCOLGPIM_Pos (14U) ¹<ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) º<ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk ½<ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U) ¾<ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) ¿<ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk Â<ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U) Ã<ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) Ä<ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk Ç<ETH_MMCTPCGR_TXPKTG_Pos (0U) È<ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) É<ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk Ì<ETH_MMCRCRCEPR_RXCRCERR_Pos (0U) Í<ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) Î<ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk Ñ<ETH_MMCRAEPR_RXALGNERR_Pos (0U) Ò<ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) Ó<ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk Ö<ETH_MMCRUPGR_RXUCASTG_Pos (0U) ×<ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) Ø<ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk Û<ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U) Ü<ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) Ý<ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk à<ETH_MMCTLPITCR_TXLPITRC_Pos (0U) á<ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) â<ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk å<ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U) æ<ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) ç<ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk ê<ETH_MMCRLPITCR_RXLPITRC_Pos (0U) ë<ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) ì<ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk ï<ETH_MACL3L4CR_L4DPIM_Pos (21U) ð<ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) ñ<ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk ò<ETH_MACL3L4CR_L4DPM_Pos (20U) ó<ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) ô<ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk õ<ETH_MACL3L4CR_L4SPIM_Pos (19U) ö<ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) ÷<ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk ø<ETH_MACL3L4CR_L4SPM_Pos (18U) ù<ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) ú<ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk û<ETH_MACL3L4CR_L4PEN_Pos (16U) ü<ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) ý<ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk þ<ETH_MACL3L4CR_L3HDBM_Pos (11U) ÿ<ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) =ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk =ETH_MACL3L4CR_L3HSBM_Pos (6U) =ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) =ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk =ETH_MACL3L4CR_L3DAIM_Pos (5U)
=ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) =ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk =ETH_MACL3L4CR_L3DAM_Pos (4U) =ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) =ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk =ETH_MACL3L4CR_L3SAIM_Pos (3U) =ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) =ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk =ETH_MACL3L4CR_L3SAM_Pos (2U) =ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) =ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk =ETH_MACL3L4CR_L3PEN_Pos (0U) =ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) =ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk =ETH_MACL4AR_L4DP_Pos (16U) =ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) =ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk =ETH_MACL4AR_L4SP_Pos (0U) =ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) =ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk =ETH_MACL3A0R_L3A0_Pos (0U) =ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) =ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk ¢=ETH_MACL3A1R_L3A1_Pos (0U) £=ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) ¤=ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk §=ETH_MACL3A2R_L3A2_Pos (0U) ¨=ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) ©=ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk ¬=ETH_MACL3A3R_L3A3_Pos (0U) =ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) ®=ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk ±=ETH_MACTSCR_TXTSSTSM_Pos (24U) ²=ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) ³=ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk ´=ETH_MACTSCR_CSC_Pos (19U) µ=ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) ¶=ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk ·=ETH_MACTSCR_TSENMACADDR_Pos (18U) ¸=ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) ¹=ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk º=ETH_MACTSCR_SNAPTYPSEL_Pos (16U) »=ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) ¼=ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk ½=ETH_MACTSCR_TSMSTRENA_Pos (15U) ¾=ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) ¿=ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk À=ETH_MACTSCR_TSEVNTENA_Pos (14U) Á=ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) Â=ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk Ã=ETH_MACTSCR_TSIPV4ENA_Pos (13U) Ä=ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) Å=ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk Æ=ETH_MACTSCR_TSIPV6ENA_Pos (12U) Ç=ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) È=ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk É=ETH_MACTSCR_TSIPENA_Pos (11U) Ê=ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) Ë=ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk Ì=ETH_MACTSCR_TSVER2ENA_Pos (10U) Í=ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) Î=ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk Ï=ETH_MACTSCR_TSCTRLSSR_Pos (9U) Ð=ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) Ñ=ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk Ò=ETH_MACTSCR_TSENALL_Pos (8U) Ó=ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) Ô=ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk Õ=ETH_MACTSCR_TSADDREG_Pos (5U) Ö=ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) ×=ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk Ø=ETH_MACTSCR_TSUPDT_Pos (3U) Ù=ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) Ú=ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk Û=ETH_MACTSCR_TSINIT_Pos (2U) Ü=ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) Ý=ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk Þ=ETH_MACTSCR_TSCFUPDT_Pos (1U) ß=ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) à=ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk á=ETH_MACTSCR_TSENA_Pos (0U) â=ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) ã=ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk æ=ETH_MACMACSSIR_SSINC_Pos (16U) ç=ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) è=ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk é=ETH_MACMACSSIR_SNSINC_Pos (8U) ê=ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) ë=ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk î=ETH_MACSTSR_TSS_Pos (0U) ï=ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) ð=ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk ó=ETH_MACSTNR_TSSS_Pos (0U) ô=ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) õ=ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk ø=ETH_MACSTSUR_TSS_Pos (0U) ù=ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) ú=ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk ý=ETH_MACSTNUR_ADDSUB_Pos (31U) þ=ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) ÿ=ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk >ETH_MACSTNUR_TSSS_Pos (0U) >ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) >ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk
>ETH_MACTSAR_TSAR_Pos (0U) >ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) >ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk >ETH_MACTSSR_ATSNS_Pos (25U) >ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) >ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk >ETH_MACTSSR_ATSSTM_Pos (24U) >ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) >ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk >ETH_MACTSSR_ATSSTN_Pos (16U) >ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) >ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk >ETH_MACTSSR_TXTSSIS_Pos (15U) >ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) >ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk >ETH_MACTSSR_TSTRGTERR0_Pos (3U) >ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) >ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk >ETH_MACTSSR_AUXTSTRIG_Pos (2U) >ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) >ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk >ETH_MACTSSR_TSTARGT0_Pos (1U) >ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) >ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk >ETH_MACTSSR_TSSOVF_Pos (0U) >ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) ¡>ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk ¤>ETH_MACTTSSNR_TXTSSMIS_Pos (31U) ¥>ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) ¦>ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk §>ETH_MACTTSSNR_TXTSSLO_Pos (0U) ¨>ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) ©>ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk ¬>ETH_MACTTSSSR_TXTSSHI_Pos (0U) >ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) ®>ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk ±>ETH_MACACR_ATSEN3_Pos (7U) ²>ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) ³>ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk ´>ETH_MACACR_ATSEN2_Pos (6U) µ>ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) ¶>ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk ·>ETH_MACACR_ATSEN1_Pos (5U) ¸>ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) ¹>ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk º>ETH_MACACR_ATSEN0_Pos (4U) »>ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) ¼>ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk ½>ETH_MACACR_ATSFC_Pos (0U) ¾>ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) ¿>ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk Â>ETH_MACATSNR_AUXTSLO_Pos (0U) Ã>ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) Ä>ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk Ç>ETH_MACATSSR_AUXTSHI_Pos (0U) È>ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) É>ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk Ì>ETH_MACTSIACR_OSTIAC_Pos (0U) Í>ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) Î>ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk Ñ>ETH_MACTSEACR_OSTEAC_Pos (0U) Ò>ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) Ó>ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk Ö>ETH_MACTSICNR_TSIC_Pos (0U) ×>ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) Ø>ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk Û>ETH_MACTSECNR_TSEC_Pos (0U) Ü>ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) Ý>ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk à>ETH_MACPPSCR_TRGTMODSEL0_Pos (5U) á>ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) â>ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk ã>ETH_MACPPSCR_PPSEN0_Pos (4U) ä>ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) å>ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk æ>ETH_MACPPSCR_PPSCTRL_Pos (0U) ç>ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) è>ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk ë>ETH_MACPPSTTSR_TSTRH0_Pos (0U) ì>ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) í>ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk ð>ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U) ñ>ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) ò>ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk ó>ETH_MACPPSTTNR_TTSL0_Pos (0U) ô>ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) õ>ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk ø>ETH_MACPPSIR_PPSINT0_Pos (0U) ù>ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) ú>ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk ý>ETH_MACPPSWR_PPSWIDTH0_Pos (0U) þ>ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) ÿ>ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk ?ETH_MACPOCR_DN_Pos (8U) ?ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) ?ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk
?ETH_MACPOCR_DRRDIS_Pos (6U) ?ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) ?ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk ?ETH_MACPOCR_APDREQTRIG_Pos (5U) ?ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) ?ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk ?ETH_MACPOCR_ASYNCTRIG_Pos (4U) ?ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) ?ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk ?ETH_MACPOCR_APDREQEN_Pos (2U) ?ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) ?ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk ?ETH_MACPOCR_ASYNCEN_Pos (1U) ?ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) ?ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk ?ETH_MACPOCR_PTOEN_Pos (0U) ?ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) ?ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk ?ETH_MACSPI0R_SPI0_Pos (0U) ?ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) ?ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk ?ETH_MACSPI1R_SPI1_Pos (0U) ?ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) ?ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk £?ETH_MACSPI2R_SPI2_Pos (0U) ¤?ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) ¥?ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk ¨?ETH_MACLMIR_LMPDRI_Pos (24U) ©?ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) ª?ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk «?ETH_MACLMIR_DRSYNCR_Pos (8U) ¬?ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) ?ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk ®?ETH_MACLMIR_LSI_Pos (0U) ¯?ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) °?ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk ³?ETH_MTLOMR_CNTCLR_Pos (9U) ´?ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) µ?ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk ¶?ETH_MTLOMR_CNTPRST_Pos (8U) ·?ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) ¸?ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk ¹?ETH_MTLOMR_DTXSTS_Pos (1U) º?ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) »?ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk ¾?ETH_MTLISR_MACIS_Pos (16U) ¿?ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) À?ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk Á?ETH_MTLISR_QIS_Pos (0U) Â?ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) Ã?ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk Æ?ETH_MTLTQOMR_TTC_Pos (4U) Ç?ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) È?ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk É?ETH_MTLTQOMR_TTC_32BITS (0U) Ê?ETH_MTLTQOMR_TTC_64BITS (0x00000010U) Ë?ETH_MTLTQOMR_TTC_96BITS (0x00000020U) Ì?ETH_MTLTQOMR_TTC_128BITS (0x00000030U) Í?ETH_MTLTQOMR_TTC_192BITS (0x00000040U) Î?ETH_MTLTQOMR_TTC_256BITS (0x00000050U) Ï?ETH_MTLTQOMR_TTC_384BITS (0x00000060U) Ð?ETH_MTLTQOMR_TTC_512BITS (0x00000070U) Ñ?ETH_MTLTQOMR_TSF_Pos (1U) Ò?ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) Ó?ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk Ô?ETH_MTLTQOMR_FTQ_Pos (0U) Õ?ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) Ö?ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk Ù?ETH_MTLTQUR_UFCNTOVF_Pos (11U) Ú?ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) Û?ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk Ü?ETH_MTLTQUR_UFPKTCNT_Pos (0U) Ý?ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) Þ?ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk á?ETH_MTLTQDR_STXSTSF_Pos (20U) â?ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) ã?ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk ä?ETH_MTLTQDR_PTXQ_Pos (16U) å?ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) æ?ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk ç?ETH_MTLTQDR_TXSTSFSTS_Pos (5U) è?ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) é?ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk ê?ETH_MTLTQDR_TXQSTS_Pos (4U) ë?ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) ì?ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk í?ETH_MTLTQDR_TWCSTS_Pos (3U) î?ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) ï?ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk ð?ETH_MTLTQDR_TRCSTS_Pos (1U) ñ?ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) ò?ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk ó?ETH_MTLTQDR_TRCSTS_IDLE (0U) ô?ETH_MTLTQDR_TRCSTS_READ (0x00000002U) õ?ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) ö?ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) ÷?ETH_MTLTQDR_TXQPAUSED_Pos (0U) ø?ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) ù?ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk ü?ETH_MTLQICSR_RXOIE_Pos (24U) ý?ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) þ?ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk ÿ?ETH_MTLQICSR_RXOVFIS_Pos (16U) @ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) @ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk @ETH_MTLQICSR_TXUIE_Pos (8U) @ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) @ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk
@ETH_MTLQICSR_TXUNFIS_Pos (0U) @ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) @ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk @ETH_MTLRQOMR_RQS_Pos (20U) @ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) @ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk @ETH_MTLRQOMR_RFD_Pos (14U) @ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) @ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk @ETH_MTLRQOMR_RFA_Pos (8U) @ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) @ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk @ETH_MTLRQOMR_EHFC_Pos (7U) @ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) @ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk @ETH_MTLRQOMR_DISTCPEF_Pos (6U) @ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) @ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk @ETH_MTLRQOMR_RSF_Pos (5U) @ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) @ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk @ETH_MTLRQOMR_FEP_Pos (4U) @ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) @ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk @ETH_MTLRQOMR_FUP_Pos (3U) @ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) ¡@ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk ¢@ETH_MTLRQOMR_RTC_Pos (0U) £@ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) ¤@ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk ¥@ETH_MTLRQOMR_RTC_64BITS (0U) ¦@ETH_MTLRQOMR_RTC_32BITS (0x00000001U) §@ETH_MTLRQOMR_RTC_96BITS (0x00000002U) ¨@ETH_MTLRQOMR_RTC_128BITS (0x00000003U) «@ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) ¬@ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) @ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk ®@ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U) ¯@ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) °@ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk ±@ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U) ²@ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) ³@ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk ´@ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U) µ@ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) ¶@ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk ¹@ETH_MTLRQDR_PRXQ_Pos (16U) º@ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) »@ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk ¼@ETH_MTLRQDR_RXQSTS_Pos (4U) ½@ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) ¾@ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk ¿@ETH_MTLRQDR_RXQSTS_EMPTY (0U) À@ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) Á@ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) Â@ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk Ã@ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U) Ä@ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) Å@ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk Æ@ETH_MTLRQDR_RXQSTS_FULL_Pos (4U) Ç@ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) È@ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk É@ETH_MTLRQDR_RRCSTS_Pos (1U) Ê@ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) Ë@ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk Ì@ETH_MTLRQDR_RRCSTS_IDLE (0U) Í@ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) Î@ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) Ï@ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk Ð@ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U) Ñ@ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) Ò@ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk Ó@ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U) Ô@ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) Õ@ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk Ö@ETH_MTLRQDR_RWCSTS_Pos (0U) ×@ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) Ø@ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk Û@ETH_MTLRQCR_RQPA_Pos (3U) Ü@ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) Ý@ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk Þ@ETH_MTLRQCR_RQW_Pos (0U) ß@ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) à@ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk ã@ETH_DMAMR_INTM_Pos (16U) ä@ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) å@ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk æ@ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) ç@ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) è@ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) é@ETH_DMAMR_PR_Pos (12U) ê@ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) ë@ETH_DMAMR_PR ETH_DMAMR_PR_Msk ì@ETH_DMAMR_PR_1_1 (0U) í@ETH_DMAMR_PR_2_1 (0x00001000U) î@ETH_DMAMR_PR_3_1 (0x00002000U) ï@ETH_DMAMR_PR_4_1 (0x00003000U) ð@ETH_DMAMR_PR_5_1 (0x00004000U) ñ@ETH_DMAMR_PR_6_1 (0x00005000U) ò@ETH_DMAMR_PR_7_1 (0x00006000U) ó@ETH_DMAMR_PR_8_1 (0x00007000U) ô@ETH_DMAMR_TXPR_Pos (11U) õ@ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) ö@ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk ÷@ETH_DMAMR_DA_Pos (1U) ø@ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) ù@ETH_DMAMR_DA ETH_DMAMR_DA_Msk ú@ETH_DMAMR_SWR_Pos (0U) û@ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) ü@ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk ÿ@ETH_DMASBMR_RB_Pos (15U) AETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) AETH_DMASBMR_RB ETH_DMASBMR_RB_Msk AETH_DMASBMR_MB_Pos (14U) AETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) AETH_DMASBMR_MB ETH_DMASBMR_MB_Msk
AETH_DMASBMR_AAL_Pos (12U) AETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) AETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk AETH_DMASBMR_FB_Pos (0U) AETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) AETH_DMASBMR_FB ETH_DMASBMR_FB_Msk AETH_DMAISR_MACIS_Pos (17U) AETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) AETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk AETH_DMAISR_MTLIS_Pos (16U) AETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) AETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk AETH_DMAISR_DMACIS_Pos (0U) AETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) AETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk AETH_DMADSR_TPS_Pos (12U) AETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) AETH_DMADSR_TPS ETH_DMADSR_TPS_Msk AETH_DMADSR_TPS_STOPPED (0U) AETH_DMADSR_TPS_FETCHING_Pos (12U) AETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) AETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk AETH_DMADSR_TPS_WAITING_Pos (13U) AETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) ¡AETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk ¢AETH_DMADSR_TPS_READING_Pos (12U) £AETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) ¤AETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk ¥AETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U) ¦AETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) §AETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk ¨AETH_DMADSR_TPS_SUSPENDED_Pos (13U) ©AETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) ªAETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk «AETH_DMADSR_TPS_CLOSING_Pos (12U) ¬AETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) AETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk ®AETH_DMADSR_RPS_Pos (8U) ¯AETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) °AETH_DMADSR_RPS ETH_DMADSR_RPS_Msk ±AETH_DMADSR_RPS_STOPPED (0U) ²AETH_DMADSR_RPS_FETCHING_Pos (12U) ³AETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) ´AETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk µAETH_DMADSR_RPS_WAITING_Pos (12U) ¶AETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) ·AETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk ¸AETH_DMADSR_RPS_SUSPENDED_Pos (14U) ¹AETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) ºAETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk »AETH_DMADSR_RPS_CLOSING_Pos (12U) ¼AETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) ½AETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk ¾AETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U) ¿AETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) ÀAETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk ÁAETH_DMADSR_RPS_TRANSFERRING_Pos (12U) ÂAETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) ÃAETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk ÆAETH_DMACCR_DSL_Pos (18U) ÇAETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) ÈAETH_DMACCR_DSL ETH_DMACCR_DSL_Msk ÉAETH_DMACCR_DSL_0BIT (0U) ÊAETH_DMACCR_DSL_32BIT (0x00040000U) ËAETH_DMACCR_DSL_64BIT (0x00080000U) ÌAETH_DMACCR_DSL_128BIT (0x00100000U) ÍAETH_DMACCR_8PBL (0x00010000U) ÎAETH_DMACCR_MSS_Pos (0U) ÏAETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) ÐAETH_DMACCR_MSS ETH_DMACCR_MSS_Msk ÓAETH_DMACTCR_TPBL_Pos (16U) ÔAETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) ÕAETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk ÖAETH_DMACTCR_TPBL_1PBL (0x00010000U) ×AETH_DMACTCR_TPBL_2PBL (0x00020000U) ØAETH_DMACTCR_TPBL_4PBL (0x00040000U) ÙAETH_DMACTCR_TPBL_8PBL (0x00080000U) ÚAETH_DMACTCR_TPBL_16PBL (0x00100000U) ÛAETH_DMACTCR_TPBL_32PBL (0x00200000U) ÜAETH_DMACTCR_TSE_Pos (12U) ÝAETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) ÞAETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk ßAETH_DMACTCR_OSP_Pos (4U) àAETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) áAETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk âAETH_DMACTCR_ST_Pos (0U) ãAETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) äAETH_DMACTCR_ST ETH_DMACTCR_ST_Msk çAETH_DMACRCR_RPF_Pos (31U) èAETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) éAETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk êAETH_DMACRCR_RPBL_Pos (16U) ëAETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) ìAETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk íAETH_DMACRCR_RPBL_1PBL (0x00010000U) îAETH_DMACRCR_RPBL_2PBL (0x00020000U) ïAETH_DMACRCR_RPBL_4PBL (0x00040000U) ðAETH_DMACRCR_RPBL_8PBL (0x00080000U) ñAETH_DMACRCR_RPBL_16PBL (0x00100000U) òAETH_DMACRCR_RPBL_32PBL (0x00200000U) óAETH_DMACRCR_RBSZ_Pos (1U) ôAETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) õAETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk öAETH_DMACRCR_SR_Pos (0U) ÷AETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) øAETH_DMACRCR_SR ETH_DMACRCR_SR_Msk ûAETH_DMACTDLAR_TDESLA_Pos (2U) üAETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) ýAETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk BETH_DMACRDLAR_RDESLA_Pos (2U) BETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) BETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk
BETH_DMACTDTPR_TDT_Pos (2U) BETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) BETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk BETH_DMACRDTPR_RDT_Pos (2U) BETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) BETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk BETH_DMACTDRLR_TDRL_Pos (0U) BETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) BETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk BETH_DMACRDRLR_RDRL_Pos (0U) BETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) BETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk BETH_DMACIER_NIE_Pos (15U) BETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) BETH_DMACIER_NIE ETH_DMACIER_NIE_Msk BETH_DMACIER_AIE_Pos (14U) BETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) BETH_DMACIER_AIE ETH_DMACIER_AIE_Msk BETH_DMACIER_CDEE_Pos (13U) BETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) ¡BETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk ¢BETH_DMACIER_FBEE_Pos (12U) £BETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) ¤BETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk ¥BETH_DMACIER_ERIE_Pos (11U) ¦BETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) §BETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk ¨BETH_DMACIER_ETIE_Pos (10U) ©BETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) ªBETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk «BETH_DMACIER_RWTE_Pos (9U) ¬BETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) BETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk ®BETH_DMACIER_RSE_Pos (8U) ¯BETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) °BETH_DMACIER_RSE ETH_DMACIER_RSE_Msk ±BETH_DMACIER_RBUE_Pos (7U) ²BETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) ³BETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk ´BETH_DMACIER_RIE_Pos (6U) µBETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) ¶BETH_DMACIER_RIE ETH_DMACIER_RIE_Msk ·BETH_DMACIER_TBUE_Pos (2U) ¸BETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) ¹BETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk ºBETH_DMACIER_TXSE_Pos (1U) »BETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) ¼BETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk ½BETH_DMACIER_TIE_Pos (0U) ¾BETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) ¿BETH_DMACIER_TIE ETH_DMACIER_TIE_Msk ÂBETH_DMACRIWTR_RWT_Pos (0U) ÃBETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) ÄBETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk ÇBETH_DMACCATDR_CURTDESAPTR_Pos (0U) ÈBETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) ÉBETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk ÌBETH_DMACCARDR_CURRDESAPTR_Pos (0U) ÍBETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) ÎBETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk ÑBETH_DMACCATBR_CURTBUFAPTR_Pos (0U) ÒBETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) ÓBETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk ÖBETH_DMACCARBR_CURRBUFAPTR_Pos (0U) ×BETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) ØBETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk ÛBETH_DMACSR_REB_Pos (19U) ÜBETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) ÝBETH_DMACSR_REB ETH_DMACSR_REB_Msk ÞBETH_DMACSR_TEB_Pos (16U) ßBETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) àBETH_DMACSR_TEB ETH_DMACSR_TEB_Msk áBETH_DMACSR_NIS_Pos (15U) âBETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) ãBETH_DMACSR_NIS ETH_DMACSR_NIS_Msk äBETH_DMACSR_AIS_Pos (14U) åBETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) æBETH_DMACSR_AIS ETH_DMACSR_AIS_Msk çBETH_DMACSR_CDE_Pos (13U) èBETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) éBETH_DMACSR_CDE ETH_DMACSR_CDE_Msk êBETH_DMACSR_FBE_Pos (12U) ëBETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) ìBETH_DMACSR_FBE ETH_DMACSR_FBE_Msk íBETH_DMACSR_ERI_Pos (11U) îBETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) ïBETH_DMACSR_ERI ETH_DMACSR_ERI_Msk ðBETH_DMACSR_ETI_Pos (10U) ñBETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) òBETH_DMACSR_ETI ETH_DMACSR_ETI_Msk óBETH_DMACSR_RWT_Pos (9U) ôBETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) õBETH_DMACSR_RWT ETH_DMACSR_RWT_Msk öBETH_DMACSR_RPS_Pos (8U) ÷BETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) øBETH_DMACSR_RPS ETH_DMACSR_RPS_Msk ùBETH_DMACSR_RBU_Pos (7U) úBETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) ûBETH_DMACSR_RBU ETH_DMACSR_RBU_Msk üBETH_DMACSR_RI_Pos (6U) ýBETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) þBETH_DMACSR_RI ETH_DMACSR_RI_Msk ÿBETH_DMACSR_TBU_Pos (2U) CETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) CETH_DMACSR_TBU ETH_DMACSR_TBU_Msk CETH_DMACSR_TPS_Pos (1U) CETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) CETH_DMACSR_TPS ETH_DMACSR_TPS_Msk
CETH_DMACSR_TI_Pos (0U) CETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) CETH_DMACSR_TI ETH_DMACSR_TI_Msk CETH_DMACMFCR_MFCO_Pos (15U) CETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) CETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk CETH_DMACMFCR_MFC_Pos (0U) CETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) CETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk CDMA_SxCR_MBURST_Pos (23U) CDMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) CDMA_SxCR_MBURST DMA_SxCR_MBURST_Msk CDMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) CDMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) CDMA_SxCR_PBURST_Pos (21U) CDMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) CDMA_SxCR_PBURST DMA_SxCR_PBURST_Msk CDMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) CDMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) ¡CDMA_SxCR_TRBUFF_Pos (20U) ¢CDMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) £CDMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk ¤CDMA_SxCR_CT_Pos (19U) ¥CDMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) ¦CDMA_SxCR_CT DMA_SxCR_CT_Msk §CDMA_SxCR_DBM_Pos (18U) ¨CDMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) ©CDMA_SxCR_DBM DMA_SxCR_DBM_Msk ªCDMA_SxCR_PL_Pos (16U) «CDMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) ¬CDMA_SxCR_PL DMA_SxCR_PL_Msk CDMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) ®CDMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) ¯CDMA_SxCR_PINCOS_Pos (15U) °CDMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) ±CDMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk ²CDMA_SxCR_MSIZE_Pos (13U) ³CDMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) ´CDMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk µCDMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) ¶CDMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) ·CDMA_SxCR_PSIZE_Pos (11U) ¸CDMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) ¹CDMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk ºCDMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) »CDMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) ¼CDMA_SxCR_MINC_Pos (10U) ½CDMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) ¾CDMA_SxCR_MINC DMA_SxCR_MINC_Msk ¿CDMA_SxCR_PINC_Pos (9U) ÀCDMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) ÁCDMA_SxCR_PINC DMA_SxCR_PINC_Msk ÂCDMA_SxCR_CIRC_Pos (8U) ÃCDMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) ÄCDMA_SxCR_CIRC DMA_SxCR_CIRC_Msk ÅCDMA_SxCR_DIR_Pos (6U) ÆCDMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) ÇCDMA_SxCR_DIR DMA_SxCR_DIR_Msk ÈCDMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) ÉCDMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) ÊCDMA_SxCR_PFCTRL_Pos (5U) ËCDMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) ÌCDMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk ÍCDMA_SxCR_TCIE_Pos (4U) ÎCDMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) ÏCDMA_SxCR_TCIE DMA_SxCR_TCIE_Msk ÐCDMA_SxCR_HTIE_Pos (3U) ÑCDMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) ÒCDMA_SxCR_HTIE DMA_SxCR_HTIE_Msk ÓCDMA_SxCR_TEIE_Pos (2U) ÔCDMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) ÕCDMA_SxCR_TEIE DMA_SxCR_TEIE_Msk ÖCDMA_SxCR_DMEIE_Pos (1U) ×CDMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) ØCDMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk ÙCDMA_SxCR_EN_Pos (0U) ÚCDMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) ÛCDMA_SxCR_EN DMA_SxCR_EN_Msk ÞCDMA_SxNDT_Pos (0U) ßCDMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) àCDMA_SxNDT DMA_SxNDT_Msk áCDMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) âCDMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) ãCDMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) äCDMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) åCDMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) æCDMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) çCDMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) èCDMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) éCDMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) êCDMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) ëCDMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) ìCDMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) íCDMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) îCDMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) ïCDMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) ðCDMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) óCDMA_SxFCR_FEIE_Pos (7U) ôCDMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) õCDMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk öCDMA_SxFCR_FS_Pos (3U) ÷CDMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) øCDMA_SxFCR_FS DMA_SxFCR_FS_Msk ùCDMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) úCDMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) ûCDMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) üCDMA_SxFCR_DMDIS_Pos (2U) ýCDMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) þCDMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk ÿCDMA_SxFCR_FTH_Pos (0U) DDMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) DDMA_SxFCR_FTH DMA_SxFCR_FTH_Msk DDMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) DDMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) DDMA_LISR_TCIF3_Pos (27U) DDMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) DDMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk DDMA_LISR_HTIF3_Pos (26U) DDMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) DDMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk DDMA_LISR_TEIF3_Pos (25U) DDMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) DDMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk DDMA_LISR_DMEIF3_Pos (24U) DDMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) DDMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk DDMA_LISR_FEIF3_Pos (22U) DDMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) DDMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk DDMA_LISR_TCIF2_Pos (21U) DDMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) DDMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk DDMA_LISR_HTIF2_Pos (20U) DDMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) DDMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk DDMA_LISR_TEIF2_Pos (19U) DDMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) DDMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk DDMA_LISR_DMEIF2_Pos (18U) DDMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) DDMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk ¡DDMA_LISR_FEIF2_Pos (16U) ¢DDMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) £DDMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk ¤DDMA_LISR_TCIF1_Pos (11U) ¥DDMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) ¦DDMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk §DDMA_LISR_HTIF1_Pos (10U) ¨DDMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) ©DDMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk ªDDMA_LISR_TEIF1_Pos (9U) «DDMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) ¬DDMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk DDMA_LISR_DMEIF1_Pos (8U) ®DDMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) ¯DDMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk °DDMA_LISR_FEIF1_Pos (6U) ±DDMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) ²DDMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk ³DDMA_LISR_TCIF0_Pos (5U) ´DDMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) µDDMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk ¶DDMA_LISR_HTIF0_Pos (4U) ·DDMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) ¸DDMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk ¹DDMA_LISR_TEIF0_Pos (3U) ºDDMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) »DDMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk ¼DDMA_LISR_DMEIF0_Pos (2U) ½DDMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) ¾DDMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk ¿DDMA_LISR_FEIF0_Pos (0U) ÀDDMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) ÁDDMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk ÄDDMA_HISR_TCIF7_Pos (27U) ÅDDMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) ÆDDMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk ÇDDMA_HISR_HTIF7_Pos (26U) ÈDDMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) ÉDDMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk ÊDDMA_HISR_TEIF7_Pos (25U) ËDDMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) ÌDDMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk ÍDDMA_HISR_DMEIF7_Pos (24U) ÎDDMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) ÏDDMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk ÐDDMA_HISR_FEIF7_Pos (22U) ÑDDMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) ÒDDMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk ÓDDMA_HISR_TCIF6_Pos (21U) ÔDDMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) ÕDDMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk ÖDDMA_HISR_HTIF6_Pos (20U) ×DDMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) ØDDMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk ÙDDMA_HISR_TEIF6_Pos (19U) ÚDDMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) ÛDDMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk ÜDDMA_HISR_DMEIF6_Pos (18U) ÝDDMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) ÞDDMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk ßDDMA_HISR_FEIF6_Pos (16U) àDDMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) áDDMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk âDDMA_HISR_TCIF5_Pos (11U) ãDDMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) äDDMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk åDDMA_HISR_HTIF5_Pos (10U) æDDMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) çDDMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk èDDMA_HISR_TEIF5_Pos (9U) éDDMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) êDDMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk ëDDMA_HISR_DMEIF5_Pos (8U) ìDDMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) íDDMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk îDDMA_HISR_FEIF5_Pos (6U) ïDDMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) ðDDMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk ñDDMA_HISR_TCIF4_Pos (5U) òDDMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) óDDMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk ôDDMA_HISR_HTIF4_Pos (4U) õDDMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) öDDMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk ÷DDMA_HISR_TEIF4_Pos (3U) øDDMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) ùDDMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk úDDMA_HISR_DMEIF4_Pos (2U) ûDDMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) üDDMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk ýDDMA_HISR_FEIF4_Pos (0U) þDDMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) ÿDDMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk EDMA_LIFCR_CTCIF3_Pos (27U) EDMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) EDMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
EDMA_LIFCR_CHTIF3_Pos (26U) EDMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) EDMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk EDMA_LIFCR_CTEIF3_Pos (25U) EDMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) EDMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk EDMA_LIFCR_CDMEIF3_Pos (24U) EDMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) EDMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk EDMA_LIFCR_CFEIF3_Pos (22U) EDMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) EDMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk EDMA_LIFCR_CTCIF2_Pos (21U) EDMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) EDMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk EDMA_LIFCR_CHTIF2_Pos (20U) EDMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) EDMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk EDMA_LIFCR_CTEIF2_Pos (19U) EDMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) EDMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk EDMA_LIFCR_CDMEIF2_Pos (18U) EDMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) EDMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk EDMA_LIFCR_CFEIF2_Pos (16U) EDMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) EDMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk EDMA_LIFCR_CTCIF1_Pos (11U) ¡EDMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) ¢EDMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk £EDMA_LIFCR_CHTIF1_Pos (10U) ¤EDMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) ¥EDMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk ¦EDMA_LIFCR_CTEIF1_Pos (9U) §EDMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) ¨EDMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk ©EDMA_LIFCR_CDMEIF1_Pos (8U) ªEDMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) «EDMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk ¬EDMA_LIFCR_CFEIF1_Pos (6U) EDMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) ®EDMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk ¯EDMA_LIFCR_CTCIF0_Pos (5U) °EDMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) ±EDMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk ²EDMA_LIFCR_CHTIF0_Pos (4U) ³EDMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) ´EDMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk µEDMA_LIFCR_CTEIF0_Pos (3U) ¶EDMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) ·EDMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk ¸EDMA_LIFCR_CDMEIF0_Pos (2U) ¹EDMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) ºEDMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk »EDMA_LIFCR_CFEIF0_Pos (0U) ¼EDMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) ½EDMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk ÀEDMA_HIFCR_CTCIF7_Pos (27U) ÁEDMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) ÂEDMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk ÃEDMA_HIFCR_CHTIF7_Pos (26U) ÄEDMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) ÅEDMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk ÆEDMA_HIFCR_CTEIF7_Pos (25U) ÇEDMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) ÈEDMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk ÉEDMA_HIFCR_CDMEIF7_Pos (24U) ÊEDMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) ËEDMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk ÌEDMA_HIFCR_CFEIF7_Pos (22U) ÍEDMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) ÎEDMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk ÏEDMA_HIFCR_CTCIF6_Pos (21U) ÐEDMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) ÑEDMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk ÒEDMA_HIFCR_CHTIF6_Pos (20U) ÓEDMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) ÔEDMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk ÕEDMA_HIFCR_CTEIF6_Pos (19U) ÖEDMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) ×EDMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk ØEDMA_HIFCR_CDMEIF6_Pos (18U) ÙEDMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) ÚEDMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk ÛEDMA_HIFCR_CFEIF6_Pos (16U) ÜEDMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) ÝEDMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk ÞEDMA_HIFCR_CTCIF5_Pos (11U) ßEDMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) àEDMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk áEDMA_HIFCR_CHTIF5_Pos (10U) âEDMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) ãEDMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk äEDMA_HIFCR_CTEIF5_Pos (9U) åEDMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) æEDMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk çEDMA_HIFCR_CDMEIF5_Pos (8U) èEDMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) éEDMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk êEDMA_HIFCR_CFEIF5_Pos (6U) ëEDMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) ìEDMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk íEDMA_HIFCR_CTCIF4_Pos (5U) îEDMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) ïEDMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk ðEDMA_HIFCR_CHTIF4_Pos (4U) ñEDMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) òEDMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk óEDMA_HIFCR_CTEIF4_Pos (3U) ôEDMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) õEDMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk öEDMA_HIFCR_CDMEIF4_Pos (2U) ÷EDMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) øEDMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk ùEDMA_HIFCR_CFEIF4_Pos (0U) úEDMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) ûEDMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk þEDMA_SxPAR_PA_Pos (0U) ÿEDMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) FDMA_SxPAR_PA DMA_SxPAR_PA_Msk FDMA_SxM0AR_M0A_Pos (0U) FDMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
FDMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk FDMA_SxM1AR_M1A_Pos (0U) FDMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) FDMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk FDMAMUX_CxCR_DMAREQ_ID_Pos (0U) FDMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk FDMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) FDMAMUX_CxCR_SOIE_Pos (8U) FDMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) FDMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk FDMAMUX_CxCR_EGE_Pos (9U) ¡FDMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) ¢FDMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk £FDMAMUX_CxCR_SE_Pos (16U) ¤FDMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) ¥FDMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk ¦FDMAMUX_CxCR_SPOL_Pos (17U) §FDMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) ¨FDMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk ©FDMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) ªFDMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) «FDMAMUX_CxCR_NBREQ_Pos (19U) ¬FDMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) FDMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk ®FDMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) ¯FDMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) °FDMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) ±FDMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) ²FDMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) ³FDMAMUX_CxCR_SYNC_ID_Pos (24U) ´FDMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) µFDMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk ¶FDMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) ·FDMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) ¸FDMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) ¹FDMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) ºFDMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) ½FDMAMUX_CSR_SOF0_Pos (0U) ¾FDMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) ¿FDMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk ÀFDMAMUX_CSR_SOF1_Pos (1U) ÁFDMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) ÂFDMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk ÃFDMAMUX_CSR_SOF2_Pos (2U) ÄFDMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) ÅFDMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk ÆFDMAMUX_CSR_SOF3_Pos (3U) ÇFDMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) ÈFDMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk ÉFDMAMUX_CSR_SOF4_Pos (4U) ÊFDMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) ËFDMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk ÌFDMAMUX_CSR_SOF5_Pos (5U) ÍFDMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) ÎFDMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk ÏFDMAMUX_CSR_SOF6_Pos (6U) ÐFDMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) ÑFDMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk ÒFDMAMUX_CSR_SOF7_Pos (7U) ÓFDMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) ÔFDMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk ÕFDMAMUX_CSR_SOF8_Pos (8U) ÖFDMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) ×FDMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk ØFDMAMUX_CSR_SOF9_Pos (9U) ÙFDMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) ÚFDMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk ÛFDMAMUX_CSR_SOF10_Pos (10U) ÜFDMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) ÝFDMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk ÞFDMAMUX_CSR_SOF11_Pos (11U) ßFDMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) àFDMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk áFDMAMUX_CSR_SOF12_Pos (12U) âFDMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) ãFDMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk äFDMAMUX_CSR_SOF13_Pos (13U) åFDMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) æFDMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk çFDMAMUX_CSR_SOF14_Pos (14U) èFDMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) éFDMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk êFDMAMUX_CSR_SOF15_Pos (15U) ëFDMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) ìFDMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk ïFDMAMUX_CFR_CSOF0_Pos (0U) ðFDMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) ñFDMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk òFDMAMUX_CFR_CSOF1_Pos (1U) óFDMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) ôFDMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk õFDMAMUX_CFR_CSOF2_Pos (2U) öFDMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) ÷FDMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk øFDMAMUX_CFR_CSOF3_Pos (3U) ùFDMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) úFDMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk ûFDMAMUX_CFR_CSOF4_Pos (4U) üFDMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) ýFDMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk þFDMAMUX_CFR_CSOF5_Pos (5U) ÿFDMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) GDMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk GDMAMUX_CFR_CSOF6_Pos (6U) GDMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) GDMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk GDMAMUX_CFR_CSOF7_Pos (7U)
GDMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) GDMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk GDMAMUX_CFR_CSOF8_Pos (8U) GDMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) GDMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk GDMAMUX_CFR_CSOF9_Pos (9U) GDMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) GDMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk GDMAMUX_CFR_CSOF10_Pos (10U) GDMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) GDMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk GDMAMUX_CFR_CSOF11_Pos (11U) GDMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) GDMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk GDMAMUX_CFR_CSOF12_Pos (12U) GDMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) GDMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk GDMAMUX_CFR_CSOF13_Pos (13U) GDMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) GDMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk GDMAMUX_CFR_CSOF14_Pos (14U) GDMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) GDMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk GDMAMUX_CFR_CSOF15_Pos (15U) GDMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) GDMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk ¡GDMAMUX_RGxCR_SIG_ID_Pos (0U) ¢GDMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) £GDMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk ¤GDMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) ¥GDMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) ¦GDMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) §GDMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) ¨GDMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) ©GDMAMUX_RGxCR_OIE_Pos (8U) ªGDMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) «GDMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk ¬GDMAMUX_RGxCR_GE_Pos (16U) GDMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) ®GDMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk ¯GDMAMUX_RGxCR_GPOL_Pos (17U) °GDMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) ±GDMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk ²GDMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) ³GDMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) ´GDMAMUX_RGxCR_GNBREQ_Pos (19U) µGDMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) ¶GDMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk ·GDMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) ¸GDMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) ¹GDMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) ºGDMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) »GDMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) ¾GDMAMUX_RGSR_OF0_Pos (0U) ¿GDMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) ÀGDMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk ÁGDMAMUX_RGSR_OF1_Pos (1U) ÂGDMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) ÃGDMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk ÄGDMAMUX_RGSR_OF2_Pos (2U) ÅGDMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) ÆGDMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk ÇGDMAMUX_RGSR_OF3_Pos (3U) ÈGDMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) ÉGDMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk ÊGDMAMUX_RGSR_OF4_Pos (4U) ËGDMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) ÌGDMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk ÍGDMAMUX_RGSR_OF5_Pos (5U) ÎGDMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) ÏGDMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk ÐGDMAMUX_RGSR_OF6_Pos (6U) ÑGDMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) ÒGDMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk ÓGDMAMUX_RGSR_OF7_Pos (7U) ÔGDMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) ÕGDMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk ØGDMAMUX_RGCFR_COF0_Pos (0U) ÙGDMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) ÚGDMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk ÛGDMAMUX_RGCFR_COF1_Pos (1U) ÜGDMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) ÝGDMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk ÞGDMAMUX_RGCFR_COF2_Pos (2U) ßGDMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) àGDMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk áGDMAMUX_RGCFR_COF3_Pos (3U) âGDMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) ãGDMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk äGDMAMUX_RGCFR_COF4_Pos (4U) åGDMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) æGDMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk çGDMAMUX_RGCFR_COF5_Pos (5U) èGDMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) éGDMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk êGDMAMUX_RGCFR_COF6_Pos (6U) ëGDMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) ìGDMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk íGDMAMUX_RGCFR_COF7_Pos (7U) îGDMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) ïGDMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk ùGDMA2D_CR_START_Pos (0U) úGDMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) ûGDMA2D_CR_START DMA2D_CR_START_Msk üGDMA2D_CR_SUSP_Pos (1U) ýGDMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) þGDMA2D_CR_SUSP DMA2D_CR_SUSP_Msk ÿGDMA2D_CR_ABORT_Pos (2U) HDMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) HDMA2D_CR_ABORT DMA2D_CR_ABORT_Msk HDMA2D_CR_LOM_Pos (6U) HDMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) HDMA2D_CR_LOM DMA2D_CR_LOM_Msk
HDMA2D_CR_TEIE_Pos (8U) HDMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) HDMA2D_CR_TEIE DMA2D_CR_TEIE_Msk HDMA2D_CR_TCIE_Pos (9U) HDMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) HDMA2D_CR_TCIE DMA2D_CR_TCIE_Msk HDMA2D_CR_TWIE_Pos (10U) HDMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) HDMA2D_CR_TWIE DMA2D_CR_TWIE_Msk HDMA2D_CR_CAEIE_Pos (11U) HDMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) HDMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk HDMA2D_CR_CTCIE_Pos (12U) HDMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) HDMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk HDMA2D_CR_CEIE_Pos (13U) HDMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) HDMA2D_CR_CEIE DMA2D_CR_CEIE_Msk HDMA2D_CR_MODE_Pos (16U) HDMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) HDMA2D_CR_MODE DMA2D_CR_MODE_Msk HDMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) HDMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) HDMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) HDMA2D_ISR_TEIF_Pos (0U) ¡HDMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) ¢HDMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk £HDMA2D_ISR_TCIF_Pos (1U) ¤HDMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) ¥HDMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk ¦HDMA2D_ISR_TWIF_Pos (2U) §HDMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) ¨HDMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk ©HDMA2D_ISR_CAEIF_Pos (3U) ªHDMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) «HDMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk ¬HDMA2D_ISR_CTCIF_Pos (4U) HDMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) ®HDMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk ¯HDMA2D_ISR_CEIF_Pos (5U) °HDMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) ±HDMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk µHDMA2D_IFCR_CTEIF_Pos (0U) ¶HDMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) ·HDMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk ¸HDMA2D_IFCR_CTCIF_Pos (1U) ¹HDMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) ºHDMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk »HDMA2D_IFCR_CTWIF_Pos (2U) ¼HDMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) ½HDMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk ¾HDMA2D_IFCR_CAECIF_Pos (3U) ¿HDMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) ÀHDMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk ÁHDMA2D_IFCR_CCTCIF_Pos (4U) ÂHDMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) ÃHDMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk ÄHDMA2D_IFCR_CCEIF_Pos (5U) ÅHDMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) ÆHDMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk ÊHDMA2D_FGMAR_MA_Pos (0U) ËHDMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) ÌHDMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk ÐHDMA2D_FGOR_LO_Pos (0U) ÑHDMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) ÒHDMA2D_FGOR_LO DMA2D_FGOR_LO_Msk ÖHDMA2D_BGMAR_MA_Pos (0U) ×HDMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) ØHDMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk ÜHDMA2D_BGOR_LO_Pos (0U) ÝHDMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) ÞHDMA2D_BGOR_LO DMA2D_BGOR_LO_Msk âHDMA2D_FGPFCCR_CM_Pos (0U) ãHDMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) äHDMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk åHDMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) æHDMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) çHDMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) èHDMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) éHDMA2D_FGPFCCR_CCM_Pos (4U) êHDMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) ëHDMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk ìHDMA2D_FGPFCCR_START_Pos (5U) íHDMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) îHDMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk ïHDMA2D_FGPFCCR_CS_Pos (8U) ðHDMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) ñHDMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk òHDMA2D_FGPFCCR_AM_Pos (16U) óHDMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) ôHDMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk õHDMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) öHDMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) ÷HDMA2D_FGPFCCR_CSS_Pos (18U) øHDMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) ùHDMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk úHDMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) ûHDMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) üHDMA2D_FGPFCCR_AI_Pos (20U) ýHDMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) þHDMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk ÿHDMA2D_FGPFCCR_RBS_Pos (21U) IDMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) IDMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk IDMA2D_FGPFCCR_ALPHA_Pos (24U) IDMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) IDMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk IDMA2D_FGCOLR_BLUE_Pos (0U) IDMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) IDMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk IDMA2D_FGCOLR_GREEN_Pos (8U) IDMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) IDMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk IDMA2D_FGCOLR_RED_Pos (16U) IDMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) IDMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk IDMA2D_BGPFCCR_CM_Pos (0U) IDMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) IDMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk IDMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) IDMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) IDMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) IDMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) IDMA2D_BGPFCCR_CCM_Pos (4U) IDMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) IDMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk IDMA2D_BGPFCCR_START_Pos (5U) IDMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) IDMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk ¡IDMA2D_BGPFCCR_CS_Pos (8U) ¢IDMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) £IDMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk ¤IDMA2D_BGPFCCR_AM_Pos (16U) ¥IDMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) ¦IDMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk §IDMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) ¨IDMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) ©IDMA2D_BGPFCCR_AI_Pos (20U) ªIDMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) «IDMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk ¬IDMA2D_BGPFCCR_RBS_Pos (21U) IDMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) ®IDMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk ¯IDMA2D_BGPFCCR_ALPHA_Pos (24U) °IDMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) ±IDMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk µIDMA2D_BGCOLR_BLUE_Pos (0U) ¶IDMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) ·IDMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk ¸IDMA2D_BGCOLR_GREEN_Pos (8U) ¹IDMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) ºIDMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk »IDMA2D_BGCOLR_RED_Pos (16U) ¼IDMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) ½IDMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk ÁIDMA2D_FGCMAR_MA_Pos (0U) ÂIDMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) ÃIDMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk ÇIDMA2D_BGCMAR_MA_Pos (0U) ÈIDMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) ÉIDMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk ÍIDMA2D_OPFCCR_CM_Pos (0U) ÎIDMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) ÏIDMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk ÐIDMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) ÑIDMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) ÒIDMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) ÓIDMA2D_OPFCCR_SB_Pos (8U) ÔIDMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) ÕIDMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk ÖIDMA2D_OPFCCR_AI_Pos (20U) ×IDMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) ØIDMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk ÙIDMA2D_OPFCCR_RBS_Pos (21U) ÚIDMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) ÛIDMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk áIDMA2D_OCOLR_BLUE_1_Pos (0U) âIDMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) ãIDMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk äIDMA2D_OCOLR_GREEN_1_Pos (8U) åIDMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) æIDMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk çIDMA2D_OCOLR_RED_1_Pos (16U) èIDMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) éIDMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk êIDMA2D_OCOLR_ALPHA_1_Pos (24U) ëIDMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) ìIDMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk ïIDMA2D_OCOLR_BLUE_2_Pos (0U) ðIDMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) ñIDMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk òIDMA2D_OCOLR_GREEN_2_Pos (5U) óIDMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) ôIDMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk õIDMA2D_OCOLR_RED_2_Pos (11U) öIDMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) ÷IDMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk úIDMA2D_OCOLR_BLUE_3_Pos (0U) ûIDMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) üIDMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk ýIDMA2D_OCOLR_GREEN_3_Pos (5U) þIDMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) ÿIDMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk JDMA2D_OCOLR_RED_3_Pos (10U) JDMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) JDMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk JDMA2D_OCOLR_ALPHA_3_Pos (15U) JDMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)
JDMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk JDMA2D_OCOLR_BLUE_4_Pos (0U) JDMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) JDMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk JDMA2D_OCOLR_GREEN_4_Pos (4U) JDMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) JDMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk JDMA2D_OCOLR_RED_4_Pos (8U) JDMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) JDMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk JDMA2D_OCOLR_ALPHA_4_Pos (12U) JDMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) JDMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk JDMA2D_OMAR_MA_Pos (0U) JDMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) JDMA2D_OMAR_MA DMA2D_OMAR_MA_Msk JDMA2D_OOR_LO_Pos (0U) JDMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) JDMA2D_OOR_LO DMA2D_OOR_LO_Msk £JDMA2D_NLR_NL_Pos (0U) ¤JDMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) ¥JDMA2D_NLR_NL DMA2D_NLR_NL_Msk ¦JDMA2D_NLR_PL_Pos (16U) §JDMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) ¨JDMA2D_NLR_PL DMA2D_NLR_PL_Msk ¬JDMA2D_LWR_LW_Pos (0U) JDMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) ®JDMA2D_LWR_LW DMA2D_LWR_LW_Msk ²JDMA2D_AMTCR_EN_Pos (0U) ³JDMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) ´JDMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk µJDMA2D_AMTCR_DT_Pos (8U) ¶JDMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) ·JDMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk ÅJEXTI_RTSR1_TR_Pos (0U) ÆJEXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) ÇJEXTI_RTSR1_TR EXTI_RTSR1_TR_Msk ÈJEXTI_RTSR1_TR0_Pos (0U) ÉJEXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) ÊJEXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk ËJEXTI_RTSR1_TR1_Pos (1U) ÌJEXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) ÍJEXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk ÎJEXTI_RTSR1_TR2_Pos (2U) ÏJEXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) ÐJEXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk ÑJEXTI_RTSR1_TR3_Pos (3U) ÒJEXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) ÓJEXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk ÔJEXTI_RTSR1_TR4_Pos (4U) ÕJEXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) ÖJEXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk ×JEXTI_RTSR1_TR5_Pos (5U) ØJEXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) ÙJEXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk ÚJEXTI_RTSR1_TR6_Pos (6U) ÛJEXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) ÜJEXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk ÝJEXTI_RTSR1_TR7_Pos (7U) ÞJEXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) ßJEXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk àJEXTI_RTSR1_TR8_Pos (8U) áJEXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) âJEXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk ãJEXTI_RTSR1_TR9_Pos (9U) äJEXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) åJEXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk æJEXTI_RTSR1_TR10_Pos (10U) çJEXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) èJEXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk éJEXTI_RTSR1_TR11_Pos (11U) êJEXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) ëJEXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk ìJEXTI_RTSR1_TR12_Pos (12U) íJEXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) îJEXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk ïJEXTI_RTSR1_TR13_Pos (13U) ðJEXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) ñJEXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk òJEXTI_RTSR1_TR14_Pos (14U) óJEXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) ôJEXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk õJEXTI_RTSR1_TR15_Pos (15U) öJEXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) ÷JEXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk øJEXTI_RTSR1_TR16_Pos (16U) ùJEXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) úJEXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk ûJEXTI_RTSR1_TR17_Pos (17U) üJEXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) ýJEXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk þJEXTI_RTSR1_TR18_Pos (18U) ÿJEXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) KEXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk KEXTI_RTSR1_TR19_Pos (19U) KEXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) KEXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk KEXTI_RTSR1_TR20_Pos (20U)
KEXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) KEXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk KEXTI_RTSR1_TR21_Pos (21U) KEXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) KEXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk KEXTI_FTSR1_TR_Pos (0U) KEXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) KEXTI_FTSR1_TR EXTI_FTSR1_TR_Msk KEXTI_FTSR1_TR0_Pos (0U) KEXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) KEXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk KEXTI_FTSR1_TR1_Pos (1U) KEXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) KEXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk KEXTI_FTSR1_TR2_Pos (2U) KEXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) KEXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk KEXTI_FTSR1_TR3_Pos (3U) KEXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) KEXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk KEXTI_FTSR1_TR4_Pos (4U) KEXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) KEXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk KEXTI_FTSR1_TR5_Pos (5U) KEXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) KEXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk ¡KEXTI_FTSR1_TR6_Pos (6U) ¢KEXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) £KEXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk ¤KEXTI_FTSR1_TR7_Pos (7U) ¥KEXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) ¦KEXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk §KEXTI_FTSR1_TR8_Pos (8U) ¨KEXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) ©KEXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk ªKEXTI_FTSR1_TR9_Pos (9U) «KEXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) ¬KEXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk KEXTI_FTSR1_TR10_Pos (10U) ®KEXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) ¯KEXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk °KEXTI_FTSR1_TR11_Pos (11U) ±KEXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) ²KEXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk ³KEXTI_FTSR1_TR12_Pos (12U) ´KEXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) µKEXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk ¶KEXTI_FTSR1_TR13_Pos (13U) ·KEXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) ¸KEXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk ¹KEXTI_FTSR1_TR14_Pos (14U) ºKEXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) »KEXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk ¼KEXTI_FTSR1_TR15_Pos (15U) ½KEXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) ¾KEXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk ¿KEXTI_FTSR1_TR16_Pos (16U) ÀKEXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) ÁKEXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk ÂKEXTI_FTSR1_TR17_Pos (17U) ÃKEXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) ÄKEXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk ÅKEXTI_FTSR1_TR18_Pos (18U) ÆKEXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) ÇKEXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk ÈKEXTI_FTSR1_TR19_Pos (19U) ÉKEXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) ÊKEXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk ËKEXTI_FTSR1_TR20_Pos (20U) ÌKEXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) ÍKEXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk ÎKEXTI_FTSR1_TR21_Pos (21U) ÏKEXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) ÐKEXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk ÓKEXTI_SWIER1_SWIER0_Pos (0U) ÔKEXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) ÕKEXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk ÖKEXTI_SWIER1_SWIER1_Pos (1U) ×KEXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) ØKEXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk ÙKEXTI_SWIER1_SWIER2_Pos (2U) ÚKEXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) ÛKEXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk ÜKEXTI_SWIER1_SWIER3_Pos (3U) ÝKEXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) ÞKEXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk ßKEXTI_SWIER1_SWIER4_Pos (4U) àKEXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) áKEXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk âKEXTI_SWIER1_SWIER5_Pos (5U) ãKEXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) äKEXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk åKEXTI_SWIER1_SWIER6_Pos (6U) æKEXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) çKEXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk èKEXTI_SWIER1_SWIER7_Pos (7U) éKEXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) êKEXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk ëKEXTI_SWIER1_SWIER8_Pos (8U) ìKEXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) íKEXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk îKEXTI_SWIER1_SWIER9_Pos (9U) ïKEXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) ðKEXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk ñKEXTI_SWIER1_SWIER10_Pos (10U) òKEXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) óKEXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk ôKEXTI_SWIER1_SWIER11_Pos (11U) õKEXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) öKEXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk ÷KEXTI_SWIER1_SWIER12_Pos (12U) øKEXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) ùKEXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk úKEXTI_SWIER1_SWIER13_Pos (13U) ûKEXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) üKEXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk ýKEXTI_SWIER1_SWIER14_Pos (14U) þKEXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) ÿKEXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk LEXTI_SWIER1_SWIER15_Pos (15U) LEXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) LEXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk LEXTI_SWIER1_SWIER16_Pos (16U) LEXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
LEXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk LEXTI_SWIER1_SWIER17_Pos (17U) LEXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) LEXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk LEXTI_SWIER1_SWIER18_Pos (18U) LEXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) LEXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk LEXTI_SWIER1_SWIER19_Pos (19U) LEXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) LEXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk LEXTI_SWIER1_SWIER20_Pos (20U) LEXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) LEXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk LEXTI_SWIER1_SWIER21_Pos (21U) LEXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) LEXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk LEXTI_D3PMR1_MR0_Pos (0U) LEXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) LEXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk LEXTI_D3PMR1_MR1_Pos (1U) LEXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) LEXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk LEXTI_D3PMR1_MR2_Pos (2U) LEXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) LEXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk LEXTI_D3PMR1_MR3_Pos (3U) ¡LEXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) ¢LEXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk £LEXTI_D3PMR1_MR4_Pos (4U) ¤LEXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) ¥LEXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk ¦LEXTI_D3PMR1_MR5_Pos (5U) §LEXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) ¨LEXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk ©LEXTI_D3PMR1_MR6_Pos (6U) ªLEXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) «LEXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk ¬LEXTI_D3PMR1_MR7_Pos (7U) LEXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) ®LEXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk ¯LEXTI_D3PMR1_MR8_Pos (8U) °LEXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) ±LEXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk ²LEXTI_D3PMR1_MR9_Pos (9U) ³LEXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) ´LEXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk µLEXTI_D3PMR1_MR10_Pos (10U) ¶LEXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) ·LEXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk ¸LEXTI_D3PMR1_MR11_Pos (11U) ¹LEXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) ºLEXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk »LEXTI_D3PMR1_MR12_Pos (12U) ¼LEXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) ½LEXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk ¾LEXTI_D3PMR1_MR13_Pos (13U) ¿LEXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) ÀLEXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk ÁLEXTI_D3PMR1_MR14_Pos (14U) ÂLEXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) ÃLEXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk ÄLEXTI_D3PMR1_MR15_Pos (15U) ÅLEXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) ÆLEXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk ÇLEXTI_D3PMR1_MR19_Pos (19U) ÈLEXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) ÉLEXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk ÊLEXTI_D3PMR1_MR20_Pos (20U) ËLEXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) ÌLEXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk ÍLEXTI_D3PMR1_MR21_Pos (21U) ÎLEXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) ÏLEXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk ÐLEXTI_D3PMR1_MR25_Pos (24U) ÑLEXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) ÒLEXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk ÕLEXTI_D3PCR1L_PCS0_Pos (0U) ÖLEXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) ×LEXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk ØLEXTI_D3PCR1L_PCS1_Pos (2U) ÙLEXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) ÚLEXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk ÛLEXTI_D3PCR1L_PCS2_Pos (4U) ÜLEXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) ÝLEXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk ÞLEXTI_D3PCR1L_PCS3_Pos (6U) ßLEXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) àLEXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk áLEXTI_D3PCR1L_PCS4_Pos (8U) âLEXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) ãLEXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk äLEXTI_D3PCR1L_PCS5_Pos (10U) åLEXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) æLEXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk çLEXTI_D3PCR1L_PCS6_Pos (12U) èLEXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) éLEXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk êLEXTI_D3PCR1L_PCS7_Pos (14U) ëLEXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) ìLEXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk íLEXTI_D3PCR1L_PCS8_Pos (16U) îLEXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) ïLEXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk ðLEXTI_D3PCR1L_PCS9_Pos (18U) ñLEXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) òLEXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk óLEXTI_D3PCR1L_PCS10_Pos (20U) ôLEXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) õLEXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk öLEXTI_D3PCR1L_PCS11_Pos (22U) ÷LEXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) øLEXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk ùLEXTI_D3PCR1L_PCS12_Pos (24U) úLEXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) ûLEXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk üLEXTI_D3PCR1L_PCS13_Pos (26U) ýLEXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) þLEXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk ÿLEXTI_D3PCR1L_PCS14_Pos (28U) MEXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) MEXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk MEXTI_D3PCR1L_PCS15_Pos (30U) MEXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) MEXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk MEXTI_D3PCR1H_PCS19_Pos (6U) MEXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) MEXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk MEXTI_D3PCR1H_PCS20_Pos (8U) MEXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) MEXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk MEXTI_D3PCR1H_PCS21_Pos (10U) MEXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) MEXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk MEXTI_D3PCR1H_PCS25_Pos (18U) MEXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) MEXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk MEXTI_RTSR2_TR_Pos (17U) MEXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) MEXTI_RTSR2_TR EXTI_RTSR2_TR_Msk MEXTI_RTSR2_TR49_Pos (17U) MEXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) MEXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk MEXTI_RTSR2_TR51_Pos (19U) MEXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) MEXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk MEXTI_FTSR2_TR_Pos (17U) ¡MEXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) ¢MEXTI_FTSR2_TR EXTI_FTSR2_TR_Msk £MEXTI_FTSR2_TR49_Pos (17U) ¤MEXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) ¥MEXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk ¦MEXTI_FTSR2_TR51_Pos (19U) §MEXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) ¨MEXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk «MEXTI_SWIER2_SWIER49_Pos (17U) ¬MEXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) MEXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk ®MEXTI_SWIER2_SWIER51_Pos (19U) ¯MEXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) °MEXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk ³MEXTI_D3PMR2_MR34_Pos (2U) ´MEXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) µMEXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk ¶MEXTI_D3PMR2_MR35_Pos (3U) ·MEXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) ¸MEXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk ¹MEXTI_D3PMR2_MR41_Pos (9U) ºMEXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) »MEXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk ¼MEXTI_D3PMR2_MR48_Pos (16U) ½MEXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) ¾MEXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk ¿MEXTI_D3PMR2_MR49_Pos (17U) ÀMEXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) ÁMEXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk ÂMEXTI_D3PMR2_MR50_Pos (18U) ÃMEXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) ÄMEXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk ÅMEXTI_D3PMR2_MR51_Pos (19U) ÆMEXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) ÇMEXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk ÈMEXTI_D3PMR2_MR52_Pos (20U) ÉMEXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) ÊMEXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk ËMEXTI_D3PMR2_MR53_Pos (21U) ÌMEXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) ÍMEXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk ÏMEXTI_D3PCR2L_PCS34_Pos (4U) ÐMEXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) ÑMEXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk ÒMEXTI_D3PCR2L_PCS35_Pos (6U) ÓMEXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) ÔMEXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk ÕMEXTI_D3PCR2L_PCS41_Pos (18U) ÖMEXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) ×MEXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk ÛMEXTI_D3PCR2H_PCS48_Pos (0U) ÜMEXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) ÝMEXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk ÞMEXTI_D3PCR2H_PCS49_Pos (2U) ßMEXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) àMEXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk áMEXTI_D3PCR2H_PCS50_Pos (4U) âMEXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) ãMEXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk äMEXTI_D3PCR2H_PCS51_Pos (6U) åMEXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) æMEXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk çMEXTI_D3PCR2H_PCS52_Pos (8U) èMEXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) éMEXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk êMEXTI_D3PCR2H_PCS53_Pos (10U) ëMEXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) ìMEXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk îMEXTI_RTSR3_TR_Pos (18U) ïMEXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) ðMEXTI_RTSR3_TR EXTI_RTSR3_TR_Msk ñMEXTI_RTSR3_TR82_Pos (18U) òMEXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) óMEXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk ôMEXTI_RTSR3_TR84_Pos (20U) õMEXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) öMEXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk ÷MEXTI_RTSR3_TR85_Pos (21U) øMEXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) ùMEXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk úMEXTI_RTSR3_TR86_Pos (22U) ûMEXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) üMEXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk ÿMEXTI_FTSR3_TR_Pos (18U) NEXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) NEXTI_FTSR3_TR EXTI_FTSR3_TR_Msk NEXTI_FTSR3_TR82_Pos (18U) NEXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) NEXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk
NEXTI_FTSR3_TR84_Pos (20U) NEXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) NEXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk NEXTI_FTSR3_TR85_Pos (21U) NEXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) NEXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk NEXTI_FTSR3_TR86_Pos (22U) NEXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) NEXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk NEXTI_SWIER3_SWI_Pos (18U) NEXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) NEXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk NEXTI_SWIER3_SWIER82_Pos (18U) NEXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) NEXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk NEXTI_SWIER3_SWIER84_Pos (20U) NEXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) NEXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk NEXTI_SWIER3_SWIER85_Pos (21U) NEXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) NEXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk NEXTI_SWIER3_SWIER86_Pos (22U) NEXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) NEXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk ¡NEXTI_IMR1_IM_Pos (0U) ¢NEXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) £NEXTI_IMR1_IM EXTI_IMR1_IM_Msk ¤NEXTI_IMR1_IM0_Pos (0U) ¥NEXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) ¦NEXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk §NEXTI_IMR1_IM1_Pos (1U) ¨NEXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) ©NEXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk ªNEXTI_IMR1_IM2_Pos (2U) «NEXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) ¬NEXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk NEXTI_IMR1_IM3_Pos (3U) ®NEXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) ¯NEXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk °NEXTI_IMR1_IM4_Pos (4U) ±NEXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) ²NEXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk ³NEXTI_IMR1_IM5_Pos (5U) ´NEXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) µNEXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk ¶NEXTI_IMR1_IM6_Pos (6U) ·NEXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) ¸NEXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk ¹NEXTI_IMR1_IM7_Pos (7U) ºNEXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) »NEXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk ¼NEXTI_IMR1_IM8_Pos (8U) ½NEXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) ¾NEXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk ¿NEXTI_IMR1_IM9_Pos (9U) ÀNEXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) ÁNEXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk ÂNEXTI_IMR1_IM10_Pos (10U) ÃNEXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) ÄNEXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk ÅNEXTI_IMR1_IM11_Pos (11U) ÆNEXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) ÇNEXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk ÈNEXTI_IMR1_IM12_Pos (12U) ÉNEXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) ÊNEXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk ËNEXTI_IMR1_IM13_Pos (13U) ÌNEXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) ÍNEXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk ÎNEXTI_IMR1_IM14_Pos (14U) ÏNEXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) ÐNEXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk ÑNEXTI_IMR1_IM15_Pos (15U) ÒNEXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) ÓNEXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk ÔNEXTI_IMR1_IM16_Pos (16U) ÕNEXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) ÖNEXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk ×NEXTI_IMR1_IM17_Pos (17U) ØNEXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) ÙNEXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk ÚNEXTI_IMR1_IM18_Pos (18U) ÛNEXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) ÜNEXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk ÝNEXTI_IMR1_IM19_Pos (19U) ÞNEXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) ßNEXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk àNEXTI_IMR1_IM20_Pos (20U) áNEXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) âNEXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk ãNEXTI_IMR1_IM21_Pos (21U) äNEXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) åNEXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk æNEXTI_IMR1_IM22_Pos (22U) çNEXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) èNEXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk éNEXTI_IMR1_IM23_Pos (23U) êNEXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) ëNEXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk ìNEXTI_IMR1_IM24_Pos (24U) íNEXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) îNEXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk ïNEXTI_IMR1_IM25_Pos (25U) ðNEXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) ñNEXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk òNEXTI_IMR1_IM26_Pos (26U) óNEXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) ôNEXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk õNEXTI_IMR1_IM27_Pos (27U) öNEXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) ÷NEXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk øNEXTI_IMR1_IM28_Pos (28U) ùNEXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) úNEXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk ûNEXTI_IMR1_IM29_Pos (29U) üNEXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) ýNEXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk þNEXTI_IMR1_IM30_Pos (30U) ÿNEXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) OEXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk OEXTI_IMR1_IM31_Pos (31U) OEXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) OEXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk OEXTI_EMR1_EM_Pos (0U) OEXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) OEXTI_EMR1_EM EXTI_EMR1_EM_Msk OEXTI_EMR1_EM0_Pos (0U) OEXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) OEXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk OEXTI_EMR1_EM1_Pos (1U) OEXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) OEXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk OEXTI_EMR1_EM2_Pos (2U) OEXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) OEXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk OEXTI_EMR1_EM3_Pos (3U) OEXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) OEXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk OEXTI_EMR1_EM4_Pos (4U) OEXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) OEXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk OEXTI_EMR1_EM5_Pos (5U) OEXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) OEXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk OEXTI_EMR1_EM6_Pos (6U) OEXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) OEXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk OEXTI_EMR1_EM7_Pos (7U) OEXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) OEXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk ¡OEXTI_EMR1_EM8_Pos (8U) ¢OEXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) £OEXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk ¤OEXTI_EMR1_EM9_Pos (9U) ¥OEXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) ¦OEXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk §OEXTI_EMR1_EM10_Pos (10U) ¨OEXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) ©OEXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk ªOEXTI_EMR1_EM11_Pos (11U) «OEXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) ¬OEXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk OEXTI_EMR1_EM12_Pos (12U) ®OEXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) ¯OEXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk °OEXTI_EMR1_EM13_Pos (13U) ±OEXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) ²OEXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk ³OEXTI_EMR1_EM14_Pos (14U) ´OEXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) µOEXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk ¶OEXTI_EMR1_EM15_Pos (15U) ·OEXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) ¸OEXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk ¹OEXTI_EMR1_EM16_Pos (16U) ºOEXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) »OEXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk ¼OEXTI_EMR1_EM17_Pos (17U) ½OEXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) ¾OEXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk ¿OEXTI_EMR1_EM18_Pos (18U) ÀOEXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) ÁOEXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk ÂOEXTI_EMR1_EM20_Pos (20U) ÃOEXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) ÄOEXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk ÅOEXTI_EMR1_EM21_Pos (21U) ÆOEXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) ÇOEXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk ÈOEXTI_EMR1_EM22_Pos (22U) ÉOEXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) ÊOEXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk ËOEXTI_EMR1_EM23_Pos (23U) ÌOEXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) ÍOEXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk ÎOEXTI_EMR1_EM24_Pos (24U) ÏOEXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) ÐOEXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk ÑOEXTI_EMR1_EM25_Pos (25U) ÒOEXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) ÓOEXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk ÔOEXTI_EMR1_EM26_Pos (26U) ÕOEXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) ÖOEXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk ×OEXTI_EMR1_EM27_Pos (27U) ØOEXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) ÙOEXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk ÚOEXTI_EMR1_EM28_Pos (28U) ÛOEXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) ÜOEXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk ÝOEXTI_EMR1_EM29_Pos (29U) ÞOEXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) ßOEXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk àOEXTI_EMR1_EM30_Pos (30U) áOEXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) âOEXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk ãOEXTI_EMR1_EM31_Pos (31U) äOEXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) åOEXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk èOEXTI_PR1_PR_Pos (0U) éOEXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) êOEXTI_PR1_PR EXTI_PR1_PR_Msk ëOEXTI_PR1_PR0_Pos (0U) ìOEXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) íOEXTI_PR1_PR0 EXTI_PR1_PR0_Msk îOEXTI_PR1_PR1_Pos (1U) ïOEXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) ðOEXTI_PR1_PR1 EXTI_PR1_PR1_Msk ñOEXTI_PR1_PR2_Pos (2U) òOEXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) óOEXTI_PR1_PR2 EXTI_PR1_PR2_Msk ôOEXTI_PR1_PR3_Pos (3U) õOEXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) öOEXTI_PR1_PR3 EXTI_PR1_PR3_Msk ÷OEXTI_PR1_PR4_Pos (4U) øOEXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) ùOEXTI_PR1_PR4 EXTI_PR1_PR4_Msk úOEXTI_PR1_PR5_Pos (5U) ûOEXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) üOEXTI_PR1_PR5 EXTI_PR1_PR5_Msk ýOEXTI_PR1_PR6_Pos (6U) þOEXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) ÿOEXTI_PR1_PR6 EXTI_PR1_PR6_Msk PEXTI_PR1_PR7_Pos (7U) PEXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) PEXTI_PR1_PR7 EXTI_PR1_PR7_Msk PEXTI_PR1_PR8_Pos (8U) PEXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
PEXTI_PR1_PR8 EXTI_PR1_PR8_Msk PEXTI_PR1_PR9_Pos (9U) PEXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) PEXTI_PR1_PR9 EXTI_PR1_PR9_Msk PEXTI_PR1_PR10_Pos (10U) PEXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) PEXTI_PR1_PR10 EXTI_PR1_PR10_Msk PEXTI_PR1_PR11_Pos (11U) PEXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) PEXTI_PR1_PR11 EXTI_PR1_PR11_Msk PEXTI_PR1_PR12_Pos (12U) PEXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) PEXTI_PR1_PR12 EXTI_PR1_PR12_Msk PEXTI_PR1_PR13_Pos (13U) PEXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) PEXTI_PR1_PR13 EXTI_PR1_PR13_Msk PEXTI_PR1_PR14_Pos (14U) PEXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) PEXTI_PR1_PR14 EXTI_PR1_PR14_Msk PEXTI_PR1_PR15_Pos (15U) PEXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) PEXTI_PR1_PR15 EXTI_PR1_PR15_Msk PEXTI_PR1_PR16_Pos (16U) PEXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) PEXTI_PR1_PR16 EXTI_PR1_PR16_Msk PEXTI_PR1_PR17_Pos (17U) PEXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) PEXTI_PR1_PR17 EXTI_PR1_PR17_Msk ¡PEXTI_PR1_PR18_Pos (18U) ¢PEXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) £PEXTI_PR1_PR18 EXTI_PR1_PR18_Msk ¤PEXTI_PR1_PR19_Pos (19U) ¥PEXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) ¦PEXTI_PR1_PR19 EXTI_PR1_PR19_Msk §PEXTI_PR1_PR20_Pos (20U) ¨PEXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) ©PEXTI_PR1_PR20 EXTI_PR1_PR20_Msk ªPEXTI_PR1_PR21_Pos (21U) «PEXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) ¬PEXTI_PR1_PR21 EXTI_PR1_PR21_Msk ¯PEXTI_IMR2_IM_Pos (0U) °PEXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) ±PEXTI_IMR2_IM EXTI_IMR2_IM_Msk ²PEXTI_IMR2_IM32_Pos (0U) ³PEXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) ´PEXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk µPEXTI_IMR2_IM33_Pos (1U) ¶PEXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) ·PEXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk ¸PEXTI_IMR2_IM34_Pos (2U) ¹PEXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) ºPEXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk »PEXTI_IMR2_IM35_Pos (3U) ¼PEXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) ½PEXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk ¾PEXTI_IMR2_IM36_Pos (4U) ¿PEXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) ÀPEXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk ÁPEXTI_IMR2_IM37_Pos (5U) ÂPEXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) ÃPEXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk ÄPEXTI_IMR2_IM38_Pos (6U) ÅPEXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) ÆPEXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk ÇPEXTI_IMR2_IM39_Pos (7U) ÈPEXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) ÉPEXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk ÊPEXTI_IMR2_IM40_Pos (8U) ËPEXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) ÌPEXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk ÍPEXTI_IMR2_IM41_Pos (9U) ÎPEXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) ÏPEXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk ÐPEXTI_IMR2_IM42_Pos (10U) ÑPEXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) ÒPEXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk ÓPEXTI_IMR2_IM43_Pos (11U) ÔPEXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) ÕPEXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk ÖPEXTI_IMR2_IM44_Pos (12U) ×PEXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) ØPEXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk ÙPEXTI_IMR2_IM46_Pos (14U) ÚPEXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) ÛPEXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk ÜPEXTI_IMR2_IM47_Pos (15U) ÝPEXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) ÞPEXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk ßPEXTI_IMR2_IM48_Pos (16U) àPEXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) áPEXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk âPEXTI_IMR2_IM49_Pos (17U) ãPEXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) äPEXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk åPEXTI_IMR2_IM50_Pos (18U) æPEXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) çPEXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk èPEXTI_IMR2_IM51_Pos (19U) éPEXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) êPEXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk ëPEXTI_IMR2_IM52_Pos (20U) ìPEXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) íPEXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk îPEXTI_IMR2_IM53_Pos (21U) ïPEXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) ðPEXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk ñPEXTI_IMR2_IM54_Pos (22U) òPEXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) óPEXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk ôPEXTI_IMR2_IM55_Pos (23U) õPEXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) öPEXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk ÷PEXTI_IMR2_IM56_Pos (24U) øPEXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) ùPEXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk úPEXTI_IMR2_IM57_Pos (25U) ûPEXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) üPEXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk ýPEXTI_IMR2_IM58_Pos (26U) þPEXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) ÿPEXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk QEXTI_IMR2_IM59_Pos (27U) QEXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) QEXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk QEXTI_IMR2_IM60_Pos (28U) QEXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
QEXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk QEXTI_IMR2_IM61_Pos (29U) QEXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) QEXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk QEXTI_IMR2_IM62_Pos (30U) QEXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) QEXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk QEXTI_IMR2_IM63_Pos (31U) QEXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) QEXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk QEXTI_EMR2_EM_Pos (0U) QEXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) QEXTI_EMR2_EM EXTI_EMR2_EM_Msk QEXTI_EMR2_EM32_Pos (0U) QEXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) QEXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk QEXTI_EMR2_EM33_Pos (1U) QEXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) QEXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk QEXTI_EMR2_EM34_Pos (2U) QEXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) QEXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk QEXTI_EMR2_EM35_Pos (3U) QEXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) QEXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk QEXTI_EMR2_EM36_Pos (4U) ¡QEXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) ¢QEXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk £QEXTI_EMR2_EM37_Pos (5U) ¤QEXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) ¥QEXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk ¦QEXTI_EMR2_EM38_Pos (6U) §QEXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) ¨QEXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk ©QEXTI_EMR2_EM39_Pos (7U) ªQEXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) «QEXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk ¬QEXTI_EMR2_EM40_Pos (8U) QEXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) ®QEXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk ¯QEXTI_EMR2_EM41_Pos (9U) °QEXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) ±QEXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk ²QEXTI_EMR2_EM42_Pos (10U) ³QEXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) ´QEXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk µQEXTI_EMR2_EM43_Pos (11U) ¶QEXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) ·QEXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk ¸QEXTI_EMR2_EM44_Pos (12U) ¹QEXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) ºQEXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk »QEXTI_EMR2_EM46_Pos (14U) ¼QEXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) ½QEXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk ¾QEXTI_EMR2_EM47_Pos (15U) ¿QEXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) ÀQEXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk ÁQEXTI_EMR2_EM48_Pos (16U) ÂQEXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) ÃQEXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk ÄQEXTI_EMR2_EM49_Pos (17U) ÅQEXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) ÆQEXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk ÇQEXTI_EMR2_EM50_Pos (18U) ÈQEXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) ÉQEXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk ÊQEXTI_EMR2_EM51_Pos (19U) ËQEXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) ÌQEXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk ÍQEXTI_EMR2_EM52_Pos (20U) ÎQEXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) ÏQEXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk ÐQEXTI_EMR2_EM53_Pos (21U) ÑQEXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) ÒQEXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk ÓQEXTI_EMR2_EM54_Pos (22U) ÔQEXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) ÕQEXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk ÖQEXTI_EMR2_EM55_Pos (23U) ×QEXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) ØQEXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk ÙQEXTI_EMR2_EM56_Pos (24U) ÚQEXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) ÛQEXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk ÜQEXTI_EMR2_EM57_Pos (25U) ÝQEXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) ÞQEXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk ßQEXTI_EMR2_EM58_Pos (26U) àQEXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) áQEXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk âQEXTI_EMR2_EM59_Pos (27U) ãQEXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) äQEXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk åQEXTI_EMR2_EM60_Pos (28U) æQEXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) çQEXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk èQEXTI_EMR2_EM61_Pos (29U) éQEXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) êQEXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk ëQEXTI_EMR2_EM62_Pos (30U) ìQEXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) íQEXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk îQEXTI_EMR2_EM63_Pos (31U) ïQEXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) ðQEXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk óQEXTI_PR2_PR_Pos (17U) ôQEXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) õQEXTI_PR2_PR EXTI_PR2_PR_Msk öQEXTI_PR2_PR49_Pos (17U) ÷QEXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) øQEXTI_PR2_PR49 EXTI_PR2_PR49_Msk ùQEXTI_PR2_PR51_Pos (19U) úQEXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) ûQEXTI_PR2_PR51 EXTI_PR2_PR51_Msk þQEXTI_IMR3_IM_Pos (0U) ÿQEXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) REXTI_IMR3_IM EXTI_IMR3_IM_Msk REXTI_IMR3_IM64_Pos (0U) REXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) REXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk REXTI_IMR3_IM65_Pos (1U)
REXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) REXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk REXTI_IMR3_IM66_Pos (2U) REXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) REXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk REXTI_IMR3_IM67_Pos (3U) REXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) REXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk REXTI_IMR3_IM68_Pos (4U) REXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) REXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk REXTI_IMR3_IM69_Pos (5U) REXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) REXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk REXTI_IMR3_IM70_Pos (6U) REXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) REXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk REXTI_IMR3_IM71_Pos (7U) REXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) REXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk REXTI_IMR3_IM72_Pos (8U) REXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) REXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk REXTI_IMR3_IM73_Pos (9U) REXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) REXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk REXTI_IMR3_IM74_Pos (10U) REXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) ¡REXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk ¢REXTI_IMR3_IM75_Pos (11U) £REXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) ¤REXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk ¥REXTI_IMR3_IM76_Pos (12U) ¦REXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) §REXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk ¨REXTI_IMR3_IM77_Pos (13U) ©REXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) ªREXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk «REXTI_IMR3_IM78_Pos (14U) ¬REXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) REXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk ®REXTI_IMR3_IM79_Pos (15U) ¯REXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) °REXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk ±REXTI_IMR3_IM80_Pos (16U) ²REXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) ³REXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk ´REXTI_IMR3_IM82_Pos (18U) µREXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) ¶REXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk ·REXTI_IMR3_IM84_Pos (20U) ¸REXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) ¹REXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk ºREXTI_IMR3_IM85_Pos (21U) »REXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) ¼REXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk ½REXTI_IMR3_IM86_Pos (22U) ¾REXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) ¿REXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk ÀREXTI_IMR3_IM87_Pos (23U) ÁREXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) ÂREXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk ÆREXTI_EMR3_EM_Pos (0U) ÇREXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) ÈREXTI_EMR3_EM EXTI_EMR3_EM_Msk ÉREXTI_EMR3_EM64_Pos (0U) ÊREXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) ËREXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk ÌREXTI_EMR3_EM65_Pos (1U) ÍREXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) ÎREXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk ÏREXTI_EMR3_EM66_Pos (2U) ÐREXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) ÑREXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk ÒREXTI_EMR3_EM67_Pos (3U) ÓREXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) ÔREXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk ÕREXTI_EMR3_EM68_Pos (4U) ÖREXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) ×REXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk ØREXTI_EMR3_EM69_Pos (5U) ÙREXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) ÚREXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk ÛREXTI_EMR3_EM70_Pos (6U) ÜREXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) ÝREXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk ÞREXTI_EMR3_EM71_Pos (7U) ßREXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) àREXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk áREXTI_EMR3_EM72_Pos (8U) âREXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) ãREXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk äREXTI_EMR3_EM73_Pos (9U) åREXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) æREXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk çREXTI_EMR3_EM74_Pos (10U) èREXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) éREXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk êREXTI_EMR3_EM75_Pos (11U) ëREXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) ìREXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk íREXTI_EMR3_EM76_Pos (12U) îREXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) ïREXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk ðREXTI_EMR3_EM77_Pos (13U) ñREXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) òREXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk óREXTI_EMR3_EM78_Pos (14U) ôREXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) õREXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk öREXTI_EMR3_EM79_Pos (15U) ÷REXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) øREXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk ùREXTI_EMR3_EM80_Pos (16U) úREXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) ûREXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk üREXTI_EMR3_EM81_Pos (17U) ýREXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) þREXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk ÿREXTI_EMR3_EM82_Pos (18U) SEXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) SEXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk SEXTI_EMR3_EM84_Pos (20U) SEXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) SEXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk
SEXTI_EMR3_EM85_Pos (21U) SEXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) SEXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk SEXTI_EMR3_EM86_Pos (22U) SEXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) SEXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk SEXTI_EMR3_EM87_Pos (23U) SEXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) SEXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk SEXTI_PR3_PR_Pos (18U) SEXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) SEXTI_PR3_PR EXTI_PR3_PR_Msk SEXTI_PR3_PR82_Pos (18U) SEXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) SEXTI_PR3_PR82 EXTI_PR3_PR82_Msk SEXTI_PR3_PR84_Pos (20U) SEXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) SEXTI_PR3_PR84 EXTI_PR3_PR84_Msk SEXTI_PR3_PR85_Pos (21U) SEXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) SEXTI_PR3_PR85 EXTI_PR3_PR85_Msk SEXTI_PR3_PR86_Pos (22U) SEXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) SEXTI_PR3_PR86 EXTI_PR3_PR86_Msk §SFLASH_SIZE_DATA_REGISTER 0x1FF1E880U ¨SFLASH_SECTOR_TOTAL 8U ©SFLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) ¬SFLASH_BANK_SIZE (FLASH_SIZE >> 1) SFLASH_SECTOR_SIZE 0x00020000UL ®SFLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS ¯SFLASH_NB_32BITWORD_IN_FLASHWORD 8U °SDUAL_BANK ³SFLASH_ACR_LATENCY_Pos (0U) ´SFLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) µSFLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk ¶SFLASH_ACR_LATENCY_0WS (0x00000000UL) ·SFLASH_ACR_LATENCY_1WS (0x00000001UL) ¸SFLASH_ACR_LATENCY_2WS (0x00000002UL) ¹SFLASH_ACR_LATENCY_3WS (0x00000003UL) ºSFLASH_ACR_LATENCY_4WS (0x00000004UL) »SFLASH_ACR_LATENCY_5WS (0x00000005UL) ¼SFLASH_ACR_LATENCY_6WS (0x00000006UL) ½SFLASH_ACR_LATENCY_7WS (0x00000007UL) ¿SFLASH_ACR_WRHIGHFREQ_Pos (4U) ÀSFLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) ÁSFLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk ÂSFLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) ÃSFLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) ÆSFLASH_ACR_LATENCY_8WS (0x00000008UL) ÇSFLASH_ACR_LATENCY_9WS (0x00000009UL) ÈSFLASH_ACR_LATENCY_10WS (0x0000000AUL) ÉSFLASH_ACR_LATENCY_11WS (0x0000000BUL) ÊSFLASH_ACR_LATENCY_12WS (0x0000000CUL) ËSFLASH_ACR_LATENCY_13WS (0x0000000DUL) ÌSFLASH_ACR_LATENCY_14WS (0x0000000EUL) ÍSFLASH_ACR_LATENCY_15WS (0x0000000FUL) ÏSFLASH_CR_LOCK_Pos (0U) ÐSFLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) ÑSFLASH_CR_LOCK FLASH_CR_LOCK_Msk ÒSFLASH_CR_PG_Pos (1U) ÓSFLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) ÔSFLASH_CR_PG FLASH_CR_PG_Msk ÕSFLASH_CR_SER_Pos (2U) ÖSFLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) ×SFLASH_CR_SER FLASH_CR_SER_Msk ØSFLASH_CR_BER_Pos (3U) ÙSFLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) ÚSFLASH_CR_BER FLASH_CR_BER_Msk ÛSFLASH_CR_PSIZE_Pos (4U) ÜSFLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) ÝSFLASH_CR_PSIZE FLASH_CR_PSIZE_Msk ÞSFLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) ßSFLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) àSFLASH_CR_FW_Pos (6U) áSFLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) âSFLASH_CR_FW FLASH_CR_FW_Msk ãSFLASH_CR_START_Pos (7U) äSFLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) åSFLASH_CR_START FLASH_CR_START_Msk æSFLASH_CR_SNB_Pos (8U) çSFLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) èSFLASH_CR_SNB FLASH_CR_SNB_Msk éSFLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) êSFLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) ëSFLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) ìSFLASH_CR_CRC_EN_Pos (15U) íSFLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) îSFLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk ïSFLASH_CR_EOPIE_Pos (16U) ðSFLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) ñSFLASH_CR_EOPIE FLASH_CR_EOPIE_Msk òSFLASH_CR_WRPERRIE_Pos (17U) óSFLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) ôSFLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk õSFLASH_CR_PGSERRIE_Pos (18U) öSFLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) ÷SFLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk øSFLASH_CR_STRBERRIE_Pos (19U) ùSFLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) úSFLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk ûSFLASH_CR_INCERRIE_Pos (21U) üSFLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) ýSFLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk þSFLASH_CR_OPERRIE_Pos (22U) ÿSFLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) TFLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk TFLASH_CR_RDPERRIE_Pos (23U) TFLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) TFLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk TFLASH_CR_RDSERRIE_Pos (24U)
TFLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) TFLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk TFLASH_CR_SNECCERRIE_Pos (25U) TFLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) TFLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk TFLASH_CR_DBECCERRIE_Pos (26U) TFLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) TFLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk TFLASH_CR_CRCENDIE_Pos (27U) TFLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) TFLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk TFLASH_CR_CRCRDERRIE_Pos (28U) TFLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) TFLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk TFLASH_SR_BSY_Pos (0U) TFLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) TFLASH_SR_BSY FLASH_SR_BSY_Msk TFLASH_SR_WBNE_Pos (1U) TFLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) TFLASH_SR_WBNE FLASH_SR_WBNE_Msk TFLASH_SR_QW_Pos (2U) TFLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) TFLASH_SR_QW FLASH_SR_QW_Msk TFLASH_SR_CRC_BUSY_Pos (3U) TFLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) TFLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk ¡TFLASH_SR_EOP_Pos (16U) ¢TFLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) £TFLASH_SR_EOP FLASH_SR_EOP_Msk ¤TFLASH_SR_WRPERR_Pos (17U) ¥TFLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) ¦TFLASH_SR_WRPERR FLASH_SR_WRPERR_Msk §TFLASH_SR_PGSERR_Pos (18U) ¨TFLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) ©TFLASH_SR_PGSERR FLASH_SR_PGSERR_Msk ªTFLASH_SR_STRBERR_Pos (19U) «TFLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) ¬TFLASH_SR_STRBERR FLASH_SR_STRBERR_Msk TFLASH_SR_INCERR_Pos (21U) ®TFLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) ¯TFLASH_SR_INCERR FLASH_SR_INCERR_Msk °TFLASH_SR_OPERR_Pos (22U) ±TFLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) ²TFLASH_SR_OPERR FLASH_SR_OPERR_Msk ³TFLASH_SR_RDPERR_Pos (23U) ´TFLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) µTFLASH_SR_RDPERR FLASH_SR_RDPERR_Msk ¶TFLASH_SR_RDSERR_Pos (24U) ·TFLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) ¸TFLASH_SR_RDSERR FLASH_SR_RDSERR_Msk ¹TFLASH_SR_SNECCERR_Pos (25U) ºTFLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) »TFLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk ¼TFLASH_SR_DBECCERR_Pos (26U) ½TFLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) ¾TFLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk ¿TFLASH_SR_CRCEND_Pos (27U) ÀTFLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) ÁTFLASH_SR_CRCEND FLASH_SR_CRCEND_Msk ÂTFLASH_SR_CRCRDERR_Pos (28U) ÃTFLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) ÄTFLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk ÇTFLASH_CCR_CLR_EOP_Pos (16U) ÈTFLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) ÉTFLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk ÊTFLASH_CCR_CLR_WRPERR_Pos (17U) ËTFLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) ÌTFLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk ÍTFLASH_CCR_CLR_PGSERR_Pos (18U) ÎTFLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) ÏTFLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk ÐTFLASH_CCR_CLR_STRBERR_Pos (19U) ÑTFLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) ÒTFLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk ÓTFLASH_CCR_CLR_INCERR_Pos (21U) ÔTFLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) ÕTFLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk ÖTFLASH_CCR_CLR_OPERR_Pos (22U) ×TFLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) ØTFLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk ÙTFLASH_CCR_CLR_RDPERR_Pos (23U) ÚTFLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) ÛTFLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk ÜTFLASH_CCR_CLR_RDSERR_Pos (24U) ÝTFLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) ÞTFLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk ßTFLASH_CCR_CLR_SNECCERR_Pos (25U) àTFLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) áTFLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk âTFLASH_CCR_CLR_DBECCERR_Pos (26U) ãTFLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) äTFLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk åTFLASH_CCR_CLR_CRCEND_Pos (27U) æTFLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) çTFLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk èTFLASH_CCR_CLR_CRCRDERR_Pos (28U) éTFLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) êTFLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk íTFLASH_OPTCR_OPTLOCK_Pos (0U) îTFLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) ïTFLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk ðTFLASH_OPTCR_OPTSTART_Pos (1U) ñTFLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) òTFLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk óTFLASH_OPTCR_MER_Pos (4U) ôTFLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) õTFLASH_OPTCR_MER FLASH_OPTCR_MER_Msk öTFLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) ÷TFLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) øTFLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk ùTFLASH_OPTCR_SWAP_BANK_Pos (31U) úTFLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) ûTFLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk þTFLASH_OPTSR_OPT_BUSY_Pos (0U) ÿTFLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) UFLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk UFLASH_OPTSR_BOR_LEV_Pos (2U) UFLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) UFLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk UFLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
UFLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) UFLASH_OPTSR_IWDG1_SW_Pos (4U) UFLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) UFLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk UFLASH_OPTSR_NRST_STOP_D1_Pos (6U) UFLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) UFLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk UFLASH_OPTSR_NRST_STBY_D1_Pos (7U) UFLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) UFLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk UFLASH_OPTSR_RDP_Pos (8U) UFLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) UFLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk UFLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) UFLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) UFLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk UFLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) UFLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) UFLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk UFLASH_OPTSR_ST_RAM_SIZE_Pos (19U) UFLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) UFLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk UFLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) UFLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) UFLASH_OPTSR_SECURITY_Pos (21U) UFLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) UFLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk UFLASH_OPTSR_IO_HSLV_Pos (29U) ¡UFLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) ¢UFLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk £UFLASH_OPTSR_OPTCHANGEERR_Pos (30U) ¤UFLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) ¥UFLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk ¦UFLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) §UFLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) ¨UFLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk «UFLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) ¬UFLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) UFLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk °UFLASH_PRAR_PROT_AREA_START_Pos (0U) ±UFLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) ²UFLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk ³UFLASH_PRAR_PROT_AREA_END_Pos (16U) ´UFLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) µUFLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk ¶UFLASH_PRAR_DMEP_Pos (31U) ·UFLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) ¸UFLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk »UFLASH_SCAR_SEC_AREA_START_Pos (0U) ¼UFLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) ½UFLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk ¾UFLASH_SCAR_SEC_AREA_END_Pos (16U) ¿UFLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) ÀUFLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk ÁUFLASH_SCAR_DMES_Pos (31U) ÂUFLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) ÃUFLASH_SCAR_DMES FLASH_SCAR_DMES_Msk ÆUFLASH_WPSN_WRPSN_Pos (0U) ÇUFLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) ÈUFLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk ËUFLASH_BOOT_ADD0_Pos (0U) ÌUFLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) ÍUFLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk ÎUFLASH_BOOT_ADD1_Pos (16U) ÏUFLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) ÐUFLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk ÔUFLASH_CRCCR_CRC_SECT_Pos (0U) ÕUFLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) ÖUFLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk ×UFLASH_CRCCR_CRC_BY_SECT_Pos (8U) ØUFLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) ÙUFLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk ÚUFLASH_CRCCR_ADD_SECT_Pos (9U) ÛUFLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) ÜUFLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk ÝUFLASH_CRCCR_CLEAN_SECT_Pos (10U) ÞUFLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) ßUFLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk àUFLASH_CRCCR_START_CRC_Pos (16U) áUFLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) âUFLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk ãUFLASH_CRCCR_CLEAN_CRC_Pos (17U) äUFLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) åUFLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk æUFLASH_CRCCR_CRC_BURST_Pos (20U) çUFLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) èUFLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk éUFLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) êUFLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) ëUFLASH_CRCCR_ALL_BANK_Pos (22U) ìUFLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) íUFLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk ðUFLASH_CRCSADD_CRC_START_ADDR_Pos (0U) ñUFLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) òUFLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk õUFLASH_CRCEADD_CRC_END_ADDR_Pos (0U) öUFLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) ÷UFLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk úUFLASH_CRCDATA_CRC_DATA_Pos (0U) ûUFLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) üUFLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk ÿUFLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) VFLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) VFLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk VFMC_BCR1_CCLKEN_Pos (20U) VFMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) VFMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk VFMC_BCR1_WFDIS_Pos (21U) VFMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) VFMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk VFMC_BCR1_BMAP_Pos (24U) VFMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) VFMC_BCR1_BMAP FMC_BCR1_BMAP_Msk VFMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) VFMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) VFMC_BCR1_FMCEN_Pos (31U) VFMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) VFMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk VFMC_BCRx_MBKEN_Pos (0U) VFMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) VFMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk VFMC_BCRx_MUXEN_Pos (1U) VFMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) VFMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk ¡VFMC_BCRx_MTYP_Pos (2U) ¢VFMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) £VFMC_BCRx_MTYP FMC_BCRx_MTYP_Msk ¤VFMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) ¥VFMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) §VFMC_BCRx_MWID_Pos (4U) ¨VFMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) ©VFMC_BCRx_MWID FMC_BCRx_MWID_Msk ªVFMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) «VFMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) VFMC_BCRx_FACCEN_Pos (6U) ®VFMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) ¯VFMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk °VFMC_BCRx_BURSTEN_Pos (8U) ±VFMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) ²VFMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk ³VFMC_BCRx_WAITPOL_Pos (9U) ´VFMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) µVFMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk ¶VFMC_BCRx_WAITCFG_Pos (11U) ·VFMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) ¸VFMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk ¹VFMC_BCRx_WREN_Pos (12U) ºVFMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) »VFMC_BCRx_WREN FMC_BCRx_WREN_Msk ¼VFMC_BCRx_WAITEN_Pos (13U) ½VFMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) ¾VFMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk ¿VFMC_BCRx_EXTMOD_Pos (14U) ÀVFMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) ÁVFMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk ÂVFMC_BCRx_ASYNCWAIT_Pos (15U) ÃVFMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) ÄVFMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk ÆVFMC_BCRx_CPSIZE_Pos (16U) ÇVFMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) ÈVFMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk ÉVFMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) ÊVFMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) ËVFMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) ÍVFMC_BCRx_CBURSTRW_Pos (19U) ÎVFMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) ÏVFMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk ÒVFMC_BTRx_ADDSET_Pos (0U) ÓVFMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) ÔVFMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk ÕVFMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) ÖVFMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) ×VFMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) ØVFMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) ÚVFMC_BTRx_ADDHLD_Pos (4U) ÛVFMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) ÜVFMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk ÝVFMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) ÞVFMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) ßVFMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) àVFMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) âVFMC_BTRx_DATAST_Pos (8U) ãVFMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) äVFMC_BTRx_DATAST FMC_BTRx_DATAST_Msk åVFMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) æVFMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) çVFMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) èVFMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) éVFMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) êVFMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) ëVFMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) ìVFMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) îVFMC_BTRx_BUSTURN_Pos (16U) ïVFMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) ðVFMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk ñVFMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) òVFMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) óVFMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) ôVFMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) öVFMC_BTRx_CLKDIV_Pos (20U) ÷VFMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) øVFMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk ùVFMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) úVFMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) ûVFMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) üVFMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) þVFMC_BTRx_DATLAT_Pos (24U) ÿVFMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) WFMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk WFMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) WFMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) WFMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) WFMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) WFMC_BTRx_ACCMOD_Pos (28U) WFMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) WFMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk WFMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) WFMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) WFMC_BWTRx_ADDSET_Pos (0U) WFMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) WFMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk WFMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) WFMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) WFMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) WFMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) WFMC_BWTRx_ADDHLD_Pos (4U) WFMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) WFMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk WFMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) WFMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) WFMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) WFMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) WFMC_BWTRx_DATAST_Pos (8U) WFMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) WFMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk WFMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) ¡WFMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) ¢WFMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) £WFMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) ¤WFMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) ¥WFMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) ¦WFMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) §WFMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) ©WFMC_BWTRx_BUSTURN_Pos (16U) ªWFMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) «WFMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk ¬WFMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) WFMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) ®WFMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) ¯WFMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) ±WFMC_BWTRx_ACCMOD_Pos (28U) ²WFMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) ³WFMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk ´WFMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) µWFMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) ¸WFMC_PCR_PWAITEN_Pos (1U) ¹WFMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) ºWFMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk »WFMC_PCR_PBKEN_Pos (2U) ¼WFMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) ½WFMC_PCR_PBKEN FMC_PCR_PBKEN_Msk ¿WFMC_PCR_PWID_Pos (4U) ÀWFMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) ÁWFMC_PCR_PWID FMC_PCR_PWID_Msk ÂWFMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) ÃWFMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) ÅWFMC_PCR_ECCEN_Pos (6U) ÆWFMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) ÇWFMC_PCR_ECCEN FMC_PCR_ECCEN_Msk ÉWFMC_PCR_TCLR_Pos (9U) ÊWFMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) ËWFMC_PCR_TCLR FMC_PCR_TCLR_Msk ÌWFMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) ÍWFMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) ÎWFMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) ÏWFMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) ÑWFMC_PCR_TAR_Pos (13U) ÒWFMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) ÓWFMC_PCR_TAR FMC_PCR_TAR_Msk ÔWFMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) ÕWFMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) ÖWFMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) ×WFMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) ÙWFMC_PCR_ECCPS_Pos (17U) ÚWFMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) ÛWFMC_PCR_ECCPS FMC_PCR_ECCPS_Msk ÜWFMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) ÝWFMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) ÞWFMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) áWFMC_SR_IRS_Pos (0U) âWFMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) ãWFMC_SR_IRS FMC_SR_IRS_Msk äWFMC_SR_ILS_Pos (1U) åWFMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) æWFMC_SR_ILS FMC_SR_ILS_Msk çWFMC_SR_IFS_Pos (2U) èWFMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) éWFMC_SR_IFS FMC_SR_IFS_Msk êWFMC_SR_IREN_Pos (3U) ëWFMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) ìWFMC_SR_IREN FMC_SR_IREN_Msk íWFMC_SR_ILEN_Pos (4U) îWFMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) ïWFMC_SR_ILEN FMC_SR_ILEN_Msk ðWFMC_SR_IFEN_Pos (5U) ñWFMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) òWFMC_SR_IFEN FMC_SR_IFEN_Msk óWFMC_SR_FEMPT_Pos (6U) ôWFMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) õWFMC_SR_FEMPT FMC_SR_FEMPT_Msk øWFMC_PMEM_MEMSET_Pos (0U) ùWFMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) úWFMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk ûWFMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) üWFMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) ýWFMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) þWFMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) ÿWFMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) XFMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) XFMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) XFMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) XFMC_PMEM_MEMWAIT_Pos (8U)
XFMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk XFMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) XFMC_PMEM_MEMHOLD_Pos (16U) XFMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk XFMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) XFMC_PMEM_MEMHIZ_Pos (24U) XFMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) XFMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk XFMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) XFMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) ¡XFMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) ¢XFMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) £XFMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) ¤XFMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) ¥XFMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) ¦XFMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) ©XFMC_PATT_ATTSET_Pos (0U) ªXFMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) «XFMC_PATT_ATTSET FMC_PATT_ATTSET_Msk ¬XFMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) XFMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) ®XFMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) ¯XFMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) °XFMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) ±XFMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) ²XFMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) ³XFMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) µXFMC_PATT_ATTWAIT_Pos (8U) ¶XFMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) ·XFMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk ¸XFMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) ¹XFMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) ºXFMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) »XFMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) ¼XFMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) ½XFMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) ¾XFMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) ¿XFMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) ÁXFMC_PATT_ATTHOLD_Pos (16U) ÂXFMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) ÃXFMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk ÄXFMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) ÅXFMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) ÆXFMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) ÇXFMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) ÈXFMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) ÉXFMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) ÊXFMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) ËXFMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) ÍXFMC_PATT_ATTHIZ_Pos (24U) ÎXFMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) ÏXFMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk ÐXFMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) ÑXFMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) ÒXFMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) ÓXFMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) ÔXFMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) ÕXFMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) ÖXFMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) ×XFMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) ÚXFMC_ECCR3_ECC3_Pos (0U) ÛXFMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) ÜXFMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk ßXFMC_SDCRx_NC_Pos (0U) àXFMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) áXFMC_SDCRx_NC FMC_SDCRx_NC_Msk âXFMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) ãXFMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) åXFMC_SDCRx_NR_Pos (2U) æXFMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) çXFMC_SDCRx_NR FMC_SDCRx_NR_Msk èXFMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) éXFMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) ëXFMC_SDCRx_MWID_Pos (4U) ìXFMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) íXFMC_SDCRx_MWID FMC_SDCRx_MWID_Msk îXFMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) ïXFMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) ñXFMC_SDCRx_NB_Pos (6U) òXFMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) óXFMC_SDCRx_NB FMC_SDCRx_NB_Msk õXFMC_SDCRx_CAS_Pos (7U) öXFMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) ÷XFMC_SDCRx_CAS FMC_SDCRx_CAS_Msk øXFMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) ùXFMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) ûXFMC_SDCRx_WP_Pos (9U) üXFMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) ýXFMC_SDCRx_WP FMC_SDCRx_WP_Msk ÿXFMC_SDCRx_SDCLK_Pos (10U) YFMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) YFMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk YFMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) YFMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
YFMC_SDCRx_RBURST_Pos (12U) YFMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) YFMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk YFMC_SDCRx_RPIPE_Pos (13U) YFMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) YFMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk YFMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) YFMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) YFMC_SDTRx_TMRD_Pos (0U) YFMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) YFMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk YFMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) YFMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) YFMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) YFMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) YFMC_SDTRx_TXSR_Pos (4U) YFMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) YFMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk YFMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) YFMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) YFMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) YFMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) YFMC_SDTRx_TRAS_Pos (8U) ¡YFMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) ¢YFMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk £YFMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) ¤YFMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) ¥YFMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) ¦YFMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) ¨YFMC_SDTRx_TRC_Pos (12U) ©YFMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) ªYFMC_SDTRx_TRC FMC_SDTRx_TRC_Msk «YFMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) ¬YFMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) YFMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) ¯YFMC_SDTRx_TWR_Pos (16U) °YFMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) ±YFMC_SDTRx_TWR FMC_SDTRx_TWR_Msk ²YFMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) ³YFMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) ´YFMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) ¶YFMC_SDTRx_TRP_Pos (20U) ·YFMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) ¸YFMC_SDTRx_TRP FMC_SDTRx_TRP_Msk ¹YFMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) ºYFMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) »YFMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) ½YFMC_SDTRx_TRCD_Pos (24U) ¾YFMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) ¿YFMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk ÀYFMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) ÁYFMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) ÂYFMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) ÅYFMC_SDCMR_MODE_Pos (0U) ÆYFMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) ÇYFMC_SDCMR_MODE FMC_SDCMR_MODE_Msk ÈYFMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) ÉYFMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) ÊYFMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) ÌYFMC_SDCMR_CTB2_Pos (3U) ÍYFMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) ÎYFMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk ÐYFMC_SDCMR_CTB1_Pos (4U) ÑYFMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) ÒYFMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk ÔYFMC_SDCMR_NRFS_Pos (5U) ÕYFMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) ÖYFMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk ×YFMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) ØYFMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) ÙYFMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) ÚYFMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) ÜYFMC_SDCMR_MRD_Pos (9U) ÝYFMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) ÞYFMC_SDCMR_MRD FMC_SDCMR_MRD_Msk áYFMC_SDRTR_CRE_Pos (0U) âYFMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) ãYFMC_SDRTR_CRE FMC_SDRTR_CRE_Msk åYFMC_SDRTR_COUNT_Pos (1U) æYFMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) çYFMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk éYFMC_SDRTR_REIE_Pos (14U) êYFMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) ëYFMC_SDRTR_REIE FMC_SDRTR_REIE_Msk îYFMC_SDSR_RE_Pos (0U) ïYFMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) ðYFMC_SDSR_RE FMC_SDSR_RE_Msk òYFMC_SDSR_MODES1_Pos (1U) óYFMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) ôYFMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk õYFMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) öYFMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) øYFMC_SDSR_MODES2_Pos (3U) ùYFMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) úYFMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk ûYFMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) üYFMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) ZGPIO_MODER_MODER0_Pos (0U)
ZGPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) ZGPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk ZGPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) ZGPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) ZGPIO_MODER_MODER1_Pos (2U) ZGPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) ZGPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk ZGPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) ZGPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) ZGPIO_MODER_MODER2_Pos (4U) ZGPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) ZGPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk ZGPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) ZGPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) ZGPIO_MODER_MODER3_Pos (6U) ZGPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) ZGPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk ZGPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) ZGPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) ZGPIO_MODER_MODER4_Pos (8U) ZGPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) ZGPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk ZGPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) ZGPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) ¢ZGPIO_MODER_MODER5_Pos (10U) £ZGPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) ¤ZGPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk ¥ZGPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) ¦ZGPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) ¨ZGPIO_MODER_MODER6_Pos (12U) ©ZGPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) ªZGPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk «ZGPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) ¬ZGPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) ®ZGPIO_MODER_MODER7_Pos (14U) ¯ZGPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) °ZGPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk ±ZGPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) ²ZGPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) ´ZGPIO_MODER_MODER8_Pos (16U) µZGPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) ¶ZGPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk ·ZGPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) ¸ZGPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) ºZGPIO_MODER_MODER9_Pos (18U) »ZGPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) ¼ZGPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk ½ZGPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) ¾ZGPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) ÀZGPIO_MODER_MODER10_Pos (20U) ÁZGPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) ÂZGPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk ÃZGPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) ÄZGPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) ÆZGPIO_MODER_MODER11_Pos (22U) ÇZGPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) ÈZGPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk ÉZGPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) ÊZGPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) ÌZGPIO_MODER_MODER12_Pos (24U) ÍZGPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) ÎZGPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk ÏZGPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) ÐZGPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) ÒZGPIO_MODER_MODER13_Pos (26U) ÓZGPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) ÔZGPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk ÕZGPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) ÖZGPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) ØZGPIO_MODER_MODER14_Pos (28U) ÙZGPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) ÚZGPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk ÛZGPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) ÜZGPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) ÞZGPIO_MODER_MODER15_Pos (30U) ßZGPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) àZGPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk áZGPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) âZGPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) åZGPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos æZGPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk çZGPIO_MODER_MODE0 GPIO_MODER_MODER0 èZGPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 éZGPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 ëZGPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos ìZGPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk íZGPIO_MODER_MODE1 GPIO_MODER_MODER1 îZGPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 ïZGPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 ñZGPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos òZGPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk óZGPIO_MODER_MODE2 GPIO_MODER_MODER2 ôZGPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 õZGPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 ÷ZGPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos øZGPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk ùZGPIO_MODER_MODE3 GPIO_MODER_MODER3 úZGPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 ûZGPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 ýZGPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos þZGPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk ÿZGPIO_MODER_MODE4 GPIO_MODER_MODER4 [GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 [GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 [GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos [GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
[GPIO_MODER_MODE5 GPIO_MODER_MODER5 [GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 [GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 [GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos [GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk [GPIO_MODER_MODE6 GPIO_MODER_MODER6 [GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 [GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 [GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos [GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk [GPIO_MODER_MODE7 GPIO_MODER_MODER7 [GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 [GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 [GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos [GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk [GPIO_MODER_MODE8 GPIO_MODER_MODER8 [GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 [GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 [GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos [GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk [GPIO_MODER_MODE9 GPIO_MODER_MODER9 [GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 [GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 ¡[GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po ¢[GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms £[GPIO_MODER_MODE10 GPIO_MODER_MODER10 ¤[GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 ¥[GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 §[GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po ¨[GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms ©[GPIO_MODER_MODE11 GPIO_MODER_MODER11 ª[GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 «[GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 [GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po ®[GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms ¯[GPIO_MODER_MODE12 GPIO_MODER_MODER12 °[GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 ±[GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 ³[GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po ´[GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms µ[GPIO_MODER_MODE13 GPIO_MODER_MODER13 ¶[GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 ·[GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 ¹[GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po º[GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms »[GPIO_MODER_MODE14 GPIO_MODER_MODER14 ¼[GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 ½[GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 ¿[GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po À[GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms Á[GPIO_MODER_MODE15 GPIO_MODER_MODER15 Â[GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 Ã[GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 Æ[GPIO_OTYPER_OT0_Pos (0U) Ç[GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) È[GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk É[GPIO_OTYPER_OT1_Pos (1U) Ê[GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) Ë[GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk Ì[GPIO_OTYPER_OT2_Pos (2U) Í[GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) Î[GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk Ï[GPIO_OTYPER_OT3_Pos (3U) Ð[GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) Ñ[GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk Ò[GPIO_OTYPER_OT4_Pos (4U) Ó[GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) Ô[GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk Õ[GPIO_OTYPER_OT5_Pos (5U) Ö[GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) ×[GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk Ø[GPIO_OTYPER_OT6_Pos (6U) Ù[GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) Ú[GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk Û[GPIO_OTYPER_OT7_Pos (7U) Ü[GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) Ý[GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk Þ[GPIO_OTYPER_OT8_Pos (8U) ß[GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) à[GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk á[GPIO_OTYPER_OT9_Pos (9U) â[GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) ã[GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk ä[GPIO_OTYPER_OT10_Pos (10U) å[GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) æ[GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk ç[GPIO_OTYPER_OT11_Pos (11U) è[GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) é[GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk ê[GPIO_OTYPER_OT12_Pos (12U) ë[GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) ì[GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk í[GPIO_OTYPER_OT13_Pos (13U) î[GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) ï[GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk ð[GPIO_OTYPER_OT14_Pos (14U) ñ[GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) ò[GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk ó[GPIO_OTYPER_OT15_Pos (15U) ô[GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) õ[GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk ø[GPIO_OSPEEDR_OSPEED0_Pos (0U) ù[GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) ú[GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk û[GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) ü[GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) þ[GPIO_OSPEEDR_OSPEED1_Pos (2U) ÿ[GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) \GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk \GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) \GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) \GPIO_OSPEEDR_OSPEED2_Pos (4U)
\GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) \GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk \GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) \GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) \GPIO_OSPEEDR_OSPEED3_Pos (6U) \GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) \GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk \GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) \GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) \GPIO_OSPEEDR_OSPEED4_Pos (8U) \GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) \GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk \GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) \GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) \GPIO_OSPEEDR_OSPEED5_Pos (10U) \GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) \GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk \GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) \GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) \GPIO_OSPEEDR_OSPEED6_Pos (12U) \GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) \GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk \GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) \GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) ¢\GPIO_OSPEEDR_OSPEED7_Pos (14U) £\GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) ¤\GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk ¥\GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) ¦\GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) ¨\GPIO_OSPEEDR_OSPEED8_Pos (16U) ©\GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) ª\GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk «\GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) ¬\GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) ®\GPIO_OSPEEDR_OSPEED9_Pos (18U) ¯\GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) °\GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk ±\GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) ²\GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) ´\GPIO_OSPEEDR_OSPEED10_Pos (20U) µ\GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) ¶\GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk ·\GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) ¸\GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) º\GPIO_OSPEEDR_OSPEED11_Pos (22U) »\GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) ¼\GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk ½\GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) ¾\GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) À\GPIO_OSPEEDR_OSPEED12_Pos (24U) Á\GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) Â\GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk Ã\GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) Ä\GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) Æ\GPIO_OSPEEDR_OSPEED13_Pos (26U) Ç\GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) È\GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk É\GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) Ê\GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) Ì\GPIO_OSPEEDR_OSPEED14_Pos (28U) Í\GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) Î\GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk Ï\GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) Ð\GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) Ò\GPIO_OSPEEDR_OSPEED15_Pos (30U) Ó\GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) Ô\GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk Õ\GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) Ö\GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) Ù\GPIO_PUPDR_PUPD0_Pos (0U) Ú\GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) Û\GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk Ü\GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) Ý\GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) ß\GPIO_PUPDR_PUPD1_Pos (2U) à\GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) á\GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk â\GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) ã\GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) å\GPIO_PUPDR_PUPD2_Pos (4U) æ\GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) ç\GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk è\GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) é\GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) ë\GPIO_PUPDR_PUPD3_Pos (6U) ì\GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) í\GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk î\GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) ï\GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) ñ\GPIO_PUPDR_PUPD4_Pos (8U) ò\GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) ó\GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk ô\GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) õ\GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) ÷\GPIO_PUPDR_PUPD5_Pos (10U) ø\GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) ù\GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk ú\GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) û\GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) ý\GPIO_PUPDR_PUPD6_Pos (12U) þ\GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) ÿ\GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk ]GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) ]GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) ]GPIO_PUPDR_PUPD7_Pos (14U) ]GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
]GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk ]GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) ]GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) ]GPIO_PUPDR_PUPD8_Pos (16U) ]GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) ]GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk ]GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) ]GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) ]GPIO_PUPDR_PUPD9_Pos (18U) ]GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) ]GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk ]GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) ]GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) ]GPIO_PUPDR_PUPD10_Pos (20U) ]GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) ]GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk ]GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) ]GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) ]GPIO_PUPDR_PUPD11_Pos (22U) ]GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) ]GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk ]GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) ]GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) ¡]GPIO_PUPDR_PUPD12_Pos (24U) ¢]GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) £]GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk ¤]GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) ¥]GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) §]GPIO_PUPDR_PUPD13_Pos (26U) ¨]GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) ©]GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk ª]GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) «]GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) ]GPIO_PUPDR_PUPD14_Pos (28U) ®]GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) ¯]GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk °]GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) ±]GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) ³]GPIO_PUPDR_PUPD15_Pos (30U) ´]GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) µ]GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk ¶]GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) ·]GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) º]GPIO_IDR_ID0_Pos (0U) »]GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) ¼]GPIO_IDR_ID0 GPIO_IDR_ID0_Msk ½]GPIO_IDR_ID1_Pos (1U) ¾]GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) ¿]GPIO_IDR_ID1 GPIO_IDR_ID1_Msk À]GPIO_IDR_ID2_Pos (2U) Á]GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) Â]GPIO_IDR_ID2 GPIO_IDR_ID2_Msk Ã]GPIO_IDR_ID3_Pos (3U) Ä]GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) Å]GPIO_IDR_ID3 GPIO_IDR_ID3_Msk Æ]GPIO_IDR_ID4_Pos (4U) Ç]GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) È]GPIO_IDR_ID4 GPIO_IDR_ID4_Msk É]GPIO_IDR_ID5_Pos (5U) Ê]GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) Ë]GPIO_IDR_ID5 GPIO_IDR_ID5_Msk Ì]GPIO_IDR_ID6_Pos (6U) Í]GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) Î]GPIO_IDR_ID6 GPIO_IDR_ID6_Msk Ï]GPIO_IDR_ID7_Pos (7U) Ð]GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) Ñ]GPIO_IDR_ID7 GPIO_IDR_ID7_Msk Ò]GPIO_IDR_ID8_Pos (8U) Ó]GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) Ô]GPIO_IDR_ID8 GPIO_IDR_ID8_Msk Õ]GPIO_IDR_ID9_Pos (9U) Ö]GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) ×]GPIO_IDR_ID9 GPIO_IDR_ID9_Msk Ø]GPIO_IDR_ID10_Pos (10U) Ù]GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) Ú]GPIO_IDR_ID10 GPIO_IDR_ID10_Msk Û]GPIO_IDR_ID11_Pos (11U) Ü]GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) Ý]GPIO_IDR_ID11 GPIO_IDR_ID11_Msk Þ]GPIO_IDR_ID12_Pos (12U) ß]GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) à]GPIO_IDR_ID12 GPIO_IDR_ID12_Msk á]GPIO_IDR_ID13_Pos (13U) â]GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) ã]GPIO_IDR_ID13 GPIO_IDR_ID13_Msk ä]GPIO_IDR_ID14_Pos (14U) å]GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) æ]GPIO_IDR_ID14 GPIO_IDR_ID14_Msk ç]GPIO_IDR_ID15_Pos (15U) è]GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) é]GPIO_IDR_ID15 GPIO_IDR_ID15_Msk ì]GPIO_ODR_OD0_Pos (0U) í]GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) î]GPIO_ODR_OD0 GPIO_ODR_OD0_Msk ï]GPIO_ODR_OD1_Pos (1U) ð]GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) ñ]GPIO_ODR_OD1 GPIO_ODR_OD1_Msk ò]GPIO_ODR_OD2_Pos (2U) ó]GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) ô]GPIO_ODR_OD2 GPIO_ODR_OD2_Msk õ]GPIO_ODR_OD3_Pos (3U) ö]GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) ÷]GPIO_ODR_OD3 GPIO_ODR_OD3_Msk ø]GPIO_ODR_OD4_Pos (4U) ù]GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) ú]GPIO_ODR_OD4 GPIO_ODR_OD4_Msk û]GPIO_ODR_OD5_Pos (5U) ü]GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) ý]GPIO_ODR_OD5 GPIO_ODR_OD5_Msk þ]GPIO_ODR_OD6_Pos (6U) ÿ]GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) ^GPIO_ODR_OD6 GPIO_ODR_OD6_Msk ^GPIO_ODR_OD7_Pos (7U) ^GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) ^GPIO_ODR_OD7 GPIO_ODR_OD7_Msk ^GPIO_ODR_OD8_Pos (8U)
^GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) ^GPIO_ODR_OD8 GPIO_ODR_OD8_Msk ^GPIO_ODR_OD9_Pos (9U) ^GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) ^GPIO_ODR_OD9 GPIO_ODR_OD9_Msk ^GPIO_ODR_OD10_Pos (10U) ^GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) ^GPIO_ODR_OD10 GPIO_ODR_OD10_Msk ^GPIO_ODR_OD11_Pos (11U) ^GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) ^GPIO_ODR_OD11 GPIO_ODR_OD11_Msk ^GPIO_ODR_OD12_Pos (12U) ^GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) ^GPIO_ODR_OD12 GPIO_ODR_OD12_Msk ^GPIO_ODR_OD13_Pos (13U) ^GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) ^GPIO_ODR_OD13 GPIO_ODR_OD13_Msk ^GPIO_ODR_OD14_Pos (14U) ^GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) ^GPIO_ODR_OD14 GPIO_ODR_OD14_Msk ^GPIO_ODR_OD15_Pos (15U) ^GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) ^GPIO_ODR_OD15 GPIO_ODR_OD15_Msk ^GPIO_BSRR_BS0_Pos (0U) ^GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) ^GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk ¡^GPIO_BSRR_BS1_Pos (1U) ¢^GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) £^GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk ¤^GPIO_BSRR_BS2_Pos (2U) ¥^GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) ¦^GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk §^GPIO_BSRR_BS3_Pos (3U) ¨^GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) ©^GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk ª^GPIO_BSRR_BS4_Pos (4U) «^GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) ¬^GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk ^GPIO_BSRR_BS5_Pos (5U) ®^GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) ¯^GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk °^GPIO_BSRR_BS6_Pos (6U) ±^GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) ²^GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk ³^GPIO_BSRR_BS7_Pos (7U) ´^GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) µ^GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk ¶^GPIO_BSRR_BS8_Pos (8U) ·^GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) ¸^GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk ¹^GPIO_BSRR_BS9_Pos (9U) º^GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) »^GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk ¼^GPIO_BSRR_BS10_Pos (10U) ½^GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) ¾^GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk ¿^GPIO_BSRR_BS11_Pos (11U) À^GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) Á^GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk Â^GPIO_BSRR_BS12_Pos (12U) Ã^GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) Ä^GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk Å^GPIO_BSRR_BS13_Pos (13U) Æ^GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) Ç^GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk È^GPIO_BSRR_BS14_Pos (14U) É^GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) Ê^GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk Ë^GPIO_BSRR_BS15_Pos (15U) Ì^GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) Í^GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk Î^GPIO_BSRR_BR0_Pos (16U) Ï^GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) Ð^GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk Ñ^GPIO_BSRR_BR1_Pos (17U) Ò^GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) Ó^GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk Ô^GPIO_BSRR_BR2_Pos (18U) Õ^GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) Ö^GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk ×^GPIO_BSRR_BR3_Pos (19U) Ø^GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) Ù^GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk Ú^GPIO_BSRR_BR4_Pos (20U) Û^GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) Ü^GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk Ý^GPIO_BSRR_BR5_Pos (21U) Þ^GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) ß^GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk à^GPIO_BSRR_BR6_Pos (22U) á^GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) â^GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk ã^GPIO_BSRR_BR7_Pos (23U) ä^GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) å^GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk æ^GPIO_BSRR_BR8_Pos (24U) ç^GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) è^GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk é^GPIO_BSRR_BR9_Pos (25U) ê^GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) ë^GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk ì^GPIO_BSRR_BR10_Pos (26U) í^GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) î^GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk ï^GPIO_BSRR_BR11_Pos (27U) ð^GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) ñ^GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk ò^GPIO_BSRR_BR12_Pos (28U) ó^GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) ô^GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk õ^GPIO_BSRR_BR13_Pos (29U) ö^GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) ÷^GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk ø^GPIO_BSRR_BR14_Pos (30U) ù^GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) ú^GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk û^GPIO_BSRR_BR15_Pos (31U) ü^GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) ý^GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk _GPIO_LCKR_LCK0_Pos (0U) _GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) _GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk _GPIO_LCKR_LCK1_Pos (1U) _GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
_GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk _GPIO_LCKR_LCK2_Pos (2U) _GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) _GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk _GPIO_LCKR_LCK3_Pos (3U) _GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) _GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk _GPIO_LCKR_LCK4_Pos (4U) _GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) _GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk _GPIO_LCKR_LCK5_Pos (5U) _GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) _GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk _GPIO_LCKR_LCK6_Pos (6U) _GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) _GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk _GPIO_LCKR_LCK7_Pos (7U) _GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) _GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk _GPIO_LCKR_LCK8_Pos (8U) _GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) _GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk _GPIO_LCKR_LCK9_Pos (9U) _GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) _GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk _GPIO_LCKR_LCK10_Pos (10U) _GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) _GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk ¡_GPIO_LCKR_LCK11_Pos (11U) ¢_GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) £_GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk ¤_GPIO_LCKR_LCK12_Pos (12U) ¥_GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) ¦_GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk §_GPIO_LCKR_LCK13_Pos (13U) ¨_GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) ©_GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk ª_GPIO_LCKR_LCK14_Pos (14U) «_GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) ¬_GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk _GPIO_LCKR_LCK15_Pos (15U) ®_GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) ¯_GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk °_GPIO_LCKR_LCKK_Pos (16U) ±_GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) ²_GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk µ_GPIO_AFRL_AFSEL0_Pos (0U) ¶_GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) ·_GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk ¸_GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) ¹_GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) º_GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) »_GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) ¼_GPIO_AFRL_AFSEL1_Pos (4U) ½_GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) ¾_GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk ¿_GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) À_GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) Á_GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) Â_GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) Ã_GPIO_AFRL_AFSEL2_Pos (8U) Ä_GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) Å_GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk Æ_GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) Ç_GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) È_GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) É_GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) Ê_GPIO_AFRL_AFSEL3_Pos (12U) Ë_GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) Ì_GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk Í_GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) Î_GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) Ï_GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) Ð_GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) Ñ_GPIO_AFRL_AFSEL4_Pos (16U) Ò_GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) Ó_GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk Ô_GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) Õ_GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) Ö_GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) ×_GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) Ø_GPIO_AFRL_AFSEL5_Pos (20U) Ù_GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) Ú_GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk Û_GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) Ü_GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) Ý_GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) Þ_GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) ß_GPIO_AFRL_AFSEL6_Pos (24U) à_GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) á_GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk â_GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) ã_GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) ä_GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) å_GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) æ_GPIO_AFRL_AFSEL7_Pos (28U) ç_GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) è_GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk é_GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) ê_GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) ë_GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) ì_GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) ï_GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 ð_GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 ñ_GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 ò_GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 ó_GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 ô_GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 õ_GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 ö_GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 ù_GPIO_AFRH_AFSEL8_Pos (0U) ú_GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) û_GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk ü_GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) ý_GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) þ_GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) ÿ_GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) `GPIO_AFRH_AFSEL9_Pos (4U) `GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) `GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk `GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) `GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
`GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) `GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) `GPIO_AFRH_AFSEL10_Pos (8U) `GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) `GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk `GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) `GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) `GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) `GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) `GPIO_AFRH_AFSEL11_Pos (12U) `GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) `GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk `GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) `GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) `GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) `GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) `GPIO_AFRH_AFSEL12_Pos (16U) `GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) `GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk `GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) `GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) `GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) `GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) `GPIO_AFRH_AFSEL13_Pos (20U) `GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) `GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk `GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) `GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) ¡`GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) ¢`GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) £`GPIO_AFRH_AFSEL14_Pos (24U) ¤`GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) ¥`GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk ¦`GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) §`GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) ¨`GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) ©`GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) ª`GPIO_AFRH_AFSEL15_Pos (28U) «`GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) ¬`GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk `GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) ®`GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) ¯`GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) °`GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) ³`GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 ´`GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 µ`GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 ¶`GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 ·`GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 ¸`GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 ¹`GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 º`GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 Â`HSEM_R_PROCID_Pos (0U) Ã`HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) Ä`HSEM_R_PROCID HSEM_R_PROCID_Msk Å`HSEM_R_COREID_Pos (8U) Æ`HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) Ç`HSEM_R_COREID HSEM_R_COREID_Msk È`HSEM_R_LOCK_Pos (31U) É`HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) Ê`HSEM_R_LOCK HSEM_R_LOCK_Msk Í`HSEM_RLR_PROCID_Pos (0U) Î`HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) Ï`HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk Ð`HSEM_RLR_COREID_Pos (8U) Ñ`HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) Ò`HSEM_RLR_COREID HSEM_RLR_COREID_Msk Ó`HSEM_RLR_LOCK_Pos (31U) Ô`HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) Õ`HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk Ø`HSEM_C1IER_ISE0_Pos (0U) Ù`HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) Ú`HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk Û`HSEM_C1IER_ISE1_Pos (1U) Ü`HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) Ý`HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk Þ`HSEM_C1IER_ISE2_Pos (2U) ß`HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) à`HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk á`HSEM_C1IER_ISE3_Pos (3U) â`HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) ã`HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk ä`HSEM_C1IER_ISE4_Pos (4U) å`HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) æ`HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk ç`HSEM_C1IER_ISE5_Pos (5U) è`HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) é`HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk ê`HSEM_C1IER_ISE6_Pos (6U) ë`HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) ì`HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk í`HSEM_C1IER_ISE7_Pos (7U) î`HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) ï`HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk ð`HSEM_C1IER_ISE8_Pos (8U) ñ`HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) ò`HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk ó`HSEM_C1IER_ISE9_Pos (9U) ô`HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) õ`HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk ö`HSEM_C1IER_ISE10_Pos (10U) ÷`HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) ø`HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk ù`HSEM_C1IER_ISE11_Pos (11U) ú`HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) û`HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk ü`HSEM_C1IER_ISE12_Pos (12U) ý`HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) þ`HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk ÿ`HSEM_C1IER_ISE13_Pos (13U) aHSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) aHSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk aHSEM_C1IER_ISE14_Pos (14U) aHSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) aHSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
aHSEM_C1IER_ISE15_Pos (15U) aHSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) aHSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk aHSEM_C1IER_ISE16_Pos (16U) aHSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) aHSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk aHSEM_C1IER_ISE17_Pos (17U) aHSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) aHSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk aHSEM_C1IER_ISE18_Pos (18U) aHSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) aHSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk aHSEM_C1IER_ISE19_Pos (19U) aHSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) aHSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk aHSEM_C1IER_ISE20_Pos (20U) aHSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) aHSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk aHSEM_C1IER_ISE21_Pos (21U) aHSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) aHSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk aHSEM_C1IER_ISE22_Pos (22U) aHSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) aHSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk aHSEM_C1IER_ISE23_Pos (23U) aHSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) aHSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk aHSEM_C1IER_ISE24_Pos (24U) ¡aHSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) ¢aHSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk £aHSEM_C1IER_ISE25_Pos (25U) ¤aHSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) ¥aHSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk ¦aHSEM_C1IER_ISE26_Pos (26U) §aHSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) ¨aHSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk ©aHSEM_C1IER_ISE27_Pos (27U) ªaHSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) «aHSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk ¬aHSEM_C1IER_ISE28_Pos (28U) aHSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) ®aHSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk ¯aHSEM_C1IER_ISE29_Pos (29U) °aHSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) ±aHSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk ²aHSEM_C1IER_ISE30_Pos (30U) ³aHSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) ´aHSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk µaHSEM_C1IER_ISE31_Pos (31U) ¶aHSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) ·aHSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk ºaHSEM_C1ICR_ISC0_Pos (0U) »aHSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) ¼aHSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk ½aHSEM_C1ICR_ISC1_Pos (1U) ¾aHSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) ¿aHSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk ÀaHSEM_C1ICR_ISC2_Pos (2U) ÁaHSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) ÂaHSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk ÃaHSEM_C1ICR_ISC3_Pos (3U) ÄaHSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) ÅaHSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk ÆaHSEM_C1ICR_ISC4_Pos (4U) ÇaHSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) ÈaHSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk ÉaHSEM_C1ICR_ISC5_Pos (5U) ÊaHSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) ËaHSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk ÌaHSEM_C1ICR_ISC6_Pos (6U) ÍaHSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) ÎaHSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk ÏaHSEM_C1ICR_ISC7_Pos (7U) ÐaHSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) ÑaHSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk ÒaHSEM_C1ICR_ISC8_Pos (8U) ÓaHSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) ÔaHSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk ÕaHSEM_C1ICR_ISC9_Pos (9U) ÖaHSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) ×aHSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk ØaHSEM_C1ICR_ISC10_Pos (10U) ÙaHSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) ÚaHSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk ÛaHSEM_C1ICR_ISC11_Pos (11U) ÜaHSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) ÝaHSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk ÞaHSEM_C1ICR_ISC12_Pos (12U) ßaHSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) àaHSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk áaHSEM_C1ICR_ISC13_Pos (13U) âaHSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) ãaHSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk äaHSEM_C1ICR_ISC14_Pos (14U) åaHSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) æaHSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk çaHSEM_C1ICR_ISC15_Pos (15U) èaHSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) éaHSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk êaHSEM_C1ICR_ISC16_Pos (16U) ëaHSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) ìaHSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk íaHSEM_C1ICR_ISC17_Pos (17U) îaHSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) ïaHSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk ðaHSEM_C1ICR_ISC18_Pos (18U) ñaHSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) òaHSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk óaHSEM_C1ICR_ISC19_Pos (19U) ôaHSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) õaHSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk öaHSEM_C1ICR_ISC20_Pos (20U) ÷aHSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) øaHSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk ùaHSEM_C1ICR_ISC21_Pos (21U) úaHSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) ûaHSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk üaHSEM_C1ICR_ISC22_Pos (22U) ýaHSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) þaHSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk ÿaHSEM_C1ICR_ISC23_Pos (23U) bHSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) bHSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk bHSEM_C1ICR_ISC24_Pos (24U) bHSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) bHSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
bHSEM_C1ICR_ISC25_Pos (25U) bHSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) bHSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk bHSEM_C1ICR_ISC26_Pos (26U) bHSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) bHSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk bHSEM_C1ICR_ISC27_Pos (27U) bHSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) bHSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk bHSEM_C1ICR_ISC28_Pos (28U) bHSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) bHSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk bHSEM_C1ICR_ISC29_Pos (29U) bHSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) bHSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk bHSEM_C1ICR_ISC30_Pos (30U) bHSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) bHSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk bHSEM_C1ICR_ISC31_Pos (31U) bHSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) bHSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk bHSEM_C1ISR_ISF0_Pos (0U) bHSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) bHSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk bHSEM_C1ISR_ISF1_Pos (1U) bHSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) ¡bHSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk ¢bHSEM_C1ISR_ISF2_Pos (2U) £bHSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) ¤bHSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk ¥bHSEM_C1ISR_ISF3_Pos (3U) ¦bHSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) §bHSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk ¨bHSEM_C1ISR_ISF4_Pos (4U) ©bHSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) ªbHSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk «bHSEM_C1ISR_ISF5_Pos (5U) ¬bHSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) bHSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk ®bHSEM_C1ISR_ISF6_Pos (6U) ¯bHSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) °bHSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk ±bHSEM_C1ISR_ISF7_Pos (7U) ²bHSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) ³bHSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk ´bHSEM_C1ISR_ISF8_Pos (8U) µbHSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) ¶bHSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk ·bHSEM_C1ISR_ISF9_Pos (9U) ¸bHSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) ¹bHSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk ºbHSEM_C1ISR_ISF10_Pos (10U) »bHSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) ¼bHSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk ½bHSEM_C1ISR_ISF11_Pos (11U) ¾bHSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) ¿bHSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk ÀbHSEM_C1ISR_ISF12_Pos (12U) ÁbHSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) ÂbHSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk ÃbHSEM_C1ISR_ISF13_Pos (13U) ÄbHSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) ÅbHSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk ÆbHSEM_C1ISR_ISF14_Pos (14U) ÇbHSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) ÈbHSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk ÉbHSEM_C1ISR_ISF15_Pos (15U) ÊbHSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) ËbHSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk ÌbHSEM_C1ISR_ISF16_Pos (16U) ÍbHSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) ÎbHSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk ÏbHSEM_C1ISR_ISF17_Pos (17U) ÐbHSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) ÑbHSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk ÒbHSEM_C1ISR_ISF18_Pos (18U) ÓbHSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) ÔbHSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk ÕbHSEM_C1ISR_ISF19_Pos (19U) ÖbHSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) ×bHSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk ØbHSEM_C1ISR_ISF20_Pos (20U) ÙbHSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) ÚbHSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk ÛbHSEM_C1ISR_ISF21_Pos (21U) ÜbHSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) ÝbHSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk ÞbHSEM_C1ISR_ISF22_Pos (22U) ßbHSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) àbHSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk ábHSEM_C1ISR_ISF23_Pos (23U) âbHSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) ãbHSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk äbHSEM_C1ISR_ISF24_Pos (24U) åbHSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) æbHSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk çbHSEM_C1ISR_ISF25_Pos (25U) èbHSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) ébHSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk êbHSEM_C1ISR_ISF26_Pos (26U) ëbHSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) ìbHSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk íbHSEM_C1ISR_ISF27_Pos (27U) îbHSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) ïbHSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk ðbHSEM_C1ISR_ISF28_Pos (28U) ñbHSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) òbHSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk óbHSEM_C1ISR_ISF29_Pos (29U) ôbHSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) õbHSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk öbHSEM_C1ISR_ISF30_Pos (30U) ÷bHSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) øbHSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk ùbHSEM_C1ISR_ISF31_Pos (31U) úbHSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) ûbHSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk þbHSEM_C1MISR_MISF0_Pos (0U) ÿbHSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) cHSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk cHSEM_C1MISR_MISF1_Pos (1U) cHSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) cHSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk cHSEM_C1MISR_MISF2_Pos (2U)
cHSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) cHSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk cHSEM_C1MISR_MISF3_Pos (3U) cHSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) cHSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk cHSEM_C1MISR_MISF4_Pos (4U) cHSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) cHSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk cHSEM_C1MISR_MISF5_Pos (5U) cHSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) cHSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk cHSEM_C1MISR_MISF6_Pos (6U) cHSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) cHSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk cHSEM_C1MISR_MISF7_Pos (7U) cHSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) cHSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk cHSEM_C1MISR_MISF8_Pos (8U) cHSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) cHSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk cHSEM_C1MISR_MISF9_Pos (9U) cHSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) cHSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk cHSEM_C1MISR_MISF10_Pos (10U) cHSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) cHSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk cHSEM_C1MISR_MISF11_Pos (11U) cHSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) ¡cHSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk ¢cHSEM_C1MISR_MISF12_Pos (12U) £cHSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) ¤cHSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk ¥cHSEM_C1MISR_MISF13_Pos (13U) ¦cHSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) §cHSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk ¨cHSEM_C1MISR_MISF14_Pos (14U) ©cHSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) ªcHSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk «cHSEM_C1MISR_MISF15_Pos (15U) ¬cHSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) cHSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk ®cHSEM_C1MISR_MISF16_Pos (16U) ¯cHSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) °cHSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk ±cHSEM_C1MISR_MISF17_Pos (17U) ²cHSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) ³cHSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk ´cHSEM_C1MISR_MISF18_Pos (18U) µcHSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) ¶cHSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk ·cHSEM_C1MISR_MISF19_Pos (19U) ¸cHSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) ¹cHSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk ºcHSEM_C1MISR_MISF20_Pos (20U) »cHSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) ¼cHSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk ½cHSEM_C1MISR_MISF21_Pos (21U) ¾cHSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) ¿cHSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk ÀcHSEM_C1MISR_MISF22_Pos (22U) ÁcHSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) ÂcHSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk ÃcHSEM_C1MISR_MISF23_Pos (23U) ÄcHSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) ÅcHSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk ÆcHSEM_C1MISR_MISF24_Pos (24U) ÇcHSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) ÈcHSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk ÉcHSEM_C1MISR_MISF25_Pos (25U) ÊcHSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) ËcHSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk ÌcHSEM_C1MISR_MISF26_Pos (26U) ÍcHSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) ÎcHSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk ÏcHSEM_C1MISR_MISF27_Pos (27U) ÐcHSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) ÑcHSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk ÒcHSEM_C1MISR_MISF28_Pos (28U) ÓcHSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) ÔcHSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk ÕcHSEM_C1MISR_MISF29_Pos (29U) ÖcHSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) ×cHSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk ØcHSEM_C1MISR_MISF30_Pos (30U) ÙcHSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) ÚcHSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk ÛcHSEM_C1MISR_MISF31_Pos (31U) ÜcHSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) ÝcHSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk àcHSEM_CR_COREID_Pos (8U) ácHSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) âcHSEM_CR_COREID HSEM_CR_COREID_Msk ãcHSEM_CR_KEY_Pos (16U) äcHSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) åcHSEM_CR_KEY HSEM_CR_KEY_Msk ècHSEM_KEYR_KEY_Pos (16U) écHSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) êcHSEM_KEYR_KEY HSEM_KEYR_KEY_Msk òcI2C_CR1_PE_Pos (0U) ócI2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) ôcI2C_CR1_PE I2C_CR1_PE_Msk õcI2C_CR1_TXIE_Pos (1U) öcI2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) ÷cI2C_CR1_TXIE I2C_CR1_TXIE_Msk øcI2C_CR1_RXIE_Pos (2U) ùcI2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) úcI2C_CR1_RXIE I2C_CR1_RXIE_Msk ûcI2C_CR1_ADDRIE_Pos (3U) ücI2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) ýcI2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk þcI2C_CR1_NACKIE_Pos (4U) ÿcI2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) dI2C_CR1_NACKIE I2C_CR1_NACKIE_Msk dI2C_CR1_STOPIE_Pos (5U) dI2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) dI2C_CR1_STOPIE I2C_CR1_STOPIE_Msk dI2C_CR1_TCIE_Pos (6U)
dI2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) dI2C_CR1_TCIE I2C_CR1_TCIE_Msk dI2C_CR1_ERRIE_Pos (7U) dI2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) dI2C_CR1_ERRIE I2C_CR1_ERRIE_Msk dI2C_CR1_DNF_Pos (8U) dI2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) dI2C_CR1_DNF I2C_CR1_DNF_Msk dI2C_CR1_ANFOFF_Pos (12U) dI2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) dI2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk dI2C_CR1_TXDMAEN_Pos (14U) dI2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) dI2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk dI2C_CR1_RXDMAEN_Pos (15U) dI2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) dI2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk dI2C_CR1_SBC_Pos (16U) dI2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) dI2C_CR1_SBC I2C_CR1_SBC_Msk dI2C_CR1_NOSTRETCH_Pos (17U) dI2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) dI2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk dI2C_CR1_WUPEN_Pos (18U) dI2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) dI2C_CR1_WUPEN I2C_CR1_WUPEN_Msk dI2C_CR1_GCEN_Pos (19U) dI2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) ¡dI2C_CR1_GCEN I2C_CR1_GCEN_Msk ¢dI2C_CR1_SMBHEN_Pos (20U) £dI2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) ¤dI2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk ¥dI2C_CR1_SMBDEN_Pos (21U) ¦dI2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) §dI2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk ¨dI2C_CR1_ALERTEN_Pos (22U) ©dI2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) ªdI2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk «dI2C_CR1_PECEN_Pos (23U) ¬dI2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) dI2C_CR1_PECEN I2C_CR1_PECEN_Msk °dI2C_CR2_SADD_Pos (0U) ±dI2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) ²dI2C_CR2_SADD I2C_CR2_SADD_Msk ³dI2C_CR2_RD_WRN_Pos (10U) ´dI2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) µdI2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk ¶dI2C_CR2_ADD10_Pos (11U) ·dI2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) ¸dI2C_CR2_ADD10 I2C_CR2_ADD10_Msk ¹dI2C_CR2_HEAD10R_Pos (12U) ºdI2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) »dI2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk ¼dI2C_CR2_START_Pos (13U) ½dI2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) ¾dI2C_CR2_START I2C_CR2_START_Msk ¿dI2C_CR2_STOP_Pos (14U) ÀdI2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) ÁdI2C_CR2_STOP I2C_CR2_STOP_Msk ÂdI2C_CR2_NACK_Pos (15U) ÃdI2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) ÄdI2C_CR2_NACK I2C_CR2_NACK_Msk ÅdI2C_CR2_NBYTES_Pos (16U) ÆdI2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) ÇdI2C_CR2_NBYTES I2C_CR2_NBYTES_Msk ÈdI2C_CR2_RELOAD_Pos (24U) ÉdI2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) ÊdI2C_CR2_RELOAD I2C_CR2_RELOAD_Msk ËdI2C_CR2_AUTOEND_Pos (25U) ÌdI2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) ÍdI2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk ÎdI2C_CR2_PECBYTE_Pos (26U) ÏdI2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) ÐdI2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk ÓdI2C_OAR1_OA1_Pos (0U) ÔdI2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) ÕdI2C_OAR1_OA1 I2C_OAR1_OA1_Msk ÖdI2C_OAR1_OA1MODE_Pos (10U) ×dI2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) ØdI2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk ÙdI2C_OAR1_OA1EN_Pos (15U) ÚdI2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) ÛdI2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk ÞdI2C_OAR2_OA2_Pos (1U) ßdI2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) àdI2C_OAR2_OA2 I2C_OAR2_OA2_Msk ádI2C_OAR2_OA2MSK_Pos (8U) âdI2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) ãdI2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk ädI2C_OAR2_OA2NOMASK 0x00000000UL ådI2C_OAR2_OA2MASK01_Pos (8U) ædI2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) çdI2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk èdI2C_OAR2_OA2MASK02_Pos (9U) édI2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) êdI2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk ëdI2C_OAR2_OA2MASK03_Pos (8U) ìdI2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) ídI2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk îdI2C_OAR2_OA2MASK04_Pos (10U) ïdI2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) ðdI2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk ñdI2C_OAR2_OA2MASK05_Pos (8U) òdI2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) ódI2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk ôdI2C_OAR2_OA2MASK06_Pos (9U) õdI2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) ödI2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk ÷dI2C_OAR2_OA2MASK07_Pos (8U) ødI2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) ùdI2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk údI2C_OAR2_OA2EN_Pos (15U) ûdI2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) üdI2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk ÿdI2C_TIMINGR_SCLL_Pos (0U) eI2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) eI2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk eI2C_TIMINGR_SCLH_Pos (8U) eI2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) eI2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
eI2C_TIMINGR_SDADEL_Pos (16U) eI2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) eI2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk eI2C_TIMINGR_SCLDEL_Pos (20U) eI2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) eI2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk eI2C_TIMINGR_PRESC_Pos (28U) eI2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) eI2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk eI2C_TIMEOUTR_TIMEOUTA_Pos (0U) eI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) eI2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk eI2C_TIMEOUTR_TIDLE_Pos (12U) eI2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) eI2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk eI2C_TIMEOUTR_TIMOUTEN_Pos (15U) eI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) eI2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk eI2C_TIMEOUTR_TIMEOUTB_Pos (16U) eI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) eI2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk eI2C_TIMEOUTR_TEXTEN_Pos (31U) eI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) eI2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk ¡eI2C_ISR_TXE_Pos (0U) ¢eI2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) £eI2C_ISR_TXE I2C_ISR_TXE_Msk ¤eI2C_ISR_TXIS_Pos (1U) ¥eI2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) ¦eI2C_ISR_TXIS I2C_ISR_TXIS_Msk §eI2C_ISR_RXNE_Pos (2U) ¨eI2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) ©eI2C_ISR_RXNE I2C_ISR_RXNE_Msk ªeI2C_ISR_ADDR_Pos (3U) «eI2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) ¬eI2C_ISR_ADDR I2C_ISR_ADDR_Msk eI2C_ISR_NACKF_Pos (4U) ®eI2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) ¯eI2C_ISR_NACKF I2C_ISR_NACKF_Msk °eI2C_ISR_STOPF_Pos (5U) ±eI2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) ²eI2C_ISR_STOPF I2C_ISR_STOPF_Msk ³eI2C_ISR_TC_Pos (6U) ´eI2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) µeI2C_ISR_TC I2C_ISR_TC_Msk ¶eI2C_ISR_TCR_Pos (7U) ·eI2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) ¸eI2C_ISR_TCR I2C_ISR_TCR_Msk ¹eI2C_ISR_BERR_Pos (8U) ºeI2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) »eI2C_ISR_BERR I2C_ISR_BERR_Msk ¼eI2C_ISR_ARLO_Pos (9U) ½eI2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) ¾eI2C_ISR_ARLO I2C_ISR_ARLO_Msk ¿eI2C_ISR_OVR_Pos (10U) ÀeI2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) ÁeI2C_ISR_OVR I2C_ISR_OVR_Msk ÂeI2C_ISR_PECERR_Pos (11U) ÃeI2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) ÄeI2C_ISR_PECERR I2C_ISR_PECERR_Msk ÅeI2C_ISR_TIMEOUT_Pos (12U) ÆeI2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) ÇeI2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk ÈeI2C_ISR_ALERT_Pos (13U) ÉeI2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) ÊeI2C_ISR_ALERT I2C_ISR_ALERT_Msk ËeI2C_ISR_BUSY_Pos (15U) ÌeI2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) ÍeI2C_ISR_BUSY I2C_ISR_BUSY_Msk ÎeI2C_ISR_DIR_Pos (16U) ÏeI2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) ÐeI2C_ISR_DIR I2C_ISR_DIR_Msk ÑeI2C_ISR_ADDCODE_Pos (17U) ÒeI2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) ÓeI2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk ÖeI2C_ICR_ADDRCF_Pos (3U) ×eI2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) ØeI2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk ÙeI2C_ICR_NACKCF_Pos (4U) ÚeI2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) ÛeI2C_ICR_NACKCF I2C_ICR_NACKCF_Msk ÜeI2C_ICR_STOPCF_Pos (5U) ÝeI2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) ÞeI2C_ICR_STOPCF I2C_ICR_STOPCF_Msk ßeI2C_ICR_BERRCF_Pos (8U) àeI2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) áeI2C_ICR_BERRCF I2C_ICR_BERRCF_Msk âeI2C_ICR_ARLOCF_Pos (9U) ãeI2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) äeI2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk åeI2C_ICR_OVRCF_Pos (10U) æeI2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) çeI2C_ICR_OVRCF I2C_ICR_OVRCF_Msk èeI2C_ICR_PECCF_Pos (11U) éeI2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) êeI2C_ICR_PECCF I2C_ICR_PECCF_Msk ëeI2C_ICR_TIMOUTCF_Pos (12U) ìeI2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) íeI2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk îeI2C_ICR_ALERTCF_Pos (13U) ïeI2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) ðeI2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk óeI2C_PECR_PEC_Pos (0U) ôeI2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) õeI2C_PECR_PEC I2C_PECR_PEC_Msk øeI2C_RXDR_RXDATA_Pos (0U) ùeI2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) úeI2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk ýeI2C_TXDR_TXDATA_Pos (0U) þeI2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) ÿeI2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk fIWDG_KR_KEY_Pos (0U) fIWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) fIWDG_KR_KEY IWDG_KR_KEY_Msk fIWDG_PR_PR_Pos (0U) fIWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) fIWDG_PR_PR IWDG_PR_PR_Msk fIWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) fIWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) fIWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) fIWDG_RLR_RL_Pos (0U) fIWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) fIWDG_RLR_RL IWDG_RLR_RL_Msk fIWDG_SR_PVU_Pos (0U) fIWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) fIWDG_SR_PVU IWDG_SR_PVU_Msk fIWDG_SR_RVU_Pos (1U) fIWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) fIWDG_SR_RVU IWDG_SR_RVU_Msk fIWDG_SR_WVU_Pos (2U) fIWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) ¡fIWDG_SR_WVU IWDG_SR_WVU_Msk ¤fIWDG_WINR_WIN_Pos (0U) ¥fIWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) ¦fIWDG_WINR_WIN IWDG_WINR_WIN_Msk ®fJPEG_CONFR0_START_Pos (0U) ¯fJPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) °fJPEG_CONFR0_START JPEG_CONFR0_START_Msk ³fJPEG_CONFR1_NF_Pos (0U) ´fJPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) µfJPEG_CONFR1_NF JPEG_CONFR1_NF_Msk ¶fJPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) ·fJPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) ¸fJPEG_CONFR1_DE_Pos (3U) ¹fJPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) ºfJPEG_CONFR1_DE JPEG_CONFR1_DE_Msk »fJPEG_CONFR1_COLORSPACE_Pos (4U) ¼fJPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) ½fJPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk ¾fJPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) ¿fJPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) ÀfJPEG_CONFR1_NS_Pos (6U) ÁfJPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) ÂfJPEG_CONFR1_NS JPEG_CONFR1_NS_Msk ÃfJPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) ÄfJPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) ÅfJPEG_CONFR1_HDR_Pos (8U) ÆfJPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) ÇfJPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk ÈfJPEG_CONFR1_YSIZE_Pos (16U) ÉfJPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) ÊfJPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk ÍfJPEG_CONFR2_NMCU_Pos (0U) ÎfJPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) ÏfJPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk ÒfJPEG_CONFR3_XSIZE_Pos (16U) ÓfJPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) ÔfJPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk ×fJPEG_CONFR4_HD_Pos (0U) ØfJPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) ÙfJPEG_CONFR4_HD JPEG_CONFR4_HD_Msk ÚfJPEG_CONFR4_HA_Pos (1U) ÛfJPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) ÜfJPEG_CONFR4_HA JPEG_CONFR4_HA_Msk ÝfJPEG_CONFR4_QT_Pos (2U) ÞfJPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) ßfJPEG_CONFR4_QT JPEG_CONFR4_QT_Msk àfJPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) áfJPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) âfJPEG_CONFR4_NB_Pos (4U) ãfJPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) äfJPEG_CONFR4_NB JPEG_CONFR4_NB_Msk åfJPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) æfJPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) çfJPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) èfJPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) éfJPEG_CONFR4_VSF_Pos (8U) êfJPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) ëfJPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk ìfJPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) ífJPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) îfJPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) ïfJPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) ðfJPEG_CONFR4_HSF_Pos (12U) ñfJPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) òfJPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk ófJPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) ôfJPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) õfJPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) öfJPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) ùfJPEG_CONFR5_HD_Pos (0U) úfJPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) ûfJPEG_CONFR5_HD JPEG_CONFR5_HD_Msk üfJPEG_CONFR5_HA_Pos (1U) ýfJPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) þfJPEG_CONFR5_HA JPEG_CONFR5_HA_Msk ÿfJPEG_CONFR5_QT_Pos (2U) gJPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) gJPEG_CONFR5_QT JPEG_CONFR5_QT_Msk gJPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) gJPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) gJPEG_CONFR5_NB_Pos (4U)
gJPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) gJPEG_CONFR5_NB JPEG_CONFR5_NB_Msk gJPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) gJPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) gJPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) gJPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) gJPEG_CONFR5_VSF_Pos (8U) gJPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) gJPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk gJPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) gJPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) gJPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) gJPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) gJPEG_CONFR5_HSF_Pos (12U) gJPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) gJPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk gJPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) gJPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) gJPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) gJPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) gJPEG_CONFR6_HD_Pos (0U) gJPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) gJPEG_CONFR6_HD JPEG_CONFR6_HD_Msk gJPEG_CONFR6_HA_Pos (1U) gJPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) gJPEG_CONFR6_HA JPEG_CONFR6_HA_Msk ¡gJPEG_CONFR6_QT_Pos (2U) ¢gJPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) £gJPEG_CONFR6_QT JPEG_CONFR6_QT_Msk ¤gJPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) ¥gJPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) ¦gJPEG_CONFR6_NB_Pos (4U) §gJPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) ¨gJPEG_CONFR6_NB JPEG_CONFR6_NB_Msk ©gJPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) ªgJPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) «gJPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) ¬gJPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) gJPEG_CONFR6_VSF_Pos (8U) ®gJPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) ¯gJPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk °gJPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) ±gJPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) ²gJPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) ³gJPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) ´gJPEG_CONFR6_HSF_Pos (12U) µgJPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) ¶gJPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk ·gJPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) ¸gJPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) ¹gJPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) ºgJPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) ½gJPEG_CONFR7_HD_Pos (0U) ¾gJPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) ¿gJPEG_CONFR7_HD JPEG_CONFR7_HD_Msk ÀgJPEG_CONFR7_HA_Pos (1U) ÁgJPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) ÂgJPEG_CONFR7_HA JPEG_CONFR7_HA_Msk ÃgJPEG_CONFR7_QT_Pos (2U) ÄgJPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) ÅgJPEG_CONFR7_QT JPEG_CONFR7_QT_Msk ÆgJPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) ÇgJPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) ÈgJPEG_CONFR7_NB_Pos (4U) ÉgJPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) ÊgJPEG_CONFR7_NB JPEG_CONFR7_NB_Msk ËgJPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) ÌgJPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) ÍgJPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) ÎgJPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) ÏgJPEG_CONFR7_VSF_Pos (8U) ÐgJPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) ÑgJPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk ÒgJPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) ÓgJPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) ÔgJPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) ÕgJPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) ÖgJPEG_CONFR7_HSF_Pos (12U) ×gJPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) ØgJPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk ÙgJPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) ÚgJPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) ÛgJPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) ÜgJPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) ßgJPEG_CR_JCEN_Pos (0U) àgJPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) ágJPEG_CR_JCEN JPEG_CR_JCEN_Msk âgJPEG_CR_IFTIE_Pos (1U) ãgJPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) ägJPEG_CR_IFTIE JPEG_CR_IFTIE_Msk ågJPEG_CR_IFNFIE_Pos (2U) ægJPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) çgJPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk ègJPEG_CR_OFTIE_Pos (3U) égJPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) êgJPEG_CR_OFTIE JPEG_CR_OFTIE_Msk ëgJPEG_CR_OFNEIE_Pos (4U) ìgJPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) ígJPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk îgJPEG_CR_EOCIE_Pos (5U) ïgJPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) ðgJPEG_CR_EOCIE JPEG_CR_EOCIE_Msk ñgJPEG_CR_HPDIE_Pos (6U) ògJPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) ógJPEG_CR_HPDIE JPEG_CR_HPDIE_Msk ôgJPEG_CR_IFF_Pos (13U) õgJPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) ögJPEG_CR_IFF JPEG_CR_IFF_Msk ÷gJPEG_CR_OFF_Pos (14U) øgJPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) ùgJPEG_CR_OFF JPEG_CR_OFF_Msk ügJPEG_SR_IFTF_Pos (1U) ýgJPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) þgJPEG_SR_IFTF JPEG_SR_IFTF_Msk ÿgJPEG_SR_IFNFF_Pos (2U) hJPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) hJPEG_SR_IFNFF JPEG_SR_IFNFF_Msk hJPEG_SR_OFTF_Pos (3U) hJPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) hJPEG_SR_OFTF JPEG_SR_OFTF_Msk
hJPEG_SR_OFNEF_Pos (4U) hJPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) hJPEG_SR_OFNEF JPEG_SR_OFNEF_Msk hJPEG_SR_EOCF_Pos (5U) hJPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) hJPEG_SR_EOCF JPEG_SR_EOCF_Msk hJPEG_SR_HPDF_Pos (6U) hJPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) hJPEG_SR_HPDF JPEG_SR_HPDF_Msk hJPEG_SR_COF_Pos (7U) hJPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) hJPEG_SR_COF JPEG_SR_COF_Msk hJPEG_CFR_CEOCF_Pos (5U) hJPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) hJPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk hJPEG_CFR_CHPDF_Pos (6U) hJPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) hJPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk hJPEG_DIR_DATAIN_Pos (0U) hJPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) hJPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk hJPEG_DOR_DATAOUT_Pos (0U) ¡hJPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) ¢hJPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk ¬hLTDC_SSCR_VSH_Pos (0U) hLTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) ®hLTDC_SSCR_VSH LTDC_SSCR_VSH_Msk ¯hLTDC_SSCR_HSW_Pos (16U) °hLTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) ±hLTDC_SSCR_HSW LTDC_SSCR_HSW_Msk µhLTDC_BPCR_AVBP_Pos (0U) ¶hLTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) ·hLTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk ¸hLTDC_BPCR_AHBP_Pos (16U) ¹hLTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) ºhLTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk ¾hLTDC_AWCR_AAH_Pos (0U) ¿hLTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) ÀhLTDC_AWCR_AAH LTDC_AWCR_AAH_Msk ÁhLTDC_AWCR_AAW_Pos (16U) ÂhLTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) ÃhLTDC_AWCR_AAW LTDC_AWCR_AAW_Msk ÇhLTDC_TWCR_TOTALH_Pos (0U) ÈhLTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) ÉhLTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk ÊhLTDC_TWCR_TOTALW_Pos (16U) ËhLTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) ÌhLTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk ÐhLTDC_GCR_LTDCEN_Pos (0U) ÑhLTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) ÒhLTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk ÓhLTDC_GCR_DBW_Pos (4U) ÔhLTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) ÕhLTDC_GCR_DBW LTDC_GCR_DBW_Msk ÖhLTDC_GCR_DGW_Pos (8U) ×hLTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) ØhLTDC_GCR_DGW LTDC_GCR_DGW_Msk ÙhLTDC_GCR_DRW_Pos (12U) ÚhLTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) ÛhLTDC_GCR_DRW LTDC_GCR_DRW_Msk ÜhLTDC_GCR_DEN_Pos (16U) ÝhLTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) ÞhLTDC_GCR_DEN LTDC_GCR_DEN_Msk ßhLTDC_GCR_PCPOL_Pos (28U) àhLTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) áhLTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk âhLTDC_GCR_DEPOL_Pos (29U) ãhLTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) ähLTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk åhLTDC_GCR_VSPOL_Pos (30U) æhLTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) çhLTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk èhLTDC_GCR_HSPOL_Pos (31U) éhLTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) êhLTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk ïhLTDC_SRCR_IMR_Pos (0U) ðhLTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) ñhLTDC_SRCR_IMR LTDC_SRCR_IMR_Msk òhLTDC_SRCR_VBR_Pos (1U) óhLTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) ôhLTDC_SRCR_VBR LTDC_SRCR_VBR_Msk øhLTDC_BCCR_BCBLUE_Pos (0U) ùhLTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) úhLTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk ûhLTDC_BCCR_BCGREEN_Pos (8U) ühLTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) ýhLTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk þhLTDC_BCCR_BCRED_Pos (16U) ÿhLTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) iLTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk iLTDC_IER_LIE_Pos (0U)
iLTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) iLTDC_IER_LIE LTDC_IER_LIE_Msk iLTDC_IER_FUIE_Pos (1U) iLTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) iLTDC_IER_FUIE LTDC_IER_FUIE_Msk iLTDC_IER_TERRIE_Pos (2U) iLTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) iLTDC_IER_TERRIE LTDC_IER_TERRIE_Msk iLTDC_IER_RRIE_Pos (3U) iLTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) iLTDC_IER_RRIE LTDC_IER_RRIE_Msk iLTDC_ISR_LIF_Pos (0U) iLTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) iLTDC_ISR_LIF LTDC_ISR_LIF_Msk iLTDC_ISR_FUIF_Pos (1U) iLTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) iLTDC_ISR_FUIF LTDC_ISR_FUIF_Msk iLTDC_ISR_TERRIF_Pos (2U) iLTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) iLTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk iLTDC_ISR_RRIF_Pos (3U) iLTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) iLTDC_ISR_RRIF LTDC_ISR_RRIF_Msk ¢iLTDC_ICR_CLIF_Pos (0U) £iLTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) ¤iLTDC_ICR_CLIF LTDC_ICR_CLIF_Msk ¥iLTDC_ICR_CFUIF_Pos (1U) ¦iLTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) §iLTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk ¨iLTDC_ICR_CTERRIF_Pos (2U) ©iLTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) ªiLTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk «iLTDC_ICR_CRRIF_Pos (3U) ¬iLTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) iLTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk ±iLTDC_LIPCR_LIPOS_Pos (0U) ²iLTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) ³iLTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk ·iLTDC_CPSR_CYPOS_Pos (0U) ¸iLTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) ¹iLTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk ºiLTDC_CPSR_CXPOS_Pos (16U) »iLTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) ¼iLTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk ÀiLTDC_CDSR_VDES_Pos (0U) ÁiLTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) ÂiLTDC_CDSR_VDES LTDC_CDSR_VDES_Msk ÃiLTDC_CDSR_HDES_Pos (1U) ÄiLTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) ÅiLTDC_CDSR_HDES LTDC_CDSR_HDES_Msk ÆiLTDC_CDSR_VSYNCS_Pos (2U) ÇiLTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) ÈiLTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk ÉiLTDC_CDSR_HSYNCS_Pos (3U) ÊiLTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) ËiLTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk ÏiLTDC_LxCR_LEN_Pos (0U) ÐiLTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) ÑiLTDC_LxCR_LEN LTDC_LxCR_LEN_Msk ÒiLTDC_LxCR_COLKEN_Pos (1U) ÓiLTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) ÔiLTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk ÕiLTDC_LxCR_CLUTEN_Pos (4U) ÖiLTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) ×iLTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk ÛiLTDC_LxWHPCR_WHSTPOS_Pos (0U) ÜiLTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) ÝiLTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk ÞiLTDC_LxWHPCR_WHSPPOS_Pos (16U) ßiLTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) àiLTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk äiLTDC_LxWVPCR_WVSTPOS_Pos (0U) åiLTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) æiLTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk çiLTDC_LxWVPCR_WVSPPOS_Pos (16U) èiLTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) éiLTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk íiLTDC_LxCKCR_CKBLUE_Pos (0U) îiLTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) ïiLTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk ðiLTDC_LxCKCR_CKGREEN_Pos (8U) ñiLTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) òiLTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk óiLTDC_LxCKCR_CKRED_Pos (16U) ôiLTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) õiLTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk ùiLTDC_LxPFCR_PF_Pos (0U) úiLTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) ûiLTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk ÿiLTDC_LxCACR_CONSTA_Pos (0U) jLTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) jLTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
jLTDC_LxDCCR_DCBLUE_Pos (0U) jLTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) jLTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk jLTDC_LxDCCR_DCGREEN_Pos (8U) jLTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) jLTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk jLTDC_LxDCCR_DCRED_Pos (16U) jLTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) jLTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk jLTDC_LxDCCR_DCALPHA_Pos (24U) jLTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) jLTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk jLTDC_LxBFCR_BF2_Pos (0U) jLTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) jLTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk jLTDC_LxBFCR_BF1_Pos (8U) jLTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) jLTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk jLTDC_LxCFBAR_CFBADD_Pos (0U) jLTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) jLTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk £jLTDC_LxCFBLR_CFBLL_Pos (0U) ¤jLTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) ¥jLTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk ¦jLTDC_LxCFBLR_CFBP_Pos (16U) §jLTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) ¨jLTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk ¬jLTDC_LxCFBLNR_CFBLNBR_Pos (0U) jLTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) ®jLTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk ²jLTDC_LxCLUTWR_BLUE_Pos (0U) ³jLTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) ´jLTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk µjLTDC_LxCLUTWR_GREEN_Pos (8U) ¶jLTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) ·jLTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk ¸jLTDC_LxCLUTWR_RED_Pos (16U) ¹jLTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) ºjLTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk »jLTDC_LxCLUTWR_CLUTADD_Pos (24U) ¼jLTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) ½jLTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk ÅjMDMA_GISR0_GIF0_Pos (0U) ÆjMDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) ÇjMDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk ÈjMDMA_GISR0_GIF1_Pos (1U) ÉjMDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) ÊjMDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk ËjMDMA_GISR0_GIF2_Pos (2U) ÌjMDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) ÍjMDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk ÎjMDMA_GISR0_GIF3_Pos (3U) ÏjMDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) ÐjMDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk ÑjMDMA_GISR0_GIF4_Pos (4U) ÒjMDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) ÓjMDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk ÔjMDMA_GISR0_GIF5_Pos (5U) ÕjMDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) ÖjMDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk ×jMDMA_GISR0_GIF6_Pos (6U) ØjMDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) ÙjMDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk ÚjMDMA_GISR0_GIF7_Pos (7U) ÛjMDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) ÜjMDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk ÝjMDMA_GISR0_GIF8_Pos (8U) ÞjMDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) ßjMDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk àjMDMA_GISR0_GIF9_Pos (9U) ájMDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) âjMDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk ãjMDMA_GISR0_GIF10_Pos (10U) äjMDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) åjMDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk æjMDMA_GISR0_GIF11_Pos (11U) çjMDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) èjMDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk éjMDMA_GISR0_GIF12_Pos (12U) êjMDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) ëjMDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk ìjMDMA_GISR0_GIF13_Pos (13U) íjMDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) îjMDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk ïjMDMA_GISR0_GIF14_Pos (14U) ðjMDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) ñjMDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk òjMDMA_GISR0_GIF15_Pos (15U) ójMDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) ôjMDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk ÷jMDMA_CISR_TEIF_Pos (0U) øjMDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) ùjMDMA_CISR_TEIF MDMA_CISR_TEIF_Msk újMDMA_CISR_CTCIF_Pos (1U) ûjMDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) üjMDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk ýjMDMA_CISR_BRTIF_Pos (2U) þjMDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) ÿjMDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk kMDMA_CISR_BTIF_Pos (3U) kMDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) kMDMA_CISR_BTIF MDMA_CISR_BTIF_Msk kMDMA_CISR_TCIF_Pos (4U) kMDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
kMDMA_CISR_TCIF MDMA_CISR_TCIF_Msk kMDMA_CISR_CRQA_Pos (16U) kMDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) kMDMA_CISR_CRQA MDMA_CISR_CRQA_Msk kMDMA_CIFCR_CTEIF_Pos (0U) kMDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) kMDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk kMDMA_CIFCR_CCTCIF_Pos (1U) kMDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) kMDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk kMDMA_CIFCR_CBRTIF_Pos (2U) kMDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) kMDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk kMDMA_CIFCR_CBTIF_Pos (3U) kMDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) kMDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk kMDMA_CIFCR_CLTCIF_Pos (4U) kMDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) kMDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk kMDMA_CESR_TEA_Pos (0U) kMDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) kMDMA_CESR_TEA MDMA_CESR_TEA_Msk kMDMA_CESR_TED_Pos (7U) kMDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) ¡kMDMA_CESR_TED MDMA_CESR_TED_Msk ¢kMDMA_CESR_TELD_Pos (8U) £kMDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) ¤kMDMA_CESR_TELD MDMA_CESR_TELD_Msk ¥kMDMA_CESR_TEMD_Pos (9U) ¦kMDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) §kMDMA_CESR_TEMD MDMA_CESR_TEMD_Msk ¨kMDMA_CESR_ASE_Pos (10U) ©kMDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) ªkMDMA_CESR_ASE MDMA_CESR_ASE_Msk «kMDMA_CESR_BSE_Pos (11U) ¬kMDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) kMDMA_CESR_BSE MDMA_CESR_BSE_Msk °kMDMA_CCR_EN_Pos (0U) ±kMDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) ²kMDMA_CCR_EN MDMA_CCR_EN_Msk ³kMDMA_CCR_TEIE_Pos (1U) ´kMDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) µkMDMA_CCR_TEIE MDMA_CCR_TEIE_Msk ¶kMDMA_CCR_CTCIE_Pos (2U) ·kMDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) ¸kMDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk ¹kMDMA_CCR_BRTIE_Pos (3U) ºkMDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) »kMDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk ¼kMDMA_CCR_BTIE_Pos (4U) ½kMDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) ¾kMDMA_CCR_BTIE MDMA_CCR_BTIE_Msk ¿kMDMA_CCR_TCIE_Pos (5U) ÀkMDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) ÁkMDMA_CCR_TCIE MDMA_CCR_TCIE_Msk ÂkMDMA_CCR_PL_Pos (6U) ÃkMDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) ÄkMDMA_CCR_PL MDMA_CCR_PL_Msk ÅkMDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) ÆkMDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) ÇkMDMA_CCR_BEX_Pos (12U) ÈkMDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) ÉkMDMA_CCR_BEX MDMA_CCR_BEX_Msk ÊkMDMA_CCR_HEX_Pos (13U) ËkMDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) ÌkMDMA_CCR_HEX MDMA_CCR_HEX_Msk ÍkMDMA_CCR_WEX_Pos (14U) ÎkMDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) ÏkMDMA_CCR_WEX MDMA_CCR_WEX_Msk ÐkMDMA_CCR_SWRQ_Pos (16U) ÑkMDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) ÒkMDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk ÕkMDMA_CTCR_SINC_Pos (0U) ÖkMDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) ×kMDMA_CTCR_SINC MDMA_CTCR_SINC_Msk ØkMDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) ÙkMDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) ÚkMDMA_CTCR_DINC_Pos (2U) ÛkMDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) ÜkMDMA_CTCR_DINC MDMA_CTCR_DINC_Msk ÝkMDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) ÞkMDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) ßkMDMA_CTCR_SSIZE_Pos (4U) àkMDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) ákMDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk âkMDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) ãkMDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) äkMDMA_CTCR_DSIZE_Pos (6U) åkMDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) ækMDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk çkMDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) èkMDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) ékMDMA_CTCR_SINCOS_Pos (8U) êkMDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) ëkMDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk ìkMDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) íkMDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) îkMDMA_CTCR_DINCOS_Pos (10U) ïkMDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) ðkMDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk ñkMDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) òkMDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) ókMDMA_CTCR_SBURST_Pos (12U) ôkMDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) õkMDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk ökMDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) ÷kMDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) økMDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) ùkMDMA_CTCR_DBURST_Pos (15U) úkMDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) ûkMDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk ükMDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) ýkMDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) þkMDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) ÿkMDMA_CTCR_TLEN_Pos (18U) lMDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) lMDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk lMDMA_CTCR_PKE_Pos (25U) lMDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) lMDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
lMDMA_CTCR_PAM_Pos (26U) lMDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) lMDMA_CTCR_PAM MDMA_CTCR_PAM_Msk lMDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) lMDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) lMDMA_CTCR_TRGM_Pos (28U) lMDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) lMDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk lMDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) lMDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) lMDMA_CTCR_SWRM_Pos (30U) lMDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) lMDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk lMDMA_CTCR_BWM_Pos (31U) lMDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) lMDMA_CTCR_BWM MDMA_CTCR_BWM_Msk lMDMA_CBNDTR_BNDT_Pos (0U) lMDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) lMDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk lMDMA_CBNDTR_BRSUM_Pos (18U) lMDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) lMDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk lMDMA_CBNDTR_BRDUM_Pos (19U) lMDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) lMDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk lMDMA_CBNDTR_BRC_Pos (20U) ¡lMDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) ¢lMDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk ¥lMDMA_CSAR_SAR_Pos (0U) ¦lMDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) §lMDMA_CSAR_SAR MDMA_CSAR_SAR_Msk ªlMDMA_CDAR_DAR_Pos (0U) «lMDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) ¬lMDMA_CDAR_DAR MDMA_CDAR_DAR_Msk ¯lMDMA_CBRUR_SUV_Pos (0U) °lMDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) ±lMDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk ²lMDMA_CBRUR_DUV_Pos (16U) ³lMDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) ´lMDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk ·lMDMA_CLAR_LAR_Pos (0U) ¸lMDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) ¹lMDMA_CLAR_LAR MDMA_CLAR_LAR_Msk ¼lMDMA_CTBR_TSEL_Pos (0U) ½lMDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) ¾lMDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk ¿lMDMA_CTBR_SBUS_Pos (16U) ÀlMDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) ÁlMDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk ÂlMDMA_CTBR_DBUS_Pos (17U) ÃlMDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) ÄlMDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk ÇlMDMA_CMAR_MAR_Pos (0U) ÈlMDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) ÉlMDMA_CMAR_MAR MDMA_CMAR_MAR_Msk ÌlMDMA_CMDR_MDR_Pos (0U) ÍlMDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) ÎlMDMA_CMDR_MDR MDMA_CMDR_MDR_Msk ÖlOPAMP_CSR_OPAMPxEN_Pos (0U) ×lOPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) ØlOPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk ÙlOPAMP_CSR_FORCEVP_Pos (1U) ÚlOPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) ÛlOPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk ÝlOPAMP_CSR_VPSEL_Pos (2U) ÞlOPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) ßlOPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk àlOPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) álOPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) ãlOPAMP_CSR_VMSEL_Pos (5U) älOPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) ålOPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk ælOPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) çlOPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) élOPAMP_CSR_OPAHSM_Pos (8U) êlOPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) ëlOPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk ìlOPAMP_CSR_CALON_Pos (11U) ílOPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) îlOPAMP_CSR_CALON OPAMP_CSR_CALON_Msk ðlOPAMP_CSR_CALSEL_Pos (12U) ñlOPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) òlOPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk ólOPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) ôlOPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) ölOPAMP_CSR_PGGAIN_Pos (14U) ÷lOPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) ølOPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk ùlOPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) úlOPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) ûlOPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) ülOPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) þlOPAMP_CSR_USERTRIM_Pos (18U) ÿlOPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) mOPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk mOPAMP_CSR_TSTREF_Pos (29U) mOPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) mOPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk mOPAMP_CSR_CALOUT_Pos (30U)
mOPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) mOPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk mOPAMP1_CSR_OPAEN_Pos (0U) mOPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) mOPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk mOPAMP1_CSR_FORCEVP_Pos (1U) mOPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) mOPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk mOPAMP1_CSR_VPSEL_Pos (2U) mOPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) mOPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk mOPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) mOPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) mOPAMP1_CSR_VMSEL_Pos (5U) mOPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) mOPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk mOPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) mOPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) mOPAMP1_CSR_OPAHSM_Pos (8U) mOPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) mOPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk mOPAMP1_CSR_CALON_Pos (11U) mOPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) ¡mOPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk £mOPAMP1_CSR_CALSEL_Pos (12U) ¤mOPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) ¥mOPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk ¦mOPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) §mOPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) ©mOPAMP1_CSR_PGGAIN_Pos (14U) ªmOPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) «mOPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk ¬mOPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) mOPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) ®mOPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) ¯mOPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) ±mOPAMP1_CSR_USERTRIM_Pos (18U) ²mOPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) ³mOPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk ´mOPAMP1_CSR_TSTREF_Pos (29U) µmOPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) ¶mOPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk ·mOPAMP1_CSR_CALOUT_Pos (30U) ¸mOPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) ¹mOPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk ¼mOPAMP2_CSR_OPAEN_Pos (0U) ½mOPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) ¾mOPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk ¿mOPAMP2_CSR_FORCEVP_Pos (1U) ÀmOPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) ÁmOPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk ÃmOPAMP2_CSR_VPSEL_Pos (2U) ÄmOPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) ÅmOPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk ÆmOPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) ÇmOPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) ÉmOPAMP2_CSR_VMSEL_Pos (5U) ÊmOPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) ËmOPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk ÌmOPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) ÍmOPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) ÏmOPAMP2_CSR_OPAHSM_Pos (8U) ÐmOPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) ÑmOPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk ÒmOPAMP2_CSR_CALON_Pos (11U) ÓmOPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) ÔmOPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk ÖmOPAMP2_CSR_CALSEL_Pos (12U) ×mOPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) ØmOPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk ÙmOPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) ÚmOPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) ÜmOPAMP2_CSR_PGGAIN_Pos (14U) ÝmOPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) ÞmOPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk ßmOPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) àmOPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) ámOPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) âmOPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) ämOPAMP2_CSR_USERTRIM_Pos (18U) åmOPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) æmOPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk çmOPAMP2_CSR_TSTREF_Pos (29U) èmOPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) émOPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk êmOPAMP2_CSR_CALOUT_Pos (30U) ëmOPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) ìmOPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk ïmOPAMP_OTR_TRIMOFFSETN_Pos (0U) ðmOPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) ñmOPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk òmOPAMP_OTR_TRIMOFFSETP_Pos (8U) ómOPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) ômOPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk ÷mOPAMP1_OTR_TRIMOFFSETN_Pos (0U) ømOPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) ùmOPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk úmOPAMP1_OTR_TRIMOFFSETP_Pos (8U) ûmOPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) ümOPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk ÿmOPAMP2_OTR_TRIMOFFSETN_Pos (0U) nOPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) nOPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk nOPAMP2_OTR_TRIMOFFSETP_Pos (8U) nOPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) nOPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk nOPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U) nOPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) nOPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk nOPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U) nOPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) nOPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk nOPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U) nOPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) nOPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk nOPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U) nOPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) nOPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk nOPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U) nOPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) nOPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk nOPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U) nOPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) nOPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk ¤nPOWER_DOMAINS_NUMBER 3U §nPWR_CR1_ALS_Pos (17U) ¨nPWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) ©nPWR_CR1_ALS PWR_CR1_ALS_Msk ªnPWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) «nPWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) ¬nPWR_CR1_AVDEN_Pos (16U) nPWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) ®nPWR_CR1_AVDEN PWR_CR1_AVDEN_Msk ¯nPWR_CR1_SVOS_Pos (14U) °nPWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) ±nPWR_CR1_SVOS PWR_CR1_SVOS_Msk ²nPWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) ³nPWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) ´nPWR_CR1_FLPS_Pos (9U) µnPWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) ¶nPWR_CR1_FLPS PWR_CR1_FLPS_Msk ·nPWR_CR1_DBP_Pos (8U) ¸nPWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) ¹nPWR_CR1_DBP PWR_CR1_DBP_Msk ºnPWR_CR1_PLS_Pos (5U) »nPWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) ¼nPWR_CR1_PLS PWR_CR1_PLS_Msk ½nPWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) ¾nPWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) ¿nPWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) ÀnPWR_CR1_PVDEN_Pos (4U) ÁnPWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) ÂnPWR_CR1_PVDEN PWR_CR1_PVDEN_Msk ÃnPWR_CR1_LPDS_Pos (0U) ÄnPWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) ÅnPWR_CR1_LPDS PWR_CR1_LPDS_Msk ÈnPWR_CR1_PLS_LEV0 (0UL) ÉnPWR_CR1_PLS_LEV1_Pos (5U) ÊnPWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) ËnPWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk ÌnPWR_CR1_PLS_LEV2_Pos (6U) ÍnPWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) ÎnPWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk ÏnPWR_CR1_PLS_LEV3_Pos (5U) ÐnPWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) ÑnPWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk ÒnPWR_CR1_PLS_LEV4_Pos (7U) ÓnPWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) ÔnPWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk ÕnPWR_CR1_PLS_LEV5_Pos (5U) ÖnPWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) ×nPWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk ØnPWR_CR1_PLS_LEV6_Pos (6U) ÙnPWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) ÚnPWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk ÛnPWR_CR1_PLS_LEV7_Pos (5U) ÜnPWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) ÝnPWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk ànPWR_CR1_ALS_LEV0 (0UL) ánPWR_CR1_ALS_LEV1_Pos (17U) ânPWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) ãnPWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk änPWR_CR1_ALS_LEV2_Pos (18U) ånPWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) ænPWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk çnPWR_CR1_ALS_LEV3_Pos (17U) ènPWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) énPWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk ìnPWR_CSR1_AVDO_Pos (16U) ínPWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) înPWR_CSR1_AVDO PWR_CSR1_AVDO_Msk ïnPWR_CSR1_ACTVOS_Pos (14U) ðnPWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) ñnPWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk ònPWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) ónPWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) ônPWR_CSR1_ACTVOSRDY_Pos (13U) õnPWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) önPWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk ÷nPWR_CSR1_PVDO_Pos (4U) ønPWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) ùnPWR_CSR1_PVDO PWR_CSR1_PVDO_Msk ünPWR_CR2_TEMPH_Pos (23U) ýnPWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) þnPWR_CR2_TEMPH PWR_CR2_TEMPH_Msk ÿnPWR_CR2_TEMPL_Pos (22U) oPWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) oPWR_CR2_TEMPL PWR_CR2_TEMPL_Msk oPWR_CR2_VBATH_Pos (21U) oPWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) oPWR_CR2_VBATH PWR_CR2_VBATH_Msk
oPWR_CR2_VBATL_Pos (20U) oPWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) oPWR_CR2_VBATL PWR_CR2_VBATL_Msk oPWR_CR2_BRRDY_Pos (16U) oPWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) oPWR_CR2_BRRDY PWR_CR2_BRRDY_Msk oPWR_CR2_MONEN_Pos (4U) oPWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) oPWR_CR2_MONEN PWR_CR2_MONEN_Msk oPWR_CR2_BREN_Pos (0U) oPWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) oPWR_CR2_BREN PWR_CR2_BREN_Msk oPWR_CR3_USB33RDY_Pos (26U) oPWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) oPWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk oPWR_CR3_USBREGEN_Pos (25U) oPWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) oPWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk oPWR_CR3_USB33DEN_Pos (24U) oPWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) oPWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk oPWR_CR3_VBRS_Pos (9U) oPWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) oPWR_CR3_VBRS PWR_CR3_VBRS_Msk oPWR_CR3_VBE_Pos (8U) oPWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) ¡oPWR_CR3_VBE PWR_CR3_VBE_Msk ¢oPWR_CR3_SCUEN_Pos (2U) £oPWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos) ¤oPWR_CR3_SCUEN PWR_CR3_SCUEN_Msk ¥oPWR_CR3_LDOEN_Pos (1U) ¦oPWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) §oPWR_CR3_LDOEN PWR_CR3_LDOEN_Msk ¨oPWR_CR3_BYPASS_Pos (0U) ©oPWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) ªoPWR_CR3_BYPASS PWR_CR3_BYPASS_Msk oPWR_CPUCR_RUN_D3_Pos (11U) ®oPWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) ¯oPWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk °oPWR_CPUCR_CSSF_Pos (9U) ±oPWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) ²oPWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk ³oPWR_CPUCR_SBF_D2_Pos (8U) ´oPWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) µoPWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk ¶oPWR_CPUCR_SBF_D1_Pos (7U) ·oPWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) ¸oPWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk ¹oPWR_CPUCR_SBF_Pos (6U) ºoPWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) »oPWR_CPUCR_SBF PWR_CPUCR_SBF_Msk ¼oPWR_CPUCR_STOPF_Pos (5U) ½oPWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) ¾oPWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk ¿oPWR_CPUCR_PDDS_D3_Pos (2U) ÀoPWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) ÁoPWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk ÂoPWR_CPUCR_PDDS_D2_Pos (1U) ÃoPWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) ÄoPWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk ÅoPWR_CPUCR_PDDS_D1_Pos (0U) ÆoPWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) ÇoPWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk ËoPWR_D3CR_VOS_Pos (14U) ÌoPWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) ÍoPWR_D3CR_VOS PWR_D3CR_VOS_Msk ÎoPWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) ÏoPWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) ÐoPWR_D3CR_VOSRDY_Pos (13U) ÑoPWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) ÒoPWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk ÕoPWR_WKUPCR_WKUPC6_Pos (5U) ÖoPWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) ×oPWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk ØoPWR_WKUPCR_WKUPC5_Pos (4U) ÙoPWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) ÚoPWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk ÛoPWR_WKUPCR_WKUPC4_Pos (3U) ÜoPWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) ÝoPWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk ÞoPWR_WKUPCR_WKUPC3_Pos (2U) ßoPWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) àoPWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk áoPWR_WKUPCR_WKUPC2_Pos (1U) âoPWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) ãoPWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk äoPWR_WKUPCR_WKUPC1_Pos (0U) åoPWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) æoPWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk éoPWR_WKUPFR_WKUPF6_Pos (5U) êoPWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) ëoPWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk ìoPWR_WKUPFR_WKUPF5_Pos (4U) íoPWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) îoPWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk ïoPWR_WKUPFR_WKUPF4_Pos (3U) ðoPWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) ñoPWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk òoPWR_WKUPFR_WKUPF3_Pos (2U) óoPWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) ôoPWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk õoPWR_WKUPFR_WKUPF2_Pos (1U) öoPWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) ÷oPWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk øoPWR_WKUPFR_WKUPF1_Pos (0U) ùoPWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) úoPWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk ýoPWR_WKUPEPR_WKUPPUPD6_Pos (26U) þoPWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) ÿoPWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk pPWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) pPWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) pPWR_WKUPEPR_WKUPPUPD5_Pos (24U) pPWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) pPWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk
pPWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) pPWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) pPWR_WKUPEPR_WKUPPUPD4_Pos (22U) pPWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) pPWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk pPWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) pPWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) pPWR_WKUPEPR_WKUPPUPD3_Pos (20U) pPWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) pPWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk pPWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) pPWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) pPWR_WKUPEPR_WKUPPUPD2_Pos (18U) pPWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) pPWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk pPWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) pPWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) pPWR_WKUPEPR_WKUPPUPD1_Pos (16U) pPWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) pPWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk pPWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) pPWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) pPWR_WKUPEPR_WKUPP6_Pos (13U) pPWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) pPWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk pPWR_WKUPEPR_WKUPP5_Pos (12U) pPWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) pPWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk ¡pPWR_WKUPEPR_WKUPP4_Pos (11U) ¢pPWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) £pPWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk ¤pPWR_WKUPEPR_WKUPP3_Pos (10U) ¥pPWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) ¦pPWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk §pPWR_WKUPEPR_WKUPP2_Pos (9U) ¨pPWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) ©pPWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk ªpPWR_WKUPEPR_WKUPP1_Pos (8U) «pPWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) ¬pPWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk pPWR_WKUPEPR_WKUPEN6_Pos (5U) ®pPWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) ¯pPWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk °pPWR_WKUPEPR_WKUPEN5_Pos (4U) ±pPWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) ²pPWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk ³pPWR_WKUPEPR_WKUPEN4_Pos (3U) ´pPWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) µpPWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk ¶pPWR_WKUPEPR_WKUPEN3_Pos (2U) ·pPWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) ¸pPWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk ¹pPWR_WKUPEPR_WKUPEN2_Pos (1U) ºpPWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) »pPWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk ¼pPWR_WKUPEPR_WKUPEN1_Pos (0U) ½pPWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) ¾pPWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk ¿pPWR_WKUPEPR_WKUPEN_Pos (0U) ÀpPWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) ÁpPWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk ÉpRCC_VER_X ÌpRCC_CR_HSION_Pos (0U) ÍpRCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) ÎpRCC_CR_HSION RCC_CR_HSION_Msk ÏpRCC_CR_HSIKERON_Pos (1U) ÐpRCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) ÑpRCC_CR_HSIKERON RCC_CR_HSIKERON_Msk ÒpRCC_CR_HSIRDY_Pos (2U) ÓpRCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) ÔpRCC_CR_HSIRDY RCC_CR_HSIRDY_Msk ÕpRCC_CR_HSIDIV_Pos (3U) ÖpRCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) ×pRCC_CR_HSIDIV RCC_CR_HSIDIV_Msk ØpRCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) ÙpRCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) ÚpRCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) ÛpRCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) ÝpRCC_CR_HSIDIVF_Pos (5U) ÞpRCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) ßpRCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk àpRCC_CR_CSION_Pos (7U) ápRCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) âpRCC_CR_CSION RCC_CR_CSION_Msk ãpRCC_CR_CSIRDY_Pos (8U) äpRCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) åpRCC_CR_CSIRDY RCC_CR_CSIRDY_Msk æpRCC_CR_CSIKERON_Pos (9U) çpRCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) èpRCC_CR_CSIKERON RCC_CR_CSIKERON_Msk épRCC_CR_HSI48ON_Pos (12U) êpRCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) ëpRCC_CR_HSI48ON RCC_CR_HSI48ON_Msk ìpRCC_CR_HSI48RDY_Pos (13U) ípRCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) îpRCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk ðpRCC_CR_D1CKRDY_Pos (14U) ñpRCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) òpRCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk ópRCC_CR_D2CKRDY_Pos (15U) ôpRCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) õpRCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk ÷pRCC_CR_HSEON_Pos (16U) øpRCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) ùpRCC_CR_HSEON RCC_CR_HSEON_Msk úpRCC_CR_HSERDY_Pos (17U) ûpRCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) üpRCC_CR_HSERDY RCC_CR_HSERDY_Msk ýpRCC_CR_HSEBYP_Pos (18U) þpRCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) ÿpRCC_CR_HSEBYP RCC_CR_HSEBYP_Msk qRCC_CR_CSSHSEON_Pos (19U) qRCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) qRCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
qRCC_CR_PLL1ON_Pos (24U) qRCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) qRCC_CR_PLL1ON RCC_CR_PLL1ON_Msk qRCC_CR_PLL1RDY_Pos (25U) qRCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) qRCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk qRCC_CR_PLL2ON_Pos (26U) qRCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) qRCC_CR_PLL2ON RCC_CR_PLL2ON_Msk qRCC_CR_PLL2RDY_Pos (27U) qRCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) qRCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk qRCC_CR_PLL3ON_Pos (28U) qRCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) qRCC_CR_PLL3ON RCC_CR_PLL3ON_Msk qRCC_CR_PLL3RDY_Pos (29U) qRCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) qRCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk qRCC_CR_PLLON_Pos (24U) qRCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) qRCC_CR_PLLON RCC_CR_PLLON_Msk qRCC_CR_PLLRDY_Pos (25U) qRCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) qRCC_CR_PLLRDY RCC_CR_PLLRDY_Msk ¢qRCC_HSICFGR_HSICAL_Pos (0U) £qRCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) ¤qRCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk ¥qRCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) ¦qRCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) §qRCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) ¨qRCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) ©qRCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) ªqRCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) «qRCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) ¬qRCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) qRCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) ®qRCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) ¯qRCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) °qRCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) ³qRCC_HSICFGR_HSITRIM_Pos (24U) ´qRCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) µqRCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk ¶qRCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) ·qRCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) ¸qRCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) ¹qRCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) ºqRCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) »qRCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) ¼qRCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) ÂqRCC_CRRCR_HSI48CAL_Pos (0U) ÃqRCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) ÄqRCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk ÅqRCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) ÆqRCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) ÇqRCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) ÈqRCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) ÉqRCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) ÊqRCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) ËqRCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) ÌqRCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) ÍqRCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) ÎqRCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) ÓqRCC_CSICFGR_CSICAL_Pos (0U) ÔqRCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) ÕqRCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk ÖqRCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) ×qRCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) ØqRCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) ÙqRCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) ÚqRCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) ÛqRCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) ÜqRCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) ÝqRCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) àqRCC_CSICFGR_CSITRIM_Pos (24U) áqRCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) âqRCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk ãqRCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) äqRCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) åqRCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) æqRCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) çqRCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) èqRCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) ìqRCC_CFGR_SW_Pos (0U) íqRCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) îqRCC_CFGR_SW RCC_CFGR_SW_Msk ïqRCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) ðqRCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) ñqRCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) óqRCC_CFGR_SW_HSI (0x00000000UL) ôqRCC_CFGR_SW_CSI (0x00000001UL) õqRCC_CFGR_SW_HSE (0x00000002UL) öqRCC_CFGR_SW_PLL1 (0x00000003UL) ùqRCC_CFGR_SWS_Pos (3U) úqRCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) ûqRCC_CFGR_SWS RCC_CFGR_SWS_Msk üqRCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) ýqRCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) þqRCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) rRCC_CFGR_SWS_HSI (0x00000000UL) rRCC_CFGR_SWS_CSI (0x00000008UL) rRCC_CFGR_SWS_HSE (0x00000010UL) rRCC_CFGR_SWS_PLL1 (0x00000018UL)
rRCC_CFGR_STOPWUCK_Pos (6U) rRCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) rRCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk rRCC_CFGR_STOPKERWUCK_Pos (7U) rRCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) rRCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk rRCC_CFGR_RTCPRE_Pos (8U) rRCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk rRCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) rRCC_CFGR_HRTIMSEL_Pos (14U) rRCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos) rRCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk rRCC_CFGR_TIMPRE_Pos (15U) rRCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) rRCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk £rRCC_CFGR_MCO1_Pos (22U) ¤rRCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos) ¥rRCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk ¦rRCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) §rRCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) ¨rRCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) ªrRCC_CFGR_MCO1PRE_Pos (18U) «rRCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) ¬rRCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk rRCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) ®rRCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) ¯rRCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) °rRCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) ²rRCC_CFGR_MCO2PRE_Pos (25U) ³rRCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) ´rRCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk µrRCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) ¶rRCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) ·rRCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) ¸rRCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) ºrRCC_CFGR_MCO2_Pos (29U) »rRCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos) ¼rRCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk ½rRCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) ¾rRCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) ¿rRCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) ÃrRCC_D1CFGR_HPRE_Pos (0U) ÄrRCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) ÅrRCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk ÆrRCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) ÇrRCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) ÈrRCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) ÉrRCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) ÌrRCC_D1CFGR_HPRE_DIV1 (0U) ÍrRCC_D1CFGR_HPRE_DIV2_Pos (3U) ÎrRCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) ÏrRCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk ÐrRCC_D1CFGR_HPRE_DIV4_Pos (0U) ÑrRCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) ÒrRCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk ÓrRCC_D1CFGR_HPRE_DIV8_Pos (1U) ÔrRCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) ÕrRCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk ÖrRCC_D1CFGR_HPRE_DIV16_Pos (0U) ×rRCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) ØrRCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk ÙrRCC_D1CFGR_HPRE_DIV64_Pos (2U) ÚrRCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) ÛrRCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk ÜrRCC_D1CFGR_HPRE_DIV128_Pos (0U) ÝrRCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) ÞrRCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk ßrRCC_D1CFGR_HPRE_DIV256_Pos (1U) àrRCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) árRCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk ârRCC_D1CFGR_HPRE_DIV512_Pos (0U) ãrRCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) ärRCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk çrRCC_D1CFGR_D1PPRE_Pos (4U) èrRCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) érRCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk êrRCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) ërRCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) ìrRCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) îrRCC_D1CFGR_D1PPRE_DIV1 (0U) ïrRCC_D1CFGR_D1PPRE_DIV2_Pos (6U) ðrRCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) ñrRCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk òrRCC_D1CFGR_D1PPRE_DIV4_Pos (4U) órRCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) ôrRCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk õrRCC_D1CFGR_D1PPRE_DIV8_Pos (5U) örRCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) ÷rRCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk ørRCC_D1CFGR_D1PPRE_DIV16_Pos (4U) ùrRCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) úrRCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk ürRCC_D1CFGR_D1CPRE_Pos (8U) ýrRCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) þrRCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk ÿrRCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) sRCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) sRCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) sRCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) sRCC_D1CFGR_D1CPRE_DIV1 (0U)
sRCC_D1CFGR_D1CPRE_DIV2_Pos (11U) sRCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) sRCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk sRCC_D1CFGR_D1CPRE_DIV4_Pos (8U) sRCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) sRCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk sRCC_D1CFGR_D1CPRE_DIV8_Pos (9U) sRCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) sRCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk sRCC_D1CFGR_D1CPRE_DIV16_Pos (8U) sRCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) sRCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk sRCC_D1CFGR_D1CPRE_DIV64_Pos (10U) sRCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) sRCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk sRCC_D1CFGR_D1CPRE_DIV128_Pos (8U) sRCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) sRCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk sRCC_D1CFGR_D1CPRE_DIV256_Pos (9U) sRCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) sRCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk sRCC_D1CFGR_D1CPRE_DIV512_Pos (8U) sRCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) sRCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk sRCC_D2CFGR_D2PPRE1_Pos (4U) ¡sRCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) ¢sRCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk £sRCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) ¤sRCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) ¥sRCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) §sRCC_D2CFGR_D2PPRE1_DIV1 (0U) ¨sRCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) ©sRCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) ªsRCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk «sRCC_D2CFGR_D2PPRE1_DIV4_Pos (4U) ¬sRCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) sRCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk ®sRCC_D2CFGR_D2PPRE1_DIV8_Pos (5U) ¯sRCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) °sRCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk ±sRCC_D2CFGR_D2PPRE1_DIV16_Pos (4U) ²sRCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) ³sRCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk ¶sRCC_D2CFGR_D2PPRE2_Pos (8U) ·sRCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) ¸sRCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk ¹sRCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) ºsRCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) »sRCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) ½sRCC_D2CFGR_D2PPRE2_DIV1 (0U) ¾sRCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) ¿sRCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) ÀsRCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk ÁsRCC_D2CFGR_D2PPRE2_DIV4_Pos (8U) ÂsRCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) ÃsRCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk ÄsRCC_D2CFGR_D2PPRE2_DIV8_Pos (9U) ÅsRCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) ÆsRCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk ÇsRCC_D2CFGR_D2PPRE2_DIV16_Pos (8U) ÈsRCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) ÉsRCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk ÍsRCC_D3CFGR_D3PPRE_Pos (4U) ÎsRCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) ÏsRCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk ÐsRCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) ÑsRCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) ÒsRCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) ÔsRCC_D3CFGR_D3PPRE_DIV1 (0U) ÕsRCC_D3CFGR_D3PPRE_DIV2_Pos (6U) ÖsRCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) ×sRCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk ØsRCC_D3CFGR_D3PPRE_DIV4_Pos (4U) ÙsRCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) ÚsRCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk ÛsRCC_D3CFGR_D3PPRE_DIV8_Pos (5U) ÜsRCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) ÝsRCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk ÞsRCC_D3CFGR_D3PPRE_DIV16_Pos (4U) ßsRCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) àsRCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk äsRCC_PLLCKSELR_PLLSRC_Pos (0U) åsRCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) æsRCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk èsRCC_PLLCKSELR_PLLSRC_HSI (0U) ésRCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) êsRCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) ësRCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk ìsRCC_PLLCKSELR_PLLSRC_HSE_Pos (1U) ísRCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) îsRCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk ïsRCC_PLLCKSELR_PLLSRC_NONE_Pos (0U) ðsRCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) ñsRCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk ósRCC_PLLCKSELR_DIVM1_Pos (4U) ôsRCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) õsRCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk ösRCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) ÷sRCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) øsRCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) ùsRCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) úsRCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) ûsRCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) ýsRCC_PLLCKSELR_DIVM2_Pos (12U) þsRCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) ÿsRCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk tRCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) tRCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) tRCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) tRCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) tRCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
tRCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) tRCC_PLLCKSELR_DIVM3_Pos (20U) tRCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk tRCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) tRCC_PLLCFGR_PLL1FRACEN_Pos (0U) tRCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) tRCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk tRCC_PLLCFGR_PLL1VCOSEL_Pos (1U) tRCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) tRCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk tRCC_PLLCFGR_PLL1RGE_Pos (2U) tRCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) tRCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk tRCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) tRCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) tRCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) tRCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) ¡tRCC_PLLCFGR_PLL2FRACEN_Pos (4U) ¢tRCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) £tRCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk ¤tRCC_PLLCFGR_PLL2VCOSEL_Pos (5U) ¥tRCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) ¦tRCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk §tRCC_PLLCFGR_PLL2RGE_Pos (6U) ¨tRCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) ©tRCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk ªtRCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) «tRCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) ¬tRCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) tRCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) ¯tRCC_PLLCFGR_PLL3FRACEN_Pos (8U) °tRCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) ±tRCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk ²tRCC_PLLCFGR_PLL3VCOSEL_Pos (9U) ³tRCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) ´tRCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk µtRCC_PLLCFGR_PLL3RGE_Pos (10U) ¶tRCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) ·tRCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk ¸tRCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) ¹tRCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) ºtRCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) »tRCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) ½tRCC_PLLCFGR_DIVP1EN_Pos (16U) ¾tRCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) ¿tRCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk ÀtRCC_PLLCFGR_DIVQ1EN_Pos (17U) ÁtRCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) ÂtRCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk ÃtRCC_PLLCFGR_DIVR1EN_Pos (18U) ÄtRCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) ÅtRCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk ÇtRCC_PLLCFGR_DIVP2EN_Pos (19U) ÈtRCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) ÉtRCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk ÊtRCC_PLLCFGR_DIVQ2EN_Pos (20U) ËtRCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) ÌtRCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk ÍtRCC_PLLCFGR_DIVR2EN_Pos (21U) ÎtRCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) ÏtRCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk ÑtRCC_PLLCFGR_DIVP3EN_Pos (22U) ÒtRCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) ÓtRCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk ÔtRCC_PLLCFGR_DIVQ3EN_Pos (23U) ÕtRCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) ÖtRCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk ×tRCC_PLLCFGR_DIVR3EN_Pos (24U) ØtRCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) ÙtRCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk ÝtRCC_PLL1DIVR_N1_Pos (0U) ÞtRCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) ßtRCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk àtRCC_PLL1DIVR_P1_Pos (9U) átRCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) âtRCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk ãtRCC_PLL1DIVR_Q1_Pos (16U) ätRCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) åtRCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk ætRCC_PLL1DIVR_R1_Pos (24U) çtRCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) ètRCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk ëtRCC_PLL1FRACR_FRACN1_Pos (3U) ìtRCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) ítRCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk ðtRCC_PLL2DIVR_N2_Pos (0U) ñtRCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) òtRCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk ótRCC_PLL2DIVR_P2_Pos (9U) ôtRCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) õtRCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk ötRCC_PLL2DIVR_Q2_Pos (16U) ÷tRCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) øtRCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk ùtRCC_PLL2DIVR_R2_Pos (24U) útRCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) ûtRCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk þtRCC_PLL2FRACR_FRACN2_Pos (3U) ÿtRCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) uRCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk uRCC_PLL3DIVR_N3_Pos (0U) uRCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
uRCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk uRCC_PLL3DIVR_P3_Pos (9U) uRCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) uRCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk uRCC_PLL3DIVR_Q3_Pos (16U) uRCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) uRCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk uRCC_PLL3DIVR_R3_Pos (24U) uRCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) uRCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk uRCC_PLL3FRACR_FRACN3_Pos (3U) uRCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) uRCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk uRCC_D1CCIPR_FMCSEL_Pos (0U) uRCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) uRCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk uRCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) uRCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) uRCC_D1CCIPR_QSPISEL_Pos (4U) uRCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) uRCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk uRCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) uRCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) uRCC_D1CCIPR_SDMMCSEL_Pos (16U) ¡uRCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) ¢uRCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk £uRCC_D1CCIPR_CKPERSEL_Pos (28U) ¤uRCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) ¥uRCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk ¦uRCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) §uRCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) ªuRCC_D2CCIP1R_SAI1SEL_Pos (0U) «uRCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) ¬uRCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk uRCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) ®uRCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) ¯uRCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) ±uRCC_D2CCIP1R_SAI23SEL_Pos (6U) ²uRCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) ³uRCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk ´uRCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) µuRCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) ¶uRCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) ¸uRCC_D2CCIP1R_SPI123SEL_Pos (12U) ¹uRCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) ºuRCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk »uRCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) ¼uRCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) ½uRCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) ¿uRCC_D2CCIP1R_SPI45SEL_Pos (16U) ÀuRCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) ÁuRCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk ÂuRCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) ÃuRCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) ÄuRCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) ÆuRCC_D2CCIP1R_SPDIFSEL_Pos (20U) ÇuRCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) ÈuRCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk ÉuRCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) ÊuRCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) ÌuRCC_D2CCIP1R_DFSDM1SEL_Pos (24U) ÍuRCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) ÎuRCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk ÐuRCC_D2CCIP1R_FDCANSEL_Pos (28U) ÑuRCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) ÒuRCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk ÓuRCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) ÔuRCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) ÖuRCC_D2CCIP1R_SWPSEL_Pos (31U) ×uRCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) ØuRCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk ÛuRCC_D2CCIP2R_USART16SEL_Pos (3U) ÜuRCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) ÝuRCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk ÞuRCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) ßuRCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) àuRCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) âuRCC_D2CCIP2R_USART28SEL_Pos (0U) ãuRCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) äuRCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk åuRCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) æuRCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) çuRCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) éuRCC_D2CCIP2R_RNGSEL_Pos (8U) êuRCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) ëuRCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk ìuRCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) íuRCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) ïuRCC_D2CCIP2R_I2C123SEL_Pos (12U) ðuRCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) ñuRCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk òuRCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) óuRCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) õuRCC_D2CCIP2R_USBSEL_Pos (20U) öuRCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) ÷uRCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk øuRCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) ùuRCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) ûuRCC_D2CCIP2R_CECSEL_Pos (22U) üuRCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) ýuRCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk þuRCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) ÿuRCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) vRCC_D2CCIP2R_LPTIM1SEL_Pos (28U) vRCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) vRCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk vRCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
vRCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) vRCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) vRCC_D3CCIPR_LPUART1SEL_Pos (0U) vRCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) vRCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk vRCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) vRCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) vRCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) vRCC_D3CCIPR_I2C4SEL_Pos (8U) vRCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) vRCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk vRCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) vRCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) vRCC_D3CCIPR_LPTIM2SEL_Pos (10U) vRCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) vRCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk vRCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) vRCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) vRCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) vRCC_D3CCIPR_LPTIM345SEL_Pos (13U) vRCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) vRCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk vRCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) ¡vRCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) ¢vRCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) ¤vRCC_D3CCIPR_SAI4ASEL_Pos (21U) ¥vRCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) ¦vRCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk §vRCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) ¨vRCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) ©vRCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) «vRCC_D3CCIPR_SAI4BSEL_Pos (24U) ¬vRCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) vRCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk ®vRCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) ¯vRCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) °vRCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) ²vRCC_D3CCIPR_ADCSEL_Pos (16U) ³vRCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) ´vRCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk µvRCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) ¶vRCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) ¸vRCC_D3CCIPR_SPI6SEL_Pos (28U) ¹vRCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) ºvRCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk »vRCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) ¼vRCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) ½vRCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) ¿vRCC_CIER_LSIRDYIE_Pos (0U) ÀvRCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) ÁvRCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk ÂvRCC_CIER_LSERDYIE_Pos (1U) ÃvRCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) ÄvRCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk ÅvRCC_CIER_HSIRDYIE_Pos (2U) ÆvRCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) ÇvRCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk ÈvRCC_CIER_HSERDYIE_Pos (3U) ÉvRCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) ÊvRCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk ËvRCC_CIER_CSIRDYIE_Pos (4U) ÌvRCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) ÍvRCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk ÎvRCC_CIER_HSI48RDYIE_Pos (5U) ÏvRCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) ÐvRCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk ÑvRCC_CIER_PLL1RDYIE_Pos (6U) ÒvRCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) ÓvRCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk ÔvRCC_CIER_PLL2RDYIE_Pos (7U) ÕvRCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) ÖvRCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk ×vRCC_CIER_PLL3RDYIE_Pos (8U) ØvRCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) ÙvRCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk ÚvRCC_CIER_LSECSSIE_Pos (9U) ÛvRCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) ÜvRCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk ßvRCC_CIFR_LSIRDYF_Pos (0U) àvRCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) ávRCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk âvRCC_CIFR_LSERDYF_Pos (1U) ãvRCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) ävRCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk åvRCC_CIFR_HSIRDYF_Pos (2U) ævRCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) çvRCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk èvRCC_CIFR_HSERDYF_Pos (3U) évRCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) êvRCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk ëvRCC_CIFR_CSIRDYF_Pos (4U) ìvRCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) ívRCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk îvRCC_CIFR_HSI48RDYF_Pos (5U) ïvRCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) ðvRCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk ñvRCC_CIFR_PLLRDYF_Pos (6U) òvRCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) óvRCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk ôvRCC_CIFR_PLL2RDYF_Pos (7U) õvRCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) övRCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk ÷vRCC_CIFR_PLL3RDYF_Pos (8U) øvRCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) ùvRCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk úvRCC_CIFR_LSECSSF_Pos (9U) ûvRCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) üvRCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk ývRCC_CIFR_HSECSSF_Pos (10U) þvRCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) ÿvRCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk wRCC_CICR_LSIRDYC_Pos (0U) wRCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) wRCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
wRCC_CICR_LSERDYC_Pos (1U) wRCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) wRCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk wRCC_CICR_HSIRDYC_Pos (2U) wRCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) wRCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk wRCC_CICR_HSERDYC_Pos (3U) wRCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) wRCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk wRCC_CICR_CSIRDYC_Pos (4U) wRCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) wRCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk wRCC_CICR_HSI48RDYC_Pos (5U) wRCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) wRCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk wRCC_CICR_PLLRDYC_Pos (6U) wRCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) wRCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk wRCC_CICR_PLL2RDYC_Pos (7U) wRCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) wRCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk wRCC_CICR_PLL3RDYC_Pos (8U) wRCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) wRCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk wRCC_CICR_LSECSSC_Pos (9U) wRCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) wRCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk wRCC_CICR_HSECSSC_Pos (10U) ¡wRCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) ¢wRCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk ¥wRCC_BDCR_LSEON_Pos (0U) ¦wRCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) §wRCC_BDCR_LSEON RCC_BDCR_LSEON_Msk ¨wRCC_BDCR_LSERDY_Pos (1U) ©wRCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) ªwRCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk «wRCC_BDCR_LSEBYP_Pos (2U) ¬wRCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) wRCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk ¯wRCC_BDCR_LSEDRV_Pos (3U) °wRCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) ±wRCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk ²wRCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) ³wRCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) µwRCC_BDCR_LSECSSON_Pos (5U) ¶wRCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) ·wRCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk ¸wRCC_BDCR_LSECSSD_Pos (6U) ¹wRCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) ºwRCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk ¼wRCC_BDCR_RTCSEL_Pos (8U) ½wRCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) ¾wRCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk ¿wRCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) ÀwRCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) ÂwRCC_BDCR_RTCEN_Pos (15U) ÃwRCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) ÄwRCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk ÅwRCC_BDCR_BDRST_Pos (16U) ÆwRCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) ÇwRCC_BDCR_BDRST RCC_BDCR_BDRST_Msk ÉwRCC_CSR_LSION_Pos (0U) ÊwRCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) ËwRCC_CSR_LSION RCC_CSR_LSION_Msk ÌwRCC_CSR_LSIRDY_Pos (1U) ÍwRCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) ÎwRCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk ÒwRCC_AHB3ENR_MDMAEN_Pos (0U) ÓwRCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) ÔwRCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk ÕwRCC_AHB3ENR_DMA2DEN_Pos (4U) ÖwRCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) ×wRCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk ØwRCC_AHB3ENR_JPGDECEN_Pos (5U) ÙwRCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) ÚwRCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk ÛwRCC_AHB3ENR_FMCEN_Pos (12U) ÜwRCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) ÝwRCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk ÞwRCC_AHB3ENR_QSPIEN_Pos (14U) ßwRCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) àwRCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk áwRCC_AHB3ENR_SDMMC1EN_Pos (16U) âwRCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) ãwRCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk æwRCC_AHB1ENR_DMA1EN_Pos (0U) çwRCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) èwRCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk éwRCC_AHB1ENR_DMA2EN_Pos (1U) êwRCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) ëwRCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk ìwRCC_AHB1ENR_ADC12EN_Pos (5U) íwRCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) îwRCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk ïwRCC_AHB1ENR_ETH1MACEN_Pos (15U) ðwRCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) ñwRCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk òwRCC_AHB1ENR_ETH1TXEN_Pos (16U) ówRCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) ôwRCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk õwRCC_AHB1ENR_ETH1RXEN_Pos (17U) öwRCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) ÷wRCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk øwRCC_AHB1ENR_USB1OTGHSEN_Pos (25U) ùwRCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) úwRCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk ûwRCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U) üwRCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) ýwRCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk þwRCC_AHB1ENR_USB2OTGFSEN_Pos (27U) ÿwRCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) xRCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk xRCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U) xRCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) xRCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk xRCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos xRCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk xRCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN xRCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos xRCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk xRCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN xRCC_AHB2ENR_DCMIEN_Pos (0U) xRCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) xRCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk xRCC_AHB2ENR_RNGEN_Pos (6U) xRCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) xRCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk xRCC_AHB2ENR_SDMMC2EN_Pos (9U) xRCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) xRCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk xRCC_AHB2ENR_SRAM1EN_Pos (29U) xRCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) xRCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk xRCC_AHB2ENR_SRAM2EN_Pos (30U) xRCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) xRCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk xRCC_AHB2ENR_SRAM3EN_Pos (31U) xRCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) xRCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk £xRCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos ¤xRCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk ¥xRCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN ¦xRCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos §xRCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk ¨xRCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN ©xRCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos ªxRCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk «xRCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN ®xRCC_AHB4ENR_GPIOAEN_Pos (0U) ¯xRCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) °xRCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk ±xRCC_AHB4ENR_GPIOBEN_Pos (1U) ²xRCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) ³xRCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk ´xRCC_AHB4ENR_GPIOCEN_Pos (2U) µxRCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) ¶xRCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk ·xRCC_AHB4ENR_GPIODEN_Pos (3U) ¸xRCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) ¹xRCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk ºxRCC_AHB4ENR_GPIOEEN_Pos (4U) »xRCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) ¼xRCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk ½xRCC_AHB4ENR_GPIOFEN_Pos (5U) ¾xRCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) ¿xRCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk ÀxRCC_AHB4ENR_GPIOGEN_Pos (6U) ÁxRCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) ÂxRCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk ÃxRCC_AHB4ENR_GPIOHEN_Pos (7U) ÄxRCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) ÅxRCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk ÆxRCC_AHB4ENR_GPIOIEN_Pos (8U) ÇxRCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) ÈxRCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk ÉxRCC_AHB4ENR_GPIOJEN_Pos (9U) ÊxRCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) ËxRCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk ÌxRCC_AHB4ENR_GPIOKEN_Pos (10U) ÍxRCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) ÎxRCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk ÏxRCC_AHB4ENR_CRCEN_Pos (19U) ÐxRCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) ÑxRCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk ÒxRCC_AHB4ENR_BDMAEN_Pos (21U) ÓxRCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) ÔxRCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk ÕxRCC_AHB4ENR_ADC3EN_Pos (24U) ÖxRCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) ×xRCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk ØxRCC_AHB4ENR_HSEMEN_Pos (25U) ÙxRCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) ÚxRCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk ÛxRCC_AHB4ENR_BKPRAMEN_Pos (28U) ÜxRCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) ÝxRCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk àxRCC_APB3ENR_LTDCEN_Pos (3U) áxRCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) âxRCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk ãxRCC_APB3ENR_WWDG1EN_Pos (6U) äxRCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) åxRCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk éxRCC_APB1LENR_TIM2EN_Pos (0U) êxRCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) ëxRCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk ìxRCC_APB1LENR_TIM3EN_Pos (1U) íxRCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) îxRCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk ïxRCC_APB1LENR_TIM4EN_Pos (2U) ðxRCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) ñxRCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk òxRCC_APB1LENR_TIM5EN_Pos (3U) óxRCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) ôxRCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk õxRCC_APB1LENR_TIM6EN_Pos (4U) öxRCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) ÷xRCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk øxRCC_APB1LENR_TIM7EN_Pos (5U) ùxRCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) úxRCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk ûxRCC_APB1LENR_TIM12EN_Pos (6U) üxRCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) ýxRCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk þxRCC_APB1LENR_TIM13EN_Pos (7U) ÿxRCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) yRCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk yRCC_APB1LENR_TIM14EN_Pos (8U) yRCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) yRCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk yRCC_APB1LENR_LPTIM1EN_Pos (9U)
yRCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) yRCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk yRCC_APB1LENR_SPI2EN_Pos (14U) yRCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) yRCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk yRCC_APB1LENR_SPI3EN_Pos (15U) yRCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) yRCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk yRCC_APB1LENR_SPDIFRXEN_Pos (16U) yRCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) yRCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk yRCC_APB1LENR_USART2EN_Pos (17U) yRCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) yRCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk yRCC_APB1LENR_USART3EN_Pos (18U) yRCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) yRCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk yRCC_APB1LENR_UART4EN_Pos (19U) yRCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) yRCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk yRCC_APB1LENR_UART5EN_Pos (20U) yRCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) yRCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk yRCC_APB1LENR_I2C1EN_Pos (21U) yRCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) yRCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk ¡yRCC_APB1LENR_I2C2EN_Pos (22U) ¢yRCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) £yRCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk ¤yRCC_APB1LENR_I2C3EN_Pos (23U) ¥yRCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) ¦yRCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk §yRCC_APB1LENR_CECEN_Pos (27U) ¨yRCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) ©yRCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk ªyRCC_APB1LENR_DAC12EN_Pos (29U) «yRCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) ¬yRCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk yRCC_APB1LENR_UART7EN_Pos (30U) ®yRCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) ¯yRCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk °yRCC_APB1LENR_UART8EN_Pos (31U) ±yRCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) ²yRCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk µyRCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos ¶yRCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk ·yRCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN ¹yRCC_APB1HENR_CRSEN_Pos (1U) ºyRCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) »yRCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk ¼yRCC_APB1HENR_SWPMIEN_Pos (2U) ½yRCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) ¾yRCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk ¿yRCC_APB1HENR_OPAMPEN_Pos (4U) ÀyRCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) ÁyRCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk ÂyRCC_APB1HENR_MDIOSEN_Pos (5U) ÃyRCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) ÄyRCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk ÅyRCC_APB1HENR_FDCANEN_Pos (8U) ÆyRCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) ÇyRCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk ÊyRCC_APB2ENR_TIM1EN_Pos (0U) ËyRCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) ÌyRCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk ÍyRCC_APB2ENR_TIM8EN_Pos (1U) ÎyRCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) ÏyRCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk ÐyRCC_APB2ENR_USART1EN_Pos (4U) ÑyRCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) ÒyRCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk ÓyRCC_APB2ENR_USART6EN_Pos (5U) ÔyRCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) ÕyRCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk ÖyRCC_APB2ENR_SPI1EN_Pos (12U) ×yRCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) ØyRCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk ÙyRCC_APB2ENR_SPI4EN_Pos (13U) ÚyRCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) ÛyRCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk ÜyRCC_APB2ENR_TIM15EN_Pos (16U) ÝyRCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) ÞyRCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk ßyRCC_APB2ENR_TIM16EN_Pos (17U) àyRCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) áyRCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk âyRCC_APB2ENR_TIM17EN_Pos (18U) ãyRCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) äyRCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk åyRCC_APB2ENR_SPI5EN_Pos (20U) æyRCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) çyRCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk èyRCC_APB2ENR_SAI1EN_Pos (22U) éyRCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) êyRCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk ëyRCC_APB2ENR_SAI2EN_Pos (23U) ìyRCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) íyRCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk îyRCC_APB2ENR_SAI3EN_Pos (24U) ïyRCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) ðyRCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk ñyRCC_APB2ENR_DFSDM1EN_Pos (28U) òyRCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) óyRCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk ôyRCC_APB2ENR_HRTIMEN_Pos (29U) õyRCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) öyRCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk ùyRCC_APB4ENR_SYSCFGEN_Pos (1U) úyRCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) ûyRCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk üyRCC_APB4ENR_LPUART1EN_Pos (3U) ýyRCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) þyRCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk ÿyRCC_APB4ENR_SPI6EN_Pos (5U) zRCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) zRCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk zRCC_APB4ENR_I2C4EN_Pos (7U) zRCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) zRCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
zRCC_APB4ENR_LPTIM2EN_Pos (9U) zRCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) zRCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk zRCC_APB4ENR_LPTIM3EN_Pos (10U) zRCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) zRCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk zRCC_APB4ENR_LPTIM4EN_Pos (11U) zRCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) zRCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk zRCC_APB4ENR_LPTIM5EN_Pos (12U) zRCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) zRCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk zRCC_APB4ENR_COMP12EN_Pos (14U) zRCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) zRCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk zRCC_APB4ENR_VREFEN_Pos (15U) zRCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) zRCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk zRCC_APB4ENR_RTCAPBEN_Pos (16U) zRCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) zRCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk zRCC_APB4ENR_SAI4EN_Pos (21U) zRCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) zRCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk zRCC_AHB3RSTR_MDMARST_Pos (0U) ¡zRCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) ¢zRCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk £zRCC_AHB3RSTR_DMA2DRST_Pos (4U) ¤zRCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) ¥zRCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk ¦zRCC_AHB3RSTR_JPGDECRST_Pos (5U) §zRCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) ¨zRCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk ©zRCC_AHB3RSTR_FMCRST_Pos (12U) ªzRCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) «zRCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk ¬zRCC_AHB3RSTR_QSPIRST_Pos (14U) zRCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) ®zRCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk ¯zRCC_AHB3RSTR_SDMMC1RST_Pos (16U) °zRCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) ±zRCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk µzRCC_AHB1RSTR_DMA1RST_Pos (0U) ¶zRCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) ·zRCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk ¸zRCC_AHB1RSTR_DMA2RST_Pos (1U) ¹zRCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) ºzRCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk »zRCC_AHB1RSTR_ADC12RST_Pos (5U) ¼zRCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) ½zRCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk ¾zRCC_AHB1RSTR_ETH1MACRST_Pos (15U) ¿zRCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) ÀzRCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk ÁzRCC_AHB1RSTR_USB1OTGHSRST_Pos (25U) ÂzRCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) ÃzRCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk ÄzRCC_AHB1RSTR_USB2OTGFSRST_Pos (27U) ÅzRCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) ÆzRCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk ÉzRCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos ÊzRCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk ËzRCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST ÎzRCC_AHB2RSTR_DCMIRST_Pos (0U) ÏzRCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) ÐzRCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk ÑzRCC_AHB2RSTR_RNGRST_Pos (6U) ÒzRCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) ÓzRCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk ÔzRCC_AHB2RSTR_SDMMC2RST_Pos (9U) ÕzRCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) ÖzRCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk ÙzRCC_AHB4RSTR_GPIOARST_Pos (0U) ÚzRCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) ÛzRCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk ÜzRCC_AHB4RSTR_GPIOBRST_Pos (1U) ÝzRCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) ÞzRCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk ßzRCC_AHB4RSTR_GPIOCRST_Pos (2U) àzRCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) ázRCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk âzRCC_AHB4RSTR_GPIODRST_Pos (3U) ãzRCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) äzRCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk åzRCC_AHB4RSTR_GPIOERST_Pos (4U) æzRCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) çzRCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk èzRCC_AHB4RSTR_GPIOFRST_Pos (5U) ézRCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) êzRCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk ëzRCC_AHB4RSTR_GPIOGRST_Pos (6U) ìzRCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) ízRCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk îzRCC_AHB4RSTR_GPIOHRST_Pos (7U) ïzRCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) ðzRCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk ñzRCC_AHB4RSTR_GPIOIRST_Pos (8U) òzRCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) ózRCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk ôzRCC_AHB4RSTR_GPIOJRST_Pos (9U) õzRCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) özRCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk ÷zRCC_AHB4RSTR_GPIOKRST_Pos (10U) øzRCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) ùzRCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk úzRCC_AHB4RSTR_CRCRST_Pos (19U) ûzRCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) üzRCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk ýzRCC_AHB4RSTR_BDMARST_Pos (21U) þzRCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) ÿzRCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk {RCC_AHB4RSTR_ADC3RST_Pos (24U) {RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) {RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk {RCC_AHB4RSTR_HSEMRST_Pos (25U) {RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
{RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk {RCC_APB3RSTR_LTDCRST_Pos (3U) {RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) {RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk {RCC_APB1LRSTR_TIM2RST_Pos (0U) {RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) {RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk {RCC_APB1LRSTR_TIM3RST_Pos (1U) {RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) {RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk {RCC_APB1LRSTR_TIM4RST_Pos (2U) {RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) {RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk {RCC_APB1LRSTR_TIM5RST_Pos (3U) {RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) {RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk {RCC_APB1LRSTR_TIM6RST_Pos (4U) {RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) {RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk {RCC_APB1LRSTR_TIM7RST_Pos (5U) {RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) {RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk ¡{RCC_APB1LRSTR_TIM12RST_Pos (6U) ¢{RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) £{RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk ¤{RCC_APB1LRSTR_TIM13RST_Pos (7U) ¥{RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) ¦{RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk §{RCC_APB1LRSTR_TIM14RST_Pos (8U) ¨{RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) ©{RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk ª{RCC_APB1LRSTR_LPTIM1RST_Pos (9U) «{RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) ¬{RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk {RCC_APB1LRSTR_SPI2RST_Pos (14U) ®{RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) ¯{RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk °{RCC_APB1LRSTR_SPI3RST_Pos (15U) ±{RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) ²{RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk ³{RCC_APB1LRSTR_SPDIFRXRST_Pos (16U) ´{RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) µ{RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk ¶{RCC_APB1LRSTR_USART2RST_Pos (17U) ·{RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) ¸{RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk ¹{RCC_APB1LRSTR_USART3RST_Pos (18U) º{RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) »{RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk ¼{RCC_APB1LRSTR_UART4RST_Pos (19U) ½{RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) ¾{RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk ¿{RCC_APB1LRSTR_UART5RST_Pos (20U) À{RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) Á{RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk Â{RCC_APB1LRSTR_I2C1RST_Pos (21U) Ã{RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) Ä{RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk Å{RCC_APB1LRSTR_I2C2RST_Pos (22U) Æ{RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) Ç{RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk È{RCC_APB1LRSTR_I2C3RST_Pos (23U) É{RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) Ê{RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk Ë{RCC_APB1LRSTR_CECRST_Pos (27U) Ì{RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) Í{RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk Î{RCC_APB1LRSTR_DAC12RST_Pos (29U) Ï{RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) Ð{RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk Ñ{RCC_APB1LRSTR_UART7RST_Pos (30U) Ò{RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) Ó{RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk Ô{RCC_APB1LRSTR_UART8RST_Pos (31U) Õ{RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) Ö{RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk Ù{RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos Ú{RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk Û{RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST Ý{RCC_APB1HRSTR_CRSRST_Pos (1U) Þ{RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) ß{RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk à{RCC_APB1HRSTR_SWPMIRST_Pos (2U) á{RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) â{RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk ã{RCC_APB1HRSTR_OPAMPRST_Pos (4U) ä{RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) å{RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk æ{RCC_APB1HRSTR_MDIOSRST_Pos (5U) ç{RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) è{RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk é{RCC_APB1HRSTR_FDCANRST_Pos (8U) ê{RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) ë{RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk î{RCC_APB2RSTR_TIM1RST_Pos (0U) ï{RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) ð{RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk ñ{RCC_APB2RSTR_TIM8RST_Pos (1U) ò{RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) ó{RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk ô{RCC_APB2RSTR_USART1RST_Pos (4U) õ{RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) ö{RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk ÷{RCC_APB2RSTR_USART6RST_Pos (5U) ø{RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) ù{RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk ú{RCC_APB2RSTR_SPI1RST_Pos (12U) û{RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) ü{RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk ý{RCC_APB2RSTR_SPI4RST_Pos (13U) þ{RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) ÿ{RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk |RCC_APB2RSTR_TIM15RST_Pos (16U) |RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) |RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk |RCC_APB2RSTR_TIM16RST_Pos (17U) |RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
|RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk |RCC_APB2RSTR_TIM17RST_Pos (18U) |RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) |RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk |RCC_APB2RSTR_SPI5RST_Pos (20U) |RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) |RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk |RCC_APB2RSTR_SAI1RST_Pos (22U) |RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) |RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk |RCC_APB2RSTR_SAI2RST_Pos (23U) |RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) |RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk |RCC_APB2RSTR_SAI3RST_Pos (24U) |RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) |RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk |RCC_APB2RSTR_DFSDM1RST_Pos (28U) |RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) |RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk |RCC_APB2RSTR_HRTIMRST_Pos (29U) |RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) |RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk |RCC_APB4RSTR_SYSCFGRST_Pos (1U) |RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) |RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk |RCC_APB4RSTR_LPUART1RST_Pos (3U) ¡|RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) ¢|RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk £|RCC_APB4RSTR_SPI6RST_Pos (5U) ¤|RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) ¥|RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk ¦|RCC_APB4RSTR_I2C4RST_Pos (7U) §|RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) ¨|RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk ©|RCC_APB4RSTR_LPTIM2RST_Pos (9U) ª|RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) «|RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk ¬|RCC_APB4RSTR_LPTIM3RST_Pos (10U) |RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) ®|RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk ¯|RCC_APB4RSTR_LPTIM4RST_Pos (11U) °|RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) ±|RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk ²|RCC_APB4RSTR_LPTIM5RST_Pos (12U) ³|RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) ´|RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk µ|RCC_APB4RSTR_COMP12RST_Pos (14U) ¶|RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) ·|RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk ¸|RCC_APB4RSTR_VREFRST_Pos (15U) ¹|RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) º|RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk »|RCC_APB4RSTR_SAI4RST_Pos (21U) ¼|RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) ½|RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk Á|RCC_GCR_WW1RSC_Pos (0U) Â|RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) Ã|RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk Æ|RCC_D3AMR_BDMAAMEN_Pos (0U) Ç|RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) È|RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk É|RCC_D3AMR_LPUART1AMEN_Pos (3U) Ê|RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) Ë|RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk Ì|RCC_D3AMR_SPI6AMEN_Pos (5U) Í|RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) Î|RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk Ï|RCC_D3AMR_I2C4AMEN_Pos (7U) Ð|RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) Ñ|RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk Ò|RCC_D3AMR_LPTIM2AMEN_Pos (9U) Ó|RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) Ô|RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk Õ|RCC_D3AMR_LPTIM3AMEN_Pos (10U) Ö|RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) ×|RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk Ø|RCC_D3AMR_LPTIM4AMEN_Pos (11U) Ù|RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) Ú|RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk Û|RCC_D3AMR_LPTIM5AMEN_Pos (12U) Ü|RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) Ý|RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk Þ|RCC_D3AMR_COMP12AMEN_Pos (14U) ß|RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) à|RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk á|RCC_D3AMR_VREFAMEN_Pos (15U) â|RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) ã|RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk ä|RCC_D3AMR_RTCAMEN_Pos (16U) å|RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) æ|RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk ç|RCC_D3AMR_CRCAMEN_Pos (19U) è|RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) é|RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk ê|RCC_D3AMR_SAI4AMEN_Pos (21U) ë|RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) ì|RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk í|RCC_D3AMR_ADC3AMEN_Pos (24U) î|RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) ï|RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk ò|RCC_D3AMR_BKPRAMAMEN_Pos (28U) ó|RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) ô|RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk õ|RCC_D3AMR_SRAM4AMEN_Pos (29U) ö|RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) ÷|RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk ù|RCC_AHB3LPENR_MDMALPEN_Pos (0U) ú|RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) û|RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk ü|RCC_AHB3LPENR_DMA2DLPEN_Pos (4U) ý|RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) þ|RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk ÿ|RCC_AHB3LPENR_JPGDECLPEN_Pos (5U) }RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) }RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk }RCC_AHB3LPENR_FLASHLPEN_Pos (8U) }RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) }RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
}RCC_AHB3LPENR_FMCLPEN_Pos (12U) }RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) }RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk }RCC_AHB3LPENR_QSPILPEN_Pos (14U) }RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) }RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk }RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U) }RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) }RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk }RCC_AHB3LPENR_DTCM1LPEN_Pos (28U) }RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) }RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk }RCC_AHB3LPENR_DTCM2LPEN_Pos (29U) }RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) }RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk }RCC_AHB3LPENR_ITCMLPEN_Pos (30U) }RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) }RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk }RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U) }RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) }RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk }RCC_AHB1LPENR_DMA1LPEN_Pos (0U) }RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) }RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk }RCC_AHB1LPENR_DMA2LPEN_Pos (1U) ¡}RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) ¢}RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk £}RCC_AHB1LPENR_ADC12LPEN_Pos (5U) ¤}RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) ¥}RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk ¦}RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) §}RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) ¨}RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk ©}RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) ª}RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) «}RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk ¬}RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) }RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) ®}RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk ¯}RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U) °}RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) ±}RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk ²}RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U) ³}RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) ´}RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk µ}RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U) ¶}RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) ·}RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk ¸}RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U) ¹}RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) º}RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk ½}RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos ¾}RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk ¿}RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN À}RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos Á}RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk Â}RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN Å}RCC_AHB2LPENR_DCMILPEN_Pos (0U) Æ}RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) Ç}RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk È}RCC_AHB2LPENR_RNGLPEN_Pos (6U) É}RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) Ê}RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk Ë}RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) Ì}RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) Í}RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk Î}RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) Ï}RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) Ð}RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk Ñ}RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) Ò}RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) Ó}RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk Ô}RCC_AHB2LPENR_SRAM3LPEN_Pos (31U) Õ}RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) Ö}RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk Ù}RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos Ú}RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk Û}RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN Ü}RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos Ý}RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk Þ}RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN ß}RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos à}RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk á}RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN ä}RCC_AHB4LPENR_GPIOALPEN_Pos (0U) å}RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) æ}RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk ç}RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) è}RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) é}RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk ê}RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) ë}RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) ì}RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk í}RCC_AHB4LPENR_GPIODLPEN_Pos (3U) î}RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) ï}RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk ð}RCC_AHB4LPENR_GPIOELPEN_Pos (4U) ñ}RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) ò}RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk ó}RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) ô}RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) õ}RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk ö}RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) ÷}RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) ø}RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk ù}RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) ú}RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) û}RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk ü}RCC_AHB4LPENR_GPIOILPEN_Pos (8U) ý}RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) þ}RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk ÿ}RCC_AHB4LPENR_GPIOJLPEN_Pos (9U) ~RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) ~RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk ~RCC_AHB4LPENR_GPIOKLPEN_Pos (10U) ~RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) ~RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
~RCC_AHB4LPENR_CRCLPEN_Pos (19U) ~RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) ~RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk ~RCC_AHB4LPENR_BDMALPEN_Pos (21U) ~RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) ~RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk ~RCC_AHB4LPENR_ADC3LPEN_Pos (24U) ~RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) ~RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk ~RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) ~RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) ~RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk ~RCC_AHB4LPENR_SRAM4LPEN_Pos (29U) ~RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) ~RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk ~RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos ~RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk ~RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN ~RCC_APB3LPENR_LTDCLPEN_Pos (3U) ~RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) ~RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk ~RCC_APB3LPENR_WWDG1LPEN_Pos (6U) ~RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) ~RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk £~RCC_APB1LLPENR_TIM2LPEN_Pos (0U) ¤~RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) ¥~RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk ¦~RCC_APB1LLPENR_TIM3LPEN_Pos (1U) §~RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) ¨~RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk ©~RCC_APB1LLPENR_TIM4LPEN_Pos (2U) ª~RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) «~RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk ¬~RCC_APB1LLPENR_TIM5LPEN_Pos (3U) ~RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) ®~RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk ¯~RCC_APB1LLPENR_TIM6LPEN_Pos (4U) °~RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) ±~RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk ²~RCC_APB1LLPENR_TIM7LPEN_Pos (5U) ³~RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) ´~RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk µ~RCC_APB1LLPENR_TIM12LPEN_Pos (6U) ¶~RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) ·~RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk ¸~RCC_APB1LLPENR_TIM13LPEN_Pos (7U) ¹~RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) º~RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk »~RCC_APB1LLPENR_TIM14LPEN_Pos (8U) ¼~RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) ½~RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk ¾~RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U) ¿~RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) À~RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk Ã~RCC_APB1LLPENR_SPI2LPEN_Pos (14U) Ä~RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) Å~RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk Æ~RCC_APB1LLPENR_SPI3LPEN_Pos (15U) Ç~RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) È~RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk É~RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U) Ê~RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) Ë~RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk Ì~RCC_APB1LLPENR_USART2LPEN_Pos (17U) Í~RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) Î~RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk Ï~RCC_APB1LLPENR_USART3LPEN_Pos (18U) Ð~RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) Ñ~RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk Ò~RCC_APB1LLPENR_UART4LPEN_Pos (19U) Ó~RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) Ô~RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk Õ~RCC_APB1LLPENR_UART5LPEN_Pos (20U) Ö~RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) ×~RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk Ø~RCC_APB1LLPENR_I2C1LPEN_Pos (21U) Ù~RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) Ú~RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk Û~RCC_APB1LLPENR_I2C2LPEN_Pos (22U) Ü~RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) Ý~RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk Þ~RCC_APB1LLPENR_I2C3LPEN_Pos (23U) ß~RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) à~RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk á~RCC_APB1LLPENR_CECLPEN_Pos (27U) â~RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) ã~RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk ä~RCC_APB1LLPENR_DAC12LPEN_Pos (29U) å~RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) æ~RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk ç~RCC_APB1LLPENR_UART7LPEN_Pos (30U) è~RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) é~RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk ê~RCC_APB1LLPENR_UART8LPEN_Pos (31U) ë~RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) ì~RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk ï~RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos ð~RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk ñ~RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN ó~RCC_APB1HLPENR_CRSLPEN_Pos (1U) ô~RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) õ~RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk ö~RCC_APB1HLPENR_SWPMILPEN_Pos (2U) ÷~RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) ø~RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk ù~RCC_APB1HLPENR_OPAMPLPEN_Pos (4U) ú~RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) û~RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk ü~RCC_APB1HLPENR_MDIOSLPEN_Pos (5U) ý~RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) þ~RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk ÿ~RCC_APB1HLPENR_FDCANLPEN_Pos (8U) RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk RCC_APB2LPENR_TIM1LPEN_Pos (0U)
RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk RCC_APB2LPENR_TIM8LPEN_Pos (1U) RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk RCC_APB2LPENR_USART1LPEN_Pos (4U) RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk RCC_APB2LPENR_USART6LPEN_Pos (5U) RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk RCC_APB2LPENR_SPI1LPEN_Pos (12U) RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk RCC_APB2LPENR_SPI4LPEN_Pos (13U) RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk RCC_APB2LPENR_TIM15LPEN_Pos (16U) RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk RCC_APB2LPENR_TIM16LPEN_Pos (17U) RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk RCC_APB2LPENR_TIM17LPEN_Pos (18U) RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk RCC_APB2LPENR_SPI5LPEN_Pos (20U) RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) ¡RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk ¢RCC_APB2LPENR_SAI1LPEN_Pos (22U) £RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) ¤RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk ¥RCC_APB2LPENR_SAI2LPEN_Pos (23U) ¦RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) §RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk ¨RCC_APB2LPENR_SAI3LPEN_Pos (24U) ©RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) ªRCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk «RCC_APB2LPENR_DFSDM1LPEN_Pos (28U) ¬RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk ®RCC_APB2LPENR_HRTIMLPEN_Pos (29U) ¯RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) °RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk ³RCC_APB4LPENR_SYSCFGLPEN_Pos (1U) ´RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) µRCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk ¶RCC_APB4LPENR_LPUART1LPEN_Pos (3U) ·RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) ¸RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk ¹RCC_APB4LPENR_SPI6LPEN_Pos (5U) ºRCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) »RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk ¼RCC_APB4LPENR_I2C4LPEN_Pos (7U) ½RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) ¾RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk ¿RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) ÀRCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) ÁRCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk ÂRCC_APB4LPENR_LPTIM3LPEN_Pos (10U) ÃRCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) ÄRCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk ÅRCC_APB4LPENR_LPTIM4LPEN_Pos (11U) ÆRCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) ÇRCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk ÈRCC_APB4LPENR_LPTIM5LPEN_Pos (12U) ÉRCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) ÊRCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk ËRCC_APB4LPENR_COMP12LPEN_Pos (14U) ÌRCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) ÍRCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk ÎRCC_APB4LPENR_VREFLPEN_Pos (15U) ÏRCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) ÐRCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk ÑRCC_APB4LPENR_RTCAPBLPEN_Pos (16U) ÒRCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) ÓRCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk ÔRCC_APB4LPENR_SAI4LPEN_Pos (21U) ÕRCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) ÖRCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk ÚRCC_RSR_RMVF_Pos (16U) ÛRCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) ÜRCC_RSR_RMVF RCC_RSR_RMVF_Msk ÝRCC_RSR_CPURSTF_Pos (17U) ÞRCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos) ßRCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk àRCC_RSR_D1RSTF_Pos (19U) áRCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) âRCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk ãRCC_RSR_D2RSTF_Pos (20U) äRCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) åRCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk æRCC_RSR_BORRSTF_Pos (21U) çRCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) èRCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk éRCC_RSR_PINRSTF_Pos (22U) êRCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) ëRCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk ìRCC_RSR_PORRSTF_Pos (23U) íRCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) îRCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk ïRCC_RSR_SFTRSTF_Pos (24U) ðRCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) ñRCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk òRCC_RSR_IWDG1RSTF_Pos (26U) óRCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) ôRCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk õRCC_RSR_WWDG1RSTF_Pos (28U) öRCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) ÷RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk ùRCC_RSR_LPWRRSTF_Pos (30U) úRCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) ûRCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk RNG_CR_RNGEN_Pos (2U)
RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) RNG_CR_RNGEN RNG_CR_RNGEN_Msk RNG_CR_IE_Pos (3U) RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) RNG_CR_IE RNG_CR_IE_Msk RNG_CR_CED_Pos (5U) RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) RNG_CR_CED RNG_CR_CED_Msk RNG_SR_DRDY_Pos (0U) RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) RNG_SR_DRDY RNG_SR_DRDY_Msk RNG_SR_CECS_Pos (1U) RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) RNG_SR_CECS RNG_SR_CECS_Msk RNG_SR_SECS_Pos (2U) RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) RNG_SR_SECS RNG_SR_SECS_Msk RNG_SR_CEIS_Pos (5U) RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) RNG_SR_CEIS RNG_SR_CEIS_Msk RNG_SR_SEIS_Pos (6U) RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) RNG_SR_SEIS RNG_SR_SEIS_Msk ¤RTC_TAMPER2_SUPPORT ¥RTC_TAMPNOERASE_SUPPORT ¦RTC_TAMPMASKFLAG_SUPPORT §RTC_TAMPxIE_SUPPORT ªRTC_TR_PM_Pos (22U) «RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) ¬RTC_TR_PM RTC_TR_PM_Msk RTC_TR_HT_Pos (20U) ®RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) ¯RTC_TR_HT RTC_TR_HT_Msk °RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) ±RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) ²RTC_TR_HU_Pos (16U) ³RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) ´RTC_TR_HU RTC_TR_HU_Msk µRTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) ¶RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) ·RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) ¸RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) ¹RTC_TR_MNT_Pos (12U) ºRTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) »RTC_TR_MNT RTC_TR_MNT_Msk ¼RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) ½RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) ¾RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) ¿RTC_TR_MNU_Pos (8U) ÀRTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) ÁRTC_TR_MNU RTC_TR_MNU_Msk ÂRTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) ÃRTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) ÄRTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) ÅRTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) ÆRTC_TR_ST_Pos (4U) ÇRTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) ÈRTC_TR_ST RTC_TR_ST_Msk ÉRTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) ÊRTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) ËRTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) ÌRTC_TR_SU_Pos (0U) ÍRTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) ÎRTC_TR_SU RTC_TR_SU_Msk ÏRTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) ÐRTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) ÑRTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) ÒRTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) ÕRTC_DR_YT_Pos (20U) ÖRTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) ×RTC_DR_YT RTC_DR_YT_Msk ØRTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) ÙRTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) ÚRTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) ÛRTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) ÜRTC_DR_YU_Pos (16U) ÝRTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) ÞRTC_DR_YU RTC_DR_YU_Msk ßRTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) àRTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) áRTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) âRTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) ãRTC_DR_WDU_Pos (13U) äRTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) åRTC_DR_WDU RTC_DR_WDU_Msk æRTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) çRTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) èRTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) éRTC_DR_MT_Pos (12U) êRTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) ëRTC_DR_MT RTC_DR_MT_Msk ìRTC_DR_MU_Pos (8U) íRTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) îRTC_DR_MU RTC_DR_MU_Msk ïRTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) ðRTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) ñRTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) òRTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) óRTC_DR_DT_Pos (4U) ôRTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) õRTC_DR_DT RTC_DR_DT_Msk öRTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) ÷RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) øRTC_DR_DU_Pos (0U) ùRTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) úRTC_DR_DU RTC_DR_DU_Msk ûRTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) üRTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) ýRTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) þRTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) RTC_CR_ITSE_Pos (24U) RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) RTC_CR_ITSE RTC_CR_ITSE_Msk RTC_CR_COE_Pos (23U)
RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) RTC_CR_COE RTC_CR_COE_Msk RTC_CR_OSEL_Pos (21U) RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) RTC_CR_OSEL RTC_CR_OSEL_Msk RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) RTC_CR_POL_Pos (20U) RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) RTC_CR_POL RTC_CR_POL_Msk RTC_CR_COSEL_Pos (19U) RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) RTC_CR_COSEL RTC_CR_COSEL_Msk RTC_CR_BKP_Pos (18U) RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) RTC_CR_BKP RTC_CR_BKP_Msk RTC_CR_SUB1H_Pos (17U) RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) RTC_CR_SUB1H RTC_CR_SUB1H_Msk RTC_CR_ADD1H_Pos (16U) RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) RTC_CR_ADD1H RTC_CR_ADD1H_Msk RTC_CR_TSIE_Pos (15U) RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) RTC_CR_TSIE RTC_CR_TSIE_Msk RTC_CR_WUTIE_Pos (14U) RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) RTC_CR_WUTIE RTC_CR_WUTIE_Msk ¡RTC_CR_ALRBIE_Pos (13U) ¢RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) £RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk ¤RTC_CR_ALRAIE_Pos (12U) ¥RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) ¦RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk §RTC_CR_TSE_Pos (11U) ¨RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) ©RTC_CR_TSE RTC_CR_TSE_Msk ªRTC_CR_WUTE_Pos (10U) «RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) ¬RTC_CR_WUTE RTC_CR_WUTE_Msk RTC_CR_ALRBE_Pos (9U) ®RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) ¯RTC_CR_ALRBE RTC_CR_ALRBE_Msk °RTC_CR_ALRAE_Pos (8U) ±RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) ²RTC_CR_ALRAE RTC_CR_ALRAE_Msk ³RTC_CR_FMT_Pos (6U) ´RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) µRTC_CR_FMT RTC_CR_FMT_Msk ¶RTC_CR_BYPSHAD_Pos (5U) ·RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) ¸RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk ¹RTC_CR_REFCKON_Pos (4U) ºRTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) »RTC_CR_REFCKON RTC_CR_REFCKON_Msk ¼RTC_CR_TSEDGE_Pos (3U) ½RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) ¾RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk ¿RTC_CR_WUCKSEL_Pos (0U) ÀRTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) ÁRTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk ÂRTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) ÃRTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) ÄRTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) ÇRTC_ISR_ITSF_Pos (17U) ÈRTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) ÉRTC_ISR_ITSF RTC_ISR_ITSF_Msk ÊRTC_ISR_RECALPF_Pos (16U) ËRTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) ÌRTC_ISR_RECALPF RTC_ISR_RECALPF_Msk ÍRTC_ISR_TAMP3F_Pos (15U) ÎRTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) ÏRTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk ÐRTC_ISR_TAMP2F_Pos (14U) ÑRTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) ÒRTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk ÓRTC_ISR_TAMP1F_Pos (13U) ÔRTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) ÕRTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk ÖRTC_ISR_TSOVF_Pos (12U) ×RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) ØRTC_ISR_TSOVF RTC_ISR_TSOVF_Msk ÙRTC_ISR_TSF_Pos (11U) ÚRTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) ÛRTC_ISR_TSF RTC_ISR_TSF_Msk ÜRTC_ISR_WUTF_Pos (10U) ÝRTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) ÞRTC_ISR_WUTF RTC_ISR_WUTF_Msk ßRTC_ISR_ALRBF_Pos (9U) àRTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) áRTC_ISR_ALRBF RTC_ISR_ALRBF_Msk âRTC_ISR_ALRAF_Pos (8U) ãRTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) äRTC_ISR_ALRAF RTC_ISR_ALRAF_Msk åRTC_ISR_INIT_Pos (7U) æRTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) çRTC_ISR_INIT RTC_ISR_INIT_Msk èRTC_ISR_INITF_Pos (6U) éRTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) êRTC_ISR_INITF RTC_ISR_INITF_Msk ëRTC_ISR_RSF_Pos (5U) ìRTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) íRTC_ISR_RSF RTC_ISR_RSF_Msk îRTC_ISR_INITS_Pos (4U) ïRTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) ðRTC_ISR_INITS RTC_ISR_INITS_Msk ñRTC_ISR_SHPF_Pos (3U) òRTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) óRTC_ISR_SHPF RTC_ISR_SHPF_Msk ôRTC_ISR_WUTWF_Pos (2U) õRTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) öRTC_ISR_WUTWF RTC_ISR_WUTWF_Msk ÷RTC_ISR_ALRBWF_Pos (1U) øRTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) ùRTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk úRTC_ISR_ALRAWF_Pos (0U) ûRTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) üRTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk ÿRTC_PRER_PREDIV_A_Pos (16U) RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk RTC_PRER_PREDIV_S_Pos (0U) RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk RTC_WUTR_WUT_Pos (0U) RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) RTC_WUTR_WUT RTC_WUTR_WUT_Msk RTC_ALRMAR_MSK4_Pos (31U) RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk RTC_ALRMAR_WDSEL_Pos (30U) RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk RTC_ALRMAR_DT_Pos (28U) RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) RTC_ALRMAR_DU_Pos (24U) RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) RTC_ALRMAR_MSK3_Pos (23U) RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk ¡RTC_ALRMAR_PM_Pos (22U) ¢RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) £RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk ¤RTC_ALRMAR_HT_Pos (20U) ¥RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) ¦RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk §RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) ¨RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) ©RTC_ALRMAR_HU_Pos (16U) ªRTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) «RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk ¬RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) ®RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) ¯RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) °RTC_ALRMAR_MSK2_Pos (15U) ±RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) ²RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk ³RTC_ALRMAR_MNT_Pos (12U) ´RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) µRTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk ¶RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) ·RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) ¸RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) ¹RTC_ALRMAR_MNU_Pos (8U) ºRTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) »RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk ¼RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) ½RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) ¾RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) ¿RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) ÀRTC_ALRMAR_MSK1_Pos (7U) ÁRTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) ÂRTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk ÃRTC_ALRMAR_ST_Pos (4U) ÄRTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) ÅRTC_ALRMAR_ST RTC_ALRMAR_ST_Msk ÆRTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) ÇRTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) ÈRTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) ÉRTC_ALRMAR_SU_Pos (0U) ÊRTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) ËRTC_ALRMAR_SU RTC_ALRMAR_SU_Msk ÌRTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) ÍRTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) ÎRTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) ÏRTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) ÒRTC_ALRMBR_MSK4_Pos (31U) ÓRTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) ÔRTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk ÕRTC_ALRMBR_WDSEL_Pos (30U) ÖRTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) ×RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk ØRTC_ALRMBR_DT_Pos (28U) ÙRTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) ÚRTC_ALRMBR_DT RTC_ALRMBR_DT_Msk ÛRTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) ÜRTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) ÝRTC_ALRMBR_DU_Pos (24U) ÞRTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) ßRTC_ALRMBR_DU RTC_ALRMBR_DU_Msk àRTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) áRTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) âRTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) ãRTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) äRTC_ALRMBR_MSK3_Pos (23U) åRTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) æRTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk çRTC_ALRMBR_PM_Pos (22U) èRTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) éRTC_ALRMBR_PM RTC_ALRMBR_PM_Msk êRTC_ALRMBR_HT_Pos (20U) ëRTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) ìRTC_ALRMBR_HT RTC_ALRMBR_HT_Msk íRTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) îRTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) ïRTC_ALRMBR_HU_Pos (16U) ðRTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) ñRTC_ALRMBR_HU RTC_ALRMBR_HU_Msk òRTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) óRTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) ôRTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) õRTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) öRTC_ALRMBR_MSK2_Pos (15U) ÷RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) øRTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk ùRTC_ALRMBR_MNT_Pos (12U) úRTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) ûRTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk üRTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) ýRTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) þRTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) ÿRTC_ALRMBR_MNU_Pos (8U) RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) RTC_ALRMBR_MSK1_Pos (7U) RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk RTC_ALRMBR_ST_Pos (4U) RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) RTC_ALRMBR_SU_Pos (0U) RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) RTC_WPR_KEY_Pos (0U) RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) RTC_WPR_KEY RTC_WPR_KEY_Msk RTC_SSR_SS_Pos (0U) RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) RTC_SSR_SS RTC_SSR_SS_Msk ¢RTC_SHIFTR_SUBFS_Pos (0U) £RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) ¤RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk ¥RTC_SHIFTR_ADD1S_Pos (31U) ¦RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) §RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk ªRTC_TSTR_PM_Pos (22U) «RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) ¬RTC_TSTR_PM RTC_TSTR_PM_Msk RTC_TSTR_HT_Pos (20U) ®RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) ¯RTC_TSTR_HT RTC_TSTR_HT_Msk °RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) ±RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) ²RTC_TSTR_HU_Pos (16U) ³RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) ´RTC_TSTR_HU RTC_TSTR_HU_Msk µRTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) ¶RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) ·RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) ¸RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) ¹RTC_TSTR_MNT_Pos (12U) ºRTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) »RTC_TSTR_MNT RTC_TSTR_MNT_Msk ¼RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) ½RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) ¾RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) ¿RTC_TSTR_MNU_Pos (8U) ÀRTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) ÁRTC_TSTR_MNU RTC_TSTR_MNU_Msk ÂRTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) ÃRTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) ÄRTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) ÅRTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) ÆRTC_TSTR_ST_Pos (4U) ÇRTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) ÈRTC_TSTR_ST RTC_TSTR_ST_Msk ÉRTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) ÊRTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) ËRTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) ÌRTC_TSTR_SU_Pos (0U) ÍRTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) ÎRTC_TSTR_SU RTC_TSTR_SU_Msk ÏRTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) ÐRTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) ÑRTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) ÒRTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) ÕRTC_TSDR_WDU_Pos (13U) ÖRTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) ×RTC_TSDR_WDU RTC_TSDR_WDU_Msk ØRTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) ÙRTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) ÚRTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) ÛRTC_TSDR_MT_Pos (12U) ÜRTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) ÝRTC_TSDR_MT RTC_TSDR_MT_Msk ÞRTC_TSDR_MU_Pos (8U) ßRTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) àRTC_TSDR_MU RTC_TSDR_MU_Msk áRTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) âRTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) ãRTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) äRTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) åRTC_TSDR_DT_Pos (4U) æRTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) çRTC_TSDR_DT RTC_TSDR_DT_Msk èRTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) éRTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) êRTC_TSDR_DU_Pos (0U) ëRTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) ìRTC_TSDR_DU RTC_TSDR_DU_Msk íRTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) îRTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) ïRTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) ðRTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) óRTC_TSSSR_SS_Pos (0U) ôRTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) õRTC_TSSSR_SS RTC_TSSSR_SS_Msk øRTC_CALR_CALP_Pos (15U) ùRTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) úRTC_CALR_CALP RTC_CALR_CALP_Msk ûRTC_CALR_CALW8_Pos (14U) üRTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) ýRTC_CALR_CALW8 RTC_CALR_CALW8_Msk þRTC_CALR_CALW16_Pos (13U) ÿRTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) RTC_CALR_CALW16 RTC_CALR_CALW16_Msk RTC_CALR_CALM_Pos (0U) RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) RTC_CALR_CALM RTC_CALR_CALM_Msk RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) RTC_TAMPCR_TAMP3MF_Pos (24U) RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk RTC_TAMPCR_TAMP3NOERASE_Pos (23U) RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk RTC_TAMPCR_TAMP3IE_Pos (22U) RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk RTC_TAMPCR_TAMP2MF_Pos (21U) RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk RTC_TAMPCR_TAMP2NOERASE_Pos (20U) RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk RTC_TAMPCR_TAMP2IE_Pos (19U) RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk ¡RTC_TAMPCR_TAMP1MF_Pos (18U) ¢RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) £RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk ¤RTC_TAMPCR_TAMP1NOERASE_Pos (17U) ¥RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) ¦RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk §RTC_TAMPCR_TAMP1IE_Pos (16U) ¨RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) ©RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk ªRTC_TAMPCR_TAMPPUDIS_Pos (15U) «RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) ¬RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAMPCR_TAMPPRCH_Pos (13U) ®RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) ¯RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk °RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) ±RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) ²RTC_TAMPCR_TAMPFLT_Pos (11U) ³RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) ´RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk µRTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) ¶RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) ·RTC_TAMPCR_TAMPFREQ_Pos (8U) ¸RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) ¹RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk ºRTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) »RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) ¼RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) ½RTC_TAMPCR_TAMPTS_Pos (7U) ¾RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) ¿RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk ÀRTC_TAMPCR_TAMP3TRG_Pos (6U) ÁRTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) ÂRTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk ÃRTC_TAMPCR_TAMP3E_Pos (5U) ÄRTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) ÅRTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk ÆRTC_TAMPCR_TAMP2TRG_Pos (4U) ÇRTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) ÈRTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk ÉRTC_TAMPCR_TAMP2E_Pos (3U) ÊRTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) ËRTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk ÌRTC_TAMPCR_TAMPIE_Pos (2U) ÍRTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) ÎRTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk ÏRTC_TAMPCR_TAMP1TRG_Pos (1U) ÐRTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) ÑRTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk ÒRTC_TAMPCR_TAMP1E_Pos (0U) ÓRTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) ÔRTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk ×RTC_ALRMASSR_MASKSS_Pos (24U) ØRTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) ÙRTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk ÚRTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) ÛRTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) ÜRTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) ÝRTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) ÞRTC_ALRMASSR_SS_Pos (0U) ßRTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) àRTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk ãRTC_ALRMBSSR_MASKSS_Pos (24U) äRTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) åRTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk æRTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) çRTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) èRTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) éRTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) êRTC_ALRMBSSR_SS_Pos (0U) ëRTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) ìRTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk ïRTC_OR_OUT_RMP_Pos (1U) ðRTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) ñRTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk òRTC_OR_ALARMOUTTYPE_Pos (0U) óRTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) ôRTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk ÷RTC_BKP0R_Pos (0U) øRTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) ùRTC_BKP0R RTC_BKP0R_Msk üRTC_BKP1R_Pos (0U) ýRTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) þRTC_BKP1R RTC_BKP1R_Msk
RTC_BKP2R_Pos (0U)
RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
RTC_BKP2R RTC_BKP2R_Msk
RTC_BKP3R_Pos (0U)
RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
RTC_BKP3R RTC_BKP3R_Msk
RTC_BKP4R_Pos (0U)
RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
RTC_BKP4R RTC_BKP4R_Msk
RTC_BKP5R_Pos (0U)
RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
RTC_BKP5R RTC_BKP5R_Msk
RTC_BKP6R_Pos (0U)
RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
RTC_BKP6R RTC_BKP6R_Msk
RTC_BKP7R_Pos (0U)
RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
RTC_BKP7R RTC_BKP7R_Msk
RTC_BKP8R_Pos (0U)
RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) ¡
RTC_BKP8R RTC_BKP8R_Msk ¤
RTC_BKP9R_Pos (0U) ¥
RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) ¦
RTC_BKP9R RTC_BKP9R_Msk ©
RTC_BKP10R_Pos (0U) ª
RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) «
RTC_BKP10R RTC_BKP10R_Msk ®
RTC_BKP11R_Pos (0U) ¯
RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) °
RTC_BKP11R RTC_BKP11R_Msk ³
RTC_BKP12R_Pos (0U) ´
RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) µ
RTC_BKP12R RTC_BKP12R_Msk ¸
RTC_BKP13R_Pos (0U) ¹
RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) º
RTC_BKP13R RTC_BKP13R_Msk ½
RTC_BKP14R_Pos (0U) ¾
RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) ¿
RTC_BKP14R RTC_BKP14R_Msk Â
RTC_BKP15R_Pos (0U) Ã
RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) Ä
RTC_BKP15R RTC_BKP15R_Msk Ç
RTC_BKP16R_Pos (0U) È
RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) É
RTC_BKP16R RTC_BKP16R_Msk Ì
RTC_BKP17R_Pos (0U) Í
RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) Î
RTC_BKP17R RTC_BKP17R_Msk Ñ
RTC_BKP18R_Pos (0U) Ò
RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) Ó
RTC_BKP18R RTC_BKP18R_Msk Ö
RTC_BKP19R_Pos (0U) ×
RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) Ø
RTC_BKP19R RTC_BKP19R_Msk Û
RTC_BKP20R_Pos (0U) Ü
RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) Ý
RTC_BKP20R RTC_BKP20R_Msk à
RTC_BKP21R_Pos (0U) á
RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) â
RTC_BKP21R RTC_BKP21R_Msk å
RTC_BKP22R_Pos (0U) æ
RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) ç
RTC_BKP22R RTC_BKP22R_Msk ê
RTC_BKP23R_Pos (0U) ë
RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) ì
RTC_BKP23R RTC_BKP23R_Msk ï
RTC_BKP24R_Pos (0U) ð
RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) ñ
RTC_BKP24R RTC_BKP24R_Msk ô
RTC_BKP25R_Pos (0U) õ
RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) ö
RTC_BKP25R RTC_BKP25R_Msk ù
RTC_BKP26R_Pos (0U) ú
RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) û
RTC_BKP26R RTC_BKP26R_Msk þ
RTC_BKP27R_Pos (0U) ÿ
RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) RTC_BKP27R RTC_BKP27R_Msk RTC_BKP28R_Pos (0U) RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
RTC_BKP28R RTC_BKP28R_Msk RTC_BKP29R_Pos (0U) RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) RTC_BKP29R RTC_BKP29R_Msk RTC_BKP30R_Pos (0U) RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) RTC_BKP30R RTC_BKP30R_Msk RTC_BKP31R_Pos (0U) RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) RTC_BKP31R RTC_BKP31R_Msk RTC_BKP_NUMBER_Pos (5U) RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk ¡SPDIFRX_CR_SPDIFEN_Pos (0U) ¢SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) £SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk ¤SPDIFRX_CR_RXDMAEN_Pos (2U) ¥SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) ¦SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk §SPDIFRX_CR_RXSTEO_Pos (3U) ¨SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) ©SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk ªSPDIFRX_CR_DRFMT_Pos (4U) «SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) ¬SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk SPDIFRX_CR_PMSK_Pos (6U) ®SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) ¯SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk °SPDIFRX_CR_VMSK_Pos (7U) ±SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) ²SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk ³SPDIFRX_CR_CUMSK_Pos (8U) ´SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) µSPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk ¶SPDIFRX_CR_PTMSK_Pos (9U) ·SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) ¸SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk ¹SPDIFRX_CR_CBDMAEN_Pos (10U) ºSPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) »SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk ¼SPDIFRX_CR_CHSEL_Pos (11U) ½SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) ¾SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk ¿SPDIFRX_CR_NBTR_Pos (12U) ÀSPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) ÁSPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk ÂSPDIFRX_CR_WFA_Pos (14U) ÃSPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) ÄSPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk ÅSPDIFRX_CR_INSEL_Pos (16U) ÆSPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) ÇSPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk ÈSPDIFRX_CR_CKSEN_Pos (20U) ÉSPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) ÊSPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk ËSPDIFRX_CR_CKSBKPEN_Pos (21U) ÌSPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) ÍSPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk ÐSPDIFRX_IMR_RXNEIE_Pos (0U) ÑSPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) ÒSPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk ÓSPDIFRX_IMR_CSRNEIE_Pos (1U) ÔSPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) ÕSPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk ÖSPDIFRX_IMR_PERRIE_Pos (2U) ×SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) ØSPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk ÙSPDIFRX_IMR_OVRIE_Pos (3U) ÚSPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) ÛSPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk ÜSPDIFRX_IMR_SBLKIE_Pos (4U) ÝSPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) ÞSPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk ßSPDIFRX_IMR_SYNCDIE_Pos (5U) àSPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) áSPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk âSPDIFRX_IMR_IFEIE_Pos (6U) ãSPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) äSPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk çSPDIFRX_SR_RXNE_Pos (0U) èSPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) éSPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk êSPDIFRX_SR_CSRNE_Pos (1U) ëSPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) ìSPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk íSPDIFRX_SR_PERR_Pos (2U) îSPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) ïSPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk ðSPDIFRX_SR_OVR_Pos (3U) ñSPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) òSPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk óSPDIFRX_SR_SBD_Pos (4U) ôSPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) õSPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk öSPDIFRX_SR_SYNCD_Pos (5U) ÷SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) øSPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk ùSPDIFRX_SR_FERR_Pos (6U) úSPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) ûSPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk üSPDIFRX_SR_SERR_Pos (7U) ýSPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) þSPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk ÿSPDIFRX_SR_TERR_Pos (8U) SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk SPDIFRX_SR_WIDTH5_Pos (16U) SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk SPDIFRX_IFCR_PERRCF_Pos (2U) SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk SPDIFRX_IFCR_OVRCF_Pos (3U) SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk SPDIFRX_IFCR_SBDCF_Pos (4U) SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk SPDIFRX_IFCR_SYNCDCF_Pos (5U) SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk SPDIFRX_DR0_DR_Pos (0U) SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk SPDIFRX_DR0_PE_Pos (24U) SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk SPDIFRX_DR0_V_Pos (25U) SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk SPDIFRX_DR0_U_Pos (26U) SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk ¡SPDIFRX_DR0_C_Pos (27U) ¢SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) £SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk ¤SPDIFRX_DR0_PT_Pos (28U) ¥SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) ¦SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk ©SPDIFRX_DR1_DR_Pos (8U) ªSPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) «SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk ¬SPDIFRX_DR1_PT_Pos (4U) SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) ®SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk ¯SPDIFRX_DR1_C_Pos (3U) °SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) ±SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk ²SPDIFRX_DR1_U_Pos (2U) ³SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) ´SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk µSPDIFRX_DR1_V_Pos (1U) ¶SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) ·SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk ¸SPDIFRX_DR1_PE_Pos (0U) ¹SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) ºSPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk ½SPDIFRX_DR1_DRNL1_Pos (16U) ¾SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) ¿SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk ÀSPDIFRX_DR1_DRNL2_Pos (0U) ÁSPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) ÂSPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk ÅSPDIFRX_CSR_USR_Pos (0U) ÆSPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) ÇSPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk ÈSPDIFRX_CSR_CS_Pos (16U) ÉSPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) ÊSPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk ËSPDIFRX_CSR_SOB_Pos (24U) ÌSPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) ÍSPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk ÐSPDIFRX_DIR_THI_Pos (0U) ÑSPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) ÒSPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk ÓSPDIFRX_DIR_TLO_Pos (16U) ÔSPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) ÕSPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk ØSPDIFRX_VERR_MINREV_Pos (0U) ÙSPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) ÚSPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk ÛSPDIFRX_VERR_MAJREV_Pos (4U) ÜSPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) ÝSPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk àSPDIFRX_IDR_ID_Pos (0U) áSPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) âSPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk åSPDIFRX_SIDR_SID_Pos (0U) æSPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) çSPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk ïSAI_VER_V2_X òSAI_GCR_SYNCIN_Pos (0U) óSAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) ôSAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk õSAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) öSAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) øSAI_GCR_SYNCOUT_Pos (4U) ùSAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) úSAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk ûSAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) üSAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) ÿSAI_xCR1_MODE_Pos (0U) SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) SAI_xCR1_MODE SAI_xCR1_MODE_Msk SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
SAI_xCR1_PRTCFG_Pos (2U) SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) SAI_xCR1_DS_Pos (5U) SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) SAI_xCR1_DS SAI_xCR1_DS_Msk SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) SAI_xCR1_LSBFIRST_Pos (8U) SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk SAI_xCR1_CKSTR_Pos (9U) SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk SAI_xCR1_SYNCEN_Pos (10U) SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) SAI_xCR1_MONO_Pos (12U) SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) ¡SAI_xCR1_MONO SAI_xCR1_MONO_Msk ¢SAI_xCR1_OUTDRIV_Pos (13U) £SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) ¤SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk ¥SAI_xCR1_SAIEN_Pos (16U) ¦SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) §SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk ¨SAI_xCR1_DMAEN_Pos (17U) ©SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) ªSAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk «SAI_xCR1_NODIV_Pos (19U) ¬SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk ¯SAI_xCR1_MCKDIV_Pos (20U) °SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) ±SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk ²SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) ³SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) ´SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) µSAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) ¶SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) ·SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) ¹SAI_xCR1_MCKEN_Pos (27U) ºSAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) »SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk ½SAI_xCR1_OSR_Pos (26U) ¾SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) ¿SAI_xCR1_OSR SAI_xCR1_OSR_Msk ÂSAI_xCR1_NOMCK SAI_xCR1_NODIV ÅSAI_xCR2_FTH_Pos (0U) ÆSAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) ÇSAI_xCR2_FTH SAI_xCR2_FTH_Msk ÈSAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) ÉSAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) ÊSAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) ÌSAI_xCR2_FFLUSH_Pos (3U) ÍSAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) ÎSAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk ÏSAI_xCR2_TRIS_Pos (4U) ÐSAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) ÑSAI_xCR2_TRIS SAI_xCR2_TRIS_Msk ÒSAI_xCR2_MUTE_Pos (5U) ÓSAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) ÔSAI_xCR2_MUTE SAI_xCR2_MUTE_Msk ÕSAI_xCR2_MUTEVAL_Pos (6U) ÖSAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) ×SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk ÙSAI_xCR2_MUTECNT_Pos (7U) ÚSAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) ÛSAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk ÜSAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) ÝSAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) ÞSAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) ßSAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) àSAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) áSAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) ãSAI_xCR2_CPL_Pos (13U) äSAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) åSAI_xCR2_CPL SAI_xCR2_CPL_Msk çSAI_xCR2_COMP_Pos (14U) èSAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) éSAI_xCR2_COMP SAI_xCR2_COMP_Msk êSAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) ëSAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) îSAI_xFRCR_FRL_Pos (0U) ïSAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) ðSAI_xFRCR_FRL SAI_xFRCR_FRL_Msk ñSAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) òSAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) óSAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) ôSAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) õSAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) öSAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) ÷SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) øSAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) úSAI_xFRCR_FSALL_Pos (8U) ûSAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) üSAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk ýSAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) þSAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) ÿSAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
SAI_xFRCR_FSDEF_Pos (16U) SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk SAI_xFRCR_FSPOL_Pos (17U) SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk SAI_xFRCR_FSOFF_Pos (18U) SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk SAI_xFRCR_FSPO SAI_xFRCR_FSPOL SAI_xSLOTR_FBOFF_Pos (0U) SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) SAI_xSLOTR_SLOTSZ_Pos (6U) SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) ¢SAI_xSLOTR_NBSLOT_Pos (8U) £SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) ¤SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk ¥SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) ¦SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) §SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) ¨SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) ªSAI_xSLOTR_SLOTEN_Pos (16U) «SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) ¬SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk ¯SAI_xIMR_OVRUDRIE_Pos (0U) °SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) ±SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk ²SAI_xIMR_MUTEDETIE_Pos (1U) ³SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) ´SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk µSAI_xIMR_WCKCFGIE_Pos (2U) ¶SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) ·SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk ¸SAI_xIMR_FREQIE_Pos (3U) ¹SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) ºSAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk »SAI_xIMR_CNRDYIE_Pos (4U) ¼SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) ½SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk ¾SAI_xIMR_AFSDETIE_Pos (5U) ¿SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) ÀSAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk ÁSAI_xIMR_LFSDETIE_Pos (6U) ÂSAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) ÃSAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk ÆSAI_xSR_OVRUDR_Pos (0U) ÇSAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) ÈSAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk ÉSAI_xSR_MUTEDET_Pos (1U) ÊSAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) ËSAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk ÌSAI_xSR_WCKCFG_Pos (2U) ÍSAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) ÎSAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk ÏSAI_xSR_FREQ_Pos (3U) ÐSAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) ÑSAI_xSR_FREQ SAI_xSR_FREQ_Msk ÒSAI_xSR_CNRDY_Pos (4U) ÓSAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) ÔSAI_xSR_CNRDY SAI_xSR_CNRDY_Msk ÕSAI_xSR_AFSDET_Pos (5U) ÖSAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) ×SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk ØSAI_xSR_LFSDET_Pos (6U) ÙSAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) ÚSAI_xSR_LFSDET SAI_xSR_LFSDET_Msk ÜSAI_xSR_FLVL_Pos (16U) ÝSAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) ÞSAI_xSR_FLVL SAI_xSR_FLVL_Msk ßSAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) àSAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) áSAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) äSAI_xCLRFR_COVRUDR_Pos (0U) åSAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) æSAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk çSAI_xCLRFR_CMUTEDET_Pos (1U) èSAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) éSAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk êSAI_xCLRFR_CWCKCFG_Pos (2U) ëSAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) ìSAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk íSAI_xCLRFR_CFREQ_Pos (3U) îSAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) ïSAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk ðSAI_xCLRFR_CCNRDY_Pos (4U) ñSAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) òSAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk óSAI_xCLRFR_CAFSDET_Pos (5U) ôSAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) õSAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk öSAI_xCLRFR_CLFSDET_Pos (6U) ÷SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) øSAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk ûSAI_xDR_DATA_Pos (0U) üSAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) ýSAI_xDR_DATA SAI_xDR_DATA_Msk SAI_PDMCR_PDMEN_Pos (0U) SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk SAI_PDMCR_MICNBR_Pos (4U)
SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) SAI_PDMCR_CKEN1_Pos (8U) SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk SAI_PDMCR_CKEN2_Pos (9U) SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk SAI_PDMCR_CKEN3_Pos (10U) SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk SAI_PDMCR_CKEN4_Pos (11U) SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk SAI_PDMDLY_DLYM1L_Pos (0U) SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) SAI_PDMDLY_DLYM1R_Pos (4U) SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) ¡SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk ¢SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) £SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) ¤SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) ¦SAI_PDMDLY_DLYM2L_Pos (8U) §SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) ¨SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk ©SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) ªSAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) «SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) SAI_PDMDLY_DLYM2R_Pos (12U) ®SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) ¯SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk °SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) ±SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) ²SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) ´SAI_PDMDLY_DLYM3L_Pos (16U) µSAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) ¶SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk ·SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) ¸SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) ¹SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) »SAI_PDMDLY_DLYM3R_Pos (20U) ¼SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) ½SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk ¾SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) ¿SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) ÀSAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) ÂSAI_PDMDLY_DLYM4L_Pos (24U) ÃSAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) ÄSAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk ÅSAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) ÆSAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) ÇSAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) ÉSAI_PDMDLY_DLYM4R_Pos (28U) ÊSAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) ËSAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk ÌSAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) ÍSAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) ÎSAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) ÖSDMMC_POWER_PWRCTRL_Pos (0U) ×SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) ØSDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk ÙSDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) ÚSDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) ÛSDMMC_POWER_VSWITCH_Pos (2U) ÜSDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) ÝSDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk ÞSDMMC_POWER_VSWITCHEN_Pos (3U) ßSDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) àSDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk áSDMMC_POWER_DIRPOL_Pos (4U) âSDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) ãSDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk æSDMMC_CLKCR_CLKDIV_Pos (0U) çSDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) èSDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk éSDMMC_CLKCR_PWRSAV_Pos (12U) êSDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) ëSDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk íSDMMC_CLKCR_WIDBUS_Pos (14U) îSDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) ïSDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk ðSDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) ñSDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) óSDMMC_CLKCR_NEGEDGE_Pos (16U) ôSDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) õSDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk öSDMMC_CLKCR_HWFC_EN_Pos (17U) ÷SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) øSDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk ùSDMMC_CLKCR_DDR_Pos (18U) úSDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) ûSDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk üSDMMC_CLKCR_BUSSPEED_Pos (19U) ýSDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) þSDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk ÿSDMMC_CLKCR_SELCLKRX_Pos (20U) SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) SDMMC_ARG_CMDARG_Pos (0U) SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk SDMMC_CMD_CMDINDEX_Pos (0U) SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk SDMMC_CMD_CMDTRANS_Pos (6U) SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk SDMMC_CMD_CMDSTOP_Pos (7U) SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk SDMMC_CMD_WAITRESP_Pos (8U) SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) SDMMC_CMD_WAITINT_Pos (10U) SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk SDMMC_CMD_WAITPEND_Pos (11U) SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk ¡SDMMC_CMD_CPSMEN_Pos (12U) ¢SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) £SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk ¤SDMMC_CMD_DTHOLD_Pos (13U) ¥SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) ¦SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk §SDMMC_CMD_BOOTMODE_Pos (14U) ¨SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) ©SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk ªSDMMC_CMD_BOOTEN_Pos (15U) «SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) ¬SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk SDMMC_CMD_CMDSUSPEND_Pos (16U) ®SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) ¯SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk ²SDMMC_RESPCMD_RESPCMD_Pos (0U) ³SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) ´SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk ·SDMMC_RESP0_CARDSTATUS0_Pos (0U) ¸SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) ¹SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk ¼SDMMC_RESP1_CARDSTATUS1_Pos (0U) ½SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) ¾SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk ÁSDMMC_RESP2_CARDSTATUS2_Pos (0U) ÂSDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) ÃSDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk ÆSDMMC_RESP3_CARDSTATUS3_Pos (0U) ÇSDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) ÈSDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk ËSDMMC_RESP4_CARDSTATUS4_Pos (0U) ÌSDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) ÍSDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk ÐSDMMC_DTIMER_DATATIME_Pos (0U) ÑSDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) ÒSDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk ÕSDMMC_DLEN_DATALENGTH_Pos (0U) ÖSDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) ×SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk ÚSDMMC_DCTRL_DTEN_Pos (0U) ÛSDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) ÜSDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk ÝSDMMC_DCTRL_DTDIR_Pos (1U) ÞSDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) ßSDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk àSDMMC_DCTRL_DTMODE_Pos (2U) áSDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) âSDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk ãSDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) äSDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) æSDMMC_DCTRL_DBLOCKSIZE_Pos (4U) çSDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) èSDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk éSDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) êSDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) ëSDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) ìSDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) îSDMMC_DCTRL_RWSTART_Pos (8U) ïSDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) ðSDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk ñSDMMC_DCTRL_RWSTOP_Pos (9U) òSDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) óSDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk ôSDMMC_DCTRL_RWMOD_Pos (10U) õSDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) öSDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk ÷SDMMC_DCTRL_SDIOEN_Pos (11U) øSDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) ùSDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk úSDMMC_DCTRL_BOOTACKEN_Pos (12U) ûSDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) üSDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk ýSDMMC_DCTRL_FIFORST_Pos (13U) þSDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) ÿSDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk SDMMC_DCOUNT_DATACOUNT_Pos (0U) SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk SDMMC_STA_CCRCFAIL_Pos (0U) SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk SDMMC_STA_DCRCFAIL_Pos (1U) SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk SDMMC_STA_CTIMEOUT_Pos (2U) SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk SDMMC_STA_DTIMEOUT_Pos (3U) SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk SDMMC_STA_TXUNDERR_Pos (4U) SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk SDMMC_STA_RXOVERR_Pos (5U) SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk SDMMC_STA_CMDREND_Pos (6U) SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk SDMMC_STA_CMDSENT_Pos (7U) SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk SDMMC_STA_DATAEND_Pos (8U) SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) ¡SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk ¢SDMMC_STA_DHOLD_Pos (9U) £SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) ¤SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk ¥SDMMC_STA_DBCKEND_Pos (10U) ¦SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) §SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk ¨SDMMC_STA_DABORT_Pos (11U) ©SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) ªSDMMC_STA_DABORT SDMMC_STA_DABORT_Msk «SDMMC_STA_DPSMACT_Pos (12U) ¬SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk ®SDMMC_STA_CPSMACT_Pos (13U) ¯SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) °SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk ±SDMMC_STA_TXFIFOHE_Pos (14U) ²SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) ³SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk ´SDMMC_STA_RXFIFOHF_Pos (15U) µSDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) ¶SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk ·SDMMC_STA_TXFIFOF_Pos (16U) ¸SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) ¹SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk ºSDMMC_STA_RXFIFOF_Pos (17U) »SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) ¼SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk ½SDMMC_STA_TXFIFOE_Pos (18U) ¾SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) ¿SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk ÀSDMMC_STA_RXFIFOE_Pos (19U) ÁSDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) ÂSDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk ÃSDMMC_STA_BUSYD0_Pos (20U) ÄSDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) ÅSDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk ÆSDMMC_STA_BUSYD0END_Pos (21U) ÇSDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) ÈSDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk ÉSDMMC_STA_SDIOIT_Pos (22U) ÊSDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) ËSDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk ÌSDMMC_STA_ACKFAIL_Pos (23U) ÍSDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) ÎSDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk ÏSDMMC_STA_ACKTIMEOUT_Pos (24U) ÐSDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) ÑSDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk ÒSDMMC_STA_VSWEND_Pos (25U) ÓSDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) ÔSDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk ÕSDMMC_STA_CKSTOP_Pos (26U) ÖSDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) ×SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk ØSDMMC_STA_IDMATE_Pos (27U) ÙSDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) ÚSDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk ÛSDMMC_STA_IDMABTC_Pos (28U) ÜSDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) ÝSDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk àSDMMC_ICR_CCRCFAILC_Pos (0U) áSDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) âSDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk ãSDMMC_ICR_DCRCFAILC_Pos (1U) äSDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) åSDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk æSDMMC_ICR_CTIMEOUTC_Pos (2U) çSDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) èSDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk éSDMMC_ICR_DTIMEOUTC_Pos (3U) êSDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) ëSDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk ìSDMMC_ICR_TXUNDERRC_Pos (4U) íSDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) îSDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk ïSDMMC_ICR_RXOVERRC_Pos (5U) ðSDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) ñSDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk òSDMMC_ICR_CMDRENDC_Pos (6U) óSDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) ôSDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk õSDMMC_ICR_CMDSENTC_Pos (7U) öSDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) ÷SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk øSDMMC_ICR_DATAENDC_Pos (8U) ùSDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) úSDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk ûSDMMC_ICR_DHOLDC_Pos (9U) üSDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) ýSDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk þSDMMC_ICR_DBCKENDC_Pos (10U) ÿSDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk SDMMC_ICR_DABORTC_Pos (11U) SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk SDMMC_ICR_BUSYD0ENDC_Pos (21U)
SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk SDMMC_ICR_SDIOITC_Pos (22U) SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk SDMMC_ICR_ACKFAILC_Pos (23U) SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk SDMMC_ICR_ACKTIMEOUTC_Pos (24U) SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk SDMMC_ICR_VSWENDC_Pos (25U) SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk SDMMC_ICR_CKSTOPC_Pos (26U) SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk SDMMC_ICR_IDMATEC_Pos (27U) SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk SDMMC_ICR_IDMABTCC_Pos (28U) SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk SDMMC_MASK_CCRCFAILIE_Pos (0U) SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk ¡SDMMC_MASK_DCRCFAILIE_Pos (1U) ¢SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) £SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk ¤SDMMC_MASK_CTIMEOUTIE_Pos (2U) ¥SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) ¦SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk §SDMMC_MASK_DTIMEOUTIE_Pos (3U) ¨SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) ©SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk ªSDMMC_MASK_TXUNDERRIE_Pos (4U) «SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) ¬SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk SDMMC_MASK_RXOVERRIE_Pos (5U) ®SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) ¯SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk °SDMMC_MASK_CMDRENDIE_Pos (6U) ±SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) ²SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk ³SDMMC_MASK_CMDSENTIE_Pos (7U) ´SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) µSDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk ¶SDMMC_MASK_DATAENDIE_Pos (8U) ·SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) ¸SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk ¹SDMMC_MASK_DHOLDIE_Pos (9U) ºSDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) »SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk ¼SDMMC_MASK_DBCKENDIE_Pos (10U) ½SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) ¾SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk ¿SDMMC_MASK_DABORTIE_Pos (11U) ÀSDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) ÁSDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk ÃSDMMC_MASK_TXFIFOHEIE_Pos (14U) ÄSDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) ÅSDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk ÆSDMMC_MASK_RXFIFOHFIE_Pos (15U) ÇSDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) ÈSDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk ÊSDMMC_MASK_RXFIFOFIE_Pos (17U) ËSDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) ÌSDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk ÍSDMMC_MASK_TXFIFOEIE_Pos (18U) ÎSDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) ÏSDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk ÑSDMMC_MASK_BUSYD0ENDIE_Pos (21U) ÒSDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) ÓSDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk ÔSDMMC_MASK_SDIOITIE_Pos (22U) ÕSDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) ÖSDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk ×SDMMC_MASK_ACKFAILIE_Pos (23U) ØSDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) ÙSDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk ÚSDMMC_MASK_ACKTIMEOUTIE_Pos (24U) ÛSDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) ÜSDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk ÝSDMMC_MASK_VSWENDIE_Pos (25U) ÞSDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) ßSDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk àSDMMC_MASK_CKSTOPIE_Pos (26U) áSDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) âSDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk ãSDMMC_MASK_IDMABTCIE_Pos (28U) äSDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) åSDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk èSDMMC_ACKTIME_ACKTIME_Pos (0U) éSDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) êSDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk íSDMMC_FIFO_FIFODATA_Pos (0U) îSDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) ïSDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk òSDMMC_IDMA_IDMAEN_Pos (0U) óSDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) ôSDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk õSDMMC_IDMA_IDMABMODE_Pos (1U) öSDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) ÷SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk øSDMMC_IDMA_IDMABACT_Pos (2U) ùSDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) úSDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk ýSDMMC_IDMABSIZE_IDMABNDT_Pos (5U) þSDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) ÿSDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU)
SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) DLYB_CR_DEN_Pos (0U) DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) DLYB_CR_DEN DLYB_CR_DEN_Msk DLYB_CR_SEN_Pos (1U) DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) DLYB_CR_SEN DLYB_CR_SEN_Msk DLYB_CFGR_SEL_Pos (0U) DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) DLYB_CFGR_UNIT_Pos (8U) DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk ¡DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) ¢DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) £DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) ¤DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) ¥DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) ¦DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) §DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) ©DLYB_CFGR_LNG_Pos (16U) ªDLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) «DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk ¬DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) ®DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) ¯DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) °DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) ±DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) ²DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) ³DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) ´DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) µDLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) ¶DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) ·DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) ¹DLYB_CFGR_LNGF_Pos (31U) ºDLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) »DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk ÃSPI_CR1_SPE_Pos (0U) ÄSPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) ÅSPI_CR1_SPE SPI_CR1_SPE_Msk ÆSPI_CR1_MASRX_Pos (8U) ÇSPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) ÈSPI_CR1_MASRX SPI_CR1_MASRX_Msk ÉSPI_CR1_CSTART_Pos (9U) ÊSPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) ËSPI_CR1_CSTART SPI_CR1_CSTART_Msk ÌSPI_CR1_CSUSP_Pos (10U) ÍSPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) ÎSPI_CR1_CSUSP SPI_CR1_CSUSP_Msk ÏSPI_CR1_HDDIR_Pos (11U) ÐSPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) ÑSPI_CR1_HDDIR SPI_CR1_HDDIR_Msk ÒSPI_CR1_SSI_Pos (12U) ÓSPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) ÔSPI_CR1_SSI SPI_CR1_SSI_Msk ÕSPI_CR1_CRC33_17_Pos (13U) ÖSPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) ×SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk ØSPI_CR1_RCRCINI_Pos (14U) ÙSPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) ÚSPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk ÛSPI_CR1_TCRCINI_Pos (15U) ÜSPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) ÝSPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk ÞSPI_CR1_IOLOCK_Pos (16U) ßSPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) àSPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk ãSPI_CR2_TSER_Pos (16U) äSPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) åSPI_CR2_TSER SPI_CR2_TSER_Msk æSPI_CR2_TSIZE_Pos (0U) çSPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) èSPI_CR2_TSIZE SPI_CR2_TSIZE_Msk ëSPI_CFG1_DSIZE_Pos (0U) ìSPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) íSPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk îSPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) ïSPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) ðSPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) ñSPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) òSPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) ôSPI_CFG1_FTHLV_Pos (5U) õSPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) öSPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk ÷SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) øSPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) ùSPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) úSPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) üSPI_CFG1_UDRCFG_Pos (9U) ýSPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) þSPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk ÿSPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) SPI_CFG1_UDRDET_Pos (11U) SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) SPI_CFG1_RXDMAEN_Pos (14U) SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk SPI_CFG1_TXDMAEN_Pos (15U) SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk SPI_CFG1_CRCSIZE_Pos (16U) SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) SPI_CFG1_CRCEN_Pos (22U) SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk SPI_CFG1_MBR_Pos (28U) SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) SPI_CFG1_MBR SPI_CFG1_MBR_Msk SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) ¡SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) ¢SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) ¥SPI_CFG2_MSSI_Pos (0U) ¦SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) §SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk ¨SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) ©SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) ªSPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) «SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) SPI_CFG2_MIDI_Pos (4U) ®SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) ¯SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk °SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) ±SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) ²SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) ³SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) µSPI_CFG2_IOSWP_Pos (15U) ¶SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) ·SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk ¹SPI_CFG2_COMM_Pos (17U) ºSPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) »SPI_CFG2_COMM SPI_CFG2_COMM_Msk ¼SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) ½SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) ¿SPI_CFG2_SP_Pos (19U) ÀSPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) ÁSPI_CFG2_SP SPI_CFG2_SP_Msk ÂSPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) ÃSPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) ÄSPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) ÆSPI_CFG2_MASTER_Pos (22U) ÇSPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) ÈSPI_CFG2_MASTER SPI_CFG2_MASTER_Msk ÉSPI_CFG2_LSBFRST_Pos (23U) ÊSPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) ËSPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk ÌSPI_CFG2_CPHA_Pos (24U) ÍSPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) ÎSPI_CFG2_CPHA SPI_CFG2_CPHA_Msk ÏSPI_CFG2_CPOL_Pos (25U) ÐSPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) ÑSPI_CFG2_CPOL SPI_CFG2_CPOL_Msk ÒSPI_CFG2_SSM_Pos (26U) ÓSPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) ÔSPI_CFG2_SSM SPI_CFG2_SSM_Msk ÖSPI_CFG2_SSIOP_Pos (28U) ×SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) ØSPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk ÙSPI_CFG2_SSOE_Pos (29U) ÚSPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) ÛSPI_CFG2_SSOE SPI_CFG2_SSOE_Msk ÜSPI_CFG2_SSOM_Pos (30U) ÝSPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) ÞSPI_CFG2_SSOM SPI_CFG2_SSOM_Msk àSPI_CFG2_AFCNTR_Pos (31U) áSPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) âSPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk åSPI_IER_RXPIE_Pos (0U) æSPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) çSPI_IER_RXPIE SPI_IER_RXPIE_Msk èSPI_IER_TXPIE_Pos (1U) éSPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) êSPI_IER_TXPIE SPI_IER_TXPIE_Msk ëSPI_IER_DXPIE_Pos (2U) ìSPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) íSPI_IER_DXPIE SPI_IER_DXPIE_Msk îSPI_IER_EOTIE_Pos (3U) ïSPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) ðSPI_IER_EOTIE SPI_IER_EOTIE_Msk ñSPI_IER_TXTFIE_Pos (4U) òSPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) óSPI_IER_TXTFIE SPI_IER_TXTFIE_Msk ôSPI_IER_UDRIE_Pos (5U) õSPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) öSPI_IER_UDRIE SPI_IER_UDRIE_Msk ÷SPI_IER_OVRIE_Pos (6U) øSPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) ùSPI_IER_OVRIE SPI_IER_OVRIE_Msk úSPI_IER_CRCEIE_Pos (7U) ûSPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) üSPI_IER_CRCEIE SPI_IER_CRCEIE_Msk ýSPI_IER_TIFREIE_Pos (8U) þSPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) ÿSPI_IER_TIFREIE SPI_IER_TIFREIE_Msk SPI_IER_MODFIE_Pos (9U) SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) SPI_IER_MODFIE SPI_IER_MODFIE_Msk SPI_IER_TSERFIE_Pos (10U) SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk SPI_SR_RXP_Pos (0U) SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) SPI_SR_RXP SPI_SR_RXP_Msk SPI_SR_TXP_Pos (1U) SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) SPI_SR_TXP SPI_SR_TXP_Msk SPI_SR_DXP_Pos (2U) SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) SPI_SR_DXP SPI_SR_DXP_Msk SPI_SR_EOT_Pos (3U) SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) SPI_SR_EOT SPI_SR_EOT_Msk SPI_SR_TXTF_Pos (4U) SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) SPI_SR_TXTF SPI_SR_TXTF_Msk SPI_SR_UDR_Pos (5U) SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) SPI_SR_UDR SPI_SR_UDR_Msk SPI_SR_OVR_Pos (6U) SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) SPI_SR_OVR SPI_SR_OVR_Msk SPI_SR_CRCE_Pos (7U) SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) SPI_SR_CRCE SPI_SR_CRCE_Msk SPI_SR_TIFRE_Pos (8U) ¡SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) ¢SPI_SR_TIFRE SPI_SR_TIFRE_Msk £SPI_SR_MODF_Pos (9U) ¤SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) ¥SPI_SR_MODF SPI_SR_MODF_Msk ¦SPI_SR_TSERF_Pos (10U) §SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) ¨SPI_SR_TSERF SPI_SR_TSERF_Msk ©SPI_SR_SUSP_Pos (11U) ªSPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) «SPI_SR_SUSP SPI_SR_SUSP_Msk ¬SPI_SR_TXC_Pos (12U) SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) ®SPI_SR_TXC SPI_SR_TXC_Msk ¯SPI_SR_RXPLVL_Pos (13U) °SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) ±SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk ²SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) ³SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) ´SPI_SR_RXWNE_Pos (15U) µSPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) ¶SPI_SR_RXWNE SPI_SR_RXWNE_Msk ·SPI_SR_CTSIZE_Pos (16U) ¸SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) ¹SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk ¼SPI_IFCR_EOTC_Pos (3U) ½SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) ¾SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk ¿SPI_IFCR_TXTFC_Pos (4U) ÀSPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) ÁSPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk ÂSPI_IFCR_UDRC_Pos (5U) ÃSPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) ÄSPI_IFCR_UDRC SPI_IFCR_UDRC_Msk ÅSPI_IFCR_OVRC_Pos (6U) ÆSPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) ÇSPI_IFCR_OVRC SPI_IFCR_OVRC_Msk ÈSPI_IFCR_CRCEC_Pos (7U) ÉSPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) ÊSPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk ËSPI_IFCR_TIFREC_Pos (8U) ÌSPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) ÍSPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk ÎSPI_IFCR_MODFC_Pos (9U) ÏSPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) ÐSPI_IFCR_MODFC SPI_IFCR_MODFC_Msk ÑSPI_IFCR_TSERFC_Pos (10U) ÒSPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) ÓSPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk ÔSPI_IFCR_SUSPC_Pos (11U) ÕSPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) ÖSPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk ÙSPI_TXDR_TXDR_Pos (0U) ÚSPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) ÛSPI_TXDR_TXDR SPI_TXDR_TXDR_Msk ÞSPI_RXDR_RXDR_Pos (0U) ßSPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) àSPI_RXDR_RXDR SPI_RXDR_RXDR_Msk ãSPI_CRCPOLY_CRCPOLY_Pos (0U) äSPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) åSPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk èSPI_TXCRC_TXCRC_Pos (0U) éSPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) êSPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk íSPI_RXCRC_RXCRC_Pos (0U) îSPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) ïSPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk òSPI_UDRDR_UDRDR_Pos (0U) óSPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) ôSPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk ÷SPI_I2SCFGR_I2SMOD_Pos (0U) øSPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) ùSPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk úSPI_I2SCFGR_I2SCFG_Pos (1U) ûSPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) üSPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk ýSPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) þSPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) ÿSPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) SPI_I2SCFGR_I2SSTD_Pos (4U) SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
SPI_I2SCFGR_PCMSYNC_Pos (7U) SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk SPI_I2SCFGR_DATLEN_Pos (8U) SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) SPI_I2SCFGR_CHLEN_Pos (10U) SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk SPI_I2SCFGR_CKPOL_Pos (11U) SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk SPI_I2SCFGR_FIXCH_Pos (12U) SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk SPI_I2SCFGR_WSINV_Pos (13U) SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk SPI_I2SCFGR_DATFMT_Pos (14U) SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk SPI_I2SCFGR_I2SDIV_Pos (16U) SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk SPI_I2SCFGR_ODD_Pos (24U) SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) ¡SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk ¢SPI_I2SCFGR_MCKOE_Pos (25U) £SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) ¤SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk QUADSPI_CR_EN_Pos (0U) ®QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) ¯QUADSPI_CR_EN QUADSPI_CR_EN_Msk °QUADSPI_CR_ABORT_Pos (1U) ±QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) ²QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk ³QUADSPI_CR_DMAEN_Pos (2U) ´QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) µQUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk ¶QUADSPI_CR_TCEN_Pos (3U) ·QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) ¸QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk ¹QUADSPI_CR_SSHIFT_Pos (4U) ºQUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) »QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk ¼QUADSPI_CR_DFM_Pos (6U) ½QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) ¾QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk ¿QUADSPI_CR_FSEL_Pos (7U) ÀQUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) ÁQUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk ÂQUADSPI_CR_FTHRES_Pos (8U) ÃQUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) ÄQUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk ÅQUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) ÆQUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) ÇQUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) ÈQUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) ÉQUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) ÊQUADSPI_CR_TEIE_Pos (16U) ËQUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) ÌQUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk ÍQUADSPI_CR_TCIE_Pos (17U) ÎQUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) ÏQUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk ÐQUADSPI_CR_FTIE_Pos (18U) ÑQUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) ÒQUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk ÓQUADSPI_CR_SMIE_Pos (19U) ÔQUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) ÕQUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk ÖQUADSPI_CR_TOIE_Pos (20U) ×QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) ØQUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk ÙQUADSPI_CR_APMS_Pos (22U) ÚQUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) ÛQUADSPI_CR_APMS QUADSPI_CR_APMS_Msk ÜQUADSPI_CR_PMM_Pos (23U) ÝQUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) ÞQUADSPI_CR_PMM QUADSPI_CR_PMM_Msk ßQUADSPI_CR_PRESCALER_Pos (24U) àQUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) áQUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk âQUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) ãQUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) äQUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) åQUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) æQUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) çQUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) èQUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) éQUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) ìQUADSPI_DCR_CKMODE_Pos (0U) íQUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) îQUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk ïQUADSPI_DCR_CSHT_Pos (8U) ðQUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) ñQUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk òQUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) óQUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) ôQUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) õQUADSPI_DCR_FSIZE_Pos (16U) öQUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) ÷QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk øQUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) ùQUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) úQUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) ûQUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) üQUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) ÿQUADSPI_SR_TEF_Pos (0U) QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk QUADSPI_SR_TCF_Pos (1U) QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
QUADSPI_SR_FTF_Pos (2U) QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk QUADSPI_SR_SMF_Pos (3U) QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk QUADSPI_SR_TOF_Pos (4U) QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk QUADSPI_SR_BUSY_Pos (5U) QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk QUADSPI_SR_FLEVEL_Pos (8U) QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) QUADSPI_FCR_CTEF_Pos (0U) QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk QUADSPI_FCR_CTCF_Pos (1U) QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) ¡QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk ¢QUADSPI_FCR_CSMF_Pos (3U) £QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) ¤QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk ¥QUADSPI_FCR_CTOF_Pos (4U) ¦QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) §QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk ªQUADSPI_DLR_DL_Pos (0U) «QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) ¬QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk ¯QUADSPI_CCR_INSTRUCTION_Pos (0U) °QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) ±QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk ²QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) ³QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) ´QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) µQUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) ¶QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) ·QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) ¸QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) ¹QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) ºQUADSPI_CCR_IMODE_Pos (8U) »QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) ¼QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk ½QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) ¾QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) ¿QUADSPI_CCR_ADMODE_Pos (10U) ÀQUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) ÁQUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk ÂQUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) ÃQUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) ÄQUADSPI_CCR_ADSIZE_Pos (12U) ÅQUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) ÆQUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk ÇQUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) ÈQUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) ÉQUADSPI_CCR_ABMODE_Pos (14U) ÊQUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) ËQUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk ÌQUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) ÍQUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) ÎQUADSPI_CCR_ABSIZE_Pos (16U) ÏQUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) ÐQUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk ÑQUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) ÒQUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) ÓQUADSPI_CCR_DCYC_Pos (18U) ÔQUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) ÕQUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk ÖQUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) ×QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) ØQUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) ÙQUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) ÚQUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) ÛQUADSPI_CCR_DMODE_Pos (24U) ÜQUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) ÝQUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk ÞQUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) ßQUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) àQUADSPI_CCR_FMODE_Pos (26U) áQUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) âQUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk ãQUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) äQUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) åQUADSPI_CCR_SIOO_Pos (28U) æQUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) çQUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk èQUADSPI_CCR_DHHC_Pos (30U) éQUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) êQUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk ëQUADSPI_CCR_DDRM_Pos (31U) ìQUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) íQUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk ðQUADSPI_AR_ADDRESS_Pos (0U) ñQUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) òQUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk õQUADSPI_ABR_ALTERNATE_Pos (0U) öQUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) ÷QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk úQUADSPI_DR_DATA_Pos (0U) ûQUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) üQUADSPI_DR_DATA QUADSPI_DR_DATA_Msk ÿQUADSPI_PSMKR_MASK_Pos (0U) QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk QUADSPI_PSMAR_MATCH_Pos (0U)
QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk QUADSPI_PIR_INTERVAL_Pos (0U) QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk QUADSPI_LPTR_TIMEOUT_Pos (0U) QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk SYSCFG_PMCR_I2C1_FMP_Pos (0U) SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk SYSCFG_PMCR_I2C2_FMP_Pos (1U) SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk SYSCFG_PMCR_I2C3_FMP_Pos (2U) SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) ¡SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk ¢SYSCFG_PMCR_I2C4_FMP_Pos (3U) £SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) ¤SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk ¥SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U) ¦SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) §SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk ¨SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U) ©SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) ªSYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk «SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U) ¬SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk ®SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U) ¯SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) °SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk ±SYSCFG_PMCR_BOOSTEN_Pos (8U) ²SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) ³SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk µSYSCFG_PMCR_BOOSTVDDSEL_Pos (9U) ¶SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) ·SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk ¹SYSCFG_PMCR_EPIS_SEL_Pos (21U) ºSYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) »SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk ¼SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) ½SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) ¾SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) ¿SYSCFG_PMCR_PA0SO_Pos (24U) ÀSYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) ÁSYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk ÂSYSCFG_PMCR_PA1SO_Pos (25U) ÃSYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) ÄSYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk ÅSYSCFG_PMCR_PC2SO_Pos (26U) ÆSYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) ÇSYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk ÈSYSCFG_PMCR_PC3SO_Pos (27U) ÉSYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) ÊSYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk ÍSYSCFG_EXTICR1_EXTI0_Pos (0U) ÎSYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) ÏSYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk ÐSYSCFG_EXTICR1_EXTI1_Pos (4U) ÑSYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) ÒSYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk ÓSYSCFG_EXTICR1_EXTI2_Pos (8U) ÔSYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) ÕSYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk ÖSYSCFG_EXTICR1_EXTI3_Pos (12U) ×SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) ØSYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk ÜSYSCFG_EXTICR1_EXTI0_PA (0U) ÝSYSCFG_EXTICR1_EXTI0_PB (0x00000001U) ÞSYSCFG_EXTICR1_EXTI0_PC (0x00000002U) ßSYSCFG_EXTICR1_EXTI0_PD (0x00000003U) àSYSCFG_EXTICR1_EXTI0_PE (0x00000004U) áSYSCFG_EXTICR1_EXTI0_PF (0x00000005U) âSYSCFG_EXTICR1_EXTI0_PG (0x00000006U) ãSYSCFG_EXTICR1_EXTI0_PH (0x00000007U) äSYSCFG_EXTICR1_EXTI0_PI (0x00000008U) åSYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) æSYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) ëSYSCFG_EXTICR1_EXTI1_PA (0U) ìSYSCFG_EXTICR1_EXTI1_PB (0x00000010U) íSYSCFG_EXTICR1_EXTI1_PC (0x00000020U) îSYSCFG_EXTICR1_EXTI1_PD (0x00000030U) ïSYSCFG_EXTICR1_EXTI1_PE (0x00000040U) ðSYSCFG_EXTICR1_EXTI1_PF (0x00000050U) ñSYSCFG_EXTICR1_EXTI1_PG (0x00000060U) òSYSCFG_EXTICR1_EXTI1_PH (0x00000070U) óSYSCFG_EXTICR1_EXTI1_PI (0x00000080U) ôSYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) õSYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) ùSYSCFG_EXTICR1_EXTI2_PA (0U) úSYSCFG_EXTICR1_EXTI2_PB (0x00000100U) ûSYSCFG_EXTICR1_EXTI2_PC (0x00000200U) üSYSCFG_EXTICR1_EXTI2_PD (0x00000300U) ýSYSCFG_EXTICR1_EXTI2_PE (0x00000400U) þSYSCFG_EXTICR1_EXTI2_PF (0x00000500U) ÿSYSCFG_EXTICR1_EXTI2_PG (0x00000600U) SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) SYSCFG_EXTICR1_EXTI3_PA (0U) SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) SYSCFG_EXTICR2_EXTI4_Pos (0U) SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk SYSCFG_EXTICR2_EXTI5_Pos (4U) SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk SYSCFG_EXTICR2_EXTI6_Pos (8U) SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk SYSCFG_EXTICR2_EXTI7_Pos (12U) SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk ¤SYSCFG_EXTICR2_EXTI4_PA (0U) ¥SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) ¦SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) §SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) ¨SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) ©SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) ªSYSCFG_EXTICR2_EXTI4_PG (0x00000006U) «SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) ¬SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) ®SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) ²SYSCFG_EXTICR2_EXTI5_PA (0U) ³SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) ´SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) µSYSCFG_EXTICR2_EXTI5_PD (0x00000030U) ¶SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) ·SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) ¸SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) ¹SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) ºSYSCFG_EXTICR2_EXTI5_PI (0x00000080U) »SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) ¼SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) ÀSYSCFG_EXTICR2_EXTI6_PA (0U) ÁSYSCFG_EXTICR2_EXTI6_PB (0x00000100U) ÂSYSCFG_EXTICR2_EXTI6_PC (0x00000200U) ÃSYSCFG_EXTICR2_EXTI6_PD (0x00000300U) ÄSYSCFG_EXTICR2_EXTI6_PE (0x00000400U) ÅSYSCFG_EXTICR2_EXTI6_PF (0x00000500U) ÆSYSCFG_EXTICR2_EXTI6_PG (0x00000600U) ÇSYSCFG_EXTICR2_EXTI6_PH (0x00000700U) ÈSYSCFG_EXTICR2_EXTI6_PI (0x00000800U) ÉSYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) ÊSYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) ÏSYSCFG_EXTICR2_EXTI7_PA (0U) ÐSYSCFG_EXTICR2_EXTI7_PB (0x00001000U) ÑSYSCFG_EXTICR2_EXTI7_PC (0x00002000U) ÒSYSCFG_EXTICR2_EXTI7_PD (0x00003000U) ÓSYSCFG_EXTICR2_EXTI7_PE (0x00004000U) ÔSYSCFG_EXTICR2_EXTI7_PF (0x00005000U) ÕSYSCFG_EXTICR2_EXTI7_PG (0x00006000U) ÖSYSCFG_EXTICR2_EXTI7_PH (0x00007000U) ×SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) ØSYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) ÙSYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) ÜSYSCFG_EXTICR3_EXTI8_Pos (0U) ÝSYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) ÞSYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk ßSYSCFG_EXTICR3_EXTI9_Pos (4U) àSYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) áSYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk âSYSCFG_EXTICR3_EXTI10_Pos (8U) ãSYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) äSYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk åSYSCFG_EXTICR3_EXTI11_Pos (12U) æSYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) çSYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk ìSYSCFG_EXTICR3_EXTI8_PA (0U) íSYSCFG_EXTICR3_EXTI8_PB (0x00000001U) îSYSCFG_EXTICR3_EXTI8_PC (0x00000002U) ïSYSCFG_EXTICR3_EXTI8_PD (0x00000003U) ðSYSCFG_EXTICR3_EXTI8_PE (0x00000004U) ñSYSCFG_EXTICR3_EXTI8_PF (0x00000005U) òSYSCFG_EXTICR3_EXTI8_PG (0x00000006U) óSYSCFG_EXTICR3_EXTI8_PH (0x00000007U) ôSYSCFG_EXTICR3_EXTI8_PI (0x00000008U) õSYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) öSYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) ûSYSCFG_EXTICR3_EXTI9_PA (0U) üSYSCFG_EXTICR3_EXTI9_PB (0x00000010U) ýSYSCFG_EXTICR3_EXTI9_PC (0x00000020U) þSYSCFG_EXTICR3_EXTI9_PD (0x00000030U) ÿSYSCFG_EXTICR3_EXTI9_PE (0x00000040U) SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U)
SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) SYSCFG_EXTICR3_EXTI10_PA (0U) SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) SYSCFG_EXTICR3_EXTI11_PA (0U) SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) ¡SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) ¢SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) £SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) ¦SYSCFG_EXTICR4_EXTI12_Pos (0U) §SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) ¨SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk ©SYSCFG_EXTICR4_EXTI13_Pos (4U) ªSYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) «SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk ¬SYSCFG_EXTICR4_EXTI14_Pos (8U) SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) ®SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk ¯SYSCFG_EXTICR4_EXTI15_Pos (12U) °SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) ±SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk µSYSCFG_EXTICR4_EXTI12_PA (0U) ¶SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) ·SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) ¸SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) ¹SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) ºSYSCFG_EXTICR4_EXTI12_PF (0x00000005U) »SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) ¼SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) ½SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) ¾SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) ¿SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) ÃSYSCFG_EXTICR4_EXTI13_PA (0U) ÄSYSCFG_EXTICR4_EXTI13_PB (0x00000010U) ÅSYSCFG_EXTICR4_EXTI13_PC (0x00000020U) ÆSYSCFG_EXTICR4_EXTI13_PD (0x00000030U) ÇSYSCFG_EXTICR4_EXTI13_PE (0x00000040U) ÈSYSCFG_EXTICR4_EXTI13_PF (0x00000050U) ÉSYSCFG_EXTICR4_EXTI13_PG (0x00000060U) ÊSYSCFG_EXTICR4_EXTI13_PH (0x00000070U) ËSYSCFG_EXTICR4_EXTI13_PI (0x00000080U) ÌSYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) ÍSYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) ÑSYSCFG_EXTICR4_EXTI14_PA (0U) ÒSYSCFG_EXTICR4_EXTI14_PB (0x00000100U) ÓSYSCFG_EXTICR4_EXTI14_PC (0x00000200U) ÔSYSCFG_EXTICR4_EXTI14_PD (0x00000300U) ÕSYSCFG_EXTICR4_EXTI14_PE (0x00000400U) ÖSYSCFG_EXTICR4_EXTI14_PF (0x00000500U) ×SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) ØSYSCFG_EXTICR4_EXTI14_PH (0x00000700U) ÙSYSCFG_EXTICR4_EXTI14_PI (0x00000800U) ÚSYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) ÛSYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) ßSYSCFG_EXTICR4_EXTI15_PA (0U) àSYSCFG_EXTICR4_EXTI15_PB (0x00001000U) áSYSCFG_EXTICR4_EXTI15_PC (0x00002000U) âSYSCFG_EXTICR4_EXTI15_PD (0x00003000U) ãSYSCFG_EXTICR4_EXTI15_PE (0x00004000U) äSYSCFG_EXTICR4_EXTI15_PF (0x00005000U) åSYSCFG_EXTICR4_EXTI15_PG (0x00006000U) æSYSCFG_EXTICR4_EXTI15_PH (0x00007000U) çSYSCFG_EXTICR4_EXTI15_PI (0x00008000U) èSYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) éSYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) ìSYSCFG_CFGR_PVDL_Pos (2U) íSYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) îSYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk ïSYSCFG_CFGR_FLASHL_Pos (3U) ðSYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) ñSYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk òSYSCFG_CFGR_CM7L_Pos (6U) óSYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) ôSYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk õSYSCFG_CFGR_BKRAML_Pos (7U) öSYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) ÷SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk øSYSCFG_CFGR_SRAM4L_Pos (9U) ùSYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) úSYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk ûSYSCFG_CFGR_SRAM3L_Pos (10U) üSYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) ýSYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk þSYSCFG_CFGR_SRAM2L_Pos (11U) ÿSYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk SYSCFG_CFGR_SRAM1L_Pos (12U) SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk SYSCFG_CFGR_DTCML_Pos (13U)
SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk SYSCFG_CFGR_ITCML_Pos (14U) SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk SYSCFG_CFGR_AXISRAML_Pos (15U) SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk SYSCFG_CCCSR_EN_Pos (0U) SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk SYSCFG_CCCSR_CS_Pos (1U) SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk SYSCFG_CCCSR_READY_Pos (8U) SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk SYSCFG_CCCSR_HSLV_Pos (16U) SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk SYSCFG_CCVR_NCV_Pos (0U) SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk SYSCFG_CCVR_PCV_Pos (4U) ¡SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) ¢SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk ¥SYSCFG_CCCR_NCC_Pos (0U) ¦SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) §SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk ¨SYSCFG_CCCR_PCC_Pos (4U) ©SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) ªSYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk ¬SYSCFG_PWRCR_ODEN_Pos (0U) SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) ®SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk ±SYSCFG_PKGR_PKG_Pos (0U) ²SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) ³SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk ¶SYSCFG_UR0_BKS_Pos (0U) ·SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) ¸SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk ¹SYSCFG_UR0_RDP_Pos (16U) ºSYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) »SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk ¾SYSCFG_UR2_BORH_Pos (0U) ¿SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) ÀSYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk ÁSYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) ÂSYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) ÃSYSCFG_UR2_BOOT_ADD0_Pos (16U) ÄSYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) ÅSYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk ÇSYSCFG_UR3_BOOT_ADD1_Pos (0U) ÈSYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) ÉSYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk ÍSYSCFG_UR4_MEPAD_BANK1_Pos (16U) ÎSYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) ÏSYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk ÒSYSCFG_UR5_MESAD_BANK1_Pos (0U) ÓSYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) ÔSYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk ÕSYSCFG_UR5_WRPN_BANK1_Pos (16U) ÖSYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) ×SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk ÚSYSCFG_UR6_PABEG_BANK1_Pos (0U) ÛSYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) ÜSYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk ÝSYSCFG_UR6_PAEND_BANK1_Pos (16U) ÞSYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) ßSYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk âSYSCFG_UR7_SABEG_BANK1_Pos (0U) ãSYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) äSYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk åSYSCFG_UR7_SAEND_BANK1_Pos (16U) æSYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) çSYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk êSYSCFG_UR8_MEPAD_BANK2_Pos (0U) ëSYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) ìSYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk íSYSCFG_UR8_MESAD_BANK2_Pos (16U) îSYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) ïSYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk òSYSCFG_UR9_WRPN_BANK2_Pos (0U) óSYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) ôSYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk õSYSCFG_UR9_PABEG_BANK2_Pos (16U) öSYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) ÷SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk úSYSCFG_UR10_PAEND_BANK2_Pos (0U) ûSYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) üSYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk ýSYSCFG_UR10_SABEG_BANK2_Pos (16U) þSYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) ÿSYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk SYSCFG_UR11_SAEND_BANK2_Pos (0U) SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk
SYSCFG_UR11_IWDG1M_Pos (16U) SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk SYSCFG_UR12_SECURE_Pos (16U) SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk SYSCFG_UR13_SDRS_Pos (0U) SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk SYSCFG_UR13_D1SBRST_Pos (16U) SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk SYSCFG_UR14_D1STPRST_Pos (0U) SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk SYSCFG_UR15_FZIWDGSTB_Pos (16U) SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk ¢SYSCFG_UR16_FZIWDGSTP_Pos (0U) £SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) ¤SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk ¥SYSCFG_UR16_PKP_Pos (16U) ¦SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) §SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk ªSYSCFG_UR17_IOHSLV_Pos (0U) «SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) ¬SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk ´TIM_BREAK_INPUT_SUPPORT ·TIM_CR1_CEN_Pos (0U) ¸TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) ¹TIM_CR1_CEN TIM_CR1_CEN_Msk ºTIM_CR1_UDIS_Pos (1U) »TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) ¼TIM_CR1_UDIS TIM_CR1_UDIS_Msk ½TIM_CR1_URS_Pos (2U) ¾TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) ¿TIM_CR1_URS TIM_CR1_URS_Msk ÀTIM_CR1_OPM_Pos (3U) ÁTIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) ÂTIM_CR1_OPM TIM_CR1_OPM_Msk ÃTIM_CR1_DIR_Pos (4U) ÄTIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) ÅTIM_CR1_DIR TIM_CR1_DIR_Msk ÇTIM_CR1_CMS_Pos (5U) ÈTIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) ÉTIM_CR1_CMS TIM_CR1_CMS_Msk ÊTIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) ËTIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) ÍTIM_CR1_ARPE_Pos (7U) ÎTIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) ÏTIM_CR1_ARPE TIM_CR1_ARPE_Msk ÑTIM_CR1_CKD_Pos (8U) ÒTIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) ÓTIM_CR1_CKD TIM_CR1_CKD_Msk ÔTIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) ÕTIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) ×TIM_CR1_UIFREMAP_Pos (11U) ØTIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) ÙTIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk ÜTIM_CR2_CCPC_Pos (0U) ÝTIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) ÞTIM_CR2_CCPC TIM_CR2_CCPC_Msk ßTIM_CR2_CCUS_Pos (2U) àTIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) áTIM_CR2_CCUS TIM_CR2_CCUS_Msk âTIM_CR2_CCDS_Pos (3U) ãTIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) äTIM_CR2_CCDS TIM_CR2_CCDS_Msk æTIM_CR2_MMS_Pos (4U) çTIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) èTIM_CR2_MMS TIM_CR2_MMS_Msk éTIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) êTIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) ëTIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) íTIM_CR2_TI1S_Pos (7U) îTIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) ïTIM_CR2_TI1S TIM_CR2_TI1S_Msk ðTIM_CR2_OIS1_Pos (8U) ñTIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) òTIM_CR2_OIS1 TIM_CR2_OIS1_Msk óTIM_CR2_OIS1N_Pos (9U) ôTIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) õTIM_CR2_OIS1N TIM_CR2_OIS1N_Msk öTIM_CR2_OIS2_Pos (10U) ÷TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) øTIM_CR2_OIS2 TIM_CR2_OIS2_Msk ùTIM_CR2_OIS2N_Pos (11U) úTIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) ûTIM_CR2_OIS2N TIM_CR2_OIS2N_Msk üTIM_CR2_OIS3_Pos (12U) ýTIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) þTIM_CR2_OIS3 TIM_CR2_OIS3_Msk ÿTIM_CR2_OIS3N_Pos (13U) TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk TIM_CR2_OIS4_Pos (14U) TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
TIM_CR2_OIS5_Pos (16U) TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) TIM_CR2_OIS5 TIM_CR2_OIS5_Msk TIM_CR2_OIS6_Pos (18U) TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) TIM_CR2_OIS6 TIM_CR2_OIS6_Msk TIM_CR2_MMS2_Pos (20U) TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) TIM_CR2_MMS2 TIM_CR2_MMS2_Msk TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) TIM_SMCR_SMS_Pos (0U) TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) TIM_SMCR_SMS TIM_SMCR_SMS_Msk TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) TIM_SMCR_TS_Pos (4U) TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) TIM_SMCR_TS TIM_SMCR_TS_Msk TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) ¡TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) ¢TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) £TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) ¤TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) ¦TIM_SMCR_MSM_Pos (7U) §TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) ¨TIM_SMCR_MSM TIM_SMCR_MSM_Msk ªTIM_SMCR_ETF_Pos (8U) «TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) ¬TIM_SMCR_ETF TIM_SMCR_ETF_Msk TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) ®TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) ¯TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) °TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) ²TIM_SMCR_ETPS_Pos (12U) ³TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) ´TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk µTIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) ¶TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) ¸TIM_SMCR_ECE_Pos (14U) ¹TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) ºTIM_SMCR_ECE TIM_SMCR_ECE_Msk »TIM_SMCR_ETP_Pos (15U) ¼TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) ½TIM_SMCR_ETP TIM_SMCR_ETP_Msk ÀTIM_DIER_UIE_Pos (0U) ÁTIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) ÂTIM_DIER_UIE TIM_DIER_UIE_Msk ÃTIM_DIER_CC1IE_Pos (1U) ÄTIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) ÅTIM_DIER_CC1IE TIM_DIER_CC1IE_Msk ÆTIM_DIER_CC2IE_Pos (2U) ÇTIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) ÈTIM_DIER_CC2IE TIM_DIER_CC2IE_Msk ÉTIM_DIER_CC3IE_Pos (3U) ÊTIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) ËTIM_DIER_CC3IE TIM_DIER_CC3IE_Msk ÌTIM_DIER_CC4IE_Pos (4U) ÍTIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) ÎTIM_DIER_CC4IE TIM_DIER_CC4IE_Msk ÏTIM_DIER_COMIE_Pos (5U) ÐTIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) ÑTIM_DIER_COMIE TIM_DIER_COMIE_Msk ÒTIM_DIER_TIE_Pos (6U) ÓTIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) ÔTIM_DIER_TIE TIM_DIER_TIE_Msk ÕTIM_DIER_BIE_Pos (7U) ÖTIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) ×TIM_DIER_BIE TIM_DIER_BIE_Msk ØTIM_DIER_UDE_Pos (8U) ÙTIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) ÚTIM_DIER_UDE TIM_DIER_UDE_Msk ÛTIM_DIER_CC1DE_Pos (9U) ÜTIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) ÝTIM_DIER_CC1DE TIM_DIER_CC1DE_Msk ÞTIM_DIER_CC2DE_Pos (10U) ßTIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) àTIM_DIER_CC2DE TIM_DIER_CC2DE_Msk áTIM_DIER_CC3DE_Pos (11U) âTIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) ãTIM_DIER_CC3DE TIM_DIER_CC3DE_Msk äTIM_DIER_CC4DE_Pos (12U) åTIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) æTIM_DIER_CC4DE TIM_DIER_CC4DE_Msk çTIM_DIER_COMDE_Pos (13U) èTIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) éTIM_DIER_COMDE TIM_DIER_COMDE_Msk êTIM_DIER_TDE_Pos (14U) ëTIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) ìTIM_DIER_TDE TIM_DIER_TDE_Msk ïTIM_SR_UIF_Pos (0U) ðTIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) ñTIM_SR_UIF TIM_SR_UIF_Msk òTIM_SR_CC1IF_Pos (1U) óTIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) ôTIM_SR_CC1IF TIM_SR_CC1IF_Msk õTIM_SR_CC2IF_Pos (2U) öTIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) ÷TIM_SR_CC2IF TIM_SR_CC2IF_Msk øTIM_SR_CC3IF_Pos (3U) ùTIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) úTIM_SR_CC3IF TIM_SR_CC3IF_Msk ûTIM_SR_CC4IF_Pos (4U) üTIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) ýTIM_SR_CC4IF TIM_SR_CC4IF_Msk þTIM_SR_COMIF_Pos (5U) ÿTIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) TIM_SR_COMIF TIM_SR_COMIF_Msk TIM_SR_TIF_Pos (6U) TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) TIM_SR_TIF TIM_SR_TIF_Msk TIM_SR_BIF_Pos (7U)
TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) TIM_SR_BIF TIM_SR_BIF_Msk TIM_SR_B2IF_Pos (8U) TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) TIM_SR_B2IF TIM_SR_B2IF_Msk TIM_SR_CC1OF_Pos (9U) TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) TIM_SR_CC1OF TIM_SR_CC1OF_Msk TIM_SR_CC2OF_Pos (10U) TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) TIM_SR_CC2OF TIM_SR_CC2OF_Msk TIM_SR_CC3OF_Pos (11U) TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) TIM_SR_CC3OF TIM_SR_CC3OF_Msk TIM_SR_CC4OF_Pos (12U) TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) TIM_SR_CC4OF TIM_SR_CC4OF_Msk TIM_SR_CC5IF_Pos (16U) TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) TIM_SR_CC5IF TIM_SR_CC5IF_Msk TIM_SR_CC6IF_Pos (17U) TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) TIM_SR_CC6IF TIM_SR_CC6IF_Msk TIM_SR_SBIF_Pos (13U) TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) TIM_SR_SBIF TIM_SR_SBIF_Msk ¡TIM_EGR_UG_Pos (0U) ¢TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) £TIM_EGR_UG TIM_EGR_UG_Msk ¤TIM_EGR_CC1G_Pos (1U) ¥TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) ¦TIM_EGR_CC1G TIM_EGR_CC1G_Msk §TIM_EGR_CC2G_Pos (2U) ¨TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) ©TIM_EGR_CC2G TIM_EGR_CC2G_Msk ªTIM_EGR_CC3G_Pos (3U) «TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) ¬TIM_EGR_CC3G TIM_EGR_CC3G_Msk TIM_EGR_CC4G_Pos (4U) ®TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) ¯TIM_EGR_CC4G TIM_EGR_CC4G_Msk °TIM_EGR_COMG_Pos (5U) ±TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) ²TIM_EGR_COMG TIM_EGR_COMG_Msk ³TIM_EGR_TG_Pos (6U) ´TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) µTIM_EGR_TG TIM_EGR_TG_Msk ¶TIM_EGR_BG_Pos (7U) ·TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) ¸TIM_EGR_BG TIM_EGR_BG_Msk ¹TIM_EGR_B2G_Pos (8U) ºTIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) »TIM_EGR_B2G TIM_EGR_B2G_Msk ¿TIM_CCMR1_CC1S_Pos (0U) ÀTIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) ÁTIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk ÂTIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) ÃTIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) ÅTIM_CCMR1_OC1FE_Pos (2U) ÆTIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) ÇTIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk ÈTIM_CCMR1_OC1PE_Pos (3U) ÉTIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) ÊTIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk ÌTIM_CCMR1_OC1M_Pos (4U) ÍTIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) ÎTIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk ÏTIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) ÐTIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) ÑTIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) ÒTIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) ÔTIM_CCMR1_OC1CE_Pos (7U) ÕTIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) ÖTIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk ØTIM_CCMR1_CC2S_Pos (8U) ÙTIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) ÚTIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk ÛTIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) ÜTIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) ÞTIM_CCMR1_OC2FE_Pos (10U) ßTIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) àTIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk áTIM_CCMR1_OC2PE_Pos (11U) âTIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) ãTIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk åTIM_CCMR1_OC2M_Pos (12U) æTIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) çTIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk èTIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) éTIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) êTIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) ëTIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) íTIM_CCMR1_OC2CE_Pos (15U) îTIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) ïTIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk óTIM_CCMR1_IC1PSC_Pos (2U) ôTIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) õTIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk öTIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) ÷TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) ùTIM_CCMR1_IC1F_Pos (4U) úTIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) ûTIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk üTIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) ýTIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) þTIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) ÿTIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) TIM_CCMR1_IC2PSC_Pos (10U) TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) TIM_CCMR1_IC2F_Pos (12U) TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) TIM_CCMR2_CC3S_Pos (0U) TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) TIM_CCMR2_OC3FE_Pos (2U) TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk TIM_CCMR2_OC3PE_Pos (3U) TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk TIM_CCMR2_OC3M_Pos (4U) TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) ¡TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) ¢TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) £TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) ¥TIM_CCMR2_OC3CE_Pos (7U) ¦TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) §TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk ©TIM_CCMR2_CC4S_Pos (8U) ªTIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) «TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk ¬TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) ¯TIM_CCMR2_OC4FE_Pos (10U) °TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) ±TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk ²TIM_CCMR2_OC4PE_Pos (11U) ³TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) ´TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk ¶TIM_CCMR2_OC4M_Pos (12U) ·TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) ¸TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk ¹TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) ºTIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) »TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) ¼TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) ¾TIM_CCMR2_OC4CE_Pos (15U) ¿TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) ÀTIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk ÄTIM_CCMR2_IC3PSC_Pos (2U) ÅTIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) ÆTIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk ÇTIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) ÈTIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) ÊTIM_CCMR2_IC3F_Pos (4U) ËTIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) ÌTIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk ÍTIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) ÎTIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) ÏTIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) ÐTIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) ÒTIM_CCMR2_IC4PSC_Pos (10U) ÓTIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) ÔTIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk ÕTIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) ÖTIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) ØTIM_CCMR2_IC4F_Pos (12U) ÙTIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) ÚTIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk ÛTIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) ÜTIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) ÝTIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) ÞTIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) áTIM_CCER_CC1E_Pos (0U) âTIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) ãTIM_CCER_CC1E TIM_CCER_CC1E_Msk äTIM_CCER_CC1P_Pos (1U) åTIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) æTIM_CCER_CC1P TIM_CCER_CC1P_Msk çTIM_CCER_CC1NE_Pos (2U) èTIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) éTIM_CCER_CC1NE TIM_CCER_CC1NE_Msk êTIM_CCER_CC1NP_Pos (3U) ëTIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) ìTIM_CCER_CC1NP TIM_CCER_CC1NP_Msk íTIM_CCER_CC2E_Pos (4U) îTIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) ïTIM_CCER_CC2E TIM_CCER_CC2E_Msk ðTIM_CCER_CC2P_Pos (5U) ñTIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) òTIM_CCER_CC2P TIM_CCER_CC2P_Msk óTIM_CCER_CC2NE_Pos (6U) ôTIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) õTIM_CCER_CC2NE TIM_CCER_CC2NE_Msk öTIM_CCER_CC2NP_Pos (7U) ÷TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) øTIM_CCER_CC2NP TIM_CCER_CC2NP_Msk ùTIM_CCER_CC3E_Pos (8U) úTIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) ûTIM_CCER_CC3E TIM_CCER_CC3E_Msk üTIM_CCER_CC3P_Pos (9U) ýTIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) þTIM_CCER_CC3P TIM_CCER_CC3P_Msk ÿTIM_CCER_CC3NE_Pos (10U) TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk TIM_CCER_CC3NP_Pos (11U) TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
TIM_CCER_CC4E_Pos (12U) TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) TIM_CCER_CC4E TIM_CCER_CC4E_Msk TIM_CCER_CC4P_Pos (13U) TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) TIM_CCER_CC4P TIM_CCER_CC4P_Msk TIM_CCER_CC4NP_Pos (15U) TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk TIM_CCER_CC5E_Pos (16U) TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) TIM_CCER_CC5E TIM_CCER_CC5E_Msk TIM_CCER_CC5P_Pos (17U) TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) TIM_CCER_CC5P TIM_CCER_CC5P_Msk TIM_CCER_CC6E_Pos (20U) TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) TIM_CCER_CC6E TIM_CCER_CC6E_Msk TIM_CCER_CC6P_Pos (21U) TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) TIM_CCER_CC6P TIM_CCER_CC6P_Msk TIM_CNT_CNT_Pos (0U) TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) TIM_CNT_CNT TIM_CNT_CNT_Msk TIM_CNT_UIFCPY_Pos (31U) TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk ¢TIM_PSC_PSC_Pos (0U) £TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) ¤TIM_PSC_PSC TIM_PSC_PSC_Msk §TIM_ARR_ARR_Pos (0U) ¨TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) ©TIM_ARR_ARR TIM_ARR_ARR_Msk ¬TIM_RCR_REP_Pos (0U) TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) ®TIM_RCR_REP TIM_RCR_REP_Msk ±TIM_CCR1_CCR1_Pos (0U) ²TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) ³TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk ¶TIM_CCR2_CCR2_Pos (0U) ·TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) ¸TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk »TIM_CCR3_CCR3_Pos (0U) ¼TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) ½TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk ÀTIM_CCR4_CCR4_Pos (0U) ÁTIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) ÂTIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk ÅTIM_CCR5_CCR5_Pos (0U) ÆTIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) ÇTIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk ÈTIM_CCR5_GC5C1_Pos (29U) ÉTIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) ÊTIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk ËTIM_CCR5_GC5C2_Pos (30U) ÌTIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) ÍTIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk ÎTIM_CCR5_GC5C3_Pos (31U) ÏTIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) ÐTIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk ÓTIM_CCR6_CCR6_Pos (0U) ÔTIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) ÕTIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk ØTIM_BDTR_DTG_Pos (0U) ÙTIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) ÚTIM_BDTR_DTG TIM_BDTR_DTG_Msk ÛTIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) ÜTIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) ÝTIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) ÞTIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) ßTIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) àTIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) áTIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) âTIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) äTIM_BDTR_LOCK_Pos (8U) åTIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) æTIM_BDTR_LOCK TIM_BDTR_LOCK_Msk çTIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) èTIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) êTIM_BDTR_OSSI_Pos (10U) ëTIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) ìTIM_BDTR_OSSI TIM_BDTR_OSSI_Msk íTIM_BDTR_OSSR_Pos (11U) îTIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) ïTIM_BDTR_OSSR TIM_BDTR_OSSR_Msk ðTIM_BDTR_BKE_Pos (12U) ñTIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) òTIM_BDTR_BKE TIM_BDTR_BKE_Msk óTIM_BDTR_BKP_Pos (13U) ôTIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) õTIM_BDTR_BKP TIM_BDTR_BKP_Msk öTIM_BDTR_AOE_Pos (14U) ÷TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) øTIM_BDTR_AOE TIM_BDTR_AOE_Msk ùTIM_BDTR_MOE_Pos (15U) úTIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) ûTIM_BDTR_MOE TIM_BDTR_MOE_Msk ýTIM_BDTR_BKF_Pos (16U) þTIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) ÿTIM_BDTR_BKF TIM_BDTR_BKF_Msk TIM_BDTR_BK2F_Pos (20U) TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk TIM_BDTR_BK2E_Pos (24U)
TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk TIM_BDTR_BK2P_Pos (25U) TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk TIM_DCR_DBA_Pos (0U) TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) TIM_DCR_DBA TIM_DCR_DBA_Msk TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) TIM_DCR_DBL_Pos (8U) TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) TIM_DCR_DBL TIM_DCR_DBL_Msk TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) TIM_DMAR_DMAB_Pos (0U) TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) ¡TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk ¤TIM_CCMR3_OC5FE_Pos (2U) ¥TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) ¦TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk §TIM_CCMR3_OC5PE_Pos (3U) ¨TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) ©TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk «TIM_CCMR3_OC5M_Pos (4U) ¬TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk ®TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) ¯TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) °TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) ±TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) ³TIM_CCMR3_OC5CE_Pos (7U) ´TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) µTIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk ·TIM_CCMR3_OC6FE_Pos (10U) ¸TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) ¹TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk ºTIM_CCMR3_OC6PE_Pos (11U) »TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) ¼TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk ¾TIM_CCMR3_OC6M_Pos (12U) ¿TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) ÀTIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk ÁTIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) ÂTIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) ÃTIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) ÄTIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) ÆTIM_CCMR3_OC6CE_Pos (15U) ÇTIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) ÈTIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk ÊTIM1_AF1_BKINE_Pos (0U) ËTIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) ÌTIM1_AF1_BKINE TIM1_AF1_BKINE_Msk ÍTIM1_AF1_BKCMP1E_Pos (1U) ÎTIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) ÏTIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk ÐTIM1_AF1_BKCMP2E_Pos (2U) ÑTIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) ÒTIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk ÓTIM1_AF1_BKDF1BK0E_Pos (8U) ÔTIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) ÕTIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk ÖTIM1_AF1_BKINP_Pos (9U) ×TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) ØTIM1_AF1_BKINP TIM1_AF1_BKINP_Msk ÙTIM1_AF1_BKCMP1P_Pos (10U) ÚTIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) ÛTIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk ÜTIM1_AF1_BKCMP2P_Pos (11U) ÝTIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) ÞTIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk àTIM1_AF1_ETRSEL_Pos (14U) áTIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) âTIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk ãTIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) äTIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) åTIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) æTIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) éTIM1_AF2_BK2INE_Pos (0U) êTIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) ëTIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk ìTIM1_AF2_BK2CMP1E_Pos (1U) íTIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) îTIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk ïTIM1_AF2_BK2CMP2E_Pos (2U) ðTIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) ñTIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk òTIM1_AF2_BK2DFBK1E_Pos (8U) óTIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) ôTIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk õTIM1_AF2_BK2INP_Pos (9U) öTIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) ÷TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk øTIM1_AF2_BK2CMP1P_Pos (10U) ùTIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) úTIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk ûTIM1_AF2_BK2CMP2P_Pos (11U) üTIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) ýTIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk TIM_TISEL_TI1SEL_Pos (0U) TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) TIM_TISEL_TI2SEL_Pos (8U) TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) TIM_TISEL_TI3SEL_Pos (16U) TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) TIM_TISEL_TI4SEL_Pos (24U) TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) ¡TIM8_AF1_BKINE_Pos (0U) ¢TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) £TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk ¤TIM8_AF1_BKCMP1E_Pos (1U) ¥TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) ¦TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk §TIM8_AF1_BKCMP2E_Pos (2U) ¨TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) ©TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk ªTIM8_AF1_BKDFBK2E_Pos (8U) «TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) ¬TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk TIM8_AF1_BKINP_Pos (9U) ®TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) ¯TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk °TIM8_AF1_BKCMP1P_Pos (10U) ±TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) ²TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk ³TIM8_AF1_BKCMP2P_Pos (11U) ´TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) µTIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk ·TIM8_AF1_ETRSEL_Pos (14U) ¸TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) ¹TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk ºTIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) »TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) ¼TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) ½TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) ¿TIM8_AF2_BK2INE_Pos (0U) ÀTIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) ÁTIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk ÂTIM8_AF2_BK2CMP1E_Pos (1U) ÃTIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) ÄTIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk ÅTIM8_AF2_BK2CMP2E_Pos (2U) ÆTIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) ÇTIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk ÈTIM8_AF2_BK2DFBK3E_Pos (8U) ÉTIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) ÊTIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk ËTIM8_AF2_BK2INP_Pos (9U) ÌTIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) ÍTIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk ÎTIM8_AF2_BK2CMP1P_Pos (10U) ÏTIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) ÐTIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk ÑTIM8_AF2_BK2CMP2P_Pos (11U) ÒTIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) ÓTIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk ÖTIM2_AF1_ETRSEL_Pos (14U) ×TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) ØTIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk ÙTIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) ÚTIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) ÛTIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) ÜTIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) ßTIM3_AF1_ETRSEL_Pos (14U) àTIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) áTIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk âTIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) ãTIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) äTIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) åTIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) èTIM5_AF1_ETRSEL_Pos (14U) éTIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) êTIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk ëTIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) ìTIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) íTIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) îTIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) ñTIM15_AF1_BKINE_Pos (0U) òTIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) óTIM15_AF1_BKINE TIM15_AF1_BKINE_Msk ôTIM15_AF1_BKCMP1E_Pos (1U) õTIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) öTIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk ÷TIM15_AF1_BKCMP2E_Pos (2U) øTIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) ùTIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk úTIM15_AF1_BKDF1BK2E_Pos (8U) ûTIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) üTIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk ýTIM15_AF1_BKINP_Pos (9U) þTIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) ÿTIM15_AF1_BKINP TIM15_AF1_BKINP_Msk TIM15_AF1_BKCMP1P_Pos (10U) TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk TIM15_AF1_BKCMP2P_Pos (11U) TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk TIM16_AF1_BKINE_Pos (0U) TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk TIM16_AF1_BKCMP1E_Pos (1U) TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk TIM16_AF1_BKCMP2E_Pos (2U) TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk TIM16_AF1_BKDF1BK2E_Pos (8U) TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk TIM16_AF1_BKINP_Pos (9U) TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk TIM16_AF1_BKCMP1P_Pos (10U) TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk TIM16_AF1_BKCMP2P_Pos (11U) TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk TIM17_AF1_BKINE_Pos (0U) TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) ¡TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk ¢TIM17_AF1_BKCMP1E_Pos (1U) £TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) ¤TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk ¥TIM17_AF1_BKCMP2E_Pos (2U) ¦TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) §TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk ¨TIM17_AF1_BKDF1BK2E_Pos (8U) ©TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) ªTIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk «TIM17_AF1_BKINP_Pos (9U) ¬TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk ®TIM17_AF1_BKCMP1P_Pos (10U) ¯TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) °TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk ±TIM17_AF1_BKCMP2P_Pos (11U) ²TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) ³TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk »LPTIM_ISR_CMPM_Pos (0U) ¼LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) ½LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk ¾LPTIM_ISR_ARRM_Pos (1U) ¿LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) ÀLPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk ÁLPTIM_ISR_EXTTRIG_Pos (2U) ÂLPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) ÃLPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk ÄLPTIM_ISR_CMPOK_Pos (3U) ÅLPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) ÆLPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk ÇLPTIM_ISR_ARROK_Pos (4U) ÈLPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) ÉLPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk ÊLPTIM_ISR_UP_Pos (5U) ËLPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) ÌLPTIM_ISR_UP LPTIM_ISR_UP_Msk ÍLPTIM_ISR_DOWN_Pos (6U) ÎLPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) ÏLPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk ÒLPTIM_ICR_CMPMCF_Pos (0U) ÓLPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) ÔLPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk ÕLPTIM_ICR_ARRMCF_Pos (1U) ÖLPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) ×LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk ØLPTIM_ICR_EXTTRIGCF_Pos (2U) ÙLPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) ÚLPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk ÛLPTIM_ICR_CMPOKCF_Pos (3U) ÜLPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) ÝLPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk ÞLPTIM_ICR_ARROKCF_Pos (4U) ßLPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) àLPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk áLPTIM_ICR_UPCF_Pos (5U) âLPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) ãLPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk äLPTIM_ICR_DOWNCF_Pos (6U) åLPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) æLPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk éLPTIM_IER_CMPMIE_Pos (0U) êLPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) ëLPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk ìLPTIM_IER_ARRMIE_Pos (1U) íLPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) îLPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk ïLPTIM_IER_EXTTRIGIE_Pos (2U) ðLPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) ñLPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk òLPTIM_IER_CMPOKIE_Pos (3U) óLPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) ôLPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk õLPTIM_IER_ARROKIE_Pos (4U) öLPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) ÷LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk øLPTIM_IER_UPIE_Pos (5U) ùLPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) úLPTIM_IER_UPIE LPTIM_IER_UPIE_Msk ûLPTIM_IER_DOWNIE_Pos (6U) üLPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) ýLPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk LPTIM_CFGR_CKSEL_Pos (0U) LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk LPTIM_CFGR_CKPOL_Pos (1U)
LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) LPTIM_CFGR_CKFLT_Pos (3U) LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) LPTIM_CFGR_TRGFLT_Pos (6U) LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) LPTIM_CFGR_PRESC_Pos (9U) LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) LPTIM_CFGR_TRIGSEL_Pos (13U) LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) ¡LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) ¢LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) ¤LPTIM_CFGR_TRIGEN_Pos (17U) ¥LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) ¦LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk §LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) ¨LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) ªLPTIM_CFGR_TIMOUT_Pos (19U) «LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) ¬LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk LPTIM_CFGR_WAVE_Pos (20U) ®LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) ¯LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk °LPTIM_CFGR_WAVPOL_Pos (21U) ±LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) ²LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk ³LPTIM_CFGR_PRELOAD_Pos (22U) ´LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) µLPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk ¶LPTIM_CFGR_COUNTMODE_Pos (23U) ·LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) ¸LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk ¹LPTIM_CFGR_ENC_Pos (24U) ºLPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) »LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk ¾LPTIM_CR_ENABLE_Pos (0U) ¿LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) ÀLPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk ÁLPTIM_CR_SNGSTRT_Pos (1U) ÂLPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) ÃLPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk ÄLPTIM_CR_CNTSTRT_Pos (2U) ÅLPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) ÆLPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk ÇLPTIM_CR_COUNTRST_Pos (3U) ÈLPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) ÉLPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk ÊLPTIM_CR_RSTARE_Pos (4U) ËLPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) ÌLPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk ÐLPTIM_CMP_CMP_Pos (0U) ÑLPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) ÒLPTIM_CMP_CMP LPTIM_CMP_CMP_Msk ÕLPTIM_ARR_ARR_Pos (0U) ÖLPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) ×LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk ÚLPTIM_CNT_CNT_Pos (0U) ÛLPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) ÜLPTIM_CNT_CNT LPTIM_CNT_CNT_Msk ßLPTIM_CFGR2_IN1SEL_Pos (0U) àLPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) áLPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk âLPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) ãLPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) äLPTIM_CFGR2_IN2SEL_Pos (4U) åLPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) æLPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk çLPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) èLPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) ñCOMP_SR_C1VAL_Pos (0U) òCOMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) óCOMP_SR_C1VAL COMP_SR_C1VAL_Msk ôCOMP_SR_C2VAL_Pos (1U) õCOMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) öCOMP_SR_C2VAL COMP_SR_C2VAL_Msk ÷COMP_SR_C1IF_Pos (16U) øCOMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) ùCOMP_SR_C1IF COMP_SR_C1IF_Msk úCOMP_SR_C2IF_Pos (17U) ûCOMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) üCOMP_SR_C2IF COMP_SR_C2IF_Msk þCOMP_ICFR_C1IF_Pos (16U) ÿCOMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk COMP_ICFR_C2IF_Pos (17U) COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
COMP_OR_AFOPA6_Pos (0U) COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk COMP_OR_AFOPA8_Pos (1U) COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk COMP_OR_AFOPB12_Pos (2U) COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk COMP_OR_AFOPE6_Pos (3U) COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk COMP_OR_AFOPE15_Pos (4U) COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk COMP_OR_AFOPG2_Pos (5U) COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk COMP_OR_AFOPG3_Pos (6U) COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk COMP_OR_AFOPG4_Pos (7U) COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk COMP_OR_AFOPI1_Pos (8U) COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk COMP_OR_AFOPI4_Pos (9U) ¡ COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) ¢ COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk £ COMP_OR_AFOPK2_Pos (10U) ¤ COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) ¥ COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk ¨ COMP_CFGRx_EN_Pos (0U) © COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) ª COMP_CFGRx_EN COMP_CFGRx_EN_Msk « COMP_CFGRx_BRGEN_Pos (1U) ¬ COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk ® COMP_CFGRx_SCALEN_Pos (2U) ¯ COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) ° COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk ± COMP_CFGRx_POLARITY_Pos (3U) ² COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) ³ COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk ´ COMP_CFGRx_WINMODE_Pos (4U) µ COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) ¶ COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk · COMP_CFGRx_ITEN_Pos (6U) ¸ COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) ¹ COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk º COMP_CFGRx_HYST_Pos (8U) » COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) ¼ COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk ½ COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) ¾ COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) ¿ COMP_CFGRx_PWRMODE_Pos (12U) À COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) Á COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk  COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) à COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) Ä COMP_CFGRx_INMSEL_Pos (16U) Å COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) Æ COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk Ç COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) È COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) É COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) Ê COMP_CFGRx_INPSEL_Pos (20U) Ë COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) Ì COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk Í COMP_CFGRx_BLANKING_Pos (24U) Î COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) Ï COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk Ð COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) Ñ COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) Ò COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) Ó COMP_CFGRx_LOCK_Pos (31U) Ô COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) Õ COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk Þ USART_CR1_UE_Pos (0U) ß USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) à USART_CR1_UE USART_CR1_UE_Msk á USART_CR1_UESM_Pos (1U) â USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) ã USART_CR1_UESM USART_CR1_UESM_Msk ä USART_CR1_RE_Pos (2U) å USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) æ USART_CR1_RE USART_CR1_RE_Msk ç USART_CR1_TE_Pos (3U) è USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) é USART_CR1_TE USART_CR1_TE_Msk ê USART_CR1_IDLEIE_Pos (4U) ë USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) ì USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk í USART_CR1_RXNEIE_RXFNEIE_Pos (5U) î USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) ï USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk ð USART_CR1_TCIE_Pos (6U) ñ USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) ò USART_CR1_TCIE USART_CR1_TCIE_Msk ó USART_CR1_TXEIE_TXFNFIE_Pos (7U) ô USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) õ USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk ö USART_CR1_PEIE_Pos (8U) ÷ USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) ø USART_CR1_PEIE USART_CR1_PEIE_Msk ù USART_CR1_PS_Pos (9U) ú USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) û USART_CR1_PS USART_CR1_PS_Msk ü USART_CR1_PCE_Pos (10U) ý USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) þ USART_CR1_PCE USART_CR1_PCE_Msk ÿ USART_CR1_WAKE_Pos (11U) ¡USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) ¡USART_CR1_WAKE USART_CR1_WAKE_Msk ¡USART_CR1_M_Pos (12U) ¡USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) ¡USART_CR1_M USART_CR1_M_Msk
¡USART_CR1_M0_Pos (12U) ¡USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) ¡USART_CR1_M0 USART_CR1_M0_Msk ¡USART_CR1_MME_Pos (13U) ¡USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) ¡USART_CR1_MME USART_CR1_MME_Msk ¡USART_CR1_CMIE_Pos (14U) ¡USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) ¡USART_CR1_CMIE USART_CR1_CMIE_Msk ¡USART_CR1_OVER8_Pos (15U) ¡USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) ¡USART_CR1_OVER8 USART_CR1_OVER8_Msk ¡USART_CR1_DEDT_Pos (16U) ¡USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) ¡USART_CR1_DEDT USART_CR1_DEDT_Msk ¡USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) ¡USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) ¡USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) ¡USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) ¡USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) ¡USART_CR1_DEAT_Pos (21U) ¡USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) ¡USART_CR1_DEAT USART_CR1_DEAT_Msk ¡USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) ¡USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) ¡USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) ¡USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) ¡USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) ¡¡USART_CR1_RTOIE_Pos (26U) ¢¡USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) £¡USART_CR1_RTOIE USART_CR1_RTOIE_Msk ¤¡USART_CR1_EOBIE_Pos (27U) ¥¡USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) ¦¡USART_CR1_EOBIE USART_CR1_EOBIE_Msk §¡USART_CR1_M1_Pos (28U) ¨¡USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) ©¡USART_CR1_M1 USART_CR1_M1_Msk ª¡USART_CR1_FIFOEN_Pos (29U) «¡USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) ¬¡USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk ¡USART_CR1_TXFEIE_Pos (30U) ®¡USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) ¯¡USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk °¡USART_CR1_RXFFIE_Pos (31U) ±¡USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) ²¡USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk µ¡USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE ¶¡USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE ¹¡USART_CR2_SLVEN_Pos (0U) º¡USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) »¡USART_CR2_SLVEN USART_CR2_SLVEN_Msk ¼¡USART_CR2_DIS_NSS_Pos (3U) ½¡USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) ¾¡USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk ¿¡USART_CR2_ADDM7_Pos (4U) À¡USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) Á¡USART_CR2_ADDM7 USART_CR2_ADDM7_Msk ¡USART_CR2_LBDL_Pos (5U) áUSART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) Ä¡USART_CR2_LBDL USART_CR2_LBDL_Msk Å¡USART_CR2_LBDIE_Pos (6U) Æ¡USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) Ç¡USART_CR2_LBDIE USART_CR2_LBDIE_Msk È¡USART_CR2_LBCL_Pos (8U) É¡USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) Ê¡USART_CR2_LBCL USART_CR2_LBCL_Msk Ë¡USART_CR2_CPHA_Pos (9U) Ì¡USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) Í¡USART_CR2_CPHA USART_CR2_CPHA_Msk ΡUSART_CR2_CPOL_Pos (10U) Ï¡USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) СUSART_CR2_CPOL USART_CR2_CPOL_Msk Ñ¡USART_CR2_CLKEN_Pos (11U) Ò¡USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) Ó¡USART_CR2_CLKEN USART_CR2_CLKEN_Msk Ô¡USART_CR2_STOP_Pos (12U) Õ¡USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) Ö¡USART_CR2_STOP USART_CR2_STOP_Msk סUSART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) Ø¡USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) Ù¡USART_CR2_LINEN_Pos (14U) Ú¡USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) Û¡USART_CR2_LINEN USART_CR2_LINEN_Msk Ü¡USART_CR2_SWAP_Pos (15U) Ý¡USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) Þ¡USART_CR2_SWAP USART_CR2_SWAP_Msk ß¡USART_CR2_RXINV_Pos (16U) à¡USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) á¡USART_CR2_RXINV USART_CR2_RXINV_Msk â¡USART_CR2_TXINV_Pos (17U) ã¡USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) ä¡USART_CR2_TXINV USART_CR2_TXINV_Msk å¡USART_CR2_DATAINV_Pos (18U) æ¡USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) ç¡USART_CR2_DATAINV USART_CR2_DATAINV_Msk è¡USART_CR2_MSBFIRST_Pos (19U) é¡USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) ê¡USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk ë¡USART_CR2_ABREN_Pos (20U) ì¡USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) í¡USART_CR2_ABREN USART_CR2_ABREN_Msk î¡USART_CR2_ABRMODE_Pos (21U) ï¡USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) ð¡USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk ñ¡USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) ò¡USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) ó¡USART_CR2_RTOEN_Pos (23U) ô¡USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) õ¡USART_CR2_RTOEN USART_CR2_RTOEN_Msk ö¡USART_CR2_ADD_Pos (24U) ÷¡USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) ø¡USART_CR2_ADD USART_CR2_ADD_Msk û¡USART_CR3_EIE_Pos (0U) ü¡USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) ý¡USART_CR3_EIE USART_CR3_EIE_Msk þ¡USART_CR3_IREN_Pos (1U) ÿ¡USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) ¢USART_CR3_IREN USART_CR3_IREN_Msk ¢USART_CR3_IRLP_Pos (2U) ¢USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) ¢USART_CR3_IRLP USART_CR3_IRLP_Msk ¢USART_CR3_HDSEL_Pos (3U)
¢USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) ¢USART_CR3_HDSEL USART_CR3_HDSEL_Msk ¢USART_CR3_NACK_Pos (4U) ¢USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) ¢USART_CR3_NACK USART_CR3_NACK_Msk ¢USART_CR3_SCEN_Pos (5U) ¢USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) ¢USART_CR3_SCEN USART_CR3_SCEN_Msk ¢USART_CR3_DMAR_Pos (6U) ¢USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) ¢USART_CR3_DMAR USART_CR3_DMAR_Msk ¢USART_CR3_DMAT_Pos (7U) ¢USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) ¢USART_CR3_DMAT USART_CR3_DMAT_Msk ¢USART_CR3_RTSE_Pos (8U) ¢USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) ¢USART_CR3_RTSE USART_CR3_RTSE_Msk ¢USART_CR3_CTSE_Pos (9U) ¢USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) ¢USART_CR3_CTSE USART_CR3_CTSE_Msk ¢USART_CR3_CTSIE_Pos (10U) ¢USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) ¢USART_CR3_CTSIE USART_CR3_CTSIE_Msk ¢USART_CR3_ONEBIT_Pos (11U) ¢USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) ¢USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk ¢USART_CR3_OVRDIS_Pos (12U) ¢USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) ¡¢USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk ¢¢USART_CR3_DDRE_Pos (13U) £¢USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) ¤¢USART_CR3_DDRE USART_CR3_DDRE_Msk ¥¢USART_CR3_DEM_Pos (14U) ¦¢USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) §¢USART_CR3_DEM USART_CR3_DEM_Msk ¨¢USART_CR3_DEP_Pos (15U) ©¢USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) ª¢USART_CR3_DEP USART_CR3_DEP_Msk «¢USART_CR3_SCARCNT_Pos (17U) ¬¢USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) ¢USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk ®¢USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) ¯¢USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) °¢USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) ±¢USART_CR3_WUS_Pos (20U) ²¢USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) ³¢USART_CR3_WUS USART_CR3_WUS_Msk ´¢USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) µ¢USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) ¶¢USART_CR3_WUFIE_Pos (22U) ·¢USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) ¸¢USART_CR3_WUFIE USART_CR3_WUFIE_Msk ¹¢USART_CR3_TXFTIE_Pos (23U) º¢USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) »¢USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk ¼¢USART_CR3_TCBGTIE_Pos (24U) ½¢USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) ¾¢USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk ¿¢USART_CR3_RXFTCFG_Pos (25U) À¢USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) Á¢USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk ¢USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) âUSART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) Ä¢USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) Å¢USART_CR3_RXFTIE_Pos (28U) Æ¢USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) Ç¢USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk È¢USART_CR3_TXFTCFG_Pos (29U) É¢USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) Ê¢USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk Ë¢USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) Ì¢USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) Í¢USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) ТUSART_BRR_DIV_FRACTION_Pos (0U) Ñ¢USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) Ò¢USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk Ó¢USART_BRR_DIV_MANTISSA_Pos (4U) Ô¢USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) Õ¢USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk Ø¢USART_GTPR_PSC_Pos (0U) Ù¢USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) Ú¢USART_GTPR_PSC USART_GTPR_PSC_Msk Û¢USART_GTPR_GT_Pos (8U) Ü¢USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) Ý¢USART_GTPR_GT USART_GTPR_GT_Msk à¢USART_RTOR_RTO_Pos (0U) á¢USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) â¢USART_RTOR_RTO USART_RTOR_RTO_Msk ã¢USART_RTOR_BLEN_Pos (24U) ä¢USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) å¢USART_RTOR_BLEN USART_RTOR_BLEN_Msk è¢USART_RQR_ABRRQ_Pos (0U) é¢USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) ê¢USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk ë¢USART_RQR_SBKRQ_Pos (1U) ì¢USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) í¢USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk î¢USART_RQR_MMRQ_Pos (2U) ï¢USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) ð¢USART_RQR_MMRQ USART_RQR_MMRQ_Msk ñ¢USART_RQR_RXFRQ_Pos (3U) ò¢USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) ó¢USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk ô¢USART_RQR_TXFRQ_Pos (4U) õ¢USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) ö¢USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk ù¢USART_ISR_PE_Pos (0U) ú¢USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) û¢USART_ISR_PE USART_ISR_PE_Msk ü¢USART_ISR_FE_Pos (1U) ý¢USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) þ¢USART_ISR_FE USART_ISR_FE_Msk ÿ¢USART_ISR_NE_Pos (2U) £USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) £USART_ISR_NE USART_ISR_NE_Msk £USART_ISR_ORE_Pos (3U) £USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) £USART_ISR_ORE USART_ISR_ORE_Msk
£USART_ISR_IDLE_Pos (4U) £USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) £USART_ISR_IDLE USART_ISR_IDLE_Msk £USART_ISR_RXNE_RXFNE_Pos (5U) £USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) £USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk £USART_ISR_TC_Pos (6U) £USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) £USART_ISR_TC USART_ISR_TC_Msk £USART_ISR_TXE_TXFNF_Pos (7U) £USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) £USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk £USART_ISR_LBDF_Pos (8U) £USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) £USART_ISR_LBDF USART_ISR_LBDF_Msk £USART_ISR_CTSIF_Pos (9U) £USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) £USART_ISR_CTSIF USART_ISR_CTSIF_Msk £USART_ISR_CTS_Pos (10U) £USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) £USART_ISR_CTS USART_ISR_CTS_Msk £USART_ISR_RTOF_Pos (11U) £USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) £USART_ISR_RTOF USART_ISR_RTOF_Msk £USART_ISR_EOBF_Pos (12U) £USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) £USART_ISR_EOBF USART_ISR_EOBF_Msk £USART_ISR_UDR_Pos (13U) ¡£USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) ¢£USART_ISR_UDR USART_ISR_UDR_Msk ££USART_ISR_ABRE_Pos (14U) ¤£USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) ¥£USART_ISR_ABRE USART_ISR_ABRE_Msk ¦£USART_ISR_ABRF_Pos (15U) §£USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) ¨£USART_ISR_ABRF USART_ISR_ABRF_Msk ©£USART_ISR_BUSY_Pos (16U) ª£USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) «£USART_ISR_BUSY USART_ISR_BUSY_Msk ¬£USART_ISR_CMF_Pos (17U) £USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) ®£USART_ISR_CMF USART_ISR_CMF_Msk ¯£USART_ISR_SBKF_Pos (18U) °£USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) ±£USART_ISR_SBKF USART_ISR_SBKF_Msk ²£USART_ISR_RWU_Pos (19U) ³£USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) ´£USART_ISR_RWU USART_ISR_RWU_Msk µ£USART_ISR_WUF_Pos (20U) ¶£USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) ·£USART_ISR_WUF USART_ISR_WUF_Msk ¸£USART_ISR_TEACK_Pos (21U) ¹£USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) º£USART_ISR_TEACK USART_ISR_TEACK_Msk »£USART_ISR_REACK_Pos (22U) ¼£USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) ½£USART_ISR_REACK USART_ISR_REACK_Msk ¾£USART_ISR_TXFE_Pos (23U) ¿£USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) À£USART_ISR_TXFE USART_ISR_TXFE_Msk Á£USART_ISR_RXFF_Pos (24U) £USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) ãUSART_ISR_RXFF USART_ISR_RXFF_Msk Ä£USART_ISR_TCBGT_Pos (25U) Å£USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) Æ£USART_ISR_TCBGT USART_ISR_TCBGT_Msk Ç£USART_ISR_RXFT_Pos (26U) È£USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) É£USART_ISR_RXFT USART_ISR_RXFT_Msk Ê£USART_ISR_TXFT_Pos (27U) Ë£USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) Ì£USART_ISR_TXFT USART_ISR_TXFT_Msk Ï£USART_ICR_PECF_Pos (0U) УUSART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) Ñ£USART_ICR_PECF USART_ICR_PECF_Msk Ò£USART_ICR_FECF_Pos (1U) Ó£USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) Ô£USART_ICR_FECF USART_ICR_FECF_Msk Õ£USART_ICR_NECF_Pos (2U) Ö£USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) ×£USART_ICR_NECF USART_ICR_NECF_Msk Ø£USART_ICR_ORECF_Pos (3U) Ù£USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) Ú£USART_ICR_ORECF USART_ICR_ORECF_Msk Û£USART_ICR_IDLECF_Pos (4U) Ü£USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) Ý£USART_ICR_IDLECF USART_ICR_IDLECF_Msk Þ£USART_ICR_TXFECF_Pos (5U) ߣUSART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) à£USART_ICR_TXFECF USART_ICR_TXFECF_Msk á£USART_ICR_TCCF_Pos (6U) â£USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) ã£USART_ICR_TCCF USART_ICR_TCCF_Msk ä£USART_ICR_TCBGTCF_Pos (7U) å£USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) æ£USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk ç£USART_ICR_LBDCF_Pos (8U) è£USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) é£USART_ICR_LBDCF USART_ICR_LBDCF_Msk ê£USART_ICR_CTSCF_Pos (9U) ë£USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) ì£USART_ICR_CTSCF USART_ICR_CTSCF_Msk í£USART_ICR_RTOCF_Pos (11U) î£USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) ï£USART_ICR_RTOCF USART_ICR_RTOCF_Msk ð£USART_ICR_EOBCF_Pos (12U) ñ£USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) ò£USART_ICR_EOBCF USART_ICR_EOBCF_Msk ó£USART_ICR_UDRCF_Pos (13U) ô£USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) õ£USART_ICR_UDRCF USART_ICR_UDRCF_Msk ö£USART_ICR_CMCF_Pos (17U) ÷£USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) ø£USART_ICR_CMCF USART_ICR_CMCF_Msk ù£USART_ICR_WUCF_Pos (20U) ú£USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) û£USART_ICR_WUCF USART_ICR_WUCF_Msk þ£USART_RDR_RDR_Pos (0U) ÿ£USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) ¤USART_RDR_RDR USART_RDR_RDR_Msk ¤USART_TDR_TDR_Pos (0U) ¤USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
¤USART_TDR_TDR USART_TDR_TDR_Msk ¤USART_PRESC_PRESCALER_Pos (0U) ¤USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) ¤USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk ¤USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) ¤USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) ¤USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) ¤USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) ¤SWPMI_CR_RXDMA_Pos (0U) ¤SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) ¤SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk ¤SWPMI_CR_TXDMA_Pos (1U) ¤SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) ¤SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk ¤SWPMI_CR_RXMODE_Pos (2U) ¤SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) ¤SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk ¤SWPMI_CR_TXMODE_Pos (3U) ¡¤SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) ¢¤SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk £¤SWPMI_CR_LPBK_Pos (4U) ¤¤SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) ¥¤SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk ¦¤SWPMI_CR_SWPACT_Pos (5U) §¤SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) ¨¤SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk ©¤SWPMI_CR_DEACT_Pos (10U) ª¤SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) «¤SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk ¬¤SWPMI_CR_SWPEN_Pos (11U) ¤SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) ®¤SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk ±¤SWPMI_BRR_BR_Pos (0U) ²¤SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) ³¤SWPMI_BRR_BR SWPMI_BRR_BR_Msk ¶¤SWPMI_ISR_RXBFF_Pos (0U) ·¤SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) ¸¤SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk ¹¤SWPMI_ISR_TXBEF_Pos (1U) º¤SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) »¤SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk ¼¤SWPMI_ISR_RXBERF_Pos (2U) ½¤SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) ¾¤SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk ¿¤SWPMI_ISR_RXOVRF_Pos (3U) À¤SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) Á¤SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk ¤SWPMI_ISR_TXUNRF_Pos (4U) äSWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) ĤSWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk ŤSWPMI_ISR_RXNE_Pos (5U) ƤSWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) ǤSWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk ȤSWPMI_ISR_TXE_Pos (6U) ɤSWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) ʤSWPMI_ISR_TXE SWPMI_ISR_TXE_Msk ˤSWPMI_ISR_TCF_Pos (7U) ̤SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) ͤSWPMI_ISR_TCF SWPMI_ISR_TCF_Msk ΤSWPMI_ISR_SRF_Pos (8U) ϤSWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) ФSWPMI_ISR_SRF SWPMI_ISR_SRF_Msk ѤSWPMI_ISR_SUSP_Pos (9U) Ò¤SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) Ó¤SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk Ô¤SWPMI_ISR_DEACTF_Pos (10U) Õ¤SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) Ö¤SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk פSWPMI_ISR_RDYF_Pos (11U) ؤSWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) Ù¤SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk ܤSWPMI_ICR_CRXBFF_Pos (0U) ݤSWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) Þ¤SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk ߤSWPMI_ICR_CTXBEF_Pos (1U) à¤SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) á¤SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk â¤SWPMI_ICR_CRXBERF_Pos (2U) ã¤SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) ä¤SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk å¤SWPMI_ICR_CRXOVRF_Pos (3U) æ¤SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) ç¤SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk è¤SWPMI_ICR_CTXUNRF_Pos (4U) é¤SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) ê¤SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk ë¤SWPMI_ICR_CTCF_Pos (7U) ì¤SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) í¤SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk î¤SWPMI_ICR_CSRF_Pos (8U) ï¤SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) ð¤SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk ñ¤SWPMI_ICR_CRDYF_Pos (11U) ò¤SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) ó¤SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk ö¤SWPMI_IER_RXBFIE_Pos (0U) ÷¤SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) ø¤SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk ù¤SWPMI_IER_TXBEIE_Pos (1U) ú¤SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) û¤SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk ü¤SWPMI_IER_RXBERIE_Pos (2U) ý¤SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) þ¤SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk ÿ¤SWPMI_IER_RXOVRIE_Pos (3U) ¥SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) ¥SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk ¥SWPMI_IER_TXUNRIE_Pos (4U) ¥SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) ¥SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
¥SWPMI_IER_RIE_Pos (5U) ¥SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) ¥SWPMI_IER_RIE SWPMI_IER_RIE_Msk ¥SWPMI_IER_TIE_Pos (6U) ¥SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) ¥SWPMI_IER_TIE SWPMI_IER_TIE_Msk ¥SWPMI_IER_TCIE_Pos (7U) ¥SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) ¥SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk ¥SWPMI_IER_SRIE_Pos (8U) ¥SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) ¥SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk ¥SWPMI_IER_RDYIE_Pos (11U) ¥SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) ¥SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk ¥SWPMI_RFL_RFL_Pos (0U) ¥SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) ¥SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk ¥SWPMI_RFL_RFL_0_1 (0x00000003U) ¥SWPMI_TDR_TD_Pos (0U) ¥SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) ¥SWPMI_TDR_TD SWPMI_TDR_TD_Msk ¡¥SWPMI_RDR_RD_Pos (0U) ¢¥SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) £¥SWPMI_RDR_RD SWPMI_RDR_RD_Msk §¥SWPMI_OR_TBYP_Pos (0U) ¨¥SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) ©¥SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk ª¥SWPMI_OR_CLASS_Pos (1U) «¥SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) ¬¥SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk ´¥WWDG_CR_T_Pos (0U) µ¥WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) ¶¥WWDG_CR_T WWDG_CR_T_Msk ·¥WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) ¸¥WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) ¹¥WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) º¥WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) »¥WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) ¼¥WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) ½¥WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) ¿¥WWDG_CR_WDGA_Pos (7U) À¥WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) Á¥WWDG_CR_WDGA WWDG_CR_WDGA_Msk Ä¥WWDG_CFR_W_Pos (0U) Å¥WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) Æ¥WWDG_CFR_W WWDG_CFR_W_Msk Ç¥WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) È¥WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) É¥WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) Ê¥WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) Ë¥WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) Ì¥WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) Í¥WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) Ï¥WWDG_CFR_EWI_Pos (9U) Ð¥WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) Ñ¥WWDG_CFR_EWI WWDG_CFR_EWI_Msk Ó¥WWDG_CFR_WDGTB_Pos (11U) Ô¥WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) Õ¥WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk Ö¥WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) ×¥WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) Ø¥WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) Û¥WWDG_SR_EWIF_Pos (0U) Ü¥WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) Ý¥WWDG_SR_EWIF WWDG_SR_EWIF_Msk æ¥STM32H7_DEV_ID 0x450UL é¥DBGMCU_IDCODE_DEV_ID_Pos (0U) ê¥DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) ë¥DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk ì¥DBGMCU_IDCODE_REV_ID_Pos (16U) í¥DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) î¥DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk ñ¥DBGMCU_CR_DBG_SLEEPD1_Pos (0U) ò¥DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) ó¥DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk ô¥DBGMCU_CR_DBG_STOPD1_Pos (1U) õ¥DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) ö¥DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk ÷¥DBGMCU_CR_DBG_STANDBYD1_Pos (2U) ø¥DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) ù¥DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk ú¥DBGMCU_CR_DBG_TRACECKEN_Pos (20U) û¥DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) ü¥DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk ý¥DBGMCU_CR_DBG_CKD1EN_Pos (21U) þ¥DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) ÿ¥DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk ¦DBGMCU_CR_DBG_CKD3EN_Pos (22U) ¦DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) ¦DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk ¦DBGMCU_CR_DBG_TRGOEN_Pos (28U) ¦DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
¦DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk ¦DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U) ¦DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) ¦DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U) ¦DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U) ¦DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U) ¦DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U) ¦DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U) ¦DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U) ¦DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk ¦DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U) ¦DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) ¦DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk ¡¦DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U) ¢¦DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) £¦DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk ¤¦DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U) ¥¦DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) ¦¦DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk §¦DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U) ¨¦DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) ©¦DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk ª¦DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U) «¦DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) ¬¦DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk ¦DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U) ®¦DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) ¯¦DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk °¦DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U) ±¦DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) ²¦DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk µ¦DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U) ¶¦DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) ·¦DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk ¹¦DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U) º¦DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) »¦DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk ¼¦DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U) ½¦DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) ¾¦DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk ¿¦DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U) À¦DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) Á¦DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk ¦DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U) æDBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) ĦDBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk ŦDBGMCU_APB2FZ1_DBG_TIM17_Pos (18U) ƦDBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) ǦDBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk ȦDBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U) ɦDBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) ʦDBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk ͦDBGMCU_APB4FZ1_DBG_I2C4_Pos (7U) ΦDBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) ϦDBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk ЦDBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U) ѦDBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) Ò¦DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk Ó¦DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U) Ô¦DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) Õ¦DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk Ö¦DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U) צDBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) ئDBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk Ù¦DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U) Ú¦DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) Û¦DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk ܦDBGMCU_APB4FZ1_DBG_RTC_Pos (16U) ݦDBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) Þ¦DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk ߦDBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U) à¦DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) á¦DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk è¦HRTIM_MCR_CK_PSC_Pos (0U) é¦HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) ê¦HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk ë¦HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) ì¦HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) í¦HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) ï¦HRTIM_MCR_CONT_Pos (3U) ð¦HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) ñ¦HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk ò¦HRTIM_MCR_RETRIG_Pos (4U) ó¦HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) ô¦HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk õ¦HRTIM_MCR_HALF_Pos (5U) ö¦HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) ÷¦HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk ù¦HRTIM_MCR_SYNC_IN_Pos (8U) ú¦HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) û¦HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk ü¦HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) ý¦HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) þ¦HRTIM_MCR_SYNCRSTM_Pos (10U) ÿ¦HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) §HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk §HRTIM_MCR_SYNCSTRTM_Pos (11U) §HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) §HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk §HRTIM_MCR_SYNC_OUT_Pos (12U)
§HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) §HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk §HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) §HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) §HRTIM_MCR_SYNC_SRC_Pos (14U) §HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) §HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk §HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) §HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) §HRTIM_MCR_MCEN_Pos (16U) §HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) §HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk §HRTIM_MCR_TACEN_Pos (17U) §HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) §HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk §HRTIM_MCR_TBCEN_Pos (18U) §HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) §HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk §HRTIM_MCR_TCCEN_Pos (19U) §HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) §HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk §HRTIM_MCR_TDCEN_Pos (20U) §HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) §HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk §HRTIM_MCR_TECEN_Pos (21U) §HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) §HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk ¢§HRTIM_MCR_DACSYNC_Pos (25U) £§HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) ¤§HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk ¥§HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) ¦§HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) ¨§HRTIM_MCR_PREEN_Pos (27U) ©§HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) ª§HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk «§HRTIM_MCR_MREPU_Pos (29U) ¬§HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) §HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk ¯§HRTIM_MCR_BRSTDMA_Pos (30U) °§HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) ±§HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk ²§HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) ³§HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) ¶§HRTIM_MISR_MCMP1_Pos (0U) ·§HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) ¸§HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk ¹§HRTIM_MISR_MCMP2_Pos (1U) º§HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) »§HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk ¼§HRTIM_MISR_MCMP3_Pos (2U) ½§HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) ¾§HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk ¿§HRTIM_MISR_MCMP4_Pos (3U) À§HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) Á§HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk §HRTIM_MISR_MREP_Pos (4U) çHRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) ħHRTIM_MISR_MREP HRTIM_MISR_MREP_Msk ŧHRTIM_MISR_SYNC_Pos (5U) ƧHRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) ǧHRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk ȧHRTIM_MISR_MUPD_Pos (6U) ɧHRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) ʧHRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk ͧHRTIM_MICR_MCMP1_Pos (0U) ΧHRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) ϧHRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk ЧHRTIM_MICR_MCMP2_Pos (1U) ѧHRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) Ò§HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk Ó§HRTIM_MICR_MCMP3_Pos (2U) Ô§HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) Õ§HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk Ö§HRTIM_MICR_MCMP4_Pos (3U) קHRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) اHRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk Ù§HRTIM_MICR_MREP_Pos (4U) Ú§HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) Û§HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk ܧHRTIM_MICR_SYNC_Pos (5U) ݧHRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) Þ§HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk ߧHRTIM_MICR_MUPD_Pos (6U) à§HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) á§HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk ä§HRTIM_MDIER_MCMP1IE_Pos (0U) å§HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) æ§HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk ç§HRTIM_MDIER_MCMP2IE_Pos (1U) è§HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) é§HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk ê§HRTIM_MDIER_MCMP3IE_Pos (2U) ë§HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) ì§HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk í§HRTIM_MDIER_MCMP4IE_Pos (3U) î§HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) ï§HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk ð§HRTIM_MDIER_MREPIE_Pos (4U) ñ§HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) ò§HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk ó§HRTIM_MDIER_SYNCIE_Pos (5U) ô§HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) õ§HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk ö§HRTIM_MDIER_MUPDIE_Pos (6U) ÷§HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) ø§HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk ú§HRTIM_MDIER_MCMP1DE_Pos (16U) û§HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) ü§HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk ý§HRTIM_MDIER_MCMP2DE_Pos (17U) þ§HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) ÿ§HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk ¨HRTIM_MDIER_MCMP3DE_Pos (18U) ¨HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) ¨HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk ¨HRTIM_MDIER_MCMP4DE_Pos (19U) ¨HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)
¨HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk ¨HRTIM_MDIER_MREPDE_Pos (20U) ¨HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) ¨HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk ¨HRTIM_MDIER_SYNCDE_Pos (21U) ¨HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) ¨HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk ¨HRTIM_MDIER_MUPDDE_Pos (22U) ¨HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) ¨HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk ¨HRTIM_MCNTR_MCNTR_Pos (0U) ¨HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) ¨HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk ¨HRTIM_MPER_MPER_Pos (0U) ¨HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) ¨HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk ¨HRTIM_MREP_MREP_Pos (0U) ¨HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) ¨HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk ¨HRTIM_MCMP1R_MCMP1R_Pos (0U) ¡¨HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) ¢¨HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk ¥¨HRTIM_MCMP1R_MCMP2R_Pos (0U) ¦¨HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) §¨HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk ª¨HRTIM_MCMP1R_MCMP3R_Pos (0U) «¨HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) ¬¨HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk ¯¨HRTIM_MCMP1R_MCMP4R_Pos (0U) °¨HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) ±¨HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk ´¨HRTIM_TIMCR_CK_PSC_Pos (0U) µ¨HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) ¶¨HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk ·¨HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) ¸¨HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) ¹¨HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) »¨HRTIM_TIMCR_CONT_Pos (3U) ¼¨HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) ½¨HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk ¾¨HRTIM_TIMCR_RETRIG_Pos (4U) ¿¨HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) À¨HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk Á¨HRTIM_TIMCR_HALF_Pos (5U) ¨HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) èHRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk ĨHRTIM_TIMCR_PSHPLL_Pos (6U) ŨHRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) ƨHRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk ȨHRTIM_TIMCR_SYNCRST_Pos (10U) ɨHRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) ʨHRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk ˨HRTIM_TIMCR_SYNCSTRT_Pos (11U) ̨HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) ͨHRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk ϨHRTIM_TIMCR_DELCMP2_Pos (12U) ШHRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) ѨHRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk Ò¨HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) Ó¨HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) Ô¨HRTIM_TIMCR_DELCMP4_Pos (14U) Õ¨HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) Ö¨HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk רHRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) بHRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) Ú¨HRTIM_TIMCR_TREPU_Pos (17U) Û¨HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) ܨHRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk ݨHRTIM_TIMCR_TRSTU_Pos (18U) Þ¨HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) ߨHRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk à¨HRTIM_TIMCR_TAU_Pos (19U) á¨HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) â¨HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk ã¨HRTIM_TIMCR_TBU_Pos (20U) ä¨HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) å¨HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk æ¨HRTIM_TIMCR_TCU_Pos (21U) ç¨HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) è¨HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk é¨HRTIM_TIMCR_TDU_Pos (22U) ê¨HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) ë¨HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk ì¨HRTIM_TIMCR_TEU_Pos (23U) í¨HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) î¨HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk ï¨HRTIM_TIMCR_MSTU_Pos (24U) ð¨HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) ñ¨HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk ó¨HRTIM_TIMCR_DACSYNC_Pos (25U) ô¨HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) õ¨HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk ö¨HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) ÷¨HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) ø¨HRTIM_TIMCR_PREEN_Pos (27U) ù¨HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) ú¨HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk ü¨HRTIM_TIMCR_UPDGAT_Pos (28U) ý¨HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) þ¨HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk ÿ¨HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) ©HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) ©HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) ©HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)
©HRTIM_TIMISR_CMP1_Pos (0U) ©HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) ©HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk ©HRTIM_TIMISR_CMP2_Pos (1U) ©HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) ©HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk ©HRTIM_TIMISR_CMP3_Pos (2U) ©HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) ©HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk ©HRTIM_TIMISR_CMP4_Pos (3U) ©HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) ©HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk ©HRTIM_TIMISR_REP_Pos (4U) ©HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) ©HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk ©HRTIM_TIMISR_UPD_Pos (6U) ©HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) ©HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk ©HRTIM_TIMISR_CPT1_Pos (7U) ©HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) ©HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk ©HRTIM_TIMISR_CPT2_Pos (8U) ©HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) ©HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk ©HRTIM_TIMISR_SET1_Pos (9U) ©HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) ©HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk ©HRTIM_TIMISR_RST1_Pos (10U) ¡©HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) ¢©HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk £©HRTIM_TIMISR_SET2_Pos (11U) ¤©HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) ¥©HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk ¦©HRTIM_TIMISR_RST2_Pos (12U) §©HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) ¨©HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk ©©HRTIM_TIMISR_RST_Pos (13U) ª©HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) «©HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk ¬©HRTIM_TIMISR_DLYPRT_Pos (14U) ©HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) ®©HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk ¯©HRTIM_TIMISR_CPPSTAT_Pos (16U) °©HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) ±©HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk ²©HRTIM_TIMISR_IPPSTAT_Pos (17U) ³©HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) ´©HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk µ©HRTIM_TIMISR_O1STAT_Pos (18U) ¶©HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) ·©HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk ¸©HRTIM_TIMISR_O2STAT_Pos (19U) ¹©HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) º©HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk »©HRTIM_TIMISR_O1CPY_Pos (20U) ¼©HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) ½©HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk ¾©HRTIM_TIMISR_O2CPY_Pos (21U) ¿©HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) À©HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk éHRTIM_TIMICR_CMP1C_Pos (0U) Ä©HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) Å©HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk Æ©HRTIM_TIMICR_CMP2C_Pos (1U) Ç©HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) È©HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk É©HRTIM_TIMICR_CMP3C_Pos (2U) Ê©HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) Ë©HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk Ì©HRTIM_TIMICR_CMP4C_Pos (3U) Í©HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) ΩHRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk Ï©HRTIM_TIMICR_REPC_Pos (4U) ЩHRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) Ñ©HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk Ò©HRTIM_TIMICR_UPDC_Pos (6U) Ó©HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) Ô©HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk Õ©HRTIM_TIMICR_CPT1C_Pos (7U) Ö©HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) שHRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk Ø©HRTIM_TIMICR_CPT2C_Pos (8U) Ù©HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) Ú©HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk Û©HRTIM_TIMICR_SET1C_Pos (9U) Ü©HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) Ý©HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk Þ©HRTIM_TIMICR_RST1C_Pos (10U) ß©HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) à©HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk á©HRTIM_TIMICR_SET2C_Pos (11U) â©HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) ã©HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk ä©HRTIM_TIMICR_RST2C_Pos (12U) å©HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) æ©HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk ç©HRTIM_TIMICR_RSTC_Pos (13U) è©HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) é©HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk ê©HRTIM_TIMICR_DLYPRTC_Pos (14U) ë©HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) ì©HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk ï©HRTIM_TIMDIER_CMP1IE_Pos (0U) ð©HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) ñ©HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk ò©HRTIM_TIMDIER_CMP2IE_Pos (1U) ó©HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) ô©HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk õ©HRTIM_TIMDIER_CMP3IE_Pos (2U) ö©HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) ÷©HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk ø©HRTIM_TIMDIER_CMP4IE_Pos (3U) ù©HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) ú©HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk û©HRTIM_TIMDIER_REPIE_Pos (4U) ü©HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) ý©HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk þ©HRTIM_TIMDIER_UPDIE_Pos (6U) ÿ©HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) ªHRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk ªHRTIM_TIMDIER_CPT1IE_Pos (7U) ªHRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) ªHRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk ªHRTIM_TIMDIER_CPT2IE_Pos (8U)
ªHRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) ªHRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk ªHRTIM_TIMDIER_SET1IE_Pos (9U) ªHRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) ªHRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk ªHRTIM_TIMDIER_RST1IE_Pos (10U) ªHRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) ªHRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk ªHRTIM_TIMDIER_SET2IE_Pos (11U) ªHRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) ªHRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk ªHRTIM_TIMDIER_RST2IE_Pos (12U) ªHRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) ªHRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk ªHRTIM_TIMDIER_RSTIE_Pos (13U) ªHRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) ªHRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk ªHRTIM_TIMDIER_DLYPRTIE_Pos (14U) ªHRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) ªHRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk ªHRTIM_TIMDIER_CMP1DE_Pos (16U) ªHRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) ªHRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk ªHRTIM_TIMDIER_CMP2DE_Pos (17U) ªHRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) ªHRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk ªHRTIM_TIMDIER_CMP3DE_Pos (18U) ¡ªHRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) ¢ªHRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk £ªHRTIM_TIMDIER_CMP4DE_Pos (19U) ¤ªHRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) ¥ªHRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk ¦ªHRTIM_TIMDIER_REPDE_Pos (20U) §ªHRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) ¨ªHRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk ©ªHRTIM_TIMDIER_UPDDE_Pos (22U) ªªHRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) «ªHRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk ¬ªHRTIM_TIMDIER_CPT1DE_Pos (23U) ªHRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) ®ªHRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk ¯ªHRTIM_TIMDIER_CPT2DE_Pos (24U) °ªHRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) ±ªHRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk ²ªHRTIM_TIMDIER_SET1DE_Pos (25U) ³ªHRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) ´ªHRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk µªHRTIM_TIMDIER_RST1DE_Pos (26U) ¶ªHRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) ·ªHRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk ¸ªHRTIM_TIMDIER_SET2DE_Pos (27U) ¹ªHRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) ºªHRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk »ªHRTIM_TIMDIER_RST2DE_Pos (28U) ¼ªHRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) ½ªHRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk ¾ªHRTIM_TIMDIER_RSTDE_Pos (29U) ¿ªHRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) ÀªHRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk ÁªHRTIM_TIMDIER_DLYPRTDE_Pos (30U) ªHRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) êHRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk ƪHRTIM_CNTR_CNTR_Pos (0U) ǪHRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) ȪHRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk ˪HRTIM_PER_PER_Pos (0U) ̪HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) ͪHRTIM_PER_PER HRTIM_PER_PER_Msk ЪHRTIM_REP_REP_Pos (0U) ѪHRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) ÒªHRTIM_REP_REP HRTIM_REP_REP_Msk ÕªHRTIM_CMP1R_CMP1R_Pos (0U) ÖªHRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) תHRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk ÚªHRTIM_CMP1CR_CMP1CR_Pos (0U) ÛªHRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) ܪHRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk ߪHRTIM_CMP2R_CMP2R_Pos (0U) àªHRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) áªHRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk äªHRTIM_CMP3R_CMP3R_Pos (0U) åªHRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) æªHRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk éªHRTIM_CMP4R_CMP4R_Pos (0U) êªHRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) ëªHRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk îªHRTIM_CPT1R_CPT1R_Pos (0U) ïªHRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) ðªHRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk óªHRTIM_CPT2R_CPT2R_Pos (0U) ôªHRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) õªHRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk øªHRTIM_DTR_DTR_Pos (0U) ùªHRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) úªHRTIM_DTR_DTR HRTIM_DTR_DTR_Msk ûªHRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) üªHRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) ýªHRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) þªHRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) ÿªHRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) «HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) «HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) «HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) «HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) «HRTIM_DTR_SDTR_Pos (9U)
«HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) «HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk «HRTIM_DTR_DTPRSC_Pos (10U) «HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) «HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk «HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) «HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) «HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) «HRTIM_DTR_DTRSLK_Pos (14U) «HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) «HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk «HRTIM_DTR_DTRLK_Pos (15U) «HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) «HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk «HRTIM_DTR_DTF_Pos (16U) «HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk «HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) «HRTIM_DTR_SDTF_Pos (25U) «HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) ¡«HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk ¢«HRTIM_DTR_DTFSLK_Pos (30U) £«HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) ¤«HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk ¥«HRTIM_DTR_DTFLK_Pos (31U) ¦«HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) §«HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk ª«HRTIM_SET1R_SST_Pos (0U) ««HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) ¬«HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk «HRTIM_SET1R_RESYNC_Pos (1U) ®«HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) ¯«HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk °«HRTIM_SET1R_PER_Pos (2U) ±«HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) ²«HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk ³«HRTIM_SET1R_CMP1_Pos (3U) ´«HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) µ«HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk ¶«HRTIM_SET1R_CMP2_Pos (4U) ·«HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) ¸«HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk ¹«HRTIM_SET1R_CMP3_Pos (5U) º«HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) »«HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk ¼«HRTIM_SET1R_CMP4_Pos (6U) ½«HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) ¾«HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk À«HRTIM_SET1R_MSTPER_Pos (7U) Á«HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) «HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk ëHRTIM_SET1R_MSTCMP1_Pos (8U) Ä«HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) Å«HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk Æ«HRTIM_SET1R_MSTCMP2_Pos (9U) Ç«HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) È«HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk É«HRTIM_SET1R_MSTCMP3_Pos (10U) Ê«HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) Ë«HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk Ì«HRTIM_SET1R_MSTCMP4_Pos (11U) Í«HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) ΫHRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk ЫHRTIM_SET1R_TIMEVNT1_Pos (12U) Ñ«HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) Ò«HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk Ó«HRTIM_SET1R_TIMEVNT2_Pos (13U) Ô«HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) Õ«HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk Ö«HRTIM_SET1R_TIMEVNT3_Pos (14U) ׫HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) Ø«HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk Ù«HRTIM_SET1R_TIMEVNT4_Pos (15U) Ú«HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) Û«HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk Ü«HRTIM_SET1R_TIMEVNT5_Pos (16U) Ý«HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) Þ«HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk ß«HRTIM_SET1R_TIMEVNT6_Pos (17U) à«HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) á«HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk â«HRTIM_SET1R_TIMEVNT7_Pos (18U) ã«HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) ä«HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk å«HRTIM_SET1R_TIMEVNT8_Pos (19U) æ«HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) ç«HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk è«HRTIM_SET1R_TIMEVNT9_Pos (20U) é«HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) ê«HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk ì«HRTIM_SET1R_EXTVNT1_Pos (21U) í«HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) î«HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk ï«HRTIM_SET1R_EXTVNT2_Pos (22U) ð«HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) ñ«HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk ò«HRTIM_SET1R_EXTVNT3_Pos (23U) ó«HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) ô«HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk õ«HRTIM_SET1R_EXTVNT4_Pos (24U) ö«HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) ÷«HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk ø«HRTIM_SET1R_EXTVNT5_Pos (25U) ù«HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) ú«HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk û«HRTIM_SET1R_EXTVNT6_Pos (26U) ü«HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) ý«HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk þ«HRTIM_SET1R_EXTVNT7_Pos (27U) ÿ«HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) ¬HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk ¬HRTIM_SET1R_EXTVNT8_Pos (28U) ¬HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) ¬HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk ¬HRTIM_SET1R_EXTVNT9_Pos (29U)
¬HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) ¬HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk ¬HRTIM_SET1R_EXTVNT10_Pos (30U) ¬HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) ¬HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk ¬HRTIM_SET1R_UPDATE_Pos (31U) ¬HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) ¬HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk ¬HRTIM_RST1R_SRT_Pos (0U) ¬HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) ¬HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk ¬HRTIM_RST1R_RESYNC_Pos (1U) ¬HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) ¬HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk ¬HRTIM_RST1R_PER_Pos (2U) ¬HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) ¬HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk ¬HRTIM_RST1R_CMP1_Pos (3U) ¬HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) ¬HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk ¬HRTIM_RST1R_CMP2_Pos (4U) ¬HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) ¬HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk ¬HRTIM_RST1R_CMP3_Pos (5U) ¬HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) ¡¬HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk ¢¬HRTIM_RST1R_CMP4_Pos (6U) £¬HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) ¤¬HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk ¦¬HRTIM_RST1R_MSTPER_Pos (7U) §¬HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) ¨¬HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk ©¬HRTIM_RST1R_MSTCMP1_Pos (8U) ª¬HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) «¬HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk ¬¬HRTIM_RST1R_MSTCMP2_Pos (9U) ¬HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) ®¬HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk ¯¬HRTIM_RST1R_MSTCMP3_Pos (10U) °¬HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) ±¬HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk ²¬HRTIM_RST1R_MSTCMP4_Pos (11U) ³¬HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) ´¬HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk ¶¬HRTIM_RST1R_TIMEVNT1_Pos (12U) ·¬HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) ¸¬HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk ¹¬HRTIM_RST1R_TIMEVNT2_Pos (13U) º¬HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) »¬HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk ¼¬HRTIM_RST1R_TIMEVNT3_Pos (14U) ½¬HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) ¾¬HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk ¿¬HRTIM_RST1R_TIMEVNT4_Pos (15U) À¬HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) Á¬HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk ¬HRTIM_RST1R_TIMEVNT5_Pos (16U) ìHRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) ĬHRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk ŬHRTIM_RST1R_TIMEVNT6_Pos (17U) ƬHRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) ǬHRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk ȬHRTIM_RST1R_TIMEVNT7_Pos (18U) ɬHRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) ʬHRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk ˬHRTIM_RST1R_TIMEVNT8_Pos (19U) ̬HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) ͬHRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk άHRTIM_RST1R_TIMEVNT9_Pos (20U) ϬHRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) ЬHRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk Ò¬HRTIM_RST1R_EXTVNT1_Pos (21U) Ó¬HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) Ô¬HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk Õ¬HRTIM_RST1R_EXTVNT2_Pos (22U) Ö¬HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) ׬HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk جHRTIM_RST1R_EXTVNT3_Pos (23U) Ù¬HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) Ú¬HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk Û¬HRTIM_RST1R_EXTVNT4_Pos (24U) ܬHRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) ݬHRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk Þ¬HRTIM_RST1R_EXTVNT5_Pos (25U) ߬HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) à¬HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk á¬HRTIM_RST1R_EXTVNT6_Pos (26U) â¬HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) ã¬HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk ä¬HRTIM_RST1R_EXTVNT7_Pos (27U) å¬HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) æ¬HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk ç¬HRTIM_RST1R_EXTVNT8_Pos (28U) è¬HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) é¬HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk ê¬HRTIM_RST1R_EXTVNT9_Pos (29U) ë¬HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) ì¬HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk í¬HRTIM_RST1R_EXTVNT10_Pos (30U) î¬HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) ï¬HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk ñ¬HRTIM_RST1R_UPDATE_Pos (31U) ò¬HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) ó¬HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk ÷¬HRTIM_SET2R_SST_Pos (0U) ø¬HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) ù¬HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk ú¬HRTIM_SET2R_RESYNC_Pos (1U) û¬HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) ü¬HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk ý¬HRTIM_SET2R_PER_Pos (2U) þ¬HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) ÿ¬HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk HRTIM_SET2R_CMP1_Pos (3U) HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk HRTIM_SET2R_CMP2_Pos (4U) HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos)
HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk HRTIM_SET2R_CMP3_Pos (5U) HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk HRTIM_SET2R_CMP4_Pos (6U) HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk HRTIM_SET2R_MSTPER_Pos (7U) HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk HRTIM_SET2R_MSTCMP1_Pos (8U) HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk HRTIM_SET2R_MSTCMP2_Pos (9U) HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk HRTIM_SET2R_MSTCMP3_Pos (10U) HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk HRTIM_SET2R_MSTCMP4_Pos (11U) HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk HRTIM_SET2R_TIMEVNT1_Pos (12U) HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk HRTIM_SET2R_TIMEVNT2_Pos (13U) ¡HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) ¢HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk £HRTIM_SET2R_TIMEVNT3_Pos (14U) ¤HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) ¥HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk ¦HRTIM_SET2R_TIMEVNT4_Pos (15U) §HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) ¨HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk ©HRTIM_SET2R_TIMEVNT5_Pos (16U) ªHRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) «HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk ¬HRTIM_SET2R_TIMEVNT6_Pos (17U) HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) ®HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk ¯HRTIM_SET2R_TIMEVNT7_Pos (18U) °HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) ±HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk ²HRTIM_SET2R_TIMEVNT8_Pos (19U) ³HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) ´HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk µHRTIM_SET2R_TIMEVNT9_Pos (20U) ¶HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) ·HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk ¹HRTIM_SET2R_EXTVNT1_Pos (21U) ºHRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) »HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk ¼HRTIM_SET2R_EXTVNT2_Pos (22U) ½HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) ¾HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk ¿HRTIM_SET2R_EXTVNT3_Pos (23U) ÀHRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) ÁHRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk ÂHRTIM_SET2R_EXTVNT4_Pos (24U) ÃHRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) ÄHRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk ÅHRTIM_SET2R_EXTVNT5_Pos (25U) ÆHRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) ÇHRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk ÈHRTIM_SET2R_EXTVNT6_Pos (26U) ÉHRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) ÊHRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk ËHRTIM_SET2R_EXTVNT7_Pos (27U) ÌHRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) ÍHRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk ÎHRTIM_SET2R_EXTVNT8_Pos (28U) ÏHRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) ÐHRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk ÑHRTIM_SET2R_EXTVNT9_Pos (29U) ÒHRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) ÓHRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk ÔHRTIM_SET2R_EXTVNT10_Pos (30U) ÕHRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) ÖHRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk ØHRTIM_SET2R_UPDATE_Pos (31U) ÙHRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) ÚHRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk ÝHRTIM_RST2R_SRT_Pos (0U) ÞHRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) ßHRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk àHRTIM_RST2R_RESYNC_Pos (1U) áHRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) âHRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk ãHRTIM_RST2R_PER_Pos (2U) äHRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) åHRTIM_RST2R_PER HRTIM_RST2R_PER_Msk æHRTIM_RST2R_CMP1_Pos (3U) çHRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) èHRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk éHRTIM_RST2R_CMP2_Pos (4U) êHRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) ëHRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk ìHRTIM_RST2R_CMP3_Pos (5U) íHRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) îHRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk ïHRTIM_RST2R_CMP4_Pos (6U) ðHRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) ñHRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk óHRTIM_RST2R_MSTPER_Pos (7U) ôHRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) õHRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk öHRTIM_RST2R_MSTCMP1_Pos (8U) ÷HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) øHRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk ùHRTIM_RST2R_MSTCMP2_Pos (9U) úHRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) ûHRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk üHRTIM_RST2R_MSTCMP3_Pos (10U) ýHRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) þHRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk ÿHRTIM_RST2R_MSTCMP4_Pos (11U) ®HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) ®HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk ®HRTIM_RST2R_TIMEVNT1_Pos (12U) ®HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)
®HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk ®HRTIM_RST2R_TIMEVNT2_Pos (13U) ®HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) ®HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk ®HRTIM_RST2R_TIMEVNT3_Pos (14U) ®HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) ®HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk ®HRTIM_RST2R_TIMEVNT4_Pos (15U) ®HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) ®HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk ®HRTIM_RST2R_TIMEVNT5_Pos (16U) ®HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) ®HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk ®HRTIM_RST2R_TIMEVNT6_Pos (17U) ®HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) ®HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk ®HRTIM_RST2R_TIMEVNT7_Pos (18U) ®HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) ®HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk ®HRTIM_RST2R_TIMEVNT8_Pos (19U) ®HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) ®HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk ®HRTIM_RST2R_TIMEVNT9_Pos (20U) ®HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) ®HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk ®HRTIM_RST2R_EXTVNT1_Pos (21U) ®HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) ¡®HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk ¢®HRTIM_RST2R_EXTVNT2_Pos (22U) £®HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) ¤®HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk ¥®HRTIM_RST2R_EXTVNT3_Pos (23U) ¦®HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) §®HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk ¨®HRTIM_RST2R_EXTVNT4_Pos (24U) ©®HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) ª®HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk «®HRTIM_RST2R_EXTVNT5_Pos (25U) ¬®HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) ®HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk ®®HRTIM_RST2R_EXTVNT6_Pos (26U) ¯®HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) °®HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk ±®HRTIM_RST2R_EXTVNT7_Pos (27U) ²®HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) ³®HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk ´®HRTIM_RST2R_EXTVNT8_Pos (28U) µ®HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) ¶®HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk ·®HRTIM_RST2R_EXTVNT9_Pos (29U) ¸®HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) ¹®HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk º®HRTIM_RST2R_EXTVNT10_Pos (30U) »®HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) ¼®HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk ¾®HRTIM_RST2R_UPDATE_Pos (31U) ¿®HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) À®HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk îHRTIM_EEFR1_EE1LTCH_Pos (0U) Ä®HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) Å®HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk Æ®HRTIM_EEFR1_EE1FLTR_Pos (1U) Ç®HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) È®HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk É®HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) Ê®HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) Ë®HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) Ì®HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) ήHRTIM_EEFR1_EE2LTCH_Pos (6U) Ï®HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) ЮHRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk Ñ®HRTIM_EEFR1_EE2FLTR_Pos (7U) Ò®HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) Ó®HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk Ô®HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) Õ®HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) Ö®HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) ×®HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) Ù®HRTIM_EEFR1_EE3LTCH_Pos (12U) Ú®HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) Û®HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk Ü®HRTIM_EEFR1_EE3FLTR_Pos (13U) Ý®HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) Þ®HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk ß®HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) à®HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) á®HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) â®HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) ä®HRTIM_EEFR1_EE4LTCH_Pos (18U) å®HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) æ®HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk ç®HRTIM_EEFR1_EE4FLTR_Pos (19U) è®HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) é®HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk ê®HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) ë®HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) ì®HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) í®HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) ï®HRTIM_EEFR1_EE5LTCH_Pos (24U) ð®HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) ñ®HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk ò®HRTIM_EEFR1_EE5FLTR_Pos (25U) ó®HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) ô®HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk õ®HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) ö®HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) ÷®HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) ø®HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) û®HRTIM_EEFR2_EE6LTCH_Pos (0U) ü®HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) ý®HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk þ®HRTIM_EEFR2_EE6FLTR_Pos (1U) ÿ®HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) ¯HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk ¯HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) ¯HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) ¯HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) ¯HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) ¯HRTIM_EEFR2_EE7LTCH_Pos (6U) ¯HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) ¯HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk ¯HRTIM_EEFR2_EE7FLTR_Pos (7U) ¯HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) ¯HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk ¯HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) ¯HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) ¯HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) ¯HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) ¯HRTIM_EEFR2_EE8LTCH_Pos (12U) ¯HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) ¯HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk ¯HRTIM_EEFR2_EE8FLTR_Pos (13U) ¯HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) ¯HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk ¯HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) ¯HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) ¯HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) ¯HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) ¯HRTIM_EEFR2_EE9LTCH_Pos (18U) ¯HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) ¯HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk ¯HRTIM_EEFR2_EE9FLTR_Pos (19U) ¯HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) ¡¯HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk ¢¯HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) £¯HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) ¤¯HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) ¥¯HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) §¯HRTIM_EEFR2_EE10LTCH_Pos (24U) ¨¯HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) ©¯HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk ª¯HRTIM_EEFR2_EE10FLTR_Pos (25U) «¯HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) ¬¯HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk ¯HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) ®¯HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) ¯¯HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) °¯HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) ³¯HRTIM_RSTR_UPDATE_Pos (1U) ´¯HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) µ¯HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk ¶¯HRTIM_RSTR_CMP2_Pos (2U) ·¯HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) ¸¯HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk ¹¯HRTIM_RSTR_CMP4_Pos (3U) º¯HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) »¯HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk ½¯HRTIM_RSTR_MSTPER_Pos (4U) ¾¯HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) ¿¯HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk À¯HRTIM_RSTR_MSTCMP1_Pos (5U) Á¯HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) ¯HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk ïHRTIM_RSTR_MSTCMP2_Pos (6U) įHRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) ůHRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk ƯHRTIM_RSTR_MSTCMP3_Pos (7U) ǯHRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) ȯHRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk ɯHRTIM_RSTR_MSTCMP4_Pos (8U) ʯHRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) ˯HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk ͯHRTIM_RSTR_EXTEVNT1_Pos (9U) ίHRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) ϯHRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk ЯHRTIM_RSTR_EXTEVNT2_Pos (10U) ѯHRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) Ò¯HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk Ó¯HRTIM_RSTR_EXTEVNT3_Pos (11U) Ô¯HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) Õ¯HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk Ö¯HRTIM_RSTR_EXTEVNT4_Pos (12U) ׯHRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) دHRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk Ù¯HRTIM_RSTR_EXTEVNT5_Pos (13U) Ú¯HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) Û¯HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk ܯHRTIM_RSTR_EXTEVNT6_Pos (14U) ݯHRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) Þ¯HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk ߯HRTIM_RSTR_EXTEVNT7_Pos (15U) à¯HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) á¯HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk â¯HRTIM_RSTR_EXTEVNT8_Pos (16U) ã¯HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) ä¯HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk å¯HRTIM_RSTR_EXTEVNT9_Pos (17U) æ¯HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) ç¯HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk è¯HRTIM_RSTR_EXTEVNT10_Pos (18U) é¯HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) ê¯HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk í¯HRTIM_RSTR_TIMBCMP1_Pos (19U) î¯HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) ï¯HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk ð¯HRTIM_RSTR_TIMBCMP2_Pos (20U) ñ¯HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) ò¯HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk ó¯HRTIM_RSTR_TIMBCMP4_Pos (21U) ô¯HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) õ¯HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk ÷¯HRTIM_RSTR_TIMCCMP1_Pos (22U) ø¯HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) ù¯HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk ú¯HRTIM_RSTR_TIMCCMP2_Pos (23U) û¯HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) ü¯HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk ý¯HRTIM_RSTR_TIMCCMP4_Pos (24U) þ¯HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) ÿ¯HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk °HRTIM_RSTR_TIMDCMP1_Pos (25U) °HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) °HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk °HRTIM_RSTR_TIMDCMP2_Pos (26U)
°HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) °HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk °HRTIM_RSTR_TIMDCMP4_Pos (27U) °HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) °HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk °HRTIM_RSTR_TIMECMP1_Pos (28U) °HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) °HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk °HRTIM_RSTR_TIMECMP2_Pos (29U) °HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) °HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk °HRTIM_RSTR_TIMECMP4_Pos (30U) °HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) °HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk °HRTIM_RSTBR_TIMACMP1_Pos (19U) °HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) °HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk °HRTIM_RSTBR_TIMACMP2_Pos (20U) °HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) °HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk °HRTIM_RSTBR_TIMACMP4_Pos (21U) °HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) °HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk °HRTIM_RSTBR_TIMCCMP1_Pos (22U) ¡°HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) ¢°HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk £°HRTIM_RSTBR_TIMCCMP2_Pos (23U) ¤°HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) ¥°HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk ¦°HRTIM_RSTBR_TIMCCMP4_Pos (24U) §°HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) ¨°HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk ª°HRTIM_RSTBR_TIMDCMP1_Pos (25U) «°HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) ¬°HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk °HRTIM_RSTBR_TIMDCMP2_Pos (26U) ®°HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) ¯°HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk °°HRTIM_RSTBR_TIMDCMP4_Pos (27U) ±°HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) ²°HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk ´°HRTIM_RSTBR_TIMECMP1_Pos (28U) µ°HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) ¶°HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk ·°HRTIM_RSTBR_TIMECMP2_Pos (29U) ¸°HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) ¹°HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk º°HRTIM_RSTBR_TIMECMP4_Pos (30U) »°HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) ¼°HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk ¿°HRTIM_RSTCR_TIMACMP1_Pos (19U) À°HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) Á°HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk °HRTIM_RSTCR_TIMACMP2_Pos (20U) ðHRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) Ä°HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk Å°HRTIM_RSTCR_TIMACMP4_Pos (21U) Æ°HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) Ç°HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk É°HRTIM_RSTCR_TIMBCMP1_Pos (22U) Ê°HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) Ë°HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk Ì°HRTIM_RSTCR_TIMBCMP2_Pos (23U) Í°HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) ΰHRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk Ï°HRTIM_RSTCR_TIMBCMP4_Pos (24U) аHRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) Ñ°HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk Ó°HRTIM_RSTCR_TIMDCMP1_Pos (25U) Ô°HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) Õ°HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk Ö°HRTIM_RSTCR_TIMDCMP2_Pos (26U) ×°HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) Ø°HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk Ù°HRTIM_RSTCR_TIMDCMP4_Pos (27U) Ú°HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) Û°HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk Ý°HRTIM_RSTCR_TIMECMP1_Pos (28U) Þ°HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) ß°HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk à°HRTIM_RSTCR_TIMECMP2_Pos (29U) á°HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) â°HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk ã°HRTIM_RSTCR_TIMECMP4_Pos (30U) ä°HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) å°HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk è°HRTIM_RSTDR_TIMACMP1_Pos (19U) é°HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) ê°HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk ë°HRTIM_RSTDR_TIMACMP2_Pos (20U) ì°HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) í°HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk î°HRTIM_RSTDR_TIMACMP4_Pos (21U) ï°HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) ð°HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk ò°HRTIM_RSTDR_TIMBCMP1_Pos (22U) ó°HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) ô°HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk õ°HRTIM_RSTDR_TIMBCMP2_Pos (23U) ö°HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) ÷°HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk ø°HRTIM_RSTDR_TIMBCMP4_Pos (24U) ù°HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) ú°HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk ü°HRTIM_RSTDR_TIMCCMP1_Pos (25U) ý°HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) þ°HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk ÿ°HRTIM_RSTDR_TIMCCMP2_Pos (26U) ±HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) ±HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk ±HRTIM_RSTDR_TIMCCMP4_Pos (27U) ±HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) ±HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk ±HRTIM_RSTDR_TIMECMP1_Pos (28U) ±HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) ±HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk ±HRTIM_RSTDR_TIMECMP2_Pos (29U) ±HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) ±HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk ±HRTIM_RSTDR_TIMECMP4_Pos (30U) ±HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) ±HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk ±HRTIM_RSTER_TIMACMP1_Pos (19U) ±HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) ±HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk ±HRTIM_RSTER_TIMACMP2_Pos (20U) ±HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) ±HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk ±HRTIM_RSTER_TIMACMP4_Pos (21U) ±HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) ±HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk ±HRTIM_RSTER_TIMBCMP1_Pos (22U) ±HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) ±HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk ±HRTIM_RSTER_TIMBCMP2_Pos (23U) ±HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) ±HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk ¡±HRTIM_RSTER_TIMBCMP4_Pos (24U) ¢±HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) £±HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk ¥±HRTIM_RSTER_TIMCCMP1_Pos (25U) ¦±HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) §±HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk ¨±HRTIM_RSTER_TIMCCMP2_Pos (26U) ©±HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) ª±HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk «±HRTIM_RSTER_TIMCCMP4_Pos (27U) ¬±HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) ±HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk ¯±HRTIM_RSTER_TIMDCMP1_Pos (28U) °±HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) ±±HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk ²±HRTIM_RSTER_TIMDCMP2_Pos (29U) ³±HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) ´±HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk µ±HRTIM_RSTER_TIMDCMP4_Pos (30U) ¶±HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) ·±HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk º±HRTIM_CHPR_CARFRQ_Pos (0U) »±HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) ¼±HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk ½±HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) ¾±HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) ¿±HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) À±HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) ±HRTIM_CHPR_CARDTY_Pos (4U) ñHRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) ıHRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk űHRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) ƱHRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) DZHRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) ɱHRTIM_CHPR_STRPW_Pos (7U) ʱHRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) ˱HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk ̱HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) ͱHRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) αHRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) ϱHRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) Ò±HRTIM_CPT1CR_SWCPT_Pos (0U) Ó±HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) Ô±HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk Õ±HRTIM_CPT1CR_UPDCPT_Pos (1U) Ö±HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) ×±HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk رHRTIM_CPT1CR_EXEV1CPT_Pos (2U) Ù±HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) Ú±HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk Û±HRTIM_CPT1CR_EXEV2CPT_Pos (3U) ܱHRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) ݱHRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk Þ±HRTIM_CPT1CR_EXEV3CPT_Pos (4U) ß±HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) à±HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk á±HRTIM_CPT1CR_EXEV4CPT_Pos (5U) â±HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) ã±HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk ä±HRTIM_CPT1CR_EXEV5CPT_Pos (6U) å±HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) æ±HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk ç±HRTIM_CPT1CR_EXEV6CPT_Pos (7U) è±HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) é±HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk ê±HRTIM_CPT1CR_EXEV7CPT_Pos (8U) ë±HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) ì±HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk í±HRTIM_CPT1CR_EXEV8CPT_Pos (9U) î±HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) ï±HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk ð±HRTIM_CPT1CR_EXEV9CPT_Pos (10U) ñ±HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) ò±HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk ó±HRTIM_CPT1CR_EXEV10CPT_Pos (11U) ô±HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) õ±HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk ÷±HRTIM_CPT1CR_TA1SET_Pos (12U) ø±HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) ù±HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk ú±HRTIM_CPT1CR_TA1RST_Pos (13U) û±HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) ü±HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk ý±HRTIM_CPT1CR_TIMACMP1_Pos (14U) þ±HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) ÿ±HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk ²HRTIM_CPT1CR_TIMACMP2_Pos (15U) ²HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) ²HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk ²HRTIM_CPT1CR_TB1SET_Pos (16U)
²HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) ²HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk ²HRTIM_CPT1CR_TB1RST_Pos (17U) ²HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) ²HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk ²HRTIM_CPT1CR_TIMBCMP1_Pos (18U) ²HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) ²HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk ²HRTIM_CPT1CR_TIMBCMP2_Pos (19U) ²HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) ²HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk ²HRTIM_CPT1CR_TC1SET_Pos (20U) ²HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) ²HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk ²HRTIM_CPT1CR_TC1RST_Pos (21U) ²HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) ²HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk ²HRTIM_CPT1CR_TIMCCMP1_Pos (22U) ²HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) ²HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk ²HRTIM_CPT1CR_TIMCCMP2_Pos (23U) ²HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) ²HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk ²HRTIM_CPT1CR_TD1SET_Pos (24U) ²HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) ²HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk ¡²HRTIM_CPT1CR_TD1RST_Pos (25U) ¢²HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) £²HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk ¤²HRTIM_CPT1CR_TIMDCMP1_Pos (26U) ¥²HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) ¦²HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk §²HRTIM_CPT1CR_TIMDCMP2_Pos (27U) ¨²HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) ©²HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk «²HRTIM_CPT1CR_TE1SET_Pos (28U) ¬²HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) ²HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk ®²HRTIM_CPT1CR_TE1RST_Pos (29U) ¯²HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) °²HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk ±²HRTIM_CPT1CR_TIMECMP1_Pos (30U) ²²HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) ³²HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk ´²HRTIM_CPT1CR_TIMECMP2_Pos (31U) µ²HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) ¶²HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk ¹²HRTIM_CPT2CR_SWCPT_Pos (0U) º²HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) »²HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk ¼²HRTIM_CPT2CR_UPDCPT_Pos (1U) ½²HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) ¾²HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk ¿²HRTIM_CPT2CR_EXEV1CPT_Pos (2U) À²HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) Á²HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk ²HRTIM_CPT2CR_EXEV2CPT_Pos (3U) òHRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) IJHRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk ŲHRTIM_CPT2CR_EXEV3CPT_Pos (4U) ƲHRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) DzHRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk ȲHRTIM_CPT2CR_EXEV4CPT_Pos (5U) ɲHRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) ʲHRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk ˲HRTIM_CPT2CR_EXEV5CPT_Pos (6U) ̲HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) ͲHRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk βHRTIM_CPT2CR_EXEV6CPT_Pos (7U) ϲHRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) вHRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk ѲHRTIM_CPT2CR_EXEV7CPT_Pos (8U) Ò²HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) Ó²HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk Ô²HRTIM_CPT2CR_EXEV8CPT_Pos (9U) Õ²HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) Ö²HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk ײHRTIM_CPT2CR_EXEV9CPT_Pos (10U) زHRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) Ù²HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk Ú²HRTIM_CPT2CR_EXEV10CPT_Pos (11U) Û²HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) ܲHRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk Þ²HRTIM_CPT2CR_TA1SET_Pos (12U) ß²HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) à²HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk á²HRTIM_CPT2CR_TA1RST_Pos (13U) â²HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) ã²HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk ä²HRTIM_CPT2CR_TIMACMP1_Pos (14U) å²HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) æ²HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk ç²HRTIM_CPT2CR_TIMACMP2_Pos (15U) è²HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) é²HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk ë²HRTIM_CPT2CR_TB1SET_Pos (16U) ì²HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) í²HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk î²HRTIM_CPT2CR_TB1RST_Pos (17U) ï²HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) ð²HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk ñ²HRTIM_CPT2CR_TIMBCMP1_Pos (18U) ò²HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) ó²HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk ô²HRTIM_CPT2CR_TIMBCMP2_Pos (19U) õ²HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) ö²HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk ø²HRTIM_CPT2CR_TC1SET_Pos (20U) ù²HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) ú²HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk û²HRTIM_CPT2CR_TC1RST_Pos (21U) ü²HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) ý²HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk þ²HRTIM_CPT2CR_TIMCCMP1_Pos (22U) ÿ²HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) ³HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk ³HRTIM_CPT2CR_TIMCCMP2_Pos (23U) ³HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) ³HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk
³HRTIM_CPT2CR_TD1SET_Pos (24U) ³HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) ³HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk ³HRTIM_CPT2CR_TD1RST_Pos (25U) ³HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) ³HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk ³HRTIM_CPT2CR_TIMDCMP1_Pos (26U) ³HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) ³HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk ³HRTIM_CPT2CR_TIMDCMP2_Pos (27U) ³HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) ³HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk ³HRTIM_CPT2CR_TE1SET_Pos (28U) ³HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) ³HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk ³HRTIM_CPT2CR_TE1RST_Pos (29U) ³HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) ³HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk ³HRTIM_CPT2CR_TIMECMP1_Pos (30U) ³HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) ³HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk ³HRTIM_CPT2CR_TIMECMP2_Pos (31U) ³HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) ³HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk ³HRTIM_OUTR_POL1_Pos (1U) ¡³HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) ¢³HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk £³HRTIM_OUTR_IDLM1_Pos (2U) ¤³HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) ¥³HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk ¦³HRTIM_OUTR_IDLES1_Pos (3U) §³HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) ¨³HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk ©³HRTIM_OUTR_FAULT1_Pos (4U) ª³HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) «³HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk ¬³HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) ³HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) ®³HRTIM_OUTR_CHP1_Pos (6U) ¯³HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) °³HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk ±³HRTIM_OUTR_DIDL1_Pos (7U) ²³HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) ³³HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk µ³HRTIM_OUTR_DTEN_Pos (8U) ¶³HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) ·³HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk ¸³HRTIM_OUTR_DLYPRTEN_Pos (9U) ¹³HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) º³HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk »³HRTIM_OUTR_DLYPRT_Pos (10U) ¼³HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) ½³HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk ¾³HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) ¿³HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) À³HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) ³HRTIM_OUTR_POL2_Pos (17U) óHRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) ijHRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk ųHRTIM_OUTR_IDLM2_Pos (18U) ƳHRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) dzHRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk ȳHRTIM_OUTR_IDLES2_Pos (19U) ɳHRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) ʳHRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk ˳HRTIM_OUTR_FAULT2_Pos (20U) ̳HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) ͳHRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk γHRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) ϳHRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) гHRTIM_OUTR_CHP2_Pos (22U) ѳHRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) Ò³HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk Ó³HRTIM_OUTR_DIDL2_Pos (23U) Ô³HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) Õ³HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk سHRTIM_FLTR_FLT1EN_Pos (0U) Ù³HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) Ú³HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk Û³HRTIM_FLTR_FLT2EN_Pos (1U) ܳHRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) ݳHRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk Þ³HRTIM_FLTR_FLT3EN_Pos (2U) ß³HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) à³HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk á³HRTIM_FLTR_FLT4EN_Pos (3U) â³HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) ã³HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk ä³HRTIM_FLTR_FLT5EN_Pos (4U) å³HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) æ³HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk ç³HRTIM_FLTR_FLTLCK_Pos (31U) è³HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) é³HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk ì³HRTIM_CR1_MUDIS_Pos (0U) í³HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) î³HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk ï³HRTIM_CR1_TAUDIS_Pos (1U) ð³HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) ñ³HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk ò³HRTIM_CR1_TBUDIS_Pos (2U) ó³HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) ô³HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk õ³HRTIM_CR1_TCUDIS_Pos (3U) ö³HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) ÷³HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk ø³HRTIM_CR1_TDUDIS_Pos (4U) ù³HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) ú³HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk û³HRTIM_CR1_TEUDIS_Pos (5U) ü³HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) ý³HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk þ³HRTIM_CR1_ADC1USRC_Pos (16U) ÿ³HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) ´HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk ´HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) ´HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) ´HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) ´HRTIM_CR1_ADC2USRC_Pos (19U)
´HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) ´HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk ´HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) ´HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) ´HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) ´HRTIM_CR1_ADC3USRC_Pos (22U) ´HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) ´HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk ´HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) ´HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) ´HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) ´HRTIM_CR1_ADC4USRC_Pos (25U) ´HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) ´HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk ´HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) ´HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) ´HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) ´HRTIM_CR2_MSWU_Pos (0U) ´HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) ´HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk ´HRTIM_CR2_TASWU_Pos (1U) ´HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) ´HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk ´HRTIM_CR2_TBSWU_Pos (2U) ´HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) ´HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk ¡´HRTIM_CR2_TCSWU_Pos (3U) ¢´HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) £´HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk ¤´HRTIM_CR2_TDSWU_Pos (4U) ¥´HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) ¦´HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk §´HRTIM_CR2_TESWU_Pos (5U) ¨´HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) ©´HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk ª´HRTIM_CR2_MRST_Pos (8U) «´HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) ¬´HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk ´HRTIM_CR2_TARST_Pos (9U) ®´HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) ¯´HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk °´HRTIM_CR2_TBRST_Pos (10U) ±´HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) ²´HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk ³´HRTIM_CR2_TCRST_Pos (11U) ´´HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) µ´HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk ¶´HRTIM_CR2_TDRST_Pos (12U) ·´HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) ¸´HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk ¹´HRTIM_CR2_TERST_Pos (13U) º´HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) »´HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk ¾´HRTIM_ISR_FLT1_Pos (0U) ¿´HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) À´HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk Á´HRTIM_ISR_FLT2_Pos (1U) ´HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) ôHRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk Ä´HRTIM_ISR_FLT3_Pos (2U) Å´HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) Æ´HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk Ç´HRTIM_ISR_FLT4_Pos (3U) È´HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) É´HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk Ê´HRTIM_ISR_FLT5_Pos (4U) Ë´HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) Ì´HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk Í´HRTIM_ISR_SYSFLT_Pos (5U) δHRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) Ï´HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk дHRTIM_ISR_BMPER_Pos (17U) Ñ´HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) Ò´HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk Õ´HRTIM_ICR_FLT1C_Pos (0U) Ö´HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) ×´HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk Ø´HRTIM_ICR_FLT2C_Pos (1U) Ù´HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) Ú´HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk Û´HRTIM_ICR_FLT3C_Pos (2U) Ü´HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) Ý´HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk Þ´HRTIM_ICR_FLT4C_Pos (3U) ß´HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) à´HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk á´HRTIM_ICR_FLT5C_Pos (4U) â´HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) ã´HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk ä´HRTIM_ICR_SYSFLTC_Pos (5U) å´HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) æ´HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk ç´HRTIM_ICR_BMPERC_Pos (17U) è´HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) é´HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk ì´HRTIM_IER_FLT1_Pos (0U) í´HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) î´HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk ï´HRTIM_IER_FLT2_Pos (1U) ð´HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) ñ´HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk ò´HRTIM_IER_FLT3_Pos (2U) ó´HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) ô´HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk õ´HRTIM_IER_FLT4_Pos (3U) ö´HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) ÷´HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk ø´HRTIM_IER_FLT5_Pos (4U) ù´HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) ú´HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk û´HRTIM_IER_SYSFLT_Pos (5U) ü´HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) ý´HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk þ´HRTIM_IER_BMPER_Pos (17U) ÿ´HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) µHRTIM_IER_BMPER HRTIM_IER_BMPER_Msk µHRTIM_OENR_TA1OEN_Pos (0U) µHRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos)
µHRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk µHRTIM_OENR_TA2OEN_Pos (1U) µHRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) µHRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk µHRTIM_OENR_TB1OEN_Pos (2U) µHRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) µHRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk µHRTIM_OENR_TB2OEN_Pos (3U) µHRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) µHRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk µHRTIM_OENR_TC1OEN_Pos (4U) µHRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) µHRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk µHRTIM_OENR_TC2OEN_Pos (5U) µHRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) µHRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk µHRTIM_OENR_TD1OEN_Pos (6U) µHRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) µHRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk µHRTIM_OENR_TD2OEN_Pos (7U) µHRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) µHRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk µHRTIM_OENR_TE1OEN_Pos (8U) µHRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) µHRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk µHRTIM_OENR_TE2OEN_Pos (9U) µHRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) µHRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk £µHRTIM_ODISR_TA1ODIS_Pos (0U) ¤µHRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) ¥µHRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk ¦µHRTIM_ODISR_TA2ODIS_Pos (1U) §µHRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) ¨µHRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk ©µHRTIM_ODISR_TB1ODIS_Pos (2U) ªµHRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) «µHRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk ¬µHRTIM_ODISR_TB2ODIS_Pos (3U) µHRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) ®µHRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk ¯µHRTIM_ODISR_TC1ODIS_Pos (4U) °µHRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) ±µHRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk ²µHRTIM_ODISR_TC2ODIS_Pos (5U) ³µHRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) ´µHRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk µµHRTIM_ODISR_TD1ODIS_Pos (6U) ¶µHRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) ·µHRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk ¸µHRTIM_ODISR_TD2ODIS_Pos (7U) ¹µHRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) ºµHRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk »µHRTIM_ODISR_TE1ODIS_Pos (8U) ¼µHRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) ½µHRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk ¾µHRTIM_ODISR_TE2ODIS_Pos (9U) ¿µHRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) ÀµHRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk õHRTIM_ODSR_TA1ODS_Pos (0U) ĵHRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) ŵHRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk ƵHRTIM_ODSR_TA2ODS_Pos (1U) ǵHRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) ȵHRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk ɵHRTIM_ODSR_TB1ODS_Pos (2U) ʵHRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) ˵HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk ̵HRTIM_ODSR_TB2ODS_Pos (3U) ͵HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) εHRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk ϵHRTIM_ODSR_TC1ODS_Pos (4U) еHRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) ѵHRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk ÒµHRTIM_ODSR_TC2ODS_Pos (5U) ÓµHRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) ÔµHRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk ÕµHRTIM_ODSR_TD1ODS_Pos (6U) ÖµHRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) ×µHRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk صHRTIM_ODSR_TD2ODS_Pos (7U) ÙµHRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) ÚµHRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk ÛµHRTIM_ODSR_TE1ODS_Pos (8U) ܵHRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) ݵHRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk ÞµHRTIM_ODSR_TE2ODS_Pos (9U) ßµHRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) àµHRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk ãµHRTIM_BMCR_BME_Pos (0U) äµHRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) åµHRTIM_BMCR_BME HRTIM_BMCR_BME_Msk æµHRTIM_BMCR_BMOM_Pos (1U) çµHRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) èµHRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk éµHRTIM_BMCR_BMCLK_Pos (2U) êµHRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) ëµHRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk ìµHRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) íµHRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) îµHRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) ïµHRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) ðµHRTIM_BMCR_BMPRSC_Pos (6U) ñµHRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) òµHRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk óµHRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) ôµHRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) õµHRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) öµHRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) ÷µHRTIM_BMCR_BMPREN_Pos (10U) øµHRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) ùµHRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk úµHRTIM_BMCR_MTBM_Pos (16U) ûµHRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) üµHRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk ýµHRTIM_BMCR_TABM_Pos (17U) þµHRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) ÿµHRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk ¶HRTIM_BMCR_TBBM_Pos (18U) ¶HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) ¶HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk ¶HRTIM_BMCR_TCBM_Pos (19U) ¶HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos)
¶HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk ¶HRTIM_BMCR_TDBM_Pos (20U) ¶HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) ¶HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk ¶HRTIM_BMCR_TEBM_Pos (21U) ¶HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) ¶HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk ¶HRTIM_BMCR_BMSTAT_Pos (31U) ¶HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) ¶HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk ¶HRTIM_BMTRGR_SW_Pos (0U) ¶HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) ¶HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk ¶HRTIM_BMTRGR_MSTRST_Pos (1U) ¶HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) ¶HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk ¶HRTIM_BMTRGR_MSTREP_Pos (2U) ¶HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) ¶HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk ¶HRTIM_BMTRGR_MSTCMP1_Pos (3U) ¶HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) ¶HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk ¶HRTIM_BMTRGR_MSTCMP2_Pos (4U) ¶HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) ¶HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk ¶HRTIM_BMTRGR_MSTCMP3_Pos (5U) ¡¶HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) ¢¶HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk £¶HRTIM_BMTRGR_MSTCMP4_Pos (6U) ¤¶HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) ¥¶HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk ¦¶HRTIM_BMTRGR_TARST_Pos (7U) §¶HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) ¨¶HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk ©¶HRTIM_BMTRGR_TAREP_Pos (8U) ª¶HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) «¶HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk ¬¶HRTIM_BMTRGR_TACMP1_Pos (9U) ¶HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) ®¶HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk ¯¶HRTIM_BMTRGR_TACMP2_Pos (10U) °¶HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) ±¶HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk ²¶HRTIM_BMTRGR_TBRST_Pos (11U) ³¶HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) ´¶HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk µ¶HRTIM_BMTRGR_TBREP_Pos (12U) ¶¶HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) ·¶HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk ¸¶HRTIM_BMTRGR_TBCMP1_Pos (13U) ¹¶HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) º¶HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk »¶HRTIM_BMTRGR_TBCMP2_Pos (14U) ¼¶HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) ½¶HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk ¾¶HRTIM_BMTRGR_TCRST_Pos (15U) ¿¶HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) À¶HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk Á¶HRTIM_BMTRGR_TCREP_Pos (16U) ¶HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) öHRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk ĶHRTIM_BMTRGR_TCCMP1_Pos (17U) ŶHRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) ƶHRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk ǶHRTIM_BMTRGR_TCCMP2_Pos (18U) ȶHRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) ɶHRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk ʶHRTIM_BMTRGR_TDRST_Pos (19U) ˶HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) ̶HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk ͶHRTIM_BMTRGR_TDREP_Pos (20U) ζHRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) ϶HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk жHRTIM_BMTRGR_TDCMP1_Pos (21U) ѶHRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) Ò¶HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk Ó¶HRTIM_BMTRGR_TDCMP2_Pos (22U) Ô¶HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) Õ¶HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk Ö¶HRTIM_BMTRGR_TERST_Pos (23U) ׶HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) ضHRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk Ù¶HRTIM_BMTRGR_TEREP_Pos (24U) Ú¶HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) Û¶HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk ܶHRTIM_BMTRGR_TECMP1_Pos (25U) ݶHRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) Þ¶HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk ߶HRTIM_BMTRGR_TECMP2_Pos (26U) à¶HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) á¶HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk â¶HRTIM_BMTRGR_TAEEV7_Pos (27U) ã¶HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) ä¶HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk å¶HRTIM_BMTRGR_TDEEV8_Pos (28U) æ¶HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) ç¶HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk è¶HRTIM_BMTRGR_EEV7_Pos (29U) é¶HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) ê¶HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk ë¶HRTIM_BMTRGR_EEV8_Pos (30U) ì¶HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) í¶HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk î¶HRTIM_BMTRGR_OCHPEV_Pos (31U) ï¶HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) ð¶HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk ó¶HRTIM_BMCMPR_BMCMPR_Pos (0U) ô¶HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) õ¶HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk ø¶HRTIM_BMPER_BMPER_Pos (0U) ù¶HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) ú¶HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk ý¶HRTIM_EECR1_EE1SRC_Pos (0U) þ¶HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) ÿ¶HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk ·HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) ·HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) ·HRTIM_EECR1_EE1POL_Pos (2U) ·HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) ·HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk
·HRTIM_EECR1_EE1SNS_Pos (3U) ·HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) ·HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk ·HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) ·HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) ·HRTIM_EECR1_EE1FAST_Pos (5U) ·HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) ·HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk ·HRTIM_EECR1_EE2SRC_Pos (6U) ·HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) ·HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk ·HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) ·HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) ·HRTIM_EECR1_EE2POL_Pos (8U) ·HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) ·HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk ·HRTIM_EECR1_EE2SNS_Pos (9U) ·HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) ·HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk ·HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) ·HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) ·HRTIM_EECR1_EE2FAST_Pos (11U) ·HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) ·HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk ·HRTIM_EECR1_EE3SRC_Pos (12U) ·HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) ¡·HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk ¢·HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) £·HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) ¤·HRTIM_EECR1_EE3POL_Pos (14U) ¥·HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) ¦·HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk §·HRTIM_EECR1_EE3SNS_Pos (15U) ¨·HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) ©·HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk ª·HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) «·HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) ¬·HRTIM_EECR1_EE3FAST_Pos (17U) ·HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) ®·HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk °·HRTIM_EECR1_EE4SRC_Pos (18U) ±·HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) ²·HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk ³·HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) ´·HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) µ·HRTIM_EECR1_EE4POL_Pos (20U) ¶·HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) ··HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk ¸·HRTIM_EECR1_EE4SNS_Pos (21U) ¹·HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) º·HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk »·HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) ¼·HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) ½·HRTIM_EECR1_EE4FAST_Pos (23U) ¾·HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) ¿·HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk Á·HRTIM_EECR1_EE5SRC_Pos (24U) ·HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) ÷HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk Ä·HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) Å·HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) Æ·HRTIM_EECR1_EE5POL_Pos (26U) Ç·HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) È·HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk É·HRTIM_EECR1_EE5SNS_Pos (27U) Ê·HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) Ë·HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk Ì·HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) Í·HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) ηHRTIM_EECR1_EE5FAST_Pos (29U) Ï·HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) зHRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk Ó·HRTIM_EECR2_EE6SRC_Pos (0U) Ô·HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) Õ·HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk Ö·HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) ×·HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) Ø·HRTIM_EECR2_EE6POL_Pos (2U) Ù·HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) Ú·HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk Û·HRTIM_EECR2_EE6SNS_Pos (3U) Ü·HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) Ý·HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk Þ·HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) ß·HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) á·HRTIM_EECR2_EE7SRC_Pos (6U) â·HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) ã·HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk ä·HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) å·HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) æ·HRTIM_EECR2_EE7POL_Pos (8U) ç·HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) è·HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk é·HRTIM_EECR2_EE7SNS_Pos (9U) ê·HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) ë·HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk ì·HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) í·HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) ï·HRTIM_EECR2_EE8SRC_Pos (12U) ð·HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) ñ·HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk ò·HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) ó·HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) ô·HRTIM_EECR2_EE8POL_Pos (14U) õ·HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) ö·HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk ÷·HRTIM_EECR2_EE8SNS_Pos (15U) ø·HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) ù·HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk ú·HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) û·HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) ý·HRTIM_EECR2_EE9SRC_Pos (18U) þ·HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) ÿ·HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk ¸HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) ¸HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) ¸HRTIM_EECR2_EE9POL_Pos (20U) ¸HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) ¸HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk
¸HRTIM_EECR2_EE9SNS_Pos (21U) ¸HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) ¸HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk ¸HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) ¸HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) ¸HRTIM_EECR2_EE10SRC_Pos (24U) ¸HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) ¸HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk ¸HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) ¸HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) ¸HRTIM_EECR2_EE10POL_Pos (26U) ¸HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) ¸HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk ¸HRTIM_EECR2_EE10SNS_Pos (27U) ¸HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) ¸HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk ¸HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) ¸HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) ¸HRTIM_EECR3_EE6F_Pos (0U) ¸HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) ¸HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk ¸HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) ¸HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) ¸HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) ¸HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) ¡¸HRTIM_EECR3_EE7F_Pos (6U) ¢¸HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) £¸HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk ¤¸HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) ¥¸HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) ¦¸HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) §¸HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) ¨¸HRTIM_EECR3_EE8F_Pos (12U) ©¸HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) ª¸HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk «¸HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) ¬¸HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) ¸HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) ®¸HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) ¯¸HRTIM_EECR3_EE9F_Pos (18U) °¸HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) ±¸HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk ²¸HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) ³¸HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) ´¸HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) µ¸HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) ¶¸HRTIM_EECR3_EE10F_Pos (24U) ·¸HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) ¸¸HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk ¹¸HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) º¸HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) »¸HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) ¼¸HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) ½¸HRTIM_EECR3_EEVSD_Pos (30U) ¾¸HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) ¿¸HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk À¸HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) Á¸HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) ĸHRTIM_ADC1R_AD1MC1_Pos (0U) ŸHRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) ƸHRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk ǸHRTIM_ADC1R_AD1MC2_Pos (1U) ȸHRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) ɸHRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk ʸHRTIM_ADC1R_AD1MC3_Pos (2U) ˸HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) ̸HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk ͸HRTIM_ADC1R_AD1MC4_Pos (3U) θHRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) ϸHRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk иHRTIM_ADC1R_AD1MPER_Pos (4U) ѸHRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) Ò¸HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk Ó¸HRTIM_ADC1R_AD1EEV1_Pos (5U) Ô¸HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) Õ¸HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk Ö¸HRTIM_ADC1R_AD1EEV2_Pos (6U) ׸HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) ظHRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk Ù¸HRTIM_ADC1R_AD1EEV3_Pos (7U) Ú¸HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) Û¸HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk ܸHRTIM_ADC1R_AD1EEV4_Pos (8U) ݸHRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) Þ¸HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk ߸HRTIM_ADC1R_AD1EEV5_Pos (9U) à¸HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) á¸HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk â¸HRTIM_ADC1R_AD1TAC2_Pos (10U) ã¸HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) ä¸HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk å¸HRTIM_ADC1R_AD1TAC3_Pos (11U) æ¸HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) ç¸HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk è¸HRTIM_ADC1R_AD1TAC4_Pos (12U) é¸HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) ê¸HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk ë¸HRTIM_ADC1R_AD1TAPER_Pos (13U) ì¸HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) í¸HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk î¸HRTIM_ADC1R_AD1TARST_Pos (14U) ï¸HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) ð¸HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk ñ¸HRTIM_ADC1R_AD1TBC2_Pos (15U) ò¸HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) ó¸HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk ô¸HRTIM_ADC1R_AD1TBC3_Pos (16U) õ¸HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) ö¸HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk ÷¸HRTIM_ADC1R_AD1TBC4_Pos (17U) ø¸HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) ù¸HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk ú¸HRTIM_ADC1R_AD1TBPER_Pos (18U) û¸HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) ü¸HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk ý¸HRTIM_ADC1R_AD1TBRST_Pos (19U) þ¸HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) ÿ¸HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk ¹HRTIM_ADC1R_AD1TCC2_Pos (20U) ¹HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) ¹HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk ¹HRTIM_ADC1R_AD1TCC3_Pos (21U) ¹HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)
¹HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk ¹HRTIM_ADC1R_AD1TCC4_Pos (22U) ¹HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) ¹HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk ¹HRTIM_ADC1R_AD1TCPER_Pos (23U) ¹HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) ¹HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk ¹HRTIM_ADC1R_AD1TDC2_Pos (24U) ¹HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) ¹HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk ¹HRTIM_ADC1R_AD1TDC3_Pos (25U) ¹HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) ¹HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk ¹HRTIM_ADC1R_AD1TDC4_Pos (26U) ¹HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) ¹HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk ¹HRTIM_ADC1R_AD1TDPER_Pos (27U) ¹HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) ¹HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk ¹HRTIM_ADC1R_AD1TEC2_Pos (28U) ¹HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) ¹HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk ¹HRTIM_ADC1R_AD1TEC3_Pos (29U) ¹HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) ¹HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk ¹HRTIM_ADC1R_AD1TEC4_Pos (30U) ¹HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) ¹HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk ¡¹HRTIM_ADC1R_AD1TEPER_Pos (31U) ¢¹HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) £¹HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk ¦¹HRTIM_ADC2R_AD2MC1_Pos (0U) §¹HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) ¨¹HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk ©¹HRTIM_ADC2R_AD2MC2_Pos (1U) ª¹HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) «¹HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk ¬¹HRTIM_ADC2R_AD2MC3_Pos (2U) ¹HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) ®¹HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk ¯¹HRTIM_ADC2R_AD2MC4_Pos (3U) °¹HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) ±¹HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk ²¹HRTIM_ADC2R_AD2MPER_Pos (4U) ³¹HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) ´¹HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk µ¹HRTIM_ADC2R_AD2EEV6_Pos (5U) ¶¹HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) ·¹HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk ¸¹HRTIM_ADC2R_AD2EEV7_Pos (6U) ¹¹HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) º¹HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk »¹HRTIM_ADC2R_AD2EEV8_Pos (7U) ¼¹HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) ½¹HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk ¾¹HRTIM_ADC2R_AD2EEV9_Pos (8U) ¿¹HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) À¹HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk Á¹HRTIM_ADC2R_AD2EEV10_Pos (9U) ¹HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) ùHRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk ĹHRTIM_ADC2R_AD2TAC2_Pos (10U) ŹHRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) ƹHRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk ǹHRTIM_ADC2R_AD2TAC3_Pos (11U) ȹHRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) ɹHRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk ʹHRTIM_ADC2R_AD2TAC4_Pos (12U) ˹HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) ̹HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk ͹HRTIM_ADC2R_AD2TAPER_Pos (13U) ιHRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) ϹHRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk йHRTIM_ADC2R_AD2TBC2_Pos (14U) ѹHRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) Ò¹HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk Ó¹HRTIM_ADC2R_AD2TBC3_Pos (15U) Ô¹HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) Õ¹HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk Ö¹HRTIM_ADC2R_AD2TBC4_Pos (16U) ×¹HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) عHRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk Ù¹HRTIM_ADC2R_AD2TBPER_Pos (17U) Ú¹HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) Û¹HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk ܹHRTIM_ADC2R_AD2TCC2_Pos (18U) ݹHRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) Þ¹HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk ß¹HRTIM_ADC2R_AD2TCC3_Pos (19U) à¹HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) á¹HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk â¹HRTIM_ADC2R_AD2TCC4_Pos (20U) ã¹HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) ä¹HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk å¹HRTIM_ADC2R_AD2TCPER_Pos (21U) æ¹HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) ç¹HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk è¹HRTIM_ADC2R_AD2TCRST_Pos (22U) é¹HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) ê¹HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk ë¹HRTIM_ADC2R_AD2TDC2_Pos (23U) ì¹HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) í¹HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk î¹HRTIM_ADC2R_AD2TDC3_Pos (24U) ï¹HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) ð¹HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk ñ¹HRTIM_ADC2R_AD2TDC4_Pos (25U) ò¹HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) ó¹HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk ô¹HRTIM_ADC2R_AD2TDPER_Pos (26U) õ¹HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) ö¹HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk ÷¹HRTIM_ADC2R_AD2TDRST_Pos (27U) ø¹HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) ù¹HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk ú¹HRTIM_ADC2R_AD2TEC2_Pos (28U) û¹HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) ü¹HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk ý¹HRTIM_ADC2R_AD2TEC3_Pos (29U) þ¹HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) ÿ¹HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk ºHRTIM_ADC2R_AD2TEC4_Pos (30U) ºHRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) ºHRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk ºHRTIM_ADC2R_AD2TERST_Pos (31U) ºHRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)
ºHRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk ºHRTIM_ADC3R_AD3MC1_Pos (0U) ºHRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) ºHRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk ºHRTIM_ADC3R_AD3MC2_Pos (1U) ºHRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) ºHRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk ºHRTIM_ADC3R_AD3MC3_Pos (2U) ºHRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) ºHRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk ºHRTIM_ADC3R_AD3MC4_Pos (3U) ºHRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) ºHRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk ºHRTIM_ADC3R_AD3MPER_Pos (4U) ºHRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) ºHRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk ºHRTIM_ADC3R_AD3EEV1_Pos (5U) ºHRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) ºHRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk ºHRTIM_ADC3R_AD3EEV2_Pos (6U) ºHRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) ºHRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk ºHRTIM_ADC3R_AD3EEV3_Pos (7U) ºHRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) ºHRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk ºHRTIM_ADC3R_AD3EEV4_Pos (8U) ¡ºHRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) ¢ºHRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk £ºHRTIM_ADC3R_AD3EEV5_Pos (9U) ¤ºHRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) ¥ºHRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk ¦ºHRTIM_ADC3R_AD3TAC2_Pos (10U) §ºHRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) ¨ºHRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk ©ºHRTIM_ADC3R_AD3TAC3_Pos (11U) ªºHRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) «ºHRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk ¬ºHRTIM_ADC3R_AD3TAC4_Pos (12U) ºHRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) ®ºHRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk ¯ºHRTIM_ADC3R_AD3TAPER_Pos (13U) °ºHRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) ±ºHRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk ²ºHRTIM_ADC3R_AD3TARST_Pos (14U) ³ºHRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) ´ºHRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk µºHRTIM_ADC3R_AD3TBC2_Pos (15U) ¶ºHRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) ·ºHRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk ¸ºHRTIM_ADC3R_AD3TBC3_Pos (16U) ¹ºHRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) ººHRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk »ºHRTIM_ADC3R_AD3TBC4_Pos (17U) ¼ºHRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) ½ºHRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk ¾ºHRTIM_ADC3R_AD3TBPER_Pos (18U) ¿ºHRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) ÀºHRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk ÁºHRTIM_ADC3R_AD3TBRST_Pos (19U) ºHRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) úHRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk ĺHRTIM_ADC3R_AD3TCC2_Pos (20U) źHRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) ƺHRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk ǺHRTIM_ADC3R_AD3TCC3_Pos (21U) ȺHRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) ɺHRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk ʺHRTIM_ADC3R_AD3TCC4_Pos (22U) ˺HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) ̺HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk ͺHRTIM_ADC3R_AD3TCPER_Pos (23U) κHRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) ϺHRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk кHRTIM_ADC3R_AD3TDC2_Pos (24U) ѺHRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) ÒºHRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk ÓºHRTIM_ADC3R_AD3TDC3_Pos (25U) ÔºHRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) ÕºHRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk ÖºHRTIM_ADC3R_AD3TDC4_Pos (26U) ׺HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) غHRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk ÙºHRTIM_ADC3R_AD3TDPER_Pos (27U) ÚºHRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) ÛºHRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk ܺHRTIM_ADC3R_AD3TEC2_Pos (28U) ݺHRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) ÞºHRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk ߺHRTIM_ADC3R_AD3TEC3_Pos (29U) àºHRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) áºHRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk âºHRTIM_ADC3R_AD3TEC4_Pos (30U) ãºHRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) äºHRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk åºHRTIM_ADC3R_AD3TEPER_Pos (31U) æºHRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) çºHRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk êºHRTIM_ADC4R_AD4MC1_Pos (0U) ëºHRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) ìºHRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk íºHRTIM_ADC4R_AD4MC2_Pos (1U) îºHRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) ïºHRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk ðºHRTIM_ADC4R_AD4MC3_Pos (2U) ñºHRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) òºHRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk óºHRTIM_ADC4R_AD4MC4_Pos (3U) ôºHRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) õºHRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk öºHRTIM_ADC4R_AD4MPER_Pos (4U) ÷ºHRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) øºHRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk ùºHRTIM_ADC4R_AD4EEV6_Pos (5U) úºHRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) ûºHRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk üºHRTIM_ADC4R_AD4EEV7_Pos (6U) ýºHRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) þºHRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk ÿºHRTIM_ADC4R_AD4EEV8_Pos (7U) »HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) »HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk »HRTIM_ADC4R_AD4EEV9_Pos (8U) »HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) »HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk
»HRTIM_ADC4R_AD4EEV10_Pos (9U) »HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) »HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk »HRTIM_ADC4R_AD4TAC2_Pos (10U) »HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) »HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk »HRTIM_ADC4R_AD4TAC3_Pos (11U) »HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) »HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk »HRTIM_ADC4R_AD4TAC4_Pos (12U) »HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) »HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk »HRTIM_ADC4R_AD4TAPER_Pos (13U) »HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) »HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk »HRTIM_ADC4R_AD4TBC2_Pos (14U) »HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) »HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk »HRTIM_ADC4R_AD4TBC3_Pos (15U) »HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) »HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk »HRTIM_ADC4R_AD4TBC4_Pos (16U) »HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) »HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk »HRTIM_ADC4R_AD4TBPER_Pos (17U) »HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) »HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk »HRTIM_ADC4R_AD4TCC2_Pos (18U) ¡»HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) ¢»HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk £»HRTIM_ADC4R_AD4TCC3_Pos (19U) ¤»HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) ¥»HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk ¦»HRTIM_ADC4R_AD4TCC4_Pos (20U) §»HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) ¨»HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk ©»HRTIM_ADC4R_AD4TCPER_Pos (21U) ª»HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) «»HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk ¬»HRTIM_ADC4R_AD4TCRST_Pos (22U) »HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) ®»HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk ¯»HRTIM_ADC4R_AD4TDC2_Pos (23U) °»HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) ±»HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk ²»HRTIM_ADC4R_AD4TDC3_Pos (24U) ³»HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) ´»HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk µ»HRTIM_ADC4R_AD4TDC4_Pos (25U) ¶»HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) ·»HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk ¸»HRTIM_ADC4R_AD4TDPER_Pos (26U) ¹»HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) º»HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk »»HRTIM_ADC4R_AD4TDRST_Pos (27U) ¼»HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) ½»HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk ¾»HRTIM_ADC4R_AD4TEC2_Pos (28U) ¿»HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) À»HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk Á»HRTIM_ADC4R_AD4TEC3_Pos (29U) »HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) ûHRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk Ä»HRTIM_ADC4R_AD4TEC4_Pos (30U) Å»HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) Æ»HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk Ç»HRTIM_ADC4R_AD4TERST_Pos (31U) È»HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) É»HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk Ì»HRTIM_FLTINR1_FLT1E_Pos (0U) Í»HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) λHRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk Ï»HRTIM_FLTINR1_FLT1P_Pos (1U) лHRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) Ñ»HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk Ò»HRTIM_FLTINR1_FLT1SRC_Pos (2U) Ó»HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) Ô»HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk Õ»HRTIM_FLTINR1_FLT1F_Pos (3U) Ö»HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) ×»HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk Ø»HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) Ù»HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) Ú»HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) Û»HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) Ü»HRTIM_FLTINR1_FLT1LCK_Pos (7U) Ý»HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) Þ»HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk à»HRTIM_FLTINR1_FLT2E_Pos (8U) á»HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) â»HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk ã»HRTIM_FLTINR1_FLT2P_Pos (9U) ä»HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) å»HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk æ»HRTIM_FLTINR1_FLT2SRC_Pos (10U) ç»HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) è»HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk é»HRTIM_FLTINR1_FLT2F_Pos (11U) ê»HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) ë»HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk ì»HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) í»HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) î»HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) ï»HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) ð»HRTIM_FLTINR1_FLT2LCK_Pos (15U) ñ»HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) ò»HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk ô»HRTIM_FLTINR1_FLT3E_Pos (16U) õ»HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) ö»HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk ÷»HRTIM_FLTINR1_FLT3P_Pos (17U) ø»HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) ù»HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk ú»HRTIM_FLTINR1_FLT3SRC_Pos (18U) û»HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) ü»HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk ý»HRTIM_FLTINR1_FLT3F_Pos (19U) þ»HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) ÿ»HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk ¼HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) ¼HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) ¼HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) ¼HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) ¼HRTIM_FLTINR1_FLT3LCK_Pos (23U)
¼HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) ¼HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk ¼HRTIM_FLTINR1_FLT4E_Pos (24U) ¼HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) ¼HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk ¼HRTIM_FLTINR1_FLT4P_Pos (25U) ¼HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) ¼HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk ¼HRTIM_FLTINR1_FLT4SRC_Pos (26U) ¼HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) ¼HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk ¼HRTIM_FLTINR1_FLT4F_Pos (27U) ¼HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) ¼HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk ¼HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) ¼HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) ¼HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) ¼HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) ¼HRTIM_FLTINR1_FLT4LCK_Pos (31U) ¼HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) ¼HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk ¼HRTIM_FLTINR2_FLT5E_Pos (0U) ¼HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) ¼HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk ¼HRTIM_FLTINR2_FLT5P_Pos (1U) ¡¼HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) ¢¼HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk £¼HRTIM_FLTINR2_FLT5SRC_Pos (2U) ¤¼HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) ¥¼HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk ¦¼HRTIM_FLTINR2_FLT5F_Pos (3U) §¼HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) ¨¼HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk ©¼HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) ª¼HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) «¼HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) ¬¼HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) ¼HRTIM_FLTINR2_FLT5LCK_Pos (7U) ®¼HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) ¯¼HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk °¼HRTIM_FLTINR2_FLTSD_Pos (24U) ±¼HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) ²¼HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk ³¼HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) ´¼HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) ·¼HRTIM_BDMUPR_MCR_Pos (0U) ¸¼HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) ¹¼HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk º¼HRTIM_BDMUPR_MICR_Pos (1U) »¼HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) ¼¼HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk ½¼HRTIM_BDMUPR_MDIER_Pos (2U) ¾¼HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) ¿¼HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk À¼HRTIM_BDMUPR_MCNT_Pos (3U) Á¼HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) ¼HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk üHRTIM_BDMUPR_MPER_Pos (4U) ļHRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) żHRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk ƼHRTIM_BDMUPR_MREP_Pos (5U) ǼHRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) ȼHRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk ɼHRTIM_BDMUPR_MCMP1_Pos (6U) ʼHRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) ˼HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk ̼HRTIM_BDMUPR_MCMP2_Pos (7U) ͼHRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) μHRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk ϼHRTIM_BDMUPR_MCMP3_Pos (8U) мHRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) ѼHRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk Ò¼HRTIM_BDMUPR_MCMP4_Pos (9U) Ó¼HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) Ô¼HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk ×¼HRTIM_BDTUPR_TIMCR_Pos (0U) ؼHRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) Ù¼HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk Ú¼HRTIM_BDTUPR_TIMICR_Pos (1U) Û¼HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) ܼHRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk ݼHRTIM_BDTUPR_TIMDIER_Pos (2U) Þ¼HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) ß¼HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk à¼HRTIM_BDTUPR_TIMCNT_Pos (3U) á¼HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) â¼HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk ã¼HRTIM_BDTUPR_TIMPER_Pos (4U) ä¼HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) å¼HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk æ¼HRTIM_BDTUPR_TIMREP_Pos (5U) ç¼HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) è¼HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk é¼HRTIM_BDTUPR_TIMCMP1_Pos (6U) ê¼HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) ë¼HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk ì¼HRTIM_BDTUPR_TIMCMP2_Pos (7U) í¼HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) î¼HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk ï¼HRTIM_BDTUPR_TIMCMP3_Pos (8U) ð¼HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) ñ¼HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk ò¼HRTIM_BDTUPR_TIMCMP4_Pos (9U) ó¼HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) ô¼HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk õ¼HRTIM_BDTUPR_TIMDTR_Pos (10U) ö¼HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) ÷¼HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk ø¼HRTIM_BDTUPR_TIMSET1R_Pos (11U) ù¼HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) ú¼HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk û¼HRTIM_BDTUPR_TIMRST1R_Pos (12U) ü¼HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) ý¼HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk þ¼HRTIM_BDTUPR_TIMSET2R_Pos (13U) ÿ¼HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) ½HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk ½HRTIM_BDTUPR_TIMRST2R_Pos (14U) ½HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) ½HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk ½HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
½HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) ½HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk ½HRTIM_BDTUPR_TIMEEFR2_Pos (16U) ½HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) ½HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk ½HRTIM_BDTUPR_TIMRSTR_Pos (17U) ½HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) ½HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk ½HRTIM_BDTUPR_TIMCHPR_Pos (18U) ½HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) ½HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk ½HRTIM_BDTUPR_TIMOUTR_Pos (19U) ½HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) ½HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk ½HRTIM_BDTUPR_TIMFLTR_Pos (20U) ½HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) ½HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk ½HRTIM_BDMADR_BDMADR_Pos (0U) ½HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) ½HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk ¢½RAMECC_IER_GECCDEBWIE_Pos (3U) £½RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) ¤½RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk ¥½RAMECC_IER_GECCDEIE_Pos (2U) ¦½RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) §½RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk ¨½RAMECC_IER_GECCSEIE_Pos (1U) ©½RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) ª½RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk «½RAMECC_IER_GIE_Pos (0U) ¬½RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) ½RAMECC_IER_GIE RAMECC_IER_GIE_Msk °½RAMECC_CR_ECCELEN_Pos (5U) ±½RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) ²½RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk ³½RAMECC_CR_ECCDEBWIE_Pos (4U) ´½RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) µ½RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk ¶½RAMECC_CR_ECCDEIE_Pos (3U) ·½RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) ¸½RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk ¹½RAMECC_CR_ECCSEIE_Pos (2U) º½RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) »½RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk ¾½RAMECC_SR_DEBWDF_Pos (2U) ¿½RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) À½RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk Á½RAMECC_SR_DEDF_Pos (1U) ½RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) ýRAMECC_SR_DEDF RAMECC_SR_DEDF_Msk ĽRAMECC_SR_SEDCF_Pos (0U) ŽRAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) ƽRAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk ɽRAMECC_FAR_FADD_Pos (0U) ʽRAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) ˽RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk νRAMECC_FAR_FDATAL_Pos (0U) ϽRAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos) нRAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk Ó½RAMECC_FAR_FDATAH_Pos (0U) Ô½RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos) Õ½RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk ؽRAMECC_FECR_FEC_Pos (0U) Ù½RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) Ú½RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk â½MDIOS_CR_EN_Pos (0U) ã½MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) ä½MDIOS_CR_EN MDIOS_CR_EN_Msk å½MDIOS_CR_WRIE_Pos (1U) æ½MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) ç½MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk è½MDIOS_CR_RDIE_Pos (2U) é½MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) ê½MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk ë½MDIOS_CR_EIE_Pos (3U) ì½MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) í½MDIOS_CR_EIE MDIOS_CR_EIE_Msk î½MDIOS_CR_DPC_Pos (7U) ï½MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) ð½MDIOS_CR_DPC MDIOS_CR_DPC_Msk ñ½MDIOS_CR_PORT_ADDRESS_Pos (8U) ò½MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) ó½MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk ô½MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) õ½MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) ö½MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) ÷½MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) ø½MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) û½MDIOS_SR_PERF_Pos (0U) ü½MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) ý½MDIOS_SR_PERF MDIOS_SR_PERF_Msk þ½MDIOS_SR_SERF_Pos (1U) ÿ½MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) ¾MDIOS_SR_SERF MDIOS_SR_SERF_Msk ¾MDIOS_SR_TERF_Pos (2U) ¾MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) ¾MDIOS_SR_TERF MDIOS_SR_TERF_Msk ¾MDIOS_SR_CPERF_Pos (0U) ¾MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) ¾MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk ¾MDIOS_SR_CSERF_Pos (1U) ¾MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) ¾MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk ¾MDIOS_SR_CTERF_Pos (2U) ¾MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) ¾MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk ¾USB_OTG_GOTGCTL_SRQSCS_Pos (0U) ¾USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) ¾USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk ¾USB_OTG_GOTGCTL_SRQ_Pos (1U) ¾USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) ¾USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk ¾USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) ¾USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) ¾USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk ¾USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) ¾USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) ¡¾USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk ¢¾USB_OTG_GOTGCTL_AVALOEN_Pos (4U) £¾USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) ¤¾USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk ¥¾USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) ¦¾USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) §¾USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk ¨¾USB_OTG_GOTGCTL_BVALOEN_Pos (6U) ©¾USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) ª¾USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk «¾USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) ¬¾USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) ¾USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk ®¾USB_OTG_GOTGCTL_HNGSCS_Pos (8U) ¯¾USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) °¾USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk ±¾USB_OTG_GOTGCTL_HNPRQ_Pos (9U) ²¾USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) ³¾USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk ´¾USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) µ¾USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) ¶¾USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk ·¾USB_OTG_GOTGCTL_DHNPEN_Pos (11U) ¸¾USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) ¹¾USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk º¾USB_OTG_GOTGCTL_EHEN_Pos (12U) »¾USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) ¼¾USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk ½¾USB_OTG_GOTGCTL_CIDSTS_Pos (16U) ¾¾USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) ¿¾USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk À¾USB_OTG_GOTGCTL_DBCT_Pos (17U) Á¾USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) ¾USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk þUSB_OTG_GOTGCTL_ASVLD_Pos (18U) ľUSB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) žUSB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk ƾUSB_OTG_GOTGCTL_BSESVLD_Pos (19U) ǾUSB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) ȾUSB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk ɾUSB_OTG_GOTGCTL_OTGVER_Pos (20U) ʾUSB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) ˾USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk ̾USB_OTG_GOTGCTL_CURMOD_Pos (21U) ;USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) ξUSB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk Ò¾USB_OTG_HCFG_FSLSPCS_Pos (0U) Ó¾USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) Ô¾USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk Õ¾USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) Ö¾USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) ×¾USB_OTG_HCFG_FSLSS_Pos (2U) ؾUSB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) Ù¾USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk ݾUSB_OTG_DCFG_DSPD_Pos (0U) Þ¾USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) ß¾USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk à¾USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) á¾USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) â¾USB_OTG_DCFG_NZLSOHSK_Pos (2U) ã¾USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) ä¾USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk æ¾USB_OTG_DCFG_DAD_Pos (4U) ç¾USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) è¾USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk é¾USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) ê¾USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) ë¾USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) ì¾USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) í¾USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) î¾USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) ï¾USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) ñ¾USB_OTG_DCFG_PFIVL_Pos (11U) ò¾USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) ó¾USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk ô¾USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) õ¾USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) ÷¾USB_OTG_DCFG_XCVRDLY_Pos (14U) ø¾USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) ù¾USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk û¾USB_OTG_DCFG_ERRATIM_Pos (15U) ü¾USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) ý¾USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk ÿ¾USB_OTG_DCFG_PERSCHIVL_Pos (24U) ¿USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) ¿USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk ¿USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) ¿USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) ¿USB_OTG_PCGCR_STPPCLK_Pos (0U) ¿USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) ¿USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk ¿USB_OTG_PCGCR_GATEHCLK_Pos (1U) ¿USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) ¿USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk ¿USB_OTG_PCGCR_PHYSUSP_Pos (4U) ¿USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) ¿USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk ¿USB_OTG_GOTGINT_SEDET_Pos (2U) ¿USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) ¿USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk ¿USB_OTG_GOTGINT_SRSSCHG_Pos (8U) ¿USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) ¿USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk ¿USB_OTG_GOTGINT_HNSSCHG_Pos (9U) ¿USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) ¿USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk ¿USB_OTG_GOTGINT_HNGDET_Pos (17U) ¿USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) ¿USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk ¿USB_OTG_GOTGINT_ADTOCHG_Pos (18U) ¿USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) ¿USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk ¿USB_OTG_GOTGINT_DBCDNE_Pos (19U) ¡¿USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) ¢¿USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk ¥¿USB_OTG_DCTL_RWUSIG_Pos (0U) ¦¿USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) §¿USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk ¨¿USB_OTG_DCTL_SDIS_Pos (1U) ©¿USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) ª¿USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk «¿USB_OTG_DCTL_GINSTS_Pos (2U) ¬¿USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) ¿USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk ®¿USB_OTG_DCTL_GONSTS_Pos (3U) ¯¿USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) °¿USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk ²¿USB_OTG_DCTL_TCTL_Pos (4U) ³¿USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) ´¿USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk µ¿USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) ¶¿USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) ·¿USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) ¸¿USB_OTG_DCTL_SGINAK_Pos (7U) ¹¿USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) º¿USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk »¿USB_OTG_DCTL_CGINAK_Pos (8U) ¼¿USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) ½¿USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk ¾¿USB_OTG_DCTL_SGONAK_Pos (9U) ¿¿USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) À¿USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk Á¿USB_OTG_DCTL_CGONAK_Pos (10U) ¿USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) ÿUSB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk Ä¿USB_OTG_DCTL_POPRGDNE_Pos (11U) Å¿USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) Æ¿USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk Ç¿USB_OTG_DCTL_ENCONTONBNA_Pos (17U) È¿USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) É¿USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk Ê¿USB_OTG_DCTL_DSBESLRJCT_Pos (18U) Ë¿USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) Ì¿USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk Ï¿USB_OTG_HFIR_FRIVL_Pos (0U) пUSB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) Ñ¿USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk Ô¿USB_OTG_HFNUM_FRNUM_Pos (0U) Õ¿USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) Ö¿USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk ׿USB_OTG_HFNUM_FTREM_Pos (16U) Ø¿USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) Ù¿USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk Ü¿USB_OTG_DSTS_SUSPSTS_Pos (0U) Ý¿USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) Þ¿USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk à¿USB_OTG_DSTS_ENUMSPD_Pos (1U) á¿USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) â¿USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk ã¿USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) ä¿USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) å¿USB_OTG_DSTS_EERR_Pos (3U) æ¿USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) ç¿USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk è¿USB_OTG_DSTS_FNSOF_Pos (8U) é¿USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) ê¿USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk í¿USB_OTG_GAHBCFG_GINT_Pos (0U) î¿USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) ï¿USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk ñ¿USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) ò¿USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) ó¿USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk ô¿USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) õ¿USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) ö¿USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) ÷¿USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) ø¿USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) ù¿USB_OTG_GAHBCFG_DMAEN_Pos (5U) ú¿USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) û¿USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk ü¿USB_OTG_GAHBCFG_TXFELVL_Pos (7U) ý¿USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) þ¿USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk ÿ¿USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) ÀUSB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) ÀUSB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
ÀUSB_OTG_GUSBCFG_TOCAL_Pos (0U) ÀUSB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) ÀUSB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk ÀUSB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) ÀUSB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) ÀUSB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) ÀUSB_OTG_GUSBCFG_PHYSEL_Pos (6U) ÀUSB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) ÀUSB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk ÀUSB_OTG_GUSBCFG_SRPCAP_Pos (8U) ÀUSB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) ÀUSB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk ÀUSB_OTG_GUSBCFG_HNPCAP_Pos (9U) ÀUSB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) ÀUSB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk ÀUSB_OTG_GUSBCFG_TRDT_Pos (10U) ÀUSB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) ÀUSB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk ÀUSB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) ÀUSB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) ÀUSB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) ÀUSB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) ÀUSB_OTG_GUSBCFG_PHYLPCS_Pos (15U) ÀUSB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) ÀUSB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk ÀUSB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) ÀUSB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) ¡ÀUSB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk ¢ÀUSB_OTG_GUSBCFG_ULPIAR_Pos (18U) £ÀUSB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) ¤ÀUSB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk ¥ÀUSB_OTG_GUSBCFG_ULPICSM_Pos (19U) ¦ÀUSB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) §ÀUSB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk ¨ÀUSB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) ©ÀUSB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) ªÀUSB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk «ÀUSB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) ¬ÀUSB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) ÀUSB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk ®ÀUSB_OTG_GUSBCFG_TSDPS_Pos (22U) ¯ÀUSB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) °ÀUSB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk ±ÀUSB_OTG_GUSBCFG_PCCI_Pos (23U) ²ÀUSB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) ³ÀUSB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk ´ÀUSB_OTG_GUSBCFG_PTCI_Pos (24U) µÀUSB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) ¶ÀUSB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk ·ÀUSB_OTG_GUSBCFG_ULPIIPD_Pos (25U) ¸ÀUSB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) ¹ÀUSB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk ºÀUSB_OTG_GUSBCFG_FHMOD_Pos (29U) »ÀUSB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) ¼ÀUSB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk ½ÀUSB_OTG_GUSBCFG_FDMOD_Pos (30U) ¾ÀUSB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) ¿ÀUSB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk ÀÀUSB_OTG_GUSBCFG_CTXPKT_Pos (31U) ÁÀUSB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) ÂÀUSB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk ÅÀUSB_OTG_GRSTCTL_CSRST_Pos (0U) ÆÀUSB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) ÇÀUSB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk ÈÀUSB_OTG_GRSTCTL_HSRST_Pos (1U) ÉÀUSB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) ÊÀUSB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk ËÀUSB_OTG_GRSTCTL_FCRST_Pos (2U) ÌÀUSB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) ÍÀUSB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk ÎÀUSB_OTG_GRSTCTL_RXFFLSH_Pos (4U) ÏÀUSB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) ÐÀUSB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk ÑÀUSB_OTG_GRSTCTL_TXFFLSH_Pos (5U) ÒÀUSB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) ÓÀUSB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk ÕÀUSB_OTG_GRSTCTL_TXFNUM_Pos (6U) ÖÀUSB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) ×ÀUSB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk ØÀUSB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) ÙÀUSB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) ÚÀUSB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) ÛÀUSB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) ÜÀUSB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) ÝÀUSB_OTG_GRSTCTL_DMAREQ_Pos (30U) ÞÀUSB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) ßÀUSB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk àÀUSB_OTG_GRSTCTL_AHBIDL_Pos (31U) áÀUSB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) âÀUSB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk åÀUSB_OTG_DIEPMSK_XFRCM_Pos (0U) æÀUSB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) çÀUSB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk èÀUSB_OTG_DIEPMSK_EPDM_Pos (1U) éÀUSB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) êÀUSB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk ëÀUSB_OTG_DIEPMSK_TOM_Pos (3U) ìÀUSB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) íÀUSB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk îÀUSB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) ïÀUSB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) ðÀUSB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk ñÀUSB_OTG_DIEPMSK_INEPNMM_Pos (5U) òÀUSB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) óÀUSB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk ôÀUSB_OTG_DIEPMSK_INEPNEM_Pos (6U) õÀUSB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) öÀUSB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk ÷ÀUSB_OTG_DIEPMSK_TXFURM_Pos (8U) øÀUSB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) ùÀUSB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk úÀUSB_OTG_DIEPMSK_BIM_Pos (9U) ûÀUSB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) üÀUSB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk ÿÀUSB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) ÁUSB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) ÁUSB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk ÁUSB_OTG_HPTXSTS_PTXQSAV_Pos (16U) ÁUSB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
ÁUSB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk ÁUSB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_Pos (24U) ÁUSB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk ÁUSB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) ÁUSB_OTG_HAINT_HAINT_Pos (0U) ÁUSB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) ÁUSB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk ¡ÁUSB_OTG_DOEPMSK_XFRCM_Pos (0U) ¢ÁUSB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) £ÁUSB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk ¤ÁUSB_OTG_DOEPMSK_EPDM_Pos (1U) ¥ÁUSB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) ¦ÁUSB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk §ÁUSB_OTG_DOEPMSK_AHBERRM_Pos (2U) ¨ÁUSB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) ©ÁUSB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk ªÁUSB_OTG_DOEPMSK_STUPM_Pos (3U) «ÁUSB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) ¬ÁUSB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk ÁUSB_OTG_DOEPMSK_OTEPDM_Pos (4U) ®ÁUSB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) ¯ÁUSB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk °ÁUSB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) ±ÁUSB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) ²ÁUSB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk ³ÁUSB_OTG_DOEPMSK_B2BSTUP_Pos (6U) ´ÁUSB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) µÁUSB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk ¶ÁUSB_OTG_DOEPMSK_OPEM_Pos (8U) ·ÁUSB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) ¸ÁUSB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk ¹ÁUSB_OTG_DOEPMSK_BOIM_Pos (9U) ºÁUSB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) »ÁUSB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk ¼ÁUSB_OTG_DOEPMSK_BERRM_Pos (12U) ½ÁUSB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) ¾ÁUSB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk ¿ÁUSB_OTG_DOEPMSK_NAKM_Pos (13U) ÀÁUSB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) ÁÁUSB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk ÂÁUSB_OTG_DOEPMSK_NYETM_Pos (14U) ÃÁUSB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) ÄÁUSB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk ÇÁUSB_OTG_GINTSTS_CMOD_Pos (0U) ÈÁUSB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) ÉÁUSB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk ÊÁUSB_OTG_GINTSTS_MMIS_Pos (1U) ËÁUSB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) ÌÁUSB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk ÍÁUSB_OTG_GINTSTS_OTGINT_Pos (2U) ÎÁUSB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) ÏÁUSB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk ÐÁUSB_OTG_GINTSTS_SOF_Pos (3U) ÑÁUSB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) ÒÁUSB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk ÓÁUSB_OTG_GINTSTS_RXFLVL_Pos (4U) ÔÁUSB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) ÕÁUSB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk ÖÁUSB_OTG_GINTSTS_NPTXFE_Pos (5U) ×ÁUSB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) ØÁUSB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk ÙÁUSB_OTG_GINTSTS_GINAKEFF_Pos (6U) ÚÁUSB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) ÛÁUSB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk ÜÁUSB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) ÝÁUSB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) ÞÁUSB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk ßÁUSB_OTG_GINTSTS_ESUSP_Pos (10U) àÁUSB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) áÁUSB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk âÁUSB_OTG_GINTSTS_USBSUSP_Pos (11U) ãÁUSB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) äÁUSB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk åÁUSB_OTG_GINTSTS_USBRST_Pos (12U) æÁUSB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) çÁUSB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk èÁUSB_OTG_GINTSTS_ENUMDNE_Pos (13U) éÁUSB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) êÁUSB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk ëÁUSB_OTG_GINTSTS_ISOODRP_Pos (14U) ìÁUSB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) íÁUSB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk îÁUSB_OTG_GINTSTS_EOPF_Pos (15U) ïÁUSB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) ðÁUSB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk ñÁUSB_OTG_GINTSTS_IEPINT_Pos (18U) òÁUSB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) óÁUSB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk ôÁUSB_OTG_GINTSTS_OEPINT_Pos (19U) õÁUSB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) öÁUSB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk ÷ÁUSB_OTG_GINTSTS_IISOIXFR_Pos (20U) øÁUSB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) ùÁUSB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk úÁUSB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) ûÁUSB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) üÁUSB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk ýÁUSB_OTG_GINTSTS_DATAFSUSP_Pos (22U) þÁUSB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) ÿÁUSB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk ÂUSB_OTG_GINTSTS_RSTDET_Pos (23U) ÂUSB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) ÂUSB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk ÂUSB_OTG_GINTSTS_HPRTINT_Pos (24U) ÂUSB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
ÂUSB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk ÂUSB_OTG_GINTSTS_HCINT_Pos (25U) ÂUSB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) ÂUSB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk ÂUSB_OTG_GINTSTS_PTXFE_Pos (26U) ÂUSB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) ÂUSB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk ÂUSB_OTG_GINTSTS_LPMINT_Pos (27U) ÂUSB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) ÂUSB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk ÂUSB_OTG_GINTSTS_CIDSCHG_Pos (28U) ÂUSB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) ÂUSB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk ÂUSB_OTG_GINTSTS_DISCINT_Pos (29U) ÂUSB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) ÂUSB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk ÂUSB_OTG_GINTSTS_SRQINT_Pos (30U) ÂUSB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) ÂUSB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk ÂUSB_OTG_GINTSTS_WKUINT_Pos (31U) ÂUSB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) ÂUSB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk ÂUSB_OTG_GINTMSK_MMISM_Pos (1U) ÂUSB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) ÂUSB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk ÂUSB_OTG_GINTMSK_OTGINT_Pos (2U) ¡ÂUSB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) ¢ÂUSB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk £ÂUSB_OTG_GINTMSK_SOFM_Pos (3U) ¤ÂUSB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) ¥ÂUSB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk ¦ÂUSB_OTG_GINTMSK_RXFLVLM_Pos (4U) §ÂUSB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) ¨ÂUSB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk ©ÂUSB_OTG_GINTMSK_NPTXFEM_Pos (5U) ªÂUSB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) «ÂUSB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk ¬ÂUSB_OTG_GINTMSK_GINAKEFFM_Pos (6U) ÂUSB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) ®ÂUSB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk ¯ÂUSB_OTG_GINTMSK_GONAKEFFM_Pos (7U) °ÂUSB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) ±ÂUSB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk ²ÂUSB_OTG_GINTMSK_ESUSPM_Pos (10U) ³ÂUSB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) ´ÂUSB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk µÂUSB_OTG_GINTMSK_USBSUSPM_Pos (11U) ¶ÂUSB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) ·ÂUSB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk ¸ÂUSB_OTG_GINTMSK_USBRST_Pos (12U) ¹ÂUSB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) ºÂUSB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk »ÂUSB_OTG_GINTMSK_ENUMDNEM_Pos (13U) ¼ÂUSB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) ½ÂUSB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk ¾ÂUSB_OTG_GINTMSK_ISOODRPM_Pos (14U) ¿ÂUSB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) ÀÂUSB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk ÁÂUSB_OTG_GINTMSK_EOPFM_Pos (15U) ÂÂUSB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) ÃÂUSB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk ÄÂUSB_OTG_GINTMSK_EPMISM_Pos (17U) ÅÂUSB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) ÆÂUSB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk ÇÂUSB_OTG_GINTMSK_IEPINT_Pos (18U) ÈÂUSB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) ÉÂUSB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk ÊÂUSB_OTG_GINTMSK_OEPINT_Pos (19U) ËÂUSB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) ÌÂUSB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk ÍÂUSB_OTG_GINTMSK_IISOIXFRM_Pos (20U) ÎÂUSB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) ÏÂUSB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk ÐÂUSB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) ÑÂUSB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) ÒÂUSB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk ÓÂUSB_OTG_GINTMSK_FSUSPM_Pos (22U) ÔÂUSB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) ÕÂUSB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk ÖÂUSB_OTG_GINTMSK_RSTDEM_Pos (23U) ×ÂUSB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) ØÂUSB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk ÙÂUSB_OTG_GINTMSK_PRTIM_Pos (24U) ÚÂUSB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) ÛÂUSB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk ÜÂUSB_OTG_GINTMSK_HCIM_Pos (25U) ÝÂUSB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) ÞÂUSB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk ßÂUSB_OTG_GINTMSK_PTXFEM_Pos (26U) àÂUSB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) áÂUSB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk âÂUSB_OTG_GINTMSK_LPMINTM_Pos (27U) ãÂUSB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) äÂUSB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk åÂUSB_OTG_GINTMSK_CIDSCHGM_Pos (28U) æÂUSB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) çÂUSB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk èÂUSB_OTG_GINTMSK_DISCINT_Pos (29U) éÂUSB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) êÂUSB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk ëÂUSB_OTG_GINTMSK_SRQIM_Pos (30U) ìÂUSB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) íÂUSB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk îÂUSB_OTG_GINTMSK_WUIM_Pos (31U) ïÂUSB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) ðÂUSB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk óÂUSB_OTG_DAINT_IEPINT_Pos (0U) ôÂUSB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) õÂUSB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk öÂUSB_OTG_DAINT_OEPINT_Pos (16U) ÷ÂUSB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) øÂUSB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk ûÂUSB_OTG_HAINTMSK_HAINTM_Pos (0U) üÂUSB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) ýÂUSB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk ÃUSB_OTG_GRXSTSP_EPNUM_Pos (0U) ÃUSB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) ÃUSB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk ÃUSB_OTG_GRXSTSP_BCNT_Pos (4U) ÃUSB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
ÃUSB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk ÃUSB_OTG_GRXSTSP_DPID_Pos (15U) ÃUSB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) ÃUSB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk ÃUSB_OTG_GRXSTSP_PKTSTS_Pos (17U) ÃUSB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) ÃUSB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk ÃUSB_OTG_DAINTMSK_IEPM_Pos (0U) ÃUSB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) ÃUSB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk ÃUSB_OTG_DAINTMSK_OEPM_Pos (16U) ÃUSB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) ÃUSB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk ÃUSB_OTG_CHNUM_Pos (0U) ÃUSB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) ÃUSB_OTG_CHNUM USB_OTG_CHNUM_Msk ÃUSB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) ÃUSB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) ÃUSB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) ÃUSB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) ÃUSB_OTG_BCNT_Pos (4U) ÃUSB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) ÃUSB_OTG_BCNT USB_OTG_BCNT_Msk ¢ÃUSB_OTG_DPID_Pos (15U) £ÃUSB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) ¤ÃUSB_OTG_DPID USB_OTG_DPID_Msk ¥ÃUSB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) ¦ÃUSB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) ¨ÃUSB_OTG_PKTSTS_Pos (17U) ©ÃUSB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) ªÃUSB_OTG_PKTSTS USB_OTG_PKTSTS_Msk «ÃUSB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) ¬ÃUSB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) ÃUSB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) ®ÃUSB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) °ÃUSB_OTG_EPNUM_Pos (0U) ±ÃUSB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) ²ÃUSB_OTG_EPNUM USB_OTG_EPNUM_Msk ³ÃUSB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) ´ÃUSB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) µÃUSB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) ¶ÃUSB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) ¸ÃUSB_OTG_FRMNUM_Pos (21U) ¹ÃUSB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) ºÃUSB_OTG_FRMNUM USB_OTG_FRMNUM_Msk »ÃUSB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) ¼ÃUSB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) ½ÃUSB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) ¾ÃUSB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) ÁÃUSB_OTG_GRXFSIZ_RXFD_Pos (0U) ÂÃUSB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) ÃÃUSB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk ÆÃUSB_OTG_DVBUSDIS_VBUSDT_Pos (0U) ÇÃUSB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) ÈÃUSB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk ËÃUSB_OTG_NPTXFSA_Pos (0U) ÌÃUSB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) ÍÃUSB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk ÎÃUSB_OTG_NPTXFD_Pos (16U) ÏÃUSB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) ÐÃUSB_OTG_NPTXFD USB_OTG_NPTXFD_Msk ÑÃUSB_OTG_TX0FSA_Pos (0U) ÒÃUSB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) ÓÃUSB_OTG_TX0FSA USB_OTG_TX0FSA_Msk ÔÃUSB_OTG_TX0FD_Pos (16U) ÕÃUSB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) ÖÃUSB_OTG_TX0FD USB_OTG_TX0FD_Msk ÙÃUSB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) ÚÃUSB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) ÛÃUSB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk ÞÃUSB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) ßÃUSB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) àÃUSB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk âÃUSB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) ãÃUSB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) äÃUSB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk åÃUSB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) æÃUSB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) çÃUSB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) èÃUSB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) éÃUSB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) êÃUSB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) ëÃUSB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) ìÃUSB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) îÃUSB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) ïÃUSB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) ðÃUSB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk ñÃUSB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) òÃUSB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) óÃUSB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) ôÃUSB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) õÃUSB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) öÃUSB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) ÷ÃUSB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) úÃUSB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) ûÃUSB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) üÃUSB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk ýÃUSB_OTG_DTHRCTL_ISOTHREN_Pos (1U) þÃUSB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) ÿÃUSB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk ÄUSB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) ÄUSB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk ÄUSB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
ÄUSB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHREN_Pos (16U) ÄUSB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) ÄUSB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk ÄUSB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) ÄUSB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk ÄUSB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) ÄUSB_OTG_DTHRCTL_ARPEN_Pos (27U) ÄUSB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) ÄUSB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk ¢ÄUSB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) £ÄUSB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) ¤ÄUSB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk §ÄUSB_OTG_DEACHINT_IEP1INT_Pos (1U) ¨ÄUSB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) ©ÄUSB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk ªÄUSB_OTG_DEACHINT_OEP1INT_Pos (17U) «ÄUSB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) ¬ÄUSB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk ¯ÄUSB_OTG_GCCFG_DCDET_Pos (0U) °ÄUSB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) ±ÄUSB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk ²ÄUSB_OTG_GCCFG_PDET_Pos (1U) ³ÄUSB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) ´ÄUSB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk µÄUSB_OTG_GCCFG_SDET_Pos (2U) ¶ÄUSB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) ·ÄUSB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk ¸ÄUSB_OTG_GCCFG_PS2DET_Pos (3U) ¹ÄUSB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) ºÄUSB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk »ÄUSB_OTG_GCCFG_PWRDWN_Pos (16U) ¼ÄUSB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) ½ÄUSB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk ¾ÄUSB_OTG_GCCFG_BCDEN_Pos (17U) ¿ÄUSB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) ÀÄUSB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk ÁÄUSB_OTG_GCCFG_DCDEN_Pos (18U) ÂÄUSB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) ÃÄUSB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk ÄÄUSB_OTG_GCCFG_PDEN_Pos (19U) ÅÄUSB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) ÆÄUSB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk ÇÄUSB_OTG_GCCFG_SDEN_Pos (20U) ÈÄUSB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) ÉÄUSB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk ÊÄUSB_OTG_GCCFG_VBDEN_Pos (21U) ËÄUSB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) ÌÄUSB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk ÏÄUSB_OTG_GPWRDN_ADPMEN_Pos (0U) ÐÄUSB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) ÑÄUSB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk ÒÄUSB_OTG_GPWRDN_ADPIF_Pos (23U) ÓÄUSB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) ÔÄUSB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk ×ÄUSB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) ØÄUSB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) ÙÄUSB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk ÚÄUSB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) ÛÄUSB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) ÜÄUSB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk ßÄUSB_OTG_CID_PRODUCT_ID_Pos (0U) àÄUSB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) áÄUSB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk äÄUSB_OTG_GLPMCFG_LPMEN_Pos (0U) åÄUSB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) æÄUSB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk çÄUSB_OTG_GLPMCFG_LPMACK_Pos (1U) èÄUSB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) éÄUSB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk êÄUSB_OTG_GLPMCFG_BESL_Pos (2U) ëÄUSB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) ìÄUSB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk íÄUSB_OTG_GLPMCFG_REMWAKE_Pos (6U) îÄUSB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) ïÄUSB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk ðÄUSB_OTG_GLPMCFG_L1SSEN_Pos (7U) ñÄUSB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) òÄUSB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk óÄUSB_OTG_GLPMCFG_BESLTHRS_Pos (8U) ôÄUSB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) õÄUSB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk öÄUSB_OTG_GLPMCFG_L1DSEN_Pos (12U) ÷ÄUSB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) øÄUSB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk ùÄUSB_OTG_GLPMCFG_LPMRSP_Pos (13U) úÄUSB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) ûÄUSB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk üÄUSB_OTG_GLPMCFG_SLPSTS_Pos (15U) ýÄUSB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) þÄUSB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk ÿÄUSB_OTG_GLPMCFG_L1RSMOK_Pos (16U) ÅUSB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) ÅUSB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk ÅUSB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) ÅUSB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) ÅUSB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
ÅUSB_OTG_GLPMCFG_LPMRCNT_Pos (21U) ÅUSB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) ÅUSB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk ÅUSB_OTG_GLPMCFG_SNDLPM_Pos (24U) ÅUSB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) ÅUSB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk ÅUSB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) ÅUSB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) ÅUSB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk ÅUSB_OTG_GLPMCFG_ENBESL_Pos (28U) ÅUSB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) ÅUSB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk ÅUSB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) ÅUSB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) ÅUSB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk ÅUSB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) ÅUSB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) ÅUSB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk ÅUSB_OTG_DIEPEACHMSK1_TOM_Pos (3U) ÅUSB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) ÅUSB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk ÅUSB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) ÅUSB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) ÅUSB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk ÅUSB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) ÅUSB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) ¡ÅUSB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk ¢ÅUSB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) £ÅUSB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) ¤ÅUSB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk ¥ÅUSB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) ¦ÅUSB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) §ÅUSB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk ¨ÅUSB_OTG_DIEPEACHMSK1_BIM_Pos (9U) ©ÅUSB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) ªÅUSB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk «ÅUSB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) ¬ÅUSB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) ÅUSB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk °ÅUSB_OTG_HPRT_PCSTS_Pos (0U) ±ÅUSB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) ²ÅUSB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk ³ÅUSB_OTG_HPRT_PCDET_Pos (1U) ´ÅUSB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) µÅUSB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk ¶ÅUSB_OTG_HPRT_PENA_Pos (2U) ·ÅUSB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) ¸ÅUSB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk ¹ÅUSB_OTG_HPRT_PENCHNG_Pos (3U) ºÅUSB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) »ÅUSB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk ¼ÅUSB_OTG_HPRT_POCA_Pos (4U) ½ÅUSB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) ¾ÅUSB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk ¿ÅUSB_OTG_HPRT_POCCHNG_Pos (5U) ÀÅUSB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) ÁÅUSB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk ÂÅUSB_OTG_HPRT_PRES_Pos (6U) ÃÅUSB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) ÄÅUSB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk ÅÅUSB_OTG_HPRT_PSUSP_Pos (7U) ÆÅUSB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) ÇÅUSB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk ÈÅUSB_OTG_HPRT_PRST_Pos (8U) ÉÅUSB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) ÊÅUSB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk ÌÅUSB_OTG_HPRT_PLSTS_Pos (10U) ÍÅUSB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) ÎÅUSB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk ÏÅUSB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) ÐÅUSB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) ÑÅUSB_OTG_HPRT_PPWR_Pos (12U) ÒÅUSB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) ÓÅUSB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk ÕÅUSB_OTG_HPRT_PTCTL_Pos (13U) ÖÅUSB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) ×ÅUSB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk ØÅUSB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) ÙÅUSB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) ÚÅUSB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) ÛÅUSB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) ÝÅUSB_OTG_HPRT_PSPD_Pos (17U) ÞÅUSB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) ßÅUSB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk àÅUSB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) áÅUSB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) äÅUSB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) åÅUSB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) æÅUSB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk çÅUSB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) èÅUSB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) éÅUSB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk êÅUSB_OTG_DOEPEACHMSK1_TOM_Pos (3U) ëÅUSB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) ìÅUSB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk íÅUSB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) îÅUSB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) ïÅUSB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk ðÅUSB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) ñÅUSB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) òÅUSB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk óÅUSB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) ôÅUSB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) õÅUSB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk öÅUSB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) ÷ÅUSB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) øÅUSB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk ùÅUSB_OTG_DOEPEACHMSK1_BIM_Pos (9U) úÅUSB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) ûÅUSB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk üÅUSB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) ýÅUSB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) þÅUSB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk ÿÅUSB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) ÆUSB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) ÆUSB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk ÆUSB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) ÆUSB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) ÆUSB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk ÆUSB_OTG_HPTXFSIZ_PTXSA_Pos (0U) ÆUSB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) ÆUSB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk ÆUSB_OTG_HPTXFSIZ_PTXFD_Pos (16U) ÆUSB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) ÆUSB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk ÆUSB_OTG_DIEPCTL_MPSIZ_Pos (0U) ÆUSB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) ÆUSB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk ÆUSB_OTG_DIEPCTL_USBAEP_Pos (15U) ÆUSB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) ÆUSB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk ÆUSB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) ÆUSB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) ÆUSB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk ÆUSB_OTG_DIEPCTL_NAKSTS_Pos (17U) ÆUSB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) ÆUSB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk ÆUSB_OTG_DIEPCTL_EPTYP_Pos (18U) ÆUSB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) ÆUSB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk ÆUSB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) ÆUSB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) ¡ÆUSB_OTG_DIEPCTL_STALL_Pos (21U) ¢ÆUSB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) £ÆUSB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk ¥ÆUSB_OTG_DIEPCTL_TXFNUM_Pos (22U) ¦ÆUSB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) §ÆUSB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk ¨ÆUSB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) ©ÆUSB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) ªÆUSB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) «ÆUSB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) ¬ÆUSB_OTG_DIEPCTL_CNAK_Pos (26U) ÆUSB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) ®ÆUSB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk ¯ÆUSB_OTG_DIEPCTL_SNAK_Pos (27U) °ÆUSB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) ±ÆUSB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk ²ÆUSB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) ³ÆUSB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) ´ÆUSB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk µÆUSB_OTG_DIEPCTL_SODDFRM_Pos (29U) ¶ÆUSB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) ·ÆUSB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk ¸ÆUSB_OTG_DIEPCTL_EPDIS_Pos (30U) ¹ÆUSB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) ºÆUSB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk »ÆUSB_OTG_DIEPCTL_EPENA_Pos (31U) ¼ÆUSB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) ½ÆUSB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk ÀÆUSB_OTG_HCCHAR_MPSIZ_Pos (0U) ÁÆUSB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) ÂÆUSB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk ÄÆUSB_OTG_HCCHAR_EPNUM_Pos (11U) ÅÆUSB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) ÆÆUSB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk ÇÆUSB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) ÈÆUSB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) ÉÆUSB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) ÊÆUSB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) ËÆUSB_OTG_HCCHAR_EPDIR_Pos (15U) ÌÆUSB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) ÍÆUSB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk ÎÆUSB_OTG_HCCHAR_LSDEV_Pos (17U) ÏÆUSB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) ÐÆUSB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk ÒÆUSB_OTG_HCCHAR_EPTYP_Pos (18U) ÓÆUSB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) ÔÆUSB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk ÕÆUSB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) ÖÆUSB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) ØÆUSB_OTG_HCCHAR_MC_Pos (20U) ÙÆUSB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) ÚÆUSB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk ÛÆUSB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) ÜÆUSB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) ÞÆUSB_OTG_HCCHAR_DAD_Pos (22U) ßÆUSB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) àÆUSB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk áÆUSB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) âÆUSB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) ãÆUSB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) äÆUSB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) åÆUSB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) æÆUSB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) çÆUSB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) èÆUSB_OTG_HCCHAR_ODDFRM_Pos (29U) éÆUSB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) êÆUSB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk ëÆUSB_OTG_HCCHAR_CHDIS_Pos (30U) ìÆUSB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) íÆUSB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk îÆUSB_OTG_HCCHAR_CHENA_Pos (31U) ïÆUSB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) ðÆUSB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk ôÆUSB_OTG_HCSPLT_PRTADDR_Pos (0U) õÆUSB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) öÆUSB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk ÷ÆUSB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) øÆUSB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) ùÆUSB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) úÆUSB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) ûÆUSB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) üÆUSB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) ýÆUSB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) ÿÆUSB_OTG_HCSPLT_HUBADDR_Pos (7U) ÇUSB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk ÇUSB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
ÇUSB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) ÇUSB_OTG_HCSPLT_XACTPOS_Pos (14U) ÇUSB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) ÇUSB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk ÇUSB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) ÇUSB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) ÇUSB_OTG_HCSPLT_COMPLSPLT_Pos (16U) ÇUSB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) ÇUSB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk ÇUSB_OTG_HCSPLT_SPLITEN_Pos (31U) ÇUSB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) ÇUSB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk ÇUSB_OTG_HCINT_XFRC_Pos (0U) ÇUSB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) ÇUSB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk ÇUSB_OTG_HCINT_CHH_Pos (1U) ÇUSB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) ÇUSB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk ÇUSB_OTG_HCINT_AHBERR_Pos (2U) ÇUSB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) ÇUSB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk ÇUSB_OTG_HCINT_STALL_Pos (3U) ¡ÇUSB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) ¢ÇUSB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk £ÇUSB_OTG_HCINT_NAK_Pos (4U) ¤ÇUSB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) ¥ÇUSB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk ¦ÇUSB_OTG_HCINT_ACK_Pos (5U) §ÇUSB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) ¨ÇUSB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk ©ÇUSB_OTG_HCINT_NYET_Pos (6U) ªÇUSB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) «ÇUSB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk ¬ÇUSB_OTG_HCINT_TXERR_Pos (7U) ÇUSB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) ®ÇUSB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk ¯ÇUSB_OTG_HCINT_BBERR_Pos (8U) °ÇUSB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) ±ÇUSB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk ²ÇUSB_OTG_HCINT_FRMOR_Pos (9U) ³ÇUSB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) ´ÇUSB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk µÇUSB_OTG_HCINT_DTERR_Pos (10U) ¶ÇUSB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) ·ÇUSB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk ºÇUSB_OTG_DIEPINT_XFRC_Pos (0U) »ÇUSB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) ¼ÇUSB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk ½ÇUSB_OTG_DIEPINT_EPDISD_Pos (1U) ¾ÇUSB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) ¿ÇUSB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk ÀÇUSB_OTG_DIEPINT_AHBERR_Pos (2U) ÁÇUSB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) ÂÇUSB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk ÃÇUSB_OTG_DIEPINT_TOC_Pos (3U) ÄÇUSB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) ÅÇUSB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk ÆÇUSB_OTG_DIEPINT_ITTXFE_Pos (4U) ÇÇUSB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) ÈÇUSB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk ÉÇUSB_OTG_DIEPINT_INEPNM_Pos (5U) ÊÇUSB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) ËÇUSB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk ÌÇUSB_OTG_DIEPINT_INEPNE_Pos (6U) ÍÇUSB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) ÎÇUSB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk ÏÇUSB_OTG_DIEPINT_TXFE_Pos (7U) ÐÇUSB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) ÑÇUSB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk ÒÇUSB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) ÓÇUSB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) ÔÇUSB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk ÕÇUSB_OTG_DIEPINT_BNA_Pos (9U) ÖÇUSB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) ×ÇUSB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk ØÇUSB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) ÙÇUSB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) ÚÇUSB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk ÛÇUSB_OTG_DIEPINT_BERR_Pos (12U) ÜÇUSB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) ÝÇUSB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk ÞÇUSB_OTG_DIEPINT_NAK_Pos (13U) ßÇUSB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) àÇUSB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk ãÇUSB_OTG_HCINTMSK_XFRCM_Pos (0U) äÇUSB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) åÇUSB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk æÇUSB_OTG_HCINTMSK_CHHM_Pos (1U) çÇUSB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) èÇUSB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk éÇUSB_OTG_HCINTMSK_AHBERR_Pos (2U) êÇUSB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) ëÇUSB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk ìÇUSB_OTG_HCINTMSK_STALLM_Pos (3U) íÇUSB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) îÇUSB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk ïÇUSB_OTG_HCINTMSK_NAKM_Pos (4U) ðÇUSB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) ñÇUSB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk òÇUSB_OTG_HCINTMSK_ACKM_Pos (5U) óÇUSB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) ôÇUSB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk õÇUSB_OTG_HCINTMSK_NYET_Pos (6U) öÇUSB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) ÷ÇUSB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk øÇUSB_OTG_HCINTMSK_TXERRM_Pos (7U) ùÇUSB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) úÇUSB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk ûÇUSB_OTG_HCINTMSK_BBERRM_Pos (8U) üÇUSB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) ýÇUSB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk þÇUSB_OTG_HCINTMSK_FRMORM_Pos (9U) ÿÇUSB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) ÈUSB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk ÈUSB_OTG_HCINTMSK_DTERRM_Pos (10U) ÈUSB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) ÈUSB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk ÈUSB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) ÈUSB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) ÈUSB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk ÈUSB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) ÈUSB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) ÈUSB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk ÈUSB_OTG_DIEPTSIZ_MULCNT_Pos (29U) ÈUSB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) ÈUSB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk ÈUSB_OTG_HCTSIZ_XFRSIZ_Pos (0U) ÈUSB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) ÈUSB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk ÈUSB_OTG_HCTSIZ_PKTCNT_Pos (19U) ÈUSB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) ÈUSB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk ÈUSB_OTG_HCTSIZ_DOPING_Pos (31U) ÈUSB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) ÈUSB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk ÈUSB_OTG_HCTSIZ_DPID_Pos (29U) ÈUSB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) ÈUSB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk ÈUSB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) ÈUSB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) ¡ÈUSB_OTG_DIEPDMA_DMAADDR_Pos (0U) ¢ÈUSB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) £ÈUSB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk ¦ÈUSB_OTG_HCDMA_DMAADDR_Pos (0U) §ÈUSB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) ¨ÈUSB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk «ÈUSB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) ¬ÈUSB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) ÈUSB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk °ÈUSB_OTG_DIEPTXF_INEPTXSA_Pos (0U) ±ÈUSB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) ²ÈUSB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk ³ÈUSB_OTG_DIEPTXF_INEPTXFD_Pos (16U) ´ÈUSB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) µÈUSB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk ¹ÈUSB_OTG_DOEPCTL_MPSIZ_Pos (0U) ºÈUSB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) »ÈUSB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk ¼ÈUSB_OTG_DOEPCTL_USBAEP_Pos (15U) ½ÈUSB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) ¾ÈUSB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk ¿ÈUSB_OTG_DOEPCTL_NAKSTS_Pos (17U) ÀÈUSB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) ÁÈUSB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk ÂÈUSB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) ÃÈUSB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) ÄÈUSB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk ÅÈUSB_OTG_DOEPCTL_SODDFRM_Pos (29U) ÆÈUSB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) ÇÈUSB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk ÈÈUSB_OTG_DOEPCTL_EPTYP_Pos (18U) ÉÈUSB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) ÊÈUSB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk ËÈUSB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) ÌÈUSB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) ÍÈUSB_OTG_DOEPCTL_SNPM_Pos (20U) ÎÈUSB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) ÏÈUSB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk ÐÈUSB_OTG_DOEPCTL_STALL_Pos (21U) ÑÈUSB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) ÒÈUSB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk ÓÈUSB_OTG_DOEPCTL_CNAK_Pos (26U) ÔÈUSB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) ÕÈUSB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk ÖÈUSB_OTG_DOEPCTL_SNAK_Pos (27U) ×ÈUSB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) ØÈUSB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk ÙÈUSB_OTG_DOEPCTL_EPDIS_Pos (30U) ÚÈUSB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) ÛÈUSB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk ÜÈUSB_OTG_DOEPCTL_EPENA_Pos (31U) ÝÈUSB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) ÞÈUSB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk áÈUSB_OTG_DOEPINT_XFRC_Pos (0U) âÈUSB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) ãÈUSB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk äÈUSB_OTG_DOEPINT_EPDISD_Pos (1U) åÈUSB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) æÈUSB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk çÈUSB_OTG_DOEPINT_AHBERR_Pos (2U) èÈUSB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) éÈUSB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk êÈUSB_OTG_DOEPINT_STUP_Pos (3U) ëÈUSB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) ìÈUSB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk íÈUSB_OTG_DOEPINT_OTEPDIS_Pos (4U) îÈUSB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) ïÈUSB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk ðÈUSB_OTG_DOEPINT_OTEPSPR_Pos (5U) ñÈUSB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) òÈUSB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk óÈUSB_OTG_DOEPINT_B2BSTUP_Pos (6U) ôÈUSB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) õÈUSB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk öÈUSB_OTG_DOEPINT_OUTPKTERR_Pos (8U) ÷ÈUSB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) øÈUSB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk ùÈUSB_OTG_DOEPINT_BERR_Pos (12U) úÈUSB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) ûÈUSB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk üÈUSB_OTG_DOEPINT_NAK_Pos (13U) ýÈUSB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) þÈUSB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk ÿÈUSB_OTG_DOEPINT_NYET_Pos (14U) ÉUSB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) ÉUSB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk ÉUSB_OTG_DOEPINT_STPKTRX_Pos (15U) ÉUSB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) ÉUSB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk ÉUSB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) ÉUSB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) ÉUSB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk ÉUSB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) ÉUSB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) ÉUSB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk ÉUSB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) ÉUSB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) ÉUSB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk ÉUSB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) ÉUSB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) ÉUSB_OTG_PCGCCTL_STOPCLK_Pos (0U) ÉUSB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) ÉUSB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk ÉUSB_OTG_PCGCCTL_GATECLK_Pos (1U) ÉUSB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) ÉUSB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk ÉUSB_OTG_PCGCCTL_PHYSUSP_Pos (4U) ÉUSB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) ÉUSB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk ÉIS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2) || ((INSTANCE) == ADC3)) ±ÉIS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) ³ÉIS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || ((INSTANCE) == ADC3_COMMON)) ·ÉIS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) ºÉIS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) ¼ÉIS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) ÀÉIS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) ÃÉIS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) ÅÉIS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) ÈÉIS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || ((INSTANCE) == DLYB_SDMMC2) || ((INSTANCE) == DLYB_QUADSPI)) ÌÉIS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || ((INSTANCE) == DFSDM1_Filter1) || ((INSTANCE) == DFSDM1_Filter2) || ((INSTANCE) == DFSDM1_Filter3)) ÑÉIS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || ((INSTANCE) == DFSDM1_Channel1) || ((INSTANCE) == DFSDM1_Channel2) || ((INSTANCE) == DFSDM1_Channel3) || ((INSTANCE) == DFSDM1_Channel4) || ((INSTANCE) == DFSDM1_Channel5) || ((INSTANCE) == DFSDM1_Channel6) || ((INSTANCE) == DFSDM1_Channel7)) ÚÉIS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || ((INSTANCE) == RAMECC1_Monitor2) || ((INSTANCE) == RAMECC1_Monitor3) || ((INSTANCE) == RAMECC1_Monitor4) || ((INSTANCE) == RAMECC1_Monitor5) || ((INSTANCE) == RAMECC2_Monitor1) || ((INSTANCE) == RAMECC2_Monitor2) || ((INSTANCE) == RAMECC2_Monitor3) || ((INSTANCE) == RAMECC2_Monitor4) || ((INSTANCE) == RAMECC2_Monitor5) || ((INSTANCE) == RAMECC3_Monitor1) || ((INSTANCE) == RAMECC3_Monitor2)) èÉIS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || ((INSTANCE) == DMA1_Stream1) || ((INSTANCE) == DMA1_Stream2) || ((INSTANCE) == DMA1_Stream3) || ((INSTANCE) == DMA1_Stream4) || ((INSTANCE) == DMA1_Stream5) || ((INSTANCE) == DMA1_Stream6) || ((INSTANCE) == DMA1_Stream7) || ((INSTANCE) == DMA2_Stream0) || ((INSTANCE) == DMA2_Stream1) || ((INSTANCE) == DMA2_Stream2) || ((INSTANCE) == DMA2_Stream3) || ((INSTANCE) == DMA2_Stream4) || ((INSTANCE) == DMA2_Stream5) || ((INSTANCE) == DMA2_Stream6) || ((INSTANCE) == DMA2_Stream7) || ((INSTANCE) == BDMA_Channel0) || ((INSTANCE) == BDMA_Channel1) || ((INSTANCE) == BDMA_Channel2) || ((INSTANCE) == BDMA_Channel3) || ((INSTANCE) == BDMA_Channel4) || ((INSTANCE) == BDMA_Channel5) || ((INSTANCE) == BDMA_Channel6) || ((INSTANCE) == BDMA_Channel7)) ÊIS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || ((INSTANCE) == BDMA_Channel1) || ((INSTANCE) == BDMA_Channel2) || ((INSTANCE) == BDMA_Channel3) || ((INSTANCE) == BDMA_Channel4) || ((INSTANCE) == BDMA_Channel5) || ((INSTANCE) == BDMA_Channel6) || ((INSTANCE) == BDMA_Channel7)) ÊIS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || ((INSTANCE) == DMA1_Stream1) || ((INSTANCE) == DMA1_Stream2) || ((INSTANCE) == DMA1_Stream3) || ((INSTANCE) == DMA1_Stream4) || ((INSTANCE) == DMA1_Stream5) || ((INSTANCE) == DMA1_Stream6) || ((INSTANCE) == DMA1_Stream7) || ((INSTANCE) == DMA2_Stream0) || ((INSTANCE) == DMA2_Stream1) || ((INSTANCE) == DMA2_Stream2) || ((INSTANCE) == DMA2_Stream3) || ((INSTANCE) == DMA2_Stream4) || ((INSTANCE) == DMA2_Stream5) || ((INSTANCE) == DMA2_Stream6) || ((INSTANCE) == DMA2_Stream7) || ((INSTANCE) == BDMA_Channel0) || ((INSTANCE) == BDMA_Channel1) || ((INSTANCE) == BDMA_Channel2) || ((INSTANCE) == BDMA_Channel3) || ((INSTANCE) == BDMA_Channel4) || ((INSTANCE) == BDMA_Channel5) || ((INSTANCE) == BDMA_Channel6) || ((INSTANCE) == BDMA_Channel7)) ¦ÊIS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || ((INSTANCE) == BDMA_Channel1) || ((INSTANCE) == BDMA_Channel2) || ((INSTANCE) == BDMA_Channel3) || ((INSTANCE) == BDMA_Channel4) || ((INSTANCE) == BDMA_Channel5) || ((INSTANCE) == BDMA_Channel6) || ((INSTANCE) == BDMA_Channel7)) °ÊIS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || ((INSTANCE) == DMA1_Stream1) || ((INSTANCE) == DMA1_Stream2) || ((INSTANCE) == DMA1_Stream3) || ((INSTANCE) == DMA1_Stream4) || ((INSTANCE) == DMA1_Stream5) || ((INSTANCE) == DMA1_Stream6) || ((INSTANCE) == DMA1_Stream7) || ((INSTANCE) == DMA2_Stream0) || ((INSTANCE) == DMA2_Stream1) || ((INSTANCE) == DMA2_Stream2) || ((INSTANCE) == DMA2_Stream3) || ((INSTANCE) == DMA2_Stream4) || ((INSTANCE) == DMA2_Stream5) || ((INSTANCE) == DMA2_Stream6) || ((INSTANCE) == DMA2_Stream7)) ÂÊIS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || ((INSTANCE) == DMA1_Stream1) || ((INSTANCE) == DMA1_Stream2) || ((INSTANCE) == DMA1_Stream3) || ((INSTANCE) == DMA1_Stream4) || ((INSTANCE) == DMA1_Stream5) || ((INSTANCE) == DMA1_Stream6) || ((INSTANCE) == DMA1_Stream7) || ((INSTANCE) == DMA2_Stream0) || ((INSTANCE) == DMA2_Stream1) || ((INSTANCE) == DMA2_Stream2) || ((INSTANCE) == DMA2_Stream3) || ((INSTANCE) == DMA2_Stream4) || ((INSTANCE) == DMA2_Stream5) || ((INSTANCE) == DMA2_Stream6) || ((INSTANCE) == DMA2_Stream7)) ÔÊIS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || ((INSTANCE) == DMAMUX1_RequestGenerator1) || ((INSTANCE) == DMAMUX1_RequestGenerator2) || ((INSTANCE) == DMAMUX1_RequestGenerator3) || ((INSTANCE) == DMAMUX1_RequestGenerator4) || ((INSTANCE) == DMAMUX1_RequestGenerator5) || ((INSTANCE) == DMAMUX1_RequestGenerator6) || ((INSTANCE) == DMAMUX1_RequestGenerator7) || ((INSTANCE) == DMAMUX2_RequestGenerator0) || ((INSTANCE) == DMAMUX2_RequestGenerator1) || ((INSTANCE) == DMAMUX2_RequestGenerator2) || ((INSTANCE) == DMAMUX2_RequestGenerator3) || ((INSTANCE) == DMAMUX2_RequestGenerator4) || ((INSTANCE) == DMAMUX2_RequestGenerator5) || ((INSTANCE) == DMAMUX2_RequestGenerator6) || ((INSTANCE) == DMAMUX2_RequestGenerator7)) æÊIS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) éÊIS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || ((INSTANCE) == MDMA_Channel1) || ((INSTANCE) == MDMA_Channel2) || ((INSTANCE) == MDMA_Channel3) || ((INSTANCE) == MDMA_Channel4) || ((INSTANCE) == MDMA_Channel5) || ((INSTANCE) == MDMA_Channel6) || ((INSTANCE) == MDMA_Channel7) || ((INSTANCE) == MDMA_Channel8) || ((INSTANCE) == MDMA_Channel9) || ((INSTANCE) == MDMA_Channel10) || ((INSTANCE) == MDMA_Channel11) || ((INSTANCE) == MDMA_Channel12) || ((INSTANCE) == MDMA_Channel13) || ((INSTANCE) == MDMA_Channel14) || ((INSTANCE) == MDMA_Channel15)) ûÊIS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) þÊIS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || ((__INSTANCE__) == FDCAN2)) ËIS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) ËIS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE) || ((INSTANCE) == GPIOF) || ((INSTANCE) == GPIOG) || ((INSTANCE) == GPIOH) || ((INSTANCE) == GPIOI) || ((INSTANCE) == GPIOJ) || ((INSTANCE) == GPIOK)) ËIS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) ËIS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) ËIS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) ËHSEM_CPU1_COREID (0x00000003U) ËHSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) ËHSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) ËHSEM_SEMID_MIN (0U) ËHSEM_SEMID_MAX (31U) ËHSEM_PROCESSID_MIN (0U) ¡ËHSEM_PROCESSID_MAX (255U) £ËHSEM_CLEAR_KEY_MIN (0U) ¤ËHSEM_CLEAR_KEY_MAX (0xFFFFU) §ËIS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2) || ((INSTANCE) == I2C3) || ((INSTANCE) == I2C4)) ËIS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2) || ((INSTANCE) == I2C3) || ((INSTANCE) == I2C4)) ³ËIS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) ¶ËIS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3)) »ËIS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) ¾ËIS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) ÁËIS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) ÄËIS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || ((_INSTANCE_) == SDMMC2)) ÈËIS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3) || ((INSTANCE) == SPI4) || ((INSTANCE) == SPI5) || ((INSTANCE) == SPI6)) ÏËIS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3)) ÔËIS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) ×ËIS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || ((INSTANCE) == LPTIM2) || ((INSTANCE) == LPTIM3) || ((INSTANCE) == LPTIM4) || ((INSTANCE) == LPTIM5)) ÞËIS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || ((INSTANCE) == LPTIM2)) âËIS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM13) || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) òËIS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM13) || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) ÌIS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM15)) ÌIS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ÌIS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ÌIS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8)) ÌIS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8)) ¡ÌIS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8)) §ÌIS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15)) °ÌIS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) ½ÌIS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) ÈÌIS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15)) ÑÌIS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ÙÌIS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) áÌIS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) êÌIS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ñÌIS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM15)) ýÌIS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM15)) ÍIS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8)) ÍIS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) ÍIS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) ÍIS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) ¥ÍIS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8)) ¨ÍIS_TIM_CCX_INSTANCE(INSTANCE,CHANNEL) ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_5) || ((CHANNEL) == TIM_CHANNEL_6))) || (((INSTANCE) == TIM2) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1)|| ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM4) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM5) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM8) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_5) || ((CHANNEL) == TIM_CHANNEL_6))) || (((INSTANCE) == TIM12) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM13) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM14) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM15) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM16) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM17) && (((CHANNEL) == TIM_CHANNEL_1)))) æÍIS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) îÍIS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8)) òÍIS_TIM_CCXN_INSTANCE(INSTANCE,CHANNEL) ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))) || (((INSTANCE) == TIM8) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))) || (((INSTANCE) == TIM15) && ((CHANNEL) == TIM_CHANNEL_1)) || (((INSTANCE) == TIM16) && ((CHANNEL) == TIM_CHANNEL_1)) || (((INSTANCE) == TIM17) && ((CHANNEL) == TIM_CHANNEL_1))) ÎIS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ÎIS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) ÎIS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM6) || ((__INSTANCE__) == TIM8) || ((__INSTANCE__) == TIM12) || ((__INSTANCE__) == TIM15)) ¤ÎIS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16) || ((INSTANCE) == TIM17)) °ÎIS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ¹ÎIS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8)) ÂÎIS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM15)) ÍÎIS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM15)) ØÎIS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3)) ÞÎIS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM5)) ãÎIS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8)) èÎIS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM15) || ((__INSTANCE__) == TIM8)) ñÎIS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) ôÎIS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART6)) úÎIS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART6)) ÏIS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8)) ÏIS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8)) ÏIS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8)) ÏIS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8) || ((INSTANCE) == LPUART1)) ©ÏIS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8) || ((INSTANCE) == LPUART1)) ´ÏIS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8) || ((INSTANCE) == LPUART1)) ¿ÏIS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8)) ÉÏIS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8) || ((INSTANCE) == LPUART1)) ÔÏIS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6) || ((INSTANCE) == UART7) || ((INSTANCE) == UART8)) ÞÏIS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART6)) äÏIS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) çÏIS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) éÏIS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) ìÏIS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) îÏIS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) ñÏIS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) ôÏIS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B) || ((INSTANCE) == SAI2_Block_A) || ((INSTANCE) == SAI2_Block_B) || ((INSTANCE) == SAI3_Block_A) || ((INSTANCE) == SAI3_Block_B) || ((INSTANCE) == SAI4_Block_A) || ((INSTANCE) == SAI4_Block_B)) þÏIS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) ÐIS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || ((INSTANCE) == OPAMP2)) ÐIS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) ÐIS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || ((INSTANCE) == USB_OTG_HS)) ÐIS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || ((INSTANCE) == USB_OTG_HS)) ÐHASH_RNG_IRQn RNG_IRQn ÐTIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn ÐTIM1_UP_TIM10_IRQn TIM1_UP_IRQn ÐTIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn ÐPVD_IRQn PVD_AVD_IRQn ÐHASH_RNG_IRQHandler RNG_IRQHandler ¡ÐTIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler ¢ÐTIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler £ÐTIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler ¤ÐPVD_IRQHandler PVD_AVD_IRQHandler §ÐCOMP_IRQHandler COMP1_IRQHandler Ì Á ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/ ../Drivers/CMSIS/Include/ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stm32h743xx.h core_cm7.h system_stm32h7xx.h stdint.h ìa
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../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ÜNonMaskableInt_IRQn rHardFault_IRQn sMemoryManagement_IRQn tBusFault_IRQn uUsageFault_IRQn vSVCall_IRQn {DebugMonitor_IRQn |PendSV_IRQn ~SysTick_IRQn WWDG_IRQn PVD_AVD_IRQn TAMP_STAMP_IRQn RTC_WKUP_IRQn FLASH_IRQn RCC_IRQn EXTI0_IRQn EXTI1_IRQn EXTI2_IRQn EXTI3_IRQn EXTI4_IRQn
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DMA1_Stream0_IRQn DMA1_Stream1_IRQn DMA1_Stream2_IRQn DMA1_Stream3_IRQn DMA1_Stream4_IRQn DMA1_Stream5_IRQn DMA1_Stream6_IRQn ADC_IRQn FDCAN1_IT0_IRQn FDCAN2_IT0_IRQn FDCAN1_IT1_IRQn FDCAN2_IT1_IRQn EXTI9_5_IRQn TIM1_BRK_IRQn TIM1_UP_IRQn TIM1_TRG_COM_IRQn TIM1_CC_IRQn TIM2_IRQn TIM3_IRQn TIM4_IRQn I2C1_EV_IRQn I2C1_ER_IRQn I2C2_EV_IRQn !I2C2_ER_IRQn "SPI1_IRQn #SPI2_IRQn $USART1_IRQn %USART2_IRQn &USART3_IRQn 'EXTI15_10_IRQn (RTC_Alarm_IRQn )TIM8_BRK_TIM12_IRQn +TIM8_UP_TIM13_IRQn ,TIM8_TRG_COM_TIM14_IRQn -TIM8_CC_IRQn .DMA1_Stream7_IRQn /FMC_IRQn 0SDMMC1_IRQn 1TIM5_IRQn 2SPI3_IRQn 3UART4_IRQn 4UART5_IRQn 5TIM6_DAC_IRQn 6TIM7_IRQn 7DMA2_Stream0_IRQn 8DMA2_Stream1_IRQn 9DMA2_Stream2_IRQn :DMA2_Stream3_IRQn ;DMA2_Stream4_IRQn <ETH_IRQn =ETH_WKUP_IRQn >FDCAN_CAL_IRQn ?DMA2_Stream5_IRQn Ä DMA2_Stream6_IRQn Å DMA2_Stream7_IRQn Æ USART6_IRQn Ç I2C3_EV_IRQn È I2C3_ER_IRQn É OTG_HS_EP1_OUT_IRQn Ê OTG_HS_EP1_IN_IRQn Ë OTG_HS_WKUP_IRQn Ì OTG_HS_IRQn Í DCMI_IRQn Î RNG_IRQn Ð FPU_IRQn Ñ UART7_IRQn Ò UART8_IRQn Ó SPI4_IRQn Ô SPI5_IRQn Õ SPI6_IRQn Ö SAI1_IRQn × LTDC_IRQn Ø LTDC_ER_IRQn Ù DMA2D_IRQn Ú SAI2_IRQn Û QUADSPI_IRQn Ü LPTIM1_IRQn Ý CEC_IRQn Þ I2C4_EV_IRQn ß I2C4_ER_IRQn à SPDIF_RX_IRQn á OTG_FS_EP1_OUT_IRQn â OTG_FS_EP1_IN_IRQn ã OTG_FS_WKUP_IRQn ä OTG_FS_IRQn å DMAMUX1_OVR_IRQn æ HRTIM1_Master_IRQn ç HRTIM1_TIMA_IRQn è HRTIM1_TIMB_IRQn é HRTIM1_TIMC_IRQn ê HRTIM1_TIMD_IRQn ë HRTIM1_TIME_IRQn ì HRTIM1_FLT_IRQn í DFSDM1_FLT0_IRQn î DFSDM1_FLT1_IRQn ï DFSDM1_FLT2_IRQn ð DFSDM1_FLT3_IRQn ñ SAI3_IRQn ò SWPMI1_IRQn ó TIM15_IRQn ô TIM16_IRQn õ TIM17_IRQn ö MDIOS_WKUP_IRQn ÷ MDIOS_IRQn ø JPEG_IRQn ù MDMA_IRQn ú SDMMC2_IRQn ü HSEM1_IRQn ý ADC3_IRQn ÿ DMAMUX2_OVR_IRQn BDMA_Channel0_IRQn BDMA_Channel1_IRQn BDMA_Channel2_IRQn BDMA_Channel3_IRQn BDMA_Channel4_IRQn
BDMA_Channel5_IRQn BDMA_Channel6_IRQn BDMA_Channel7_IRQn COMP_IRQn LPTIM2_IRQn LPTIM3_IRQn LPTIM4_IRQn LPTIM5_IRQn LPUART1_IRQn CRS_IRQn ECC_IRQn SAI4_IRQn WAKEUP_PIN_IRQn PIRQn_Type Æ È*áÌ ISR á # IER á # CR á # CFGR á # CFGR2 á # SMPR1 á # SMPR2 á # PCSEL á # LTR1 á # HTR1 á #$ RESERVED1 Y #( RESERVED2 Y #, SQR1 á #0 SQR2 á #4 SQR3 á #8 SQR4 á #< DR á #@ RESERVED3 Y #D RESERVED4 Y #H JSQR á #LY RESERVED5 } #P OFR1 á #` OFR2 á #d OFR3 á #h OFR4 á #lÔY RESERVED6 É #p JDR1 á # JDR2 á # JDR3 á # JDR4 á #¤Y RESERVED7 # AWD2CR á # AWD3CR á #¤ RESERVED8 Y #¨ RESERVED9 Y #¬ LTR2 á #° HTR2 á #´ LTR3 á #¸ HTR3 á #¼ DIFSEL á #À CALFACT á #Ä CALFACT2 á #È tY PADC_TypeDef n
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*¿ CSR á # RESERVED Y # CCR á # CDR á # CDR2 á # PADC_Common_TypeDef û ©*õ CSR á # CCR á # PVREFBUF_TypeDef Z ´*ü CREL á # ENDN á # RESERVED1 á # DBTP á # TEST á # RWD á # CCCR á # NBTP á # TSCC á # TSCV á #$ TOCC á #( TOCV á #,¯ á RESERVED2 � ECR á #@ PSR á #D TDCR á #H RESERVED3 á #L IR á #P IE á #T ILS á #X ILE á #\¦ á RESERVED4 #` GFC á # SIDFC á # XIDFC á # RESERVED5 á # XIDAM á # HPMS á # NDAT1 á # NDAT2 á # RXF0C á # RXF0S á #¤ RXF0A á #¨ RXBC á #¬ RXF1C á #° RXF1S á #´ RXF1A á #¸ RXESC á #¼ TXBC á #À TXFQS á #Ä TXESC á #È TXBRP á #Ì TXBAR á #Ð TXBCR á #Ô TXBTO á #Ø TXBCF á #Ü TXBTIE á #à TXBCIE á #ä á RESERVED6 $#è TXEFC á #ð TXEFS á #ô TXEFA á #ø RESERVED7 á #ü PFDCAN_GlobalTypeDef ò* # TTTMC á # TTRMC á # TTOCF á # TTMLM á # TURCF á # TTOCN á # TTGTP á # TTTMK á # TTIR á # TTIE á #$ TTILS á #( TTOST á #, TURNA á #0 TTLGT á #4 TTCTC á #8 TTCPT á #< TTCSM á #@#á n RESERVED1 x#D TTTS á # PTTCAN_TypeDef *ÿ# CREL á # CCFG á # CSTAT á # CWD á # IR á # IE á # PFDCAN_ClockCalibrationUnit_TypeDef ¶*ó$ CR á # CFGR á # TXDR á # RXDR á # ISR á # IER á # PCEC_TypeDef *ª*Õ% DR á # IDR á # CR á # RESERVED2 Y # INIT á # POL á # PCRC_TypeDef ¸*& CR á # CFGR á # ISR á # ICR á # PCRS_TypeDef éÄ*º(P CR á # SWTRIGR á # DHR12R1 á # DHR12L1 á # DHR8R1 á # DHR12R2 á # DHR12L2 á # DHR8R2 á # DHR12RD á # DHR12LD á #$ DHR8RD á #( DOR1 á #, DOR2 á #0 SR á #4 CCR á #8 MCR á #< SHSR1 á #@ SHSR2 á #D SHHR á #H SHRR á #L PDAC_TypeDef .á*¼*< FLTCR1 á # FLTCR2 á # FLTISR á # FLTICR á # FLTJCHGR á # FLTFCR á # FLTJDATAR á # FLTRDATAR á # FLTAWHTR á # FLTAWLTR á #$ FLTAWSR á #( FLTAWCFR á #, FLTEXMAX á #0 FLTEXMIN á #4 FLTCNVTIMR á #8 PDFSDM_Filter_TypeDef N÷*¬+ CHCFGR1 á # CHCFGR2 á # CHAWSCDR á # CHWDATAR á # CHDATINR á # PDFSDM_Channel_TypeDef Y*-X IDCODE á # CR á #ñ+Y
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RESERVED4 æ# APB3FZ1 á #4 RESERVED5 Y #8 APB1LFZ1 á #< RESERVED6 Y #@ APB1HFZ1 á #D RESERVED7 Y #H APB2FZ1 á #L RESERVED8 Y #P APB4FZ1 á #T PDBGMCU_TypeDef Ê*º., CR á # SR á # RISR á # IER á # MISR á # ICR á # ESCR á # ESUR á # CWSTRTR á # CWSIZER á #$ DR á #( PDCMI_TypeDef ³©*/ CR á # NDTR á # PAR á # M0AR á # M1AR á # FCR á # PDMA_Stream_TypeDef O·*ê/ LISR á # HISR á # LIFCR á # HIFCR á # PDMA_TypeDef ³¿*Á0 CCR á # CNDTR á # CPAR á # CM0AR á # CM1AR á # PBDMA_Channel_TypeDef þÈ*ú0 ISR á # IFCR á # PBDMA_TypeDef ^Î*1 CCR á # PDMAMUX_Channel_TypeDef Ó*Ù1 CSR á # CFR á # PDMAMUX_ChannelStatus_TypeDef ¾Ù*2 RGCR á # PDMAMUX_RequestGen_TypeDef þÞ*Ï2 RGSR á # RGCFR á # PDMAMUX_RequestGenStatus_TypeDef 1ä*3 GISR0 á # PMDMA_TypeDef wì*Õ48 CISR á # CIFCR á # CESR á # CCR á # CTCR á # CBNDTR á # CSAR á # CDAR á # CBRUR á # CLAR á #$ CTBR á #( RESERVED0 Y #, CMAR á #0 CMDR á #4 PMDMA_Channel_TypeDef þ*Ä7 CR á # ISR á # IFCR á # FGMAR á # FGOR á # BGMAR á # BGOR á # FGPFCCR á # FGCOLR á # BGPFCCR á #$ BGCOLR á #( FGCMAR á #, BGCMAR á #0 OPFCCR á #4 OCOLR á #8 OMAR á #< OOR á #@ NLR á #D LWR á #H AMTCR á #L7Y ë RESERVED u#P7á ÿ FGCLUT #´7á ÿ BGCLUT ª# PDMA2D_TypeDef r*ªQð" MACCR á # MACECR á # MACPFR á # MACWTR á # MACHT0R á # MACHT1R á #¿8Y RESERVED1 4 # MACVTR á #P RESERVED2 Y #T MACVHTR á #X RESERVED3 Y #\ MACVIR á #` MACIVIR á #d»9Y RESERVED4 ° #h MACTFCR á #pæ9Y RESERVED5 Û #t MACRFCR á #:Y RESERVED6 # MACISR á #° MACIER á #´ MACRXTXSR á #¸ RESERVED7 Y #¼ MACPCSR á #À MACRWKPFR á #Ä;Y RESERVED8 #È MACLCSR á #Ð MACLTCR á #Ô MACLETR á #Ø MAC1USTCR á #Üô;Y RESERVED9 é #à MACVR á # MACDR á # RESERVED10 Y # MACHWF0R á # MACHWF1R á # MACHWF2R á #¤õ<Y 5 RESERVED11 j #¨ MACMDIOAR á # MACMDIODR á #·=Y RESERVED12 ¬ # MACARPAR á #æ=Y : RESERVED13 Û # MACA0HR á # MACA0LR á # MACA1HR á # MACA1LR á # MACA2HR á # MACA2LR á # MACA3HR á # MACA3LR á #
?Y ÷ RESERVED14 y # MMCCR á # MMCRIR á # MMCTIR á # MMCRIMR á # MMCTIMR á #ï?Y RESERVED15 ä # MMCTSCGPR á #Ì MMCTMCGPR á #б@Y RESERVED16 & #Ô MMCTPCGR á #èà@Y RESERVED17 U #ì MMCRCRCEPR á # MMCRAEPR á #¢AY RESERVED18 # MMCRUPGR á #ÄÑAY RESERVED19 Æ #È MMCTLPIMSTR á #ì MMCTLPITCR á #ð MMCRLPIMSTR á #ô MMCRLPITCR á #ø½BY @ RESERVED20 2!#ü MACL3L4C0R á # MACL4A0R á #ÿBY RESERVED21 t!# MACL3A0R0R á # MACL3A1R0R á # MACL3A2R0R á # MACL3A3R0R á #éCY RESERVED22 Þ!# MACL3L4C1R á #° MACL4A1R á #´«DY RESERVED23 "#¸ MACL3A0R1R á #À MACL3A1R1R á #Ä MACL3A2R1R á #È MACL3A3R1R á #ÌEY k RESERVED24 "#Ð MACTSCR á # MACSSIR á # MACSTSR á # MACSTNR á # MACSTSUR á # MACSTNUR á # MACTSAR á # RESERVED25 Y # MACTSSR á # ÊFY RESERVED26 ?##¤ MACTTSSNR á #° MACTTSSSR á #´GY RESERVED27 ##¸ MACACR á #À RESERVED28 Y #Ä MACATSNR á #È MACATSSR á #Ì MACTSIACR á #Ð MACTSEACR á #Ô MACTSICNR á #Ø MACTSECNR á #ܸHY RESERVED29 -$#à MACPPSCR á #ðçHY RESERVED30 \$#ô MACPPSTTSR á # MACPPSTTNR á # MACPPSIR á # MACPPSWR á #ÍIY RESERVED31 Â$# MACPOCR á #À MACSPI0R á #Ä MACSPI1R á #È MACSPI2R á #Ì MACLMIR á #оJY
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RESERVED32 3%#Ô MTLOMR á #ëJY RESERVED33 `%# MTLISR á # KY 6 RESERVED34 %#¤ MTLTQOMR á # MTLTQUR á # MTLTQDR á #çKY RESERVED35 Ü%# MTLQICSR á #¬ MTLRQOMR á #° MTLRQMPOCR á #´ MTLRQDR á #¸ËLY ° RESERVED36 ?&#¼ DMAMR á # DMASBMR á # DMAISR á # DMADSR á # ¥MY ; RESERVED37 &# DMACCR á #" DMACTCR á #" DMACRCR á #"òMY RESERVED38 ç&#" DMACTDLAR á #" RESERVED39 Y #" DMACRDLAR á #" DMACTDTPR á # " RESERVED40 Y #¤" DMACRDTPR á #¨" DMACTDRLR á #¬" DMACRDRLR á #°" DMACIER á #´" DMACRIWTR á #¸" DMACSFCSR á #¼" RESERVED41 Y #À" DMACCATDR á #Ä" RESERVED42 Y #È" DMACCARDR á #Ì" RESERVED43 Y #Ð" DMACCATBR á #Ô" RESERVED44 Y #Ø" DMACCARBR á #Ü" DMACSR á #à"
QY RESERVED45 z(#ä" DMACMFCR á #ì" PETH_TypeDef ÚÌ*®U¬ RTSR1 á # FTSR1 á # SWIER1 á # D3PMR1 á # D3PCR1L á # D3PCR1H á #¢RY RESERVED1 )# RTSR2 á # FTSR2 á #$ SWIER2 á #( D3PMR2 á #, D3PCR2L á #0 D3PCR2H á #4SY RESERVED2 )#8 RTSR3 á #@ FTSR3 á #D SWIER3 á #H D3PMR3 á #L D3PCR3L á #P D3PCR3H á #TTY RESERVED3 ÷)#X IMR1 á # EMR1 á # PR1 á # RESERVED4 Y # IMR2 á # EMR2 á # PR2 á # RESERVED5 Y # IMR3 á # EMR3 á #¤ PR3 á #¨ PEXTI_TypeDef ¾(ó*×V, IMR1 á # EMR1 á # PR1 á # RESERVED1 Y # IMR2 á # EMR2 á # PR2 á # RESERVED2 Y # IMR3 á # EMR3 á #$ PR3 á #( PEXTI_Core_TypeDef Ã**Æ\ä ACR á # KEYR1 á # OPTKEYR á # CR1 á # SR1 á # CCR1 á # OPTCR á # OPTSR_CUR á # OPTSR_PRG á # OPTCCR á #$ PRAR_CUR1 á #( PRAR_PRG1 á #, SCAR_CUR1 á #0 SCAR_PRG1 á #4 WPSN_CUR1 á #8 WPSN_PRG1 á #< BOOT_CUR á #@ BOOT_PRG á #DYY RESERVED0 ,#H CRCCR1 á #P CRCSADD1 á #T CRCEADD1 á #X CRCDATA á #\ ECC_FA1 á #`õYY ' RESERVED1 ê,#d KEYR2 á # RESERVED2 Y # CR2 á # SR2 á # CCR2 á #ØZY RESERVED3 M-# PRAR_CUR2 á #¨ PRAR_PRG2 á #¬ SCAR_CUR2 á #° SCAR_PRG2 á #´ WPSN_CUR2 á #¸ WPSN_PRG2 á #¼á[Y RESERVED4 Ö-#À CRCCR2 á #Ð CRCSADD2 á #Ô CRCEADD2 á #Ø CRCDATA2 á #Ü ECC_FA2 á #à PFLASH_TypeDef q+¿*ö\ é\á BTCR `.# PFMC_Bank1_TypeDef \.È*ª] ]á BWTR .# PFMC_Bank1E_TypeDef .Ñ*^ PCR2 á # SR2 á # PMEM2 á # PATT2 á # RESERVED0 Y # ECCR2 á # PFMC_Bank2_TypeDef Å.ß*
_ PCR á # SR á # PMEM á # PATT á # RESERVED Y # ECCR á # PFMC_Bank3_TypeDef 5/í*ô_ ¬_á SDCR £/# Á_á SDTR ¸/# SDCMR á # SDRTR á # SDSR á # PFMC_Bank5_6_TypeDef /û*a( MODER á # OTYPER á # OSPEEDR á # PUPDR á # IDR á # ODR á # BSRR á # LCKR á # aá AFR y0# PGPIO_TypeDef 0*Ëa CSR á # OTR á # HSOTR á # POPAMP_TypeDef £0*eÈ RESERVED1 Y # PMCR á #bá EXTICR 1# CFGR á # RESERVED2 Y # CCCSR á # CCVR á #$ CCCR á #( PWRCR á #,øbY < RESERVED3 m1#0 PKGR á #¤¡cY u RESERVED4 1#¨ UR0 á # UR1 á # UR2 á # UR3 á # UR4 á # UR5 á # UR6 á # UR7 á # UR8 á # UR9 á #¤ UR10 á #¨ UR11 á #¬ UR12 á #° UR13 á #´ UR14 á #¸ UR15 á #¼ UR16 á #À UR17 á #Ä PSYSCFG_TypeDef á0¾*·f, CR1 á # CR2 á # OAR1 á # OAR2 á # TIMINGR á # TIMEOUTR á # ISR á # ICR á # PECR á # RXDR á #$ TXDR á #( PI2C_TypeDef «2Ñ*
g KR á # PR á # RLR á # SR á # WINR á # PIWDG_TypeDef K3Þ*Ýk CONFR0 á # CONFR1 á # CONFR2 á # CONFR3 á # CONFR4 á # CONFR5 á # CONFR6 á # CONFR7 á # hY Reserved20 4# CR á #0 SR á #4 CFR á #8 Reserved3c Y #< DIR á #@ DOR á #DiY Reserved48 u4#Hiá QMEM0 4#P±iá QMEM1 ¨4#Èiá QMEM2 ¿4#Ðßiá QMEM3 Ö4#öiá HUFFMIN í4#Ðjá HUFFBASE 5#©já S HUFFSYMB 5#Ãjá f DHTMEM :5#à Reserved4FC Y #ü ñjá W HUFFENC_AC0 h5#
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ká W HUFFENC_AC1
5#à «ká HUFFENC_DC0 ¢5#ÀÈká HUFFENC_DC1 ¿5#à PJPEG_TypeDef 3 *nLlY RESERVED0 ö5# SSCR á # BPCR á # AWCR á # TWCR á # GCR á #ØlY RESERVED1 M6# SRCR á #$mY RESERVED2 u6#( BCCR á #,¨mY RESERVED3 6#0 IER á #4 ISR á #8 ICR á #< LIPCR á #@ CPSR á #D CDSR á #H PLTDC_TypeDef ò5 *èoD CR á # WHPCR á # WVPCR á # CKCR á # PFCR á # CACR á # DCCR á # BFCR á # oY RESERVED0 y7# CFBAR á #( CFBLR á #, CFBLNR á #0ÈoY RESERVED1 ½7#4 CLUTWR á #@ PLTDC_Layer_TypeDef 7´ *q, CR1 á # CSR1 á # CR2 á # CR3 á # CPUCR á # RESERVED0 Y # D3CR á # RESERVED1 Y # WKUPCR á # WKUPFR á #$ WKUPEPR á #( PPWR_TypeDef 8Ç *íy° CR á # HSICFGR á # CRRCR á # CSICFGR á # CFGR á # RESERVED1 Y # D1CFGR á # D2CFGR á # D3CFGR á # RESERVED2 Y #$ PLLCKSELR á #( PLLCFGR á #, PLL1DIVR á #0 PLL1FRACR á #4 PLL2DIVR á #8 PLL2FRACR á #< PLL3DIVR á #@ PLL3FRACR á #D RESERVED3 Y #H D1CCIPR á #L D2CCIP1R á #P D2CCIP2R á #T D3CCIPR á #X RESERVED4 Y #\ CIER á #` CIFR á #d CICR á #h RESERVED5 Y #l BDCR á #p CSR á #t RESERVED6 Y #x AHB3RSTR á #| AHB1RSTR á # AHB2RSTR á # AHB4RSTR á # APB3RSTR á # APB1LRSTR á # APB1HRSTR á # APB2RSTR á # APB4RSTR á # GCR á # RESERVED8 Y #¤ D3AMR á #¨ävY RESERVED11 Y;#¬ RSR á #Ð AHB3ENR á #Ô AHB1ENR á #Ø AHB2ENR á #Ü AHB4ENR á #à APB3ENR á #ä APB1LENR á #è APB1HENR á #ì APB2ENR á #ð APB4ENR á #ô RESERVED12 Y #ø AHB3LPENR á #ü AHB1LPENR á # AHB2LPENR á # AHB4LPENR á # APB3LPENR á # APB1LLPENR á # APB1HLPENR á # APB2LPENR á # APB4LPENR á #ÙyY RESERVED13 Î<# PRCC_TypeDef ³8
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*ÍÐ TR á # DR á # CR á # ISR á # PRER á # WUTR á # RESERVED Y # ALRMAR á # ALRMBR á # WPR á #$ SSR á #( SHIFTR á #, TSTR á #0 TSDR á #4 TSSSR á #8 CALR á #< TAMPCR á #@ ALRMASSR á #D ALRMBSSR á #H OR á #L BKP0R á #P BKP1R á #T BKP2R á #X BKP3R á #\ BKP4R á #` BKP5R á #d BKP6R á #h BKP7R á #l BKP8R á #p BKP9R á #t BKP10R á #x BKP11R á #| BKP12R á # BKP13R á # BKP14R á # BKP15R á # BKP16R á # BKP17R á # BKP18R á # BKP19R á # BKP20R á # BKP21R á #¤ BKP22R á #¨ BKP23R á #¬ BKP24R á #° BKP25R á #´ BKP26R á #¸ BKP27R á #¼ BKP28R á #À BKP29R á #Ä BKP30R á #È BKP31R á #Ì PRTC_TypeDef =Í
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*©L GCR á # üY RESERVED0 ñ?# PDMCR á #D PDMDLY á #H PSAI_TypeDef á?Ù
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* CR1 á # CR2 á # FRCR á # SLOTR á # IMR á # SR á # CLRFR á # DR á # PSAI_Block_TypeDef =@å
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* CR á # IMR á # SR á # IFCR á # DR á # CSR á # DIR á # RESERVED2 Y # PSPDIFRX_TypeDef ¸@õ
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*Ê
POWER á # CLKCR á # ARG á # CMD á # RESPCMD ÐB# RESP1 ÐB# RESP2 ÐB# RESP3 ÐB# RESP4 ÐB# DTIMER á #$ DLEN á #( DCTRL á #, DCOUNT ÐB#0 STA ÐB#4 ICR á #8 MASK á #< ACKTIME á #@Y RESERVED0 B#D IDMACTRL á #P IDMABSIZE á #T IDMABASE0 á #X IDMABASE1 á #\ÿY RESERVED1 sB#` FIFO á #ª
Y Ý RESERVED2 B# IPVR á #ü Y tÊBPSDMMC_TypeDef 4A * CR á # CFGR á # PDLYB_TypeDef êB£ *¹È«á R !C# ¾á RLR 4C# C1IER á # C1ICR á # C1ISR á # C1MISR á #Y Reserved C# CR á #À KEYR á #Ä PHSEM_TypeDef Cµ * IER á # ICR á # ISR á # MISR á # PHSEM_Common_TypeDef ÎC½ *T CR1 á # CR2 á # CFG1 á # CFG2 á # IER á # SR á # IFCR á # RESERVED0 Y # TXDR á # Y RESERVED1 D#$ RXDR á #0ÅY RESERVED2 ¹D#4 CRCPOLY á #@ TXCRC á #D RXCRC á #H UDRDR á #L I2SCFGR á #P PSPI_TypeDef D× *Æ4 CR á # DCR á # SR á # FCR á # DLR á # CCR á # AR á # ABR á # DR á # PSMKR á #$ PSMAR á #( PIR á #, LPTR á #0 PQUADSPI_TypeDef 0Eë *§l CR1 á # CR2 á # SMCR á # DIER á # SR á # EGR á # CCMR1 á # CCMR2 á # CCER á # CNT á #$ PSC á #( ARR á #, RCR á #0 CCR1 á #4 CCR2 á #8 CCR3 á #< CCR4 á #@ BDTR á #D DCR á #H DMAR á #L RESERVED1 Y #P CCMR3 á #T CCR5 á #X CCR6 á #\ AF1 á #` AF2 á #d TISEL á #h PTIM_TypeDef ÞE *¹( ISR á # ICR á # IER á # CFGR á # CR á # CMP á # ARR á # CNT á # RESERVED1 Y # CFGR2 á #$ PLPTIM_TypeDef ;G *õ SR á # ICFR á # OR á # PCOMPOPT_TypeDef ÏG© * CFGR á # PCOMP_TypeDef H® *Æ CFGR á # PCOMP_Common_TypeDef 4H³ *ð0 CR1 á # CR2 á # CR3 á # BRR á # GTPR á # RTOR á # RQR á # ISR á # ICR á # RDR á #$ TDR á #( PRESC á #, PUSART_TypeDef bHÆ *( CR á # BRR á # RESERVED1 Y # ISR á # ICR á # IER á # RFL á # TDR á # RDR á # OR á #$ PSWPMI_TypeDef I× *» CR á # CFR á # SR á # PWWDG_TypeDef Iâ * CR á # SR á # FAR á # FDRL á # FDRH á # FECR á # PRAMECC_MonitorTypeDef ÐIð *È IER á # PRAMECC_TypeDef 7Jõ *£ MCR á # MISR á # MICR á # MDIER á # MCNTR á # MPER á # MREP á # MCMP1R á # RESERVED0 Y # MCMP2R á #$ MCMP3R á #( MCMP4R á #,Y RESERVED1 K#0 PHRTIM_Master_TypeDef _J *Ü TIMxCR á # TIMxISR á # TIMxICR á # TIMxDIER á # CNTxR á # PERxR á # REPxR á # CMP1xR á # CMP1CxR á # CMP2xR á #$ CMP3xR á #( CMP4xR á #, CPT1xR á #0 CPT2xR á #4 DTxR á #8 SETx1R á #< RSTx1R á #@ SETx2R á #D RSTx2R á #H EEFxR1 á #L EEFxR2 á #P RSTxR á #T CHPxR á #X CPT1xCR á #\ CPT2xCR á #` OUTxR á #d FLTxR á #hÊY RESERVED0 ¾L#l PHRTIM_Timerx_TypeDef @K° *t CR1 á # CR2 á # ISR á # ICR á # IER á # OENR á # ODISR á # ODSR á # BMCR á # BMTRGR á #$ BMCMPR á #( BMPER á #, EECR1 á #0 EECR2 á #4 EECR3 á #8 ADC1R á #< ADC2R á #@ ADC3R á #D ADC4R á #H RESERVED0 á #L FLTINR1 á #P FLTINR2 á #T BDMUPR á #X BDTAUPR á #\ BDTBUPR á #` BDTCUPR á #d BDTDUPR á #h BDTEUPR á #l BDMADR á #p PHRTIM_Common_TypeDef ùLÒ *ô sMasterRegs #K# ÁÜL sTimerxRegs ·N#áY RESERVED0 ÕN# sCommonRegs N# PHRTIM_TypeDef NÚ * CR á # SR á # DR á # PRNG_TypeDef Oä *§ CR á # WRFR á # CWRFR á # RDFR á # CRDFR á # SR á # CLRFR á #»Y 8 RESERVED ¯O# DINR0 á # DINR1 á # DINR2 á # DINR3 á # DINR4 á # DINR5 á # DINR6 á # DINR7 á # DINR8 á # DINR9 á #¤ DINR10 á #¨ DINR11 á #¬ DINR12 á #° DINR13 á #´ DINR14 á #¸ DINR15 á #¼ DINR16 á #À DINR17 á #Ä DINR18 á #È DINR19 á #Ì DINR20 á #Ð DINR21 á #Ô DINR22 á #Ø DINR23 á #Ü DINR24 á #à DINR25 á #ä DINR26 á #è DINR27 á #ì DINR28 á #ð DINR29 á #ô DINR30 á #ø DINR31 á #ü DOUTR0 á # DOUTR1 á # DOUTR2 á # DOUTR3 á # DOUTR4 á # DOUTR5 á # DOUTR6 á # DOUTR7 á # DOUTR8 á # DOUTR9 á #¤ DOUTR10 á #¨ DOUTR11 á #¬ DOUTR12 á #° DOUTR13 á #´ DOUTR14 á #¸ DOUTR15 á #¼ DOUTR16 á #À DOUTR17 á #Ä DOUTR18 á #È DOUTR19 á #Ì DOUTR20 á #Ð DOUTR21 á #Ô DOUTR22 á #Ø DOUTR23 á #Ü DOUTR24 á #à DOUTR25 á #ä DOUTR26 á #è DOUTR27 á #ì DOUTR28 á #ð DOUTR29 á #ô DOUTR30 á #ø DOUTR31 á #ü PMDIOS_TypeDef VO´*«À GOTGCTL á # GOTGINT á # GAHBCFG á # GUSBCFG á # GRSTCTL á # GINTSTS á # GINTMSK á # GRXSTSR á # GRXSTSP á # GRXFSIZ á #$ DIEPTXF0_HNPTXFSIZ á #( HNPTXSTS á #,©Y Reserved30 tT#0 GCCFG á #8 CID á #< GSNPSID á #@ GHWCFG1 á #D GHWCFG2 á #H GHWCFG3 á #L Reserved6 Y #P GLPMCFG á #T GPWRDN á #X GDFIFOCFG á #\ GADPCTL á #`ªY & Reserved43 6U#d HPTXFSIZ á #ïªá DIEPTXF eU# PUSB_OTG_GlobalTypeDef ®S×*ø DCFG á # DCTL á # DSTS á # Reserved0C Y # DIEPMSK á # DOEPMSK á # DAINT á # DAINTMSK á # Reserved20 Y # Reserved9 Y #$ DVBUSDIS á #( DVBUSPULSE á #, DTHRCTL á #0 DIEPEMPMSK á #4 DEACHINT á #8 DEACHMSK á #< Reserved40 Y #@ DINEP1MSK á #DÒY Reserved44 ÆV#H DOUTEP1MSK á # PUSB_OTG_DeviceTypeDef Uó*¤¯ DIEPCTL á # Reserved04 Y # DIEPINT á # Reserved0C Y # DIEPTSIZ á # DIEPDMA á # DTXFSTS á # Reserved18 Y # PUSB_OTG_INEndpointTypeDef W*Ï° DOEPCTL á # Reserved04 Y # DOEPINT á # Reserved0C Y # DOEPTSIZ á # DOEPDMA á #¼°Y Reserved18 0X# PUSB_OTG_OUTEndpointTypeDef ÆW*Þ± HCFG á # HFIR á # HFNUM á # Reserved40C Y # HPTXSTS á # HAINT á # HAINTMSK á # PUSB_OTG_HostTypeDef rX¡*ð² HCCHAR á # HCSPLT á # HCINT á # HCINTMSK á # HCTSIZ á # HCDMA á #ß²Y Reserved SY# PUSB_OTG_HostChannelTypeDef úX¯*×Ã⧳Y ó RESERVED0 Y# AXI_PERIPH_ID_4 á #Ð? AXI_PERIPH_ID_5 Y #Ô? AXI_PERIPH_ID_6 Y #Ø? AXI_PERIPH_ID_7 Y #Ü? AXI_PERIPH_ID_0 á #à? AXI_PERIPH_ID_1 á #ä? AXI_PERIPH_ID_2 á #è? AXI_PERIPH_ID_3 á #ì? AXI_COMP_ID_0 á #ð? AXI_COMP_ID_1 á #ô? AXI_COMP_ID_2 á #ø? AXI_COMP_ID_3 á #ü?âµY RESERVED1 ÖZ#@ AXI_TARG1_FN_MOD_ISS_BM á #@ ¶Y RESERVED2 [#@ AXI_TARG1_FN_MOD2 á #¤@ RESERVED3 Y #¨@ AXI_TARG1_FN_MOD_LB á #¬@·Y 5 RESERVED4 |[#°@ AXI_TARG1_FN_MOD á #BÀ·Y ¾ RESERVED5 ³[#B AXI_TARG2_FN_MOD_ISS_BM á #`þ·Y RESERVED6 ò[#` AXI_TARG2_FN_MOD2 á #¤` RESERVED7 Y #¨` AXI_TARG2_FN_MOD_LB á #¬`æ¸Y 5 RESERVED8 Z\#°` AXI_TARG2_FN_MOD á #b¹Y ¾ RESERVED9 \#b AXI_TARG3_FN_MOD_ISS_BM á #Þ¹Y þ RESERVED10 Ñ\# AXI_TARG4_FN_MOD_ISS_BM á # ºY þ RESERVED11 ]# AXI_TARG5_FN_MOD_ISS_BM á #ÀâºY þ RESERVED12 U]#À AXI_TARG6_FN_MOD_ISS_BM á #ऻY þ RESERVED13 ]#à AXI_TARG7_FN_MOD_ISS_BM á #å»Y RESERVED14 Ù]# AXI_TARG7_FN_MOD2 á #¤ RESERVED15 Y #¨ AXI_TARG7_FN_MOD_LB á #¬Ó¼Y 5 RESERVED16 G^#° AXI_TARG7_FN_MOD á #½Y ÅÏ RESERVED17 ^# AXI_INI1_FN_MOD2 á #¤À AXI_INI1_FN_MOD_AHB á #¨Àæ½Y 4 RESERVED18 Ú^#¬À AXI_INI1_READ_QOS á # AXI_INI1_WRITE_QOS á # AXI_INI1_FN_MOD á #Â×¾Y ü RESERVED19 J_# AXI_INI2_READ_QOS á #â AXI_INI2_WRITE_QOS á #â AXI_INI2_FN_MOD á #âÈ¿Y Å RESERVED20 »_#â AXI_INI3_FN_MOD2 á #¤ AXI_INI3_FN_MOD_AHB á #¨ÀY 4 RESERVED21 `#¬ AXI_INI3_READ_QOS á # AXI_INI3_WRITE_QOS á # AXI_INI3_FN_MOD á #ÁY ü RESERVED22 `# AXI_INI4_READ_QOS á #¢ AXI_INI4_WRITE_QOS á #¢ AXI_INI4_FN_MOD á #¢ÂY ü RESERVED23 ô`#¢ AXI_INI5_READ_QOS á # AXI_INI5_WRITE_QOS á # AXI_INI5_FN_MOD á #ÂòÂY ü RESERVED24 ea# AXI_INI6_READ_QOS á #â AXI_INI6_WRITE_QOS á #â AXI_INI6_FN_MOD á #â PGPV_TypeDef Y ± ² ³ ´ STM32H7xx_HAL_H =REV_ID_Y ((uint32_t)0x1003) >REV_ID_Z ((uint32_t)0x1001) ?REV_ID_A ((uint32_t)0x1000) @REV_ID_B ((uint32_t)0x2000) BREV_ID_X ((uint32_t)0x2001) FREV_ID_V ((uint32_t)0x2003) SSYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 TSYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 USYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 VSYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 YIS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) fSYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) gSYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ iIS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) lIS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) £SYSCFG_ETH_MII ((uint32_t)0x00000000) ¤SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 ¦IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || ((CONFIG) == SYSCFG_ETH_RMII)) ±SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO ²SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO ³SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO ´SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO ¹SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO ºSYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) »SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO ¼SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) ½SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO ¾SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) ¿SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO ÀSYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) ÆIS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3)) ÌIS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE)) ÙSYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) ÚSYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) ÜIS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| ((REGISTER) == SYSCFG_BOOT_ADDR1)) ßIS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE) éSYSCFG_CELL_CODE ((uint32_t)0x00000000) êSYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS ìIS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| ((SELECT) == SYSCFG_REGISTER_CODE)) ïIS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) þEXTI_MODE_IT ((uint32_t)0x00010000) ÿEXTI_MODE_EVT ((uint32_t)0x00020000) EXTI_RISING_EDGE ((uint32_t)0x00100000) EXTI_FALLING_EDGE ((uint32_t)0x00200000) IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE)) IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT)) EXTI_LINE0 ((uint32_t)0x00) EXTI_LINE1 ((uint32_t)0x01) EXTI_LINE2 ((uint32_t)0x02) EXTI_LINE3 ((uint32_t)0x03) EXTI_LINE4 ((uint32_t)0x04) EXTI_LINE5 ((uint32_t)0x05) EXTI_LINE6 ((uint32_t)0x06) EXTI_LINE7 ((uint32_t)0x07) EXTI_LINE8 ((uint32_t)0x08) EXTI_LINE9 ((uint32_t)0x09) EXTI_LINE10 ((uint32_t)0x0A) EXTI_LINE11 ((uint32_t)0x0B) EXTI_LINE12 ((uint32_t)0x0C) EXTI_LINE13 ((uint32_t)0x0D) EXTI_LINE14 ((uint32_t)0x0E) EXTI_LINE15 ((uint32_t)0x0F) EXTI_LINE16 ((uint32_t)0x10) EXTI_LINE17 ((uint32_t)0x11) EXTI_LINE18 ((uint32_t)0x12) EXTI_LINE19 ((uint32_t)0x13) EXTI_LINE20 ((uint32_t)0x14) EXTI_LINE21 ((uint32_t)0x15) EXTI_LINE22 ((uint32_t)0x16) EXTI_LINE23 ((uint32_t)0x17) EXTI_LINE24 ((uint32_t)0x18) EXTI_LINE25 ((uint32_t)0x19) EXTI_LINE26 ((uint32_t)0x1A) ¡EXTI_LINE27 ((uint32_t)0x1B) ¢EXTI_LINE28 ((uint32_t)0x1C) £EXTI_LINE29 ((uint32_t)0x1D) ¤EXTI_LINE30 ((uint32_t)0x1E) ¥EXTI_LINE31 ((uint32_t)0x1F) ¦EXTI_LINE32 ((uint32_t)0x20) §EXTI_LINE33 ((uint32_t)0x21) ¨EXTI_LINE34 ((uint32_t)0x22) ©EXTI_LINE35 ((uint32_t)0x23) ªEXTI_LINE36 ((uint32_t)0x24) «EXTI_LINE37 ((uint32_t)0x25) ¬EXTI_LINE38 ((uint32_t)0x26) EXTI_LINE39 ((uint32_t)0x27) ¯EXTI_LINE40 ((uint32_t)0x28) °EXTI_LINE41 ((uint32_t)0x29) ±EXTI_LINE42 ((uint32_t)0x2A) ²EXTI_LINE43 ((uint32_t)0x2B) ³EXTI_LINE44 ((uint32_t)0x2C) ºEXTI_LINE47 ((uint32_t)0x2F) »EXTI_LINE48 ((uint32_t)0x30) ¼EXTI_LINE49 ((uint32_t)0x31) ½EXTI_LINE50 ((uint32_t)0x32) ¾EXTI_LINE51 ((uint32_t)0x33) ¿EXTI_LINE52 ((uint32_t)0x34) ÀEXTI_LINE53 ((uint32_t)0x35) ÁEXTI_LINE54 ((uint32_t)0x36) ÂEXTI_LINE55 ((uint32_t)0x37) ÃEXTI_LINE56 ((uint32_t)0x38) ÄEXTI_LINE57 ((uint32_t)0x39) ÅEXTI_LINE58 ((uint32_t)0x3A) ÆEXTI_LINE59 ((uint32_t)0x3B) ÇEXTI_LINE60 ((uint32_t)0x3C) ÈEXTI_LINE61 ((uint32_t)0x3D) ÉEXTI_LINE62 ((uint32_t)0x3E) ÊEXTI_LINE63 ((uint32_t)0x3F) ËEXTI_LINE64 ((uint32_t)0x40) ÌEXTI_LINE65 ((uint32_t)0x41) ÍEXTI_LINE66 ((uint32_t)0x42) ÎEXTI_LINE67 ((uint32_t)0x43) ÏEXTI_LINE68 ((uint32_t)0x44) ÐEXTI_LINE69 ((uint32_t)0x45) ÑEXTI_LINE70 ((uint32_t)0x46) ÒEXTI_LINE71 ((uint32_t)0x47) ÓEXTI_LINE72 ((uint32_t)0x48) ÔEXTI_LINE73 ((uint32_t)0x49) ÕEXTI_LINE74 ((uint32_t)0x4A) ÖEXTI_LINE75 ((uint32_t)0x4B) ×EXTI_LINE76 ((uint32_t)0x4C) ïEXTI_LINE85 ((uint32_t)0x55) ðEXTI_LINE86 ((uint32_t)0x56) ñEXTI_LINE87 ((uint32_t)0x57) òEXTI_LINE88 ((uint32_t)0x58) óEXTI_LINE89 ((uint32_t)0x59) ôEXTI_LINE90 ((uint32_t)0x5A) õEXTI_LINE91 ((uint32_t)0x5B) IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) ÃIS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88)) ¤BDMA_CH6_CLEAR ((uint32_t)0x00000000) ¥BDMA_CH7_CLEAR ((uint32_t)0x00000001) §LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) ¬LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) ±IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR)) ¿FMC_SWAPBMAP_DISABLE (0x00000000U) ÀFMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0 ÁFMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1 ÃIS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || ((__MODE__) == FMC_SWAPBMAP_SDRAMB2)) ó__HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) ú__HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) ¤__HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) «__HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) ²__HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) ¹__HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) ß__HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1)) á__HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2)) â__HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3)) ã__HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4)) ä__HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5)) å__HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6)) æ__HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7)) ç__HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12)) è__HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13)) é__HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14)) ê__HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1)) ë__HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1)) ì__HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2)) í__HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3)) ò__HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN)) ü__HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1)) ý__HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8)) þ__HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15)) ÿ__HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16)) __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17)) __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM)) __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4)) __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
__HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3)) __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4)) __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5)) __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC)) __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1)) __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1)) __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2)) __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3)) __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4)) __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5)) __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6)) __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7)) __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12)) __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13)) __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14)) __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1)) __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1)) __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2)) __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3)) __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN)) ©__HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1)) ª__HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8)) «__HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15)) ¬__HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16)) __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17)) ®__HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM)) °__HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4)) ±__HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2)) ²__HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3)) ³__HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4)) ´__HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5)) µ__HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC)) ¶__HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1)) IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ)) | p ../Drivers/STM32H7xx_HAL_Driver/Inc/ ../Core/Inc/ stm32h7xx_hal.h stm32h7xx_hal_conf.h p
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM HAL_TICK_FREQ_10HZ dHAL_TICK_FREQ_100HZ
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HAL_TICK_FREQ_1KHZ HAL_TICK_FREQ_DEFAULT PHAL_TickFreqTypeDef ¿ 1tY quwTick ;quwTickPrio Y quwTickFreq 7 t A uwTick N uwTickPrio a uwTickFreq ¶ · ¸ &STM32H7xx_H 4STM32H7 l__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) m__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) n__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x06) o__STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) p__STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24) |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16) |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 ) |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC)) ~¿IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) ÏSET_BIT(REG,BIT) ((REG) |= (BIT)) ÑCLEAR_BIT(REG,BIT) ((REG) &= ~(BIT)) ÓREAD_BIT(REG,BIT) ((REG) & (BIT)) ÕCLEAR_REG(REG) ((REG) = (0x0)) ×WRITE_REG(REG,VAL) ((REG) = (VAL)) ÙREAD_REG(REG) ((REG)) ÛMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) ÝPOSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) áATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0) êATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0) óATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0) üATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0) ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0) ¤ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/ ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx.h stm32h743xx.h stm32h7xx_hal.h \
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../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ÙRESET SET PFlagStatus Ä ¸PITStatus Ä ¸DISABLE ENABLE PFunctionalState ý ¾ÈSUCCESS ERROR PErrorStatus /Å º » ¼ STM32_HAL_LEGACY #AES_FLAG_RDERR CRYP_FLAG_RDERR $AES_FLAG_WRERR CRYP_FLAG_WRERR %AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF &AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 'AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR )CRYP_DATATYPE_32B CRYP_NO_SWAP *CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +CRYP_DATATYPE_8B CRYP_BYTE_SWAP ,CRYP_DATATYPE_1B CRYP_BIT_SWAP 5ADC_RESOLUTION12b ADC_RESOLUTION_12B 6ADC_RESOLUTION10b ADC_RESOLUTION_10B 7ADC_RESOLUTION8b ADC_RESOLUTION_8B 8ADC_RESOLUTION6b ADC_RESOLUTION_6B 9OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN :OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED ;EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV <EOC_SEQ_CONV ADC_EOC_SEQ_CONV =EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV >REGULAR_GROUP ADC_REGULAR_GROUP ?INJECTED_GROUP ADC_INJECTED_GROUP @REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP AAWD_EVENT ADC_AWD_EVENT BAWD1_EVENT ADC_AWD1_EVENT CAWD2_EVENT ADC_AWD2_EVENT DAWD3_EVENT ADC_AWD3_EVENT EOVR_EVENT ADC_OVR_EVENT FJQOVF_EVENT ADC_JQOVF_EVENT GALL_CHANNELS ADC_ALL_CHANNELS HREGULAR_CHANNELS ADC_REGULAR_CHANNELS IINJECTED_CHANNELS ADC_INJECTED_CHANNELS JSYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR KSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT LADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 MADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 NADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 OADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 PADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 QADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO RADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 SADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO TADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 UADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO VADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 WADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 XADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE YADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING ZADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING [ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING \ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 ^HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY _HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY `HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC aHAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC bHAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL cHAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL dHAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 gADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT {__HAL_CEC_GET_IT __HAL_CEC_GET_FLAG COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR å__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig ôHAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse öHAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE DAC1_CHANNEL_1 DAC_CHANNEL_1 DAC1_CHANNEL_2 DAC_CHANNEL_2 DAC2_CHANNEL_1 DAC_CHANNEL_1 DAC_WAVE_NONE 0x00000000U DAC_WAVE_NOISE DAC_CR_WAVE1_0 DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 DAC_WAVEGENERATION_NONE DAC_WAVE_NONE DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL ©HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID ªHAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID ´HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 µHAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 ¶HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 ·HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 ¸HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 ¹HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 ºHAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 »HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 ¼HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 ½HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 ¾HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 ¿HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 ÀHAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 ÁHAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 ÃIS_HAL_REMAPDMA IS_DMA_REMAP Ä__HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE Å__HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE üDMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 ýDMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 ÿBDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 ¡HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT ¢HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT £HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT ¤HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT ¥HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT ¦HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT §HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT ¨HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT ªHAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT «HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING ¬HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING ¯DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT °DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT ±DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT ³DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT ´DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT ÃTYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE ÄTYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD ÅTYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD ÆTYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD ÇTYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS ÈTYPEERASE_PAGES FLASH_TYPEERASE_PAGES ÉTYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES ÊTYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE ËWRPSTATE_DISABLE OB_WRPSTATE_DISABLE ÌWRPSTATE_ENABLE OB_WRPSTATE_ENABLE ÍHAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE ÎOBEX_PCROP OPTIONBYTE_PCROP ÏOBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG ÐPCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE ÑPCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE ÒTYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE ÓTYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD ÔTYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD ÕTYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE ÖTYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD ×TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD ØTYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE ÙTYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD ÚTYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD ÞTYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE ßTYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD àTYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD áVOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 âVOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 ãVOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 äVOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 åTYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST æTYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST çWRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA èWRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB éWRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA êWRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB ëIWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE ìIWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN íIWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE îIWDG_STOP_ACTIVE OB_IWDG_STOP_RUN ïFLASH_ERROR_NONE HAL_FLASH_ERROR_NONE ðFLASH_ERROR_RD HAL_FLASH_ERROR_RD ñFLASH_ERROR_PG HAL_FLASH_ERROR_PROG òFLASH_ERROR_PGP HAL_FLASH_ERROR_PGS óFLASH_ERROR_WRP HAL_FLASH_ERROR_WRP ôFLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV õFLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR öFLASH_ERROR_PROG HAL_FLASH_ERROR_PROG ÷FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION øFLASH_ERROR_PGA HAL_FLASH_ERROR_PGA ùFLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE úFLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE ûFLASH_ERROR_PGS HAL_FLASH_ERROR_PGS üFLASH_ERROR_MIS HAL_FLASH_ERROR_MIS ýFLASH_ERROR_FAST HAL_FLASH_ERROR_FAST þFLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR ÿFLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS OB_WDG_SW OB_IWDG_SW OB_WDG_HW OB_IWDG_HW OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR OB_RDP_LEVEL0 OB_RDP_LEVEL_0 OB_RDP_LEVEL1 OB_RDP_LEVEL_1 OB_RDP_LEVEL2 OB_RDP_LEVEL_2 OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 FLASH_FLAG_WDW FLASH_FLAG_WBNE OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL ½__HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE ¾__HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE ¿__HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET À__HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET Á__HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE Â__HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE ÍHAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 ÎHAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 ÏHAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 ÐHAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 ÑHAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 ÒHAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 ÓHAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 ÔHAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 ÕHAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 ÔFMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE ÕFMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE ÖFMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 ×FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 æFSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef çFSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef ïGET_GPIO_SOURCE GPIO_GET_INDEX ðGET_GPIO_INDEX GPIO_GET_INDEX GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH «GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 æHRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED çHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 èHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 éHRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 êHRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 ëHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 ìHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 íHRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 îHRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 ð__HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER ñ__HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER ò__HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD ó__HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD ô__HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER õ__HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER ö__HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE ÷__HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE úHRTIMInterruptResquests HRTIMInterruptRequests HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 ¡HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 ¢HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 £HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 ¤HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 ¥HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 ¦HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 §HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 ¨HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 ©HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 ªHRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 «HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 ¬HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 ®HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 ¯HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 °HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 ±HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 ²HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 ³HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 ´HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 µHRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 ¶HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 ·HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 ¸HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 ¹HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 ºHRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 »HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 ¼HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 ½HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 ¾HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 ÀHRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 ÁHRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 ÂHRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 ÃHRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 ÄHRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 ÅHRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 ÆHRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 ÇHRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 ÈHRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 ÉHRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 ÊHRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 ËHRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 ÌHRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 ÍHRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 ÎHRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 ÏHRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 ÐHRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 ÑHRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 ÒHRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 ÓHRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 ÔHRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 ÕHRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 ÖHRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 ×HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 ØHRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 ÙHRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 ÚHRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 ÛHRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 ÜHRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 ÝHRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 ÞHRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 ßHRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 àHRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 áHRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 âHRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 ãHRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 äHRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 åHRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 æHRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 çHRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 èHRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 éHRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 êHRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 ëHRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 ìHRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 íHRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 îHRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 ïHRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 ðHRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 ñHRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 òHRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 óHRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 ôHRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 õHRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE §IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE ¨IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE ±KR_KEY_RELOAD IWDG_KEY_RELOAD ²KR_KEY_ENABLE IWDG_KEY_ENABLE ³KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE ´KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE ½LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ¾LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS ¿LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS ÀLPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS ÂLPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING ÃLPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING ÄLPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING ÆLPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ÇLPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS ÈLPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS ÉLPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS ÍLPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS ÎLPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS ÏLPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS ÕHAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue æHAL_NAND_Read_Page HAL_NAND_Read_Page_8b çHAL_NAND_Write_Page HAL_NAND_Write_Page_8b èHAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b éHAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b ëNAND_AddressTypedef NAND_AddressTypeDef í__ARRAY_ADDRESS ARRAY_ADDRESS î__ADDR_1st_CYCLE ADDR_1ST_CYCLE ï__ADDR_2nd_CYCLE ADDR_2ND_CYCLE ð__ADDR_3rd_CYCLE ADDR_3RD_CYCLE ñ__ADDR_4th_CYCLE ADDR_4TH_CYCLE ùNOR_StatusTypedef HAL_NOR_StatusTypeDef úNOR_SUCCESS HAL_NOR_STATUS_SUCCESS ûNOR_ONGOING HAL_NOR_STATUS_ONGOING üNOR_ERROR HAL_NOR_STATUS_ERROR ýNOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT ÿ__NOR_WRITE NOR_WRITE __NOR_ADDR_SHIFT NOR_ADDR_SHIFT OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 £ HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID ¤ HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID ´ I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS · I2S_IT_TXE I2S_IT_TXP ¸ I2S_IT_RXNE I2S_IT_RXP º I2S_FLAG_TXE I2S_FLAG_TXP » I2S_FLAG_RXNE I2S_FLAG_RXP Ê CF_DATA ATA_DATA Ë CF_SECTOR_COUNT ATA_SECTOR_COUNT Ì CF_SECTOR_NUMBER ATA_SECTOR_NUMBER Í CF_CYLINDER_LOW ATA_CYLINDER_LOW Î CF_CYLINDER_HIGH ATA_CYLINDER_HIGH Ï CF_CARD_HEAD ATA_CARD_HEAD Ð CF_STATUS_CMD ATA_STATUS_CMD Ñ CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE Ò CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA Õ CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD Ö CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD × CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD Ø CF_IDENTIFY_CMD ATA_IDENTIFY_CMD Ú PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef Û PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS Ü PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING Ý PCCARD_ERROR HAL_PCCARD_STATUS_ERROR Þ PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT ç FORMAT_BIN RTC_FORMAT_BIN è FORMAT_BCD RTC_FORMAT_BCD ê RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE ë RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE ì RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE í RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE ï RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE ð RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE ñ RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE ò RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT ó RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT õ RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT ö RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 ÷ RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 ø RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 ú RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE û RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 ü RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 þ RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT ÿ RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
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RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
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RTC_TAMPCR_TAMPXE RTC_TAMPER_X
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RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT ¡
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RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 ¢
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RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 £
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RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 ¤
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RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP ¯
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SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE °
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SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE ²
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SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE ³
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SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE ´
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SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE µ
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SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE ·
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SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE ¸
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SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE º
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SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE »
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SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE Ä
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SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE Å
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SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE Æ
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SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE Ç
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SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE È
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SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE É
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SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE Ê
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SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE Ë
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SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE Ì
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SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE Í
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SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE Î
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HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN Ö
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SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE ×
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SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE Ù
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SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE Ú
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SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE Ü
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SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE Ý
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SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE á
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SPI_FLAG_TXE SPI_FLAG_TXP â
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SPI_FLAG_RXNE SPI_FLAG_RXP ä
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SPI_IT_TXE SPI_IT_TXP å
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SPI_IT_RXNE SPI_IT_RXP ç
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SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET è
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SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET é
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SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET ê
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SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET õ
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CCER_CCxE_MASK TIM_CCER_CCxE_MASK ö
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CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK ø
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TIM_DMABase_CR1 TIM_DMABASE_CR1 ù
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TIM_DMABase_CR2 TIM_DMABASE_CR2 ú
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TIM_DMABase_SMCR TIM_DMABASE_SMCR û
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TIM_DMABase_DIER TIM_DMABASE_DIER ü
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TIM_DMABase_SR TIM_DMABASE_SR ý
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TIM_DMABase_EGR TIM_DMABASE_EGR þ
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TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 ÿ
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TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 TIM_DMABase_CCER TIM_DMABASE_CCER TIM_DMABase_CNT TIM_DMABASE_CNT TIM_DMABase_PSC TIM_DMABASE_PSC TIM_DMABase_ARR TIM_DMABASE_ARR TIM_DMABase_RCR TIM_DMABASE_RCR
TIM_DMABase_CCR1 TIM_DMABASE_CCR1 TIM_DMABase_CCR2 TIM_DMABASE_CCR2 TIM_DMABase_CCR3 TIM_DMABASE_CCR3 TIM_DMABase_CCR4 TIM_DMABASE_CCR4 TIM_DMABase_BDTR TIM_DMABASE_BDTR TIM_DMABase_DCR TIM_DMABASE_DCR TIM_DMABase_DMAR TIM_DMABASE_DMAR TIM_DMABase_OR1 TIM_DMABASE_OR1 TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 TIM_DMABase_CCR5 TIM_DMABASE_CCR5 TIM_DMABase_CCR6 TIM_DMABASE_CCR6 TIM_DMABase_OR2 TIM_DMABASE_OR2 TIM_DMABase_OR3 TIM_DMABASE_OR3 TIM_DMABase_OR TIM_DMABASE_OR TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 TIM_EventSource_COM TIM_EVENTSOURCE_COM TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER TIM_EventSource_Break TIM_EVENTSOURCE_BREAK TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS ¡ TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS ¢ TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS £ TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS ¤ TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS ¥ TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS ¦ TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS § TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS ¨ TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS © TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS ª TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS « TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS ¬ TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS ® TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS ¯ TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS » TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 ¼ TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 ½ TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 ¾ TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 ¿ TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 À TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 Á TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 Â TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 Ã TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 Ä TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 Å TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 Æ TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 Ç TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 È TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 É TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 × TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING Ø TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING à UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE á UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE â UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE ã UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE å __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE æ __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE è __DIV_SAMPLING16 UART_DIV_SAMPLING16 é __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 ê __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 ë __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 í __DIV_SAMPLING8 UART_DIV_SAMPLING8 î __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 ï __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 ð __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 ò __DIV_LPUART UART_DIV_LPUART ô UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE õ UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK USART_CLOCK_DISABLED USART_CLOCK_DISABLE USART_CLOCK_ENABLED USART_CLOCK_ENABLE USARTNACK_ENABLED USART_NACK_ENABLE USARTNACK_DISABLED USART_NACK_DISABLE CFR_BASE WWDG_CFR_BASE CAN_FilterFIFO0 CAN_FILTER_FIFO0 CAN_FilterFIFO1 CAN_FILTER_FIFO1 CAN_IT_RQCP0 CAN_IT_TME CAN_IT_RQCP1 CAN_IT_TME CAN_IT_RQCP2 CAN_IT_TME INAK_TIMEOUT CAN_TIMEOUT_VALUE SLAK_TIMEOUT CAN_TIMEOUT_VALUE CAN_TXSTATUS_FAILED ((uint8_t)0x00U) CAN_TXSTATUS_OK ((uint8_t)0x01U) CAN_TXSTATUS_PENDING ((uint8_t)0x02U) ¨ VLAN_TAG ETH_VLAN_TAG © MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD ª MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD « JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD ¬ MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK ® MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK ¯ DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK ± ETH_MMCCR 0x00000100U ² ETH_MMCRIR 0x00000104U ³ ETH_MMCTIR 0x00000108U ´ ETH_MMCRIMR 0x0000010CU µ ETH_MMCTIMR 0x00000110U ¶ ETH_MMCTGFSCCR 0x0000014CU · ETH_MMCTGFMSCCR 0x00000150U ¸ ETH_MMCTGFCR 0x00000168U ¹ ETH_MMCRFCECR 0x00000194U º ETH_MMCRFAECR 0x00000198U » ETH_MMCRGUFCR 0x000001C4U ½ ETH_MAC_TXFIFO_FULL 0x02000000U ¾ ETH_MAC_TXFIFONOT_EMPTY 0x01000000U ¿ ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U À ETH_MAC_TXFIFO_IDLE 0x00000000U Á ETH_MAC_TXFIFO_READ 0x00100000U Ã ETH_MAC_TXFIFO_WAITING 0x00200000U Å ETH_MAC_TXFIFO_WRITING 0x00300000U Ç ETH_MAC_TRANSMISSION_PAUSE 0x00080000U È ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U É ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U Ë ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U Í ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U Ï ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U Ð ETH_MAC_RXFIFO_EMPTY 0x00000000U Ñ ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U Ó ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U Õ ETH_MAC_RXFIFO_FULL 0x00000300U Ø ETH_MAC_READCONTROLLER_IDLE 0x00000000U Ù ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U Ú ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U Ý ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U ß ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U à ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U á ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U â ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U ã ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U ä ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U æ ETH_TxPacketConfig ETH_TxPacketConfigTypeDef ï HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR ð DCMI_IT_OVF DCMI_IT_OVR ñ DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI ò DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI ô HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop õ HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop ö HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 DMA2D_RGB888 DMA2D_OUTPUT_RGB888 DMA2D_RGB565 DMA2D_OUTPUT_RGB565
DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 CM_ARGB8888 DMA2D_INPUT_ARGB8888 CM_RGB888 DMA2D_INPUT_RGB888 CM_RGB565 DMA2D_INPUT_RGB565 CM_ARGB1555 DMA2D_INPUT_ARGB1555 CM_ARGB4444 DMA2D_INPUT_ARGB4444 CM_L8 DMA2D_INPUT_L8 CM_AL44 DMA2D_INPUT_AL44 CM_AL88 DMA2D_INPUT_AL88 CM_L4 DMA2D_INPUT_L4 CM_A8 DMA2D_INPUT_A8 CM_A4 DMA2D_INPUT_A4 HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort ³ HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback É HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler Ò HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef Ó HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef Ô HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish Õ HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish Ö HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish × HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish Û HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 Ü HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 Ý HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 Þ HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 à HASH_AlgoMode_HASH HASH_ALGOMODE_HASH á HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC ã HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY ä HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY è HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt é HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End ê HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT ë HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT í HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt î HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End ï HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT ð HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT ò HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt ó HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End ô HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT õ HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT ÷ HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt ø HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End ù HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT ú HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) ¦FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram §FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown ¨FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown ©HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock ªHAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock «HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase ¬HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program µHAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter ¶HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter ·HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter ¸HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter ºHAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd) == ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) ÁHAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT ÂHAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT ÃHAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT ÄHAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT ÉHAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA ÊHAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA ËHAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA ÌHAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA çHAL_PWR_PVDConfig HAL_PWR_ConfigPVD èHAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg éHAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown êHAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor ëHAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg ìHAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown íHAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor îHAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler ïHAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD ðHAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler ñHAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback òHAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive óHAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive ôHAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC õHAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC öHAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM øPWR_MODE_NORMAL PWR_PVD_MODE_NORMAL ùPWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING úPWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING ûPWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING üPWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING ýPWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING þPWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING CR_OFFSET_BB PWR_CR_OFFSET_BB CSR_OFFSET_BB PWR_CSR_OFFSET_BB PMODE_BIT_NUMBER VOS_BIT_NUMBER CR_PMODE_BB CR_VOS_BB
DBP_BitNumber DBP_BIT_NUMBER PVDE_BitNumber PVDE_BIT_NUMBER PMODE_BitNumber PMODE_BIT_NUMBER EWUP_BitNumber EWUP_BIT_NUMBER FPDS_BitNumber FPDS_BIT_NUMBER ODEN_BitNumber ODEN_BIT_NUMBER ODSWEN_BitNumber ODSWEN_BIT_NUMBER MRLVDS_BitNumber MRLVDS_BIT_NUMBER LPLVDS_BitNumber LPLVDS_BIT_NUMBER BRE_BitNumber BRE_BIT_NUMBER PWR_MODE_EVT PWR_PVD_MODE_NORMAL þHAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT ÿHAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt HAL_TIM_DMAError TIM_DMAError HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA ¤HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback ¬HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback HAL_LTDC_Relaod HAL_LTDC_Reload ®HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig ¯HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig ÂAES_IT_CC CRYP_IT_CC ÃAES_IT_ERR CRYP_IT_ERR ÄAES_FLAG_CCF CRYP_FLAG_CCF Ì__HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE Í__HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH Î__HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH Ï__HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM Ð__HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC Ñ__HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM Ò__HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC Ó__HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI Ô__HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK Õ__HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG Ö__HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG ×__HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE Ø__HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE Ù__HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE ÛSYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY ÜSYSCFG_FLAG_RC48 RCC_FLAG_HSI48 ÝIS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS ÞUFB_MODE_BitNumber UFB_MODE_BIT_NUMBER ßCMP_PD_BitNumber CMP_PD_BIT_NUMBER é__ADC_ENABLE __HAL_ADC_ENABLE ê__ADC_DISABLE __HAL_ADC_DISABLE ë__HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS ì__HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS í__HAL_ADC_IS_ENABLED ADC_IS_ENABLE î__ADC_IS_ENABLED ADC_IS_ENABLE ï__HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR ð__HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED ñ__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ò__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR ó__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED ô__HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING õ__HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE ÷__HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION ø__HAL_ADC_JSQR_RK ADC_JSQR_RK ù__HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT ú__HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR û__HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION ü__HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE ý__HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS þ__HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS ÿ__HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
__HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER __HAL_ADC_SQR1 ADC_SQR1 ¡__HAL_ADC_SMPR1 ADC_SMPR1 ¢__HAL_ADC_SMPR2 ADC_SMPR2 £__HAL_ADC_SQR3_RK ADC_SQR3_RK ¤__HAL_ADC_SQR2_RK ADC_SQR2_RK ¥__HAL_ADC_SQR1_RK ADC_SQR1_RK ¦__HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS §__HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS ¨__HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV ©__HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection ª__HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq «__HAL_ADC_JSQR ADC_JSQR __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL ®__HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS ¯__HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF °__HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT ±__HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS ²__HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN ³__HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR ´__HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ ½__HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT ¾__HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT ¿__HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT ÀIS_DAC_GENERATE_WAVE IS_DAC_WAVE É__HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 Ê__HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 Ë__HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 Ì__HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 Í__HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 Î__HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 Ï__HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 Ð__HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 Ñ__HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 Ò__HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 Ó__HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 Ô__HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 Õ__HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 Ö__HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 ×__HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 Ø__HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 Ú__HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 Û__HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 Ü__HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 Ý__HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 Þ__HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 ß__HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 à__HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 á__HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 â__HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 ã__HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 ä__HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 å__HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 æ__HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 ç__HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 ê__HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 ë__HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 ì__HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 í__HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 î__HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 ï__HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 ð__HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC ñ__HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC ó__HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 ô__HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 õ__HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 ö__HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 ý__HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT þ__HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ÿ__HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
__HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) ¢__HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) ¤__HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) ¦__HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) ¨__HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT()) ª__HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT()) ¬__HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG()) ®__HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) ²__HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE ÐIS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE)|| ((WAVE) == DAC_WAVE_TRIANGLE)) ÜIS_WRPAREA IS_OB_WRPAREA ÝIS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM ÞIS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM ßIS_TYPEERASE IS_FLASH_TYPEERASE àIS_NBSECTORS IS_FLASH_NBSECTORS áIS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE ë__HAL_I2C_RESET_CR2 I2C_RESET_CR2 ì__HAL_I2C_GENERATE_START I2C_GENERATE_START ð__HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE ò__HAL_I2C_RISE_TIME I2C_RISE_TIME ó__HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD ô__HAL_I2C_SPEED_FAST I2C_SPEED_FAST õ__HAL_I2C_SPEED I2C_SPEED ö__HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE ÷__HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ ø__HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS ù__HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE ú__HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ û__HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB ü__HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB ý__HAL_I2C_FREQRANGE I2C_FREQRANGE IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG __IRDA_DISABLE __HAL_IRDA_DISABLE __IRDA_ENABLE __HAL_IRDA_ENABLE __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE ¨__HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS ©__HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS ³__HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT ´__HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT µ__HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE ¿__OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD À__OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX Á__OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX Â__OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX Ã__OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX Ä__OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L Å__OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H Æ__OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM Ç__OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES È__OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX É__OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT Ê__OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION Ë__OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET Õ__HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT Ö__HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT ×__HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE Ø__HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE Ù__HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE Ú__HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE Û__HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE Ü__HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE Ý__HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE Þ__HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE ß__HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE à__HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE á__HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine â__HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine ã__HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig ä__HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig å__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) è__HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT é__HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT ê__HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ë__HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ì__HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE í__HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE î__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ï__HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ð__HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) ó__HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) ö__HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention ÷__HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention ø__HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 ù__HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 ú__HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE û__HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE ü__HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB ý__HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI HAL_RCC_CCSCallback HAL_RCC_CSSCallback HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET ¡__ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET ¢__ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE £__ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE ¤__ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET ¥__ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET ¦__ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE §__ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE ¨__ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE ©__ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE ª__ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET «__ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET ¬__ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE ®__ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET ¯__ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET °__AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE ±__AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE ²__AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE ³__AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE ´__AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET µ__AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET ¶__CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE ·__CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE ¸__CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE ¹__CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE º__CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET »__CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET ¼__AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE ½__AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE ¾__AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET ¿__AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET À__AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET Á__AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET Â__AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET Ã__AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET Ä__AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET Å__AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET Æ__AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET Ç__AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET È__APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET É__APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET Ê__APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET Ë__APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET Ò__BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE Ó__BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE Ô__BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET Õ__BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET Ö__CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE ×__CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE Ø__CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE Ù__CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE Ú__CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET Û__CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET Ü__CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE Ý__CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE Þ__CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET ß__CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET à__CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE á__CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE â__CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET ã__CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET ä__CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE å__CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE æ__COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE ç__COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE è__COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET é__COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET ê__COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE ë__COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE ì__CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET í__CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET î__CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE ï__CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE ð__CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE ñ__CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE ò__CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET ó__CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET ô__DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE õ__DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE ö__DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET ÷__DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET ø__DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE ù__DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE ú__DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE û__DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE ü__DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET ý__DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET þ__DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE ÿ__DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
__DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ¡__FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ¢__FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET £__FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET ¤__FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE ¥__FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE ¦__FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET §__FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET ¨__FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE ©__FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE ª__FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE «__FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE ¬__FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE ®__FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET ¯__FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET °__FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE ±__FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE ²__GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE ³__GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE ´__GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE µ__GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ¶__GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET ·__GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET ¸__GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE ¹__GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE º__GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE »__GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ¼__GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET ½__GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET ¾__GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE ¿__GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE À__GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE Á__GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE Â__GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET Ã__GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET Ä__GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE Å__GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE Æ__GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE Ç__GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE È__GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET É__GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET Ê__GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE Ë__GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE Ì__GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE Í__GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE Î__GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET Ï__GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET Ð__GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE Ñ__GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE Ò__GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE Ó__GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE Ô__GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET Õ__GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET Ö__GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE ×__GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE Ø__GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE Ù__GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE Ú__GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET Û__GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET Ü__GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE Ý__GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE Þ__GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ß__GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE à__GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET á__GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET â__I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE ã__I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE ä__I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE å__I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE æ__I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET ç__I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET è__I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE é__I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE ê__I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ë__I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ì__I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET í__I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET î__I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE ï__I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE ð__I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ñ__I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ò__I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET ó__I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET ô__LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE õ__LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE ö__LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE ÷__LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE ø__LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET ù__LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET ú__LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE û__LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE ü__LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ý__LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE þ__LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET ÿ__LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
__LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE ¡__QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE ¢__QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET £__QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET ³__RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE ´__RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE µ__RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE ¶__RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE ·__RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET ¸__RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET ¹__SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE º__SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE »__SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ¼__SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ½__SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET ¾__SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET ¿__SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE À__SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE Á__SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE Â__SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE Ã__SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET Ä__SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET Å__SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE Æ__SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE Ç__SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE È__SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE É__SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE Ê__SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE Ë__SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET Ì__SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET Í__SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE Î__SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE Ï__SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE Ð__SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE Ñ__SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET Ò__SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET Ó__SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE Ô__SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE Õ__SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE Ö__SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ×__SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET Ø__SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET Ù__SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE Ú__SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE Û__SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE Ü__SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE Ý__SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET Þ__SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET ß__SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE à__SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE á__SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE â__SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE ã__SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE ä__SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE å__SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE æ__SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE ç__SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE è__SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE é__SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET ê__SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET ë__SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE ì__SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE í__SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE î__SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ï__SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET ð__SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET ñ__TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE ò__TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE ó__TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ô__TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE õ__TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET ö__TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET ÷__TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE ø__TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE ù__TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET ú__TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET û__TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE ü__TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE ý__TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET þ__TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET ÿ__TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
__TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ¡__TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET ¢__TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET £__TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE ¤__TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE ¥__TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ¦__TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE §__TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET ¨__TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET ©__TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE ª__TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE «__TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ¬__TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET ®__TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET ¯__TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE °__TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE ±__TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE ²__TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE ³__TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET ´__TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET µ__TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE ¶__TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE ·__TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ¸__TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ¹__TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET º__TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET »__TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE ¼__TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE ½__TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ¾__TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ¿__TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET À__TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET Á__TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE Â__TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE Ã__TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE Ä__TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE Å__TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET Æ__TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET Ç__TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE È__TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE É__TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET Ê__TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET Ë__TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE Ì__TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE Í__TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE Î__TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE Ï__TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET Ð__TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET Ñ__UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE Ò__UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE Ó__UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE Ô__UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE Õ__UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET Ö__UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET ×__UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE Ø__UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE Ù__UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE Ú__UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE Û__UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET Ü__UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET Ý__USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE Þ__USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE ß__USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE à__USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE á__USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET â__USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET ã__USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE ä__USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE å__USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE æ__USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE ç__USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET è__USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET é__USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE ê__USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE ë__USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE ì__USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE í__USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET î__USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET ï__USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE ð__USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE ñ__USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE ò__USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE ó__USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET ô__USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET õ__USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE ö__USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE ÷__USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE ø__USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE ù__USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET ú__USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET û__USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE ü__USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE ý__USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET þ__USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET ÿ__USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
__USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_FORCE_RESET ((void)0U) __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE ¡__WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ¢__WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE £__WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET ¤__WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET ¦__TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE §__TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE ¨__TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET ©__TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET ª__TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE «__TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE ¬__TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE ®__TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET ¯__TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET °__TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE ±__TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE ²__CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE ³__CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE ´__CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE µ__CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE ¶__CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET ·__CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET ¸__RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE ¹__RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE »__USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET ¼__USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET ½__USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE ¾__USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE ¿__USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE À__USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE Á__USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE Â__USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE Ã__TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE Ä__TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE Å__TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE Æ__TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE Ç__TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE È__TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE É__ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE Ê__ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE Ë__ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE Ì__ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE Í__HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE Î__HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET Ï__HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET Ð__HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE Ñ__HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE Ò__HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE Ó__SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE Ô__SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE Õ__SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET Ö__SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET ×__SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE Ø__SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE Ù__SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE Ú__SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE Û__SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET Ü__SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET Ý__SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE Þ__SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE ß__LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE à__LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE á__LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET â__LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET ã__LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE ä__ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE å__ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE æ__ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE ç__ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE è__ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE é__ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE ê__TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE ë__TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE ì__TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE í__TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE î__TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE ï__TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE ð__BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE ñ__BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE ò__BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE ó__BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE ô__CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE õ__CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE ö__USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE ÷__USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE ø__USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET ù__USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET ú__USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE û__USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE ü__SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE ý__SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE þ__SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET ÿ__SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
__GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE ¡__UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE ¢__UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE £__UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET ¤__UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET ¥__UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE ¦__UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE §__OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE ¨__OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE ©__OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET ª__OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET «__OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE ¬__OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE ®__HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE ¯__HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED °__HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED ±__HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET ²__HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET ³__HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE ´__HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE µ__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED ¶__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED ·__SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE ¸__CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE ¹__CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE º__DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE »__DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE ¼__ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE ½__ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE ¾__ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE ¿__ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE À__FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET Á__FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET Â__FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE Ã__FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE Ä__SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET Å__SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET Æ__SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE Ç__SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE È__DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE É__DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE Ê__DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET Ë__DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET Ì__DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE Í__DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE Ð__HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET Ñ__HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET Ó__ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE Ô__ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE Õ__ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE Ö__ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE ×__DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE Ø__DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE Ù__TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE Ú__TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE Û__TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE Ü__TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE Ý__TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE Þ__TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE ß__HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE à__HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE á__SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE â__SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE ã__SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE ä__SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE å__SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE æ__SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE è__ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET é__ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET ê__ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET ë__ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET ì__DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET í__DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET î__TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET ï__TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET ð__TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET ñ__TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET ò__TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET ó__TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET ô__HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET õ__HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET ö__SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET ÷__SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET ø__SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET ù__SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET ú__SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET û__SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET ý__ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED þ__ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED ÿ__ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
__CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED ¡__GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED ¢__GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED £__HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED ¤__HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED ¥__I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED ¦__I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED §__I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED ¨__I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED ©__I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED ª__I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED «__PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED ¬__PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED ®__SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED ¯__SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED °__SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED ±__SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED ²__SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED ³__SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED ´__SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED µ__SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED ¶__SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED ·__SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED ¸__SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED ¹__SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED º__SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED »__SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED ¼__SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED ½__SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED ¾__SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED ¿__TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED À__TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED Á__TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED Â__TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED Ã__TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED Ä__TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED Å__TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED Æ__TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED Ç__TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED È__TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED É__TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED Ê__TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED Ë__TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED Ì__TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED Í__TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED Î__TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED Ï__TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED Ð__TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED Ñ__TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED Ò__TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED Ó__TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED Ô__TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED Õ__TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED Ö__TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED ×__TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED Ø__TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED Ù__TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED Ú__TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED Û__TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED Ü__TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED Ý__TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED Þ__TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED ß__TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED à__TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED á__TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED â__TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED ã__UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED ä__UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED å__UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED æ__UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED ç__USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED è__USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED é__USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED ê__USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED ë__USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED ì__USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED í__USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED î__USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED ï__WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED ð__WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED ¡ __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() ¢ __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() £ __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() ¤ __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() ¥ __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() ¦ __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() § __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() ¨ __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() © __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() ª __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() ¬ __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() ® __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() ¯ __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() ° __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() ± __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() ² __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() ³ __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() ´ __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() µ __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() ¸ __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG ¹ __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG » __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE ½ IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE ¾ IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE ¿ IS_RCC_SYSCLK_DIV IS_RCC_HCLK À IS_RCC_HCLK_DIV IS_RCC_PCLK Á IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK Ã RCC_IT_HSI14 RCC_IT_HSI14RDY Å RCC_IT_CSSLSE RCC_IT_LSECSS Æ RCC_IT_CSSHSE RCC_IT_CSS È RCC_PLLMUL_3 RCC_PLL_MUL3 É RCC_PLLMUL_4 RCC_PLL_MUL4 Ê RCC_PLLMUL_6 RCC_PLL_MUL6 Ë RCC_PLLMUL_8 RCC_PLL_MUL8 Ì RCC_PLLMUL_12 RCC_PLL_MUL12 Í RCC_PLLMUL_16 RCC_PLL_MUL16 Î RCC_PLLMUL_24 RCC_PLL_MUL24 Ï RCC_PLLMUL_32 RCC_PLL_MUL32 Ð RCC_PLLMUL_48 RCC_PLL_MUL48 Ò RCC_PLLDIV_2 RCC_PLL_DIV2 Ó RCC_PLLDIV_3 RCC_PLL_DIV3 Ô RCC_PLLDIV_4 RCC_PLL_DIV4 Ö IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE × __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG Ø RCC_MCO_NODIV RCC_MCODIV_1 Ù RCC_MCO_DIV1 RCC_MCODIV_1 Ú RCC_MCO_DIV2 RCC_MCODIV_2 Û RCC_MCO_DIV4 RCC_MCODIV_4 Ü RCC_MCO_DIV8 RCC_MCODIV_8 Ý RCC_MCO_DIV16 RCC_MCODIV_16 Þ RCC_MCO_DIV32 RCC_MCODIV_32 ß RCC_MCO_DIV64 RCC_MCODIV_64 à RCC_MCO_DIV128 RCC_MCODIV_128 á RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK â RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI ã RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE ä RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK å RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI æ RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 ç RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 è RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE é RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK ê RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK ë RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 õ RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK ø RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 ù RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL ú RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI û RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL ü RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL ý RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 þ RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 ÿ RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 HSION_BitNumber RCC_HSION_BIT_NUMBER HSION_BITNUMBER RCC_HSION_BIT_NUMBER HSEON_BitNumber RCC_HSEON_BIT_NUMBER HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
MSION_BITNUMBER RCC_MSION_BIT_NUMBER CSSON_BitNumber RCC_CSSON_BIT_NUMBER CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER PLLON_BitNumber RCC_PLLON_BIT_NUMBER PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER BDRST_BitNumber RCC_BDRST_BIT_NUMBER BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER LSION_BitNumber RCC_LSION_BIT_NUMBER LSION_BITNUMBER RCC_LSION_BIT_NUMBER LSEON_BitNumber RCC_LSEON_BIT_NUMBER LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER RMVF_BitNumber RCC_RMVF_BIT_NUMBER RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE ¢ CR_HSION_BB RCC_CR_HSION_BB £ CR_CSSON_BB RCC_CR_CSSON_BB ¤ CR_PLLON_BB RCC_CR_PLLON_BB ¥ CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB ¦ CR_MSION_BB RCC_CR_MSION_BB § CSR_LSION_BB RCC_CSR_LSION_BB ¨ CSR_LSEON_BB RCC_CSR_LSEON_BB © CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB ª CSR_RTCEN_BB RCC_CSR_RTCEN_BB « CSR_RTCRST_BB RCC_CSR_RTCRST_BB ¬ CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB ® BDCR_BDRST_BB RCC_BDCR_BDRST_BB ¯ CR_HSEON_BB RCC_CR_HSEON_BB ° CSR_RMVF_BB RCC_CSR_RMVF_BB ± CR_PLLSAION_BB RCC_CR_PLLSAION_BB ² DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB ´ __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE µ __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE ¶ __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE · __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE ¸ __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE º __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT ¼ RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN ½ RCC_CRS_TRIMOV RCC_CRS_TRIMOVF ¿ RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 À RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ Á RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP Â RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ Ã IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE Ä RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 Æ __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE Ç __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE È __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED É __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED Ê __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET Ë __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET Ì __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE Í __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE Î __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED Ï __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED Ð DfsdmClockSelection Dfsdm1ClockSelection Ñ RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 Ò RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 Ó RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK Ô __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG Õ __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE Ö RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 × RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 Ù RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 Ú RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 Ý RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 Þ RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ß RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 à RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 á RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 â RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 ã RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 â HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) ð __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG ò __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT ó __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG IS_ALARM IS_RTC_ALARM IS_ALARM_MASK IS_RTC_ALARM_MASK IS_TAMPER IS_RTC_TAMPER IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE ¡ IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ ¢ IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION £ IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER ¤ IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK ¥ IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER § __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE ¨ __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE · SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE ¸ SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS » eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE ¼ eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE ½ eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE ¿ SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV À SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV ø HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef ù HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef ú HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef û HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef ÿ HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE ¤ __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 ¥ __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 ¦ __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START § __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH ¨ __HAL_SMBUS_GET_DIR SMBUS_GET_DIR © __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE ª __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE « __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED ´ __HAL_SPI_1LINE_TX SPI_1LINE_TX µ __HAL_SPI_1LINE_RX SPI_1LINE_RX ¶ __HAL_SPI_RESET_CRC SPI_RESET_CRC À __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE Á __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION Â __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE Ã __UART_MASK_COMPUTATION UART_MASK_COMPUTATION Å IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD Ç IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE È IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE Ó __USART_ENABLE_IT __HAL_USART_ENABLE_IT Ô __USART_DISABLE_IT __HAL_USART_DISABLE_IT Õ __USART_ENABLE __HAL_USART_ENABLE Ö __USART_DISABLE __HAL_USART_DISABLE Ø __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE Ù __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE é USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE ë USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ì USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE í USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE î USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE ð USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ñ USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ò USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ó USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE õ __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT ö __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT ÷ __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG ø __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG ù __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE ú __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE û __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ý __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT þ __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT ÿ __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG !__HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG !__HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE !__HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE !__HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE !__HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT !__HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT !__HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT !__HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG !__HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG !__HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE !__HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE !__HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE !__HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT !HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup !HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup !HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo !HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo ¶!__HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE ·!__HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE ¹!TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE º!TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT ¼!__HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE ¾!__HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN ¿!__HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER À!__HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER Á!__HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER Â!__HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD Ã!__HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD Ä!__HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION Å!__HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION Æ!__HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER Ç!__HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER È!__HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE É!__HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE Ë!TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 Í!TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 Î!TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 ×!__HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT Ø!__HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT Ù!__HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG Ú!__HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG Û!__HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER Ü!__HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER Ý!__HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER ß!ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE à!ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE á!IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE é!__HAL_LTDC_LAYER LTDC_LAYER ê!__HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG ò!SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE ó!SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE ô!SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE õ!SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE ö!SAI_STREOMODE SAI_STEREOMODE ÷!SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY ø!SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL ù!SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL ú!SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL û!SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL ü!SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL ý!IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE þ!SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 ÿ!SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE "HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow "HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT "HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA "HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT "HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA "HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart "HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT "HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA "HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop £"HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE ` U ../Drivers/STM32H7xx_HAL_Driver/Inc/ Legacy/stm32_hal_legacy.h È
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../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ¾ ¿ À __stddef_h __ARMCLIB_VERSION 5060037 __STDDEF_DECLS __CLIBNS __CLIBNS SNULL TNULL 0 [offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb))) P D C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stddef.h C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] int unsigned int unsigned short long double Pptrdiff_t &Psize_t .Pwchar_t ¡ @ Pmax_align_t ³ _ Â Ã Ä Å __math_h __ARMCLIB_VERSION 5060037 __LONGLONG long long ,__USE_C99_MATH 1 0_ARMABI __declspec(__nothrow) 4_ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) 5__HAVE_LONGDOUBLE 1 7_ARMABI_PURE __declspec(__nothrow) __attribute__((const)) ;_ARMABI_FPEXCEPT _ARMABI __attribute__((const)) B_ARMABI_INLINE static __inline C_ARMABI_INLINE_DEF static __inline O_SOFTFP __attribute__((__pcs__("aapcs"))) h__FLT(x) (*(unsigned *)&(x)) m__HI(x) (*(1 + (unsigned *)&(x))) n__LO(x) (*(unsigned *)&(x)) r__MATH_DECLS Ý__CLIBNS ä__CLIBNS é__has_builtin(x) 0 öHUGE_VALF ((float)__INFINITY__) ÷HUGE_VALL ((long double)__INFINITY__) øINFINITY ((float)__INFINITY__) ùNAN (__ESCAPE__(0f_7FC00000)) üMATH_ERRNO 1 ýMATH_ERREXCEPT 2 HUGE_VAL ((double)__INFINITY__) Ëfpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) ÑFP_ZERO (0) ÒFP_SUBNORMAL (4) ÓFP_NORMAL (5) ÔFP_INFINITE (3) ÕFP_NAN (7) ôFP_ILOGB0 (-0x7fffffff) õFP_ILOGBNAN ( 0x80000000) ÷isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x)) ÿisgreater(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) isgreaterequal(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x)) isless(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) ¥islessequal(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) ¯islessgreater(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y))) ¹isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x)) Áisnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x)) Éisunordered(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) ¥signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x)) Ê_ARMDEFLD1(f) _ARMABI long double f ## l(long double ) Í_ARMDEFLD1P(f,T) _ARMABI long double f ## l(long double , T ) Ð_ARMDEFLD2(f) _ARMABI long double f ## l(long double , long double ) FP_FAST_FMA FP_FAST_FMAF ¡FP_FAST_FMAL ì_ARMDEFLD1 í_ARMDEFLD1P î_ARMDEFLD2 ¦
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__LONGLONG L B C:\Keil_v5\ARM\ARMCC\Bin\..\include\ math.h Ð C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] float double int unsigned int long double long long long char Pfloat_t îPdouble_t ï qmath_errhandling ÿ ;Ì'__ARM_isfinitef $ __x a__result ;ý'__ARM_isfinite $ __x a__result ;¬'__ARM_isinff $ __x a__result ;Ú'__ARM_isinf $ __x a__result ;¡¥'__ARM_islessgreaterf $ __x $ __y a__result \__f ¢ ;çª'__ARM_islessgreater $ __x $ __y a__result \__f ¢ ;´'__ARM_isnanf $ __x a__result ;͸'__ARM_isnan $ __x a__result \__xf ¢ ;À'__ARM_isnormalf $ __x a__result \__xe ¢ ;ÂÅ'__ARM_isnormal $ __x a__result \__xe ¢ ;óÍ'__ARM_signbitf $ __x a__result ;£Ñ'__ARM_signbit $ __x a__result ;Ëð_sqrt $ __x a__result ;ôõ_sqrtf $ __x a__result ;§¯$copysign $ __x $ __y a__result ;Û·#copysignf $ __x $ __y a__result ; ±#fabsf $ __f a__result ;º ¦$fmal ² $² __x $² __y $² __z a__result ² ;ã µ lrintl Á $² __x a__result Á ;
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»#llrintl É $² __x a__result É ;·
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Á lroundl Á $² __x a__result Á ;â
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Ç#llroundl É $² __x a__result É ; Í)nanl ² $__t a__result ² Ö ";Ë Þ remquol ² $² __x $² __y $Ë__q a__result ² " # Ô math_errhandling Ç È É STM32H7xx_HAL_DEF :HAL_MAX_DELAY 0xFFFFFFFFU <HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) == (BIT)) =HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == 0U) ?__HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0) FUNUSED(x) ((void)(x)) X__HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) ]__HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0) i__HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0) __ALIGN_END __ALIGN_BEGIN __align(4) ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) ³__RAM_FUNC Í__NOINLINE __attribute__ ( (noinline) ) ð ä ../Drivers/STM32H7xx_HAL_Driver/Inc/ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stm32h7xx_hal_def.h stm32h7xx.h Legacy/stm32_hal_legacy.h stddef.h math.h L
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM úHAL_OK HAL_ERROR HAL_BUSY HAL_TIMEOUT PHAL_StatusTypeDef à -¶HAL_UNLOCKED HAL_LOCKED PHAL_LockTypeDef 6 Ë Ì Í STM32H7xx_HAL_RCC_EX_H I2c1235ClockSelection I2c123ClockSelection éRCC_PERIPHCLK_USART16 ((uint64_t)(0x00000001U)) êRCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 ëRCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 íRCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16 ïRCC_PERIPHCLK_USART234578 ((uint64_t)(0x00000002U)) ðRCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 ñRCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 òRCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578 óRCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578 ôRCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 õRCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 öRCC_PERIPHCLK_LPUART1 ((uint64_t)(0x00000004U)) ÿRCC_PERIPHCLK_I2C123 ((uint64_t)(0x00000008U)) RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C4 ((uint64_t)(0x00000010U)) RCC_PERIPHCLK_LPTIM1 ((uint64_t)(0x00000020U)) RCC_PERIPHCLK_LPTIM2 ((uint64_t)(0x00000040U)) RCC_PERIPHCLK_LPTIM345 ((uint64_t)(0x00000080U)) RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345 RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345 RCC_PERIPHCLK_SAI1 ((uint64_t)(0x00000100U)) RCC_PERIPHCLK_SAI23 ((uint64_t)(0x00000200U)) RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23 RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23 RCC_PERIPHCLK_SAI4A ((uint64_t)(0x00000400U)) RCC_PERIPHCLK_SAI4B ((uint64_t)(0x00000800U)) ¢RCC_PERIPHCLK_SPI123 ((uint64_t)(0x00001000U)) £RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 ¤RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 ¥RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123 ¦RCC_PERIPHCLK_SPI45 ((uint64_t)(0x00002000U)) §RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45 ¨RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45 ©RCC_PERIPHCLK_SPI6 ((uint64_t)(0x00004000U)) ªRCC_PERIPHCLK_FDCAN ((uint64_t)(0x00008000U)) «RCC_PERIPHCLK_SDMMC ((uint64_t)(0x00010000U)) ¬RCC_PERIPHCLK_RNG ((uint64_t)(0x00020000U)) RCC_PERIPHCLK_USB ((uint64_t)(0x00040000U)) ®RCC_PERIPHCLK_ADC ((uint64_t)(0x00080000U)) ¯RCC_PERIPHCLK_SWPMI1 ((uint64_t)(0x00100000U)) °RCC_PERIPHCLK_DFSDM1 ((uint64_t)(0x00200000U)) ´RCC_PERIPHCLK_RTC ((uint64_t)(0x00400000U)) µRCC_PERIPHCLK_CEC ((uint64_t)(0x00800000U)) ¶RCC_PERIPHCLK_FMC ((uint64_t)(0x01000000U)) ¸RCC_PERIPHCLK_QSPI ((uint64_t)(0x02000000U)) ½RCC_PERIPHCLK_DSI ((uint64_t)(0x04000000U)) ¾RCC_PERIPHCLK_SPDIFRX ((uint64_t)(0x08000000U)) ÀRCC_PERIPHCLK_HRTIM1 ((uint64_t)(0x10000000U)) ÃRCC_PERIPHCLK_LTDC ((uint64_t)(0x20000000U)) ÅRCC_PERIPHCLK_TIM ((uint64_t)(0x40000000U)) ÆRCC_PERIPHCLK_CKPER ((uint64_t)(0x80000000U)) ÈRCC_PERIPHCLK_PLL2_DIVP ((uint64_t)(0x0000000100000000U)) ÉRCC_PERIPHCLK_PLL2_DIVQ ((uint64_t)(0x0000000200000000U)) ÊRCC_PERIPHCLK_PLL2_DIVR ((uint64_t)(0x0000000400000000U)) ËRCC_PERIPHCLK_PLL3_DIVP ((uint64_t)(0x0000000800000000U)) ÌRCC_PERIPHCLK_PLL3_DIVQ ((uint64_t)(0x0000001000000000U)) ÍRCC_PERIPHCLK_PLL3_DIVR ((uint64_t)(0x0000002000000000U)) ×RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN ØRCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN ÙRCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN âRCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN ãRCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN äRCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN íRCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 îRCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 ïRCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 ðRCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 úRCC_PLL2VCOWIDE (0x00000000U) ûRCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 RCC_PLL3VCOWIDE (0x00000000U) RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U) RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 ¡RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) ¢RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 £RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) ÑRCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 ÒRCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 ÓRCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 ÔRCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI ÕRCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI ÖRCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE ÞRCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 ßRCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 àRCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 áRCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI âRCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI ãRCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U) RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2 RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) ¥RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 ¦RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 §RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 ¨RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI ©RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI ªRCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE ³RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 ´RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 µRCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 ¶RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI ·RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI ¸RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE ÁRCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 ÂRCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 ÃRCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 ÄRCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI ÅRCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI ÆRCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE ÏRCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 ÐRCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 ÑRCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 ÒRCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI ÓRCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI ÔRCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE ÝRCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 ÞRCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 ßRCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 àRCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI áRCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI âRCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE ëRCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 ìRCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 íRCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 îRCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI ïRCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI ðRCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE úRCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U) üRCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1 ýRCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0 þRCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1 ÿRCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2 RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0) RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0 RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1 RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI ÂRCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 ÃRCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 ÄRCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI ÅRCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI ÕRCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 ÖRCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 ×RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI ØRCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI èRCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 éRCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 êRCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI ëRCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI öRCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U) ÷RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0 øRCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1 ùRCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) RCC_RNGCLKSOURCE_HSI48 (0x00000000U) RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0 RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1 RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL «RCC_HRTIM1CLK_TIMCLK (0x00000000U) ¬RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL ·RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0 ¸RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1 ¹RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL ÈRCC_SAI1CLKSOURCE_PLL (0x00000000U) ÉRCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0 ÊRCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1 ËRCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) ÌRCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2 ÜRCC_SAI23CLKSOURCE_PLL (0x00000000U) ÝRCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0 ÞRCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1 ßRCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) àRCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2 èRCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL éRCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 êRCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 ëRCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN ìRCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP õRCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL öRCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 ÷RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 øRCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN ùRCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP ¢RCC_SPI123CLKSOURCE_PLL (0x00000000U) £RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0 ¤RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1 ¥RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) ¦RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2 µRCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL ¶RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 ·RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 ¸RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN ¹RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP ÂRCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL ÃRCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 ÄRCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 ÅRCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN ÆRCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP ÏRCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL ÐRCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 ÑRCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 ÒRCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN ÓRCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP ÝRCC_SPI45CLKSOURCE_D2PCLK2 (0x00000000U) ÞRCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2 ßRCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0 àRCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1 áRCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) âRCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2 ãRCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) öRCC_SPI4CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2 ÷RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 øRCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 ùRCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI úRCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI ûRCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE RCC_SPI5CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U) RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0 RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1 RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2 RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) ° RCC_SAI4ACLKSOURCE_PLL (0x00000000U) ± RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0 ² RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1 ³ RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) ´ RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2 Ä RCC_SAI4BCLKSOURCE_PLL (0x00000000U) Å RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0 Æ RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1 Ç RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) È RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2 × RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U) Ù RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1 Ú RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0 Û RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1 Ü RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) Ý RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 Þ RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) ó RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) õ RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1 ö RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0 ÷ RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1 ø RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) ù RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 ú RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
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RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)
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RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1
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RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
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RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
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RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
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RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
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RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) ¨
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RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 ©
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RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 ª
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RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 «
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RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE ¬
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RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
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RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP ¶
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RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 ·
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RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 ¸
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RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 ¹
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RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE º
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RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI »
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RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP Å
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RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 Æ
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RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 Ç
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RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 È
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RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE É
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RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI Ê
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RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP Õ
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RCC_QSPICLKSOURCE_D1HCLK (0x00000000U) Ö
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RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0 ×
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RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1 Ø
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RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0 RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1 RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL ¢ RCC_FDCANCLKSOURCE_HSE (0x00000000U) £ RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0 ¤ RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1 ´ RCC_SDMMCCLKSOURCE_PLL (0x00000000U) µ RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL Ã RCC_ADCCLKSOURCE_PLL2 (0x00000000U) Ä RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0 Å RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1 Ó RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U) Ô RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL ã RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U) ä RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0 RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1 RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL RCC_CECCLKSOURCE_LSE (0x00000000U) RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0 RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1 £ RCC_CLKPSOURCE_HSI (0x00000000U) ¤ RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0 ¥ RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1 ² RCC_TIMPRES_DESACTIVATED (0x00000000U) ³ RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE Ö RCC_WWDG1 RCC_GCR_WW1RSC á RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 é RCC_CRS_NONE (0x00000000U) ê RCC_CRS_TIMEOUT (0x00000001U) ë RCC_CRS_SYNCOK (0x00000002U) ì RCC_CRS_SYNCWARN (0x00000004U) í RCC_CRS_SYNCERR (0x00000008U) î RCC_CRS_SYNCMISS (0x00000010U) ï RCC_CRS_TRIMOVF (0x00000020U) ÷ RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) ø RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 ù RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 ú RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) RCC_CRS_SYNC_DIV1 (0x00000000U)
RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) ¥ RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) · RCC_CRS_FREQERRORDIR_UP (0x00000000U) ¸ RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) À RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE Á RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE Â RCC_CRS_IT_ERR CRS_CR_ERRIE Ã RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE Ä RCC_CRS_IT_SYNCERR CRS_CR_ERRIE Å RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE Æ RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE Ï RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF Ð RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF Ñ RCC_CRS_FLAG_ERR CRS_ISR_ERRF Ò RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF Ó RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR Ô RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS Õ RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF ì __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) í __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) ÿ __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) ¬__HAL_RCC_PLL2_CONFIG(__PLL2M__,__PLL2N__,__PLL2P__,__PLL2Q__,__PLL2R__) do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); } while(0) Ã__HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) Ï__HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) Ý__HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) æ__HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) ç__HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) î__HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) ð__HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) ¦__HAL_RCC_PLL3_CONFIG(__PLL3M__,__PLL3N__,__PLL3P__,__PLL3Q__,__PLL3R__) do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); } while(0) ¾__HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) É__HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) ×__HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) æ__HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) ö__HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) ¥__HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) °__HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) ¾__HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG È__HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE Ö__HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG à__HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE «__HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) ¶__HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) Æ__HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) Ñ__HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) à__HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) ö__HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE §__HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG ´__HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE Ã__HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG Ð__HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE Ý__HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) ì__HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) ±__HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) È__HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) Ù__HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) é__HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG ô__HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG ¤__HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE ±__HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG ¼__HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE É__HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG Ô__HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE á__HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG ì__HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE ù__HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE Þ__HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) ï__HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) ¢__HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) ³__HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) Ã__HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) Ô__HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) ã__HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG î__HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE û__HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG ¡__HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) ¸__HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) ÷__HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) ¡__HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) ®__HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) ¼__HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) È__HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) Õ__HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) á__HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) î__HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) ©__HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) ·__HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) Å__HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) Ó__HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) ç__HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) ÷__HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG ª__HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE ¸__HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG Â__HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE Ò__HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) ã__HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) õ__HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE ¯__HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) Á__HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) Í__HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) ×__HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) æ__HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) õ__HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE); RCC->CFGR |= (__PRESC__); }while(0) __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) ¤ __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) ª __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) ° __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) Ð __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) × __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) Þ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) ä __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) ê __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); } while(0) ô __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); } while(0) þ __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) £ __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) ¯ __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) º __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) È RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) Ê __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) { WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); } else { WRITE_REG(CRS->ICR, (__INTERRUPT__)); } } while(0) â __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) ô RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) ö __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) { WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); } else { WRITE_REG(CRS->ICR, (__FLAG__)); } } while(0) __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) ¨ __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__,__FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) ý IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || ((VALUE) == RCC_PLL2_DIVQ) || ((VALUE) == RCC_PLL2_DIVR)) IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || ((VALUE) == RCC_PLL3_DIVQ) || ((VALUE) == RCC_PLL3_DIVR)) IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) © IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) ° IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) · IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) ¾ IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) Å IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) Ì IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) Ó IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) Ú IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) ó IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| ((SOURCE) == RCC_I2C4CLKSOURCE_CSI)) £ IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) © IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) ± IS_RCC_SAI1CLK(__SOURCE__) (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) ¹ IS_RCC_SAI23CLK(__SOURCE__) (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) À IS_RCC_SAI2CLK(__SOURCE__) (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) È IS_RCC_SAI3CLK(__SOURCE__) (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) ä IS_RCC_SPI123CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) ë IS_RCC_SPI1CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) ò IS_RCC_SPI2CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) ù IS_RCC_SPI3CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) !IS_RCC_SPI45CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) !IS_RCC_SPI4CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) !IS_RCC_SPI5CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) !IS_RCC_SPI6CLK(__SOURCE__) (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) ¬!IS_RCC_SAI4ACLK(__SOURCE__) (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) ³!IS_RCC_SAI4BCLK(__SOURCE__) (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) »!IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) ¼!IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) ½!IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) ¾!IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) ¿!IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) Á!IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) Â!IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) Ã!IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) Ä!IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) Å!IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) Ç!IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || ((VALUE) == RCC_PLL2VCIRANGE_1) || ((VALUE) == RCC_PLL2VCIRANGE_2) || ((VALUE) == RCC_PLL2VCIRANGE_3)) Ì!IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || ((VALUE) == RCC_PLL3VCIRANGE_1) || ((VALUE) == RCC_PLL3VCIRANGE_2) || ((VALUE) == RCC_PLL3VCIRANGE_3)) Ñ!IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || ((VALUE) == RCC_PLL2VCOMEDIUM)) Ô!IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || ((VALUE) == RCC_PLL3VCOMEDIUM)) ×!IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) Þ!IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) å!IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) ì!IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) ô!IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) ý!IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) "IS_RCC_QSPICLK(__SOURCE__) (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) "IS_RCC_FMCCLK(__SOURCE__) (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) ¢"IS_RCC_FDCANCLK(__SOURCE__) (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) ¨"IS_RCC_SDMMC(__SOURCE__) (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) ¬"IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) °"IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) ³"IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) »"IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) À"IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || ((SOURCE) == RCC_CECCLKSOURCE_LSI) || ((SOURCE) == RCC_CECCLKSOURCE_CSI)) Ä"IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || ((SOURCE) == RCC_CLKPSOURCE_CSI) || ((SOURCE) == RCC_CLKPSOURCE_HSE)) Ç"IS_RCC_TIMPRES(VALUE) (((VALUE) == RCC_TIMPRES_DESACTIVATED) || ((VALUE) == RCC_TIMPRES_ACTIVATED)) Ô"IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) Ø"IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) Ý"IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) â"IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) å"IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) ç"IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) é"IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) ë"IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) t i ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_rcc_ex.h stm32h7xx_hal_def.h \
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *Î PLL2M Y # PLL2N Y # PLL2P Y # PLL2Q Y # PLL2R Y # PLL2RGE Y # PLL2VCOSEL Y # PLL2FRACN Y # PRCC_PLL2InitTypeDef Æ H*ñ PLL3M Y # PLL3N Y # PLL3P Y # PLL3Q Y # PLL3R Y # PLL3RGE Y # PLL3VCOSEL Y # PLL3FRACN Y # PRCC_PLL3InitTypeDef ih*ß PLL1_P_Frequency Y # PLL1_Q_Frequency Y # PLL1_R_Frequency Y # PPLL1_ClocksTypeDef r*Ì PLL2_P_Frequency Y # PLL2_Q_Frequency Y # PLL2_R_Frequency Y # PPLL2_ClocksTypeDef y|*¹ PLL3_P_Frequency Y # PLL3_Q_Frequency Y # PLL3_R_Frequency Y # PPLL3_ClocksTypeDef æ*À PeriphClockSelection i # PLL2 N# PLL3 ñ#( FmcClockSelection Y #H QspiClockSelection Y #L SdmmcClockSelection Y #P CkperClockSelection Y #T Sai1ClockSelection Y #X Sai23ClockSelection Y #\ Spi123ClockSelection Y #` Spi45ClockSelection Y #d SpdifrxClockSelection Y #h Dfsdm1ClockSelection Y #l FdcanClockSelection Y #p Swpmi1ClockSelection Y #t Usart234578ClockSelection Y #x Usart16ClockSelection Y #| RngClockSelection Y # I2c123ClockSelection Y # UsbClockSelection Y # CecClockSelection Y # Lptim1ClockSelection Y # Lpuart1ClockSelection Y # I2c4ClockSelection Y # Lptim2ClockSelection Y # Lptim345ClockSelection Y # AdcClockSelection Y #¤ Sai4AClockSelection Y #¨ Sai4BClockSelection Y #¬ Spi6ClockSelection Y #° RTCClockSelection Y #´ Hrtim1ClockSelection Y #¸ TIMPresSelection Y #¼ PRCC_PeriphCLKInitTypeDef T*± Prescaler Y # Source Y # Polarity Y # ReloadValue Y # ErrorLimitValue Y # HSI48CalibrationValue Y # PRCC_CRSInitTypeDef *º*» ReloadValue Y # HSI48CalibrationValue Y # FreqErrorCapture Y # FreqErrorDirection Y # PRCC_CRSSynchroInfoTypeDef ÌÐ Ï Ð Ñ STM32H7xx_HAL_RCC_H RCC_OSCILLATORTYPE_NONE (0x00000000U) ¡RCC_OSCILLATORTYPE_HSE (0x00000001U) ¢RCC_OSCILLATORTYPE_HSI (0x00000002U) £RCC_OSCILLATORTYPE_LSE (0x00000004U) ¤RCC_OSCILLATORTYPE_LSI (0x00000008U) ¥RCC_OSCILLATORTYPE_CSI (0x00000010U) ¦RCC_OSCILLATORTYPE_HSI48 (0x00000020U) ¯RCC_HSE_OFF (0x00000000U) °RCC_HSE_ON RCC_CR_HSEON ±RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) ½RCC_LSE_OFF (0x00000000U) ¾RCC_LSE_ON RCC_BDCR_LSEON ¿RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) ËRCC_HSI_OFF (0x00000000U) ÌRCC_HSI_ON RCC_CR_HSION ÎRCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) ÏRCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) ÐRCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) ÑRCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) ÔRCC_HSICALIBRATION_DEFAULT (0x40U) ÜRCC_HSI48_OFF ((uint8_t)0x00) ÝRCC_HSI48_ON ((uint8_t)0x01) æRCC_LSI_OFF (0x00000000U) çRCC_LSI_ON RCC_CSR_LSION ðRCC_CSI_OFF (0x00000000U) ñRCC_CSI_ON RCC_CR_CSION óRCC_CSICALIBRATION_DEFAULT (0x20U) ûRCC_PLL_NONE (0x00000000U) üRCC_PLL_OFF (0x00000001U) ýRCC_PLL_ON (0x00000002U) RCC_PLLSOURCE_HSI (0x00000000U) RCC_PLLSOURCE_CSI (0x00000001U) RCC_PLLSOURCE_HSE (0x00000002U) RCC_PLLSOURCE_NONE (0x00000003U) RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 ¡RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 ¢RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 RCC_PLL1VCOWIDE (0x00000000U) ®RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL ¸RCC_CLOCKTYPE_SYSCLK (0x00000001U) ¹RCC_CLOCKTYPE_HCLK (0x00000002U) ºRCC_CLOCKTYPE_D1PCLK1 (0x00000004U) »RCC_CLOCKTYPE_PCLK1 (0x00000008U) ¼RCC_CLOCKTYPE_PCLK2 (0x00000010U) ½RCC_CLOCKTYPE_D3PCLK1 (0x00000020U) ÆRCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI ÇRCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI ÈRCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE ÉRCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1 ÒRCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI ÓRCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI ÔRCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE ÕRCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 ÞRCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1 ßRCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2 àRCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4 áRCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8 âRCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16 ãRCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64 äRCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128 åRCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256 æRCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512 ûRCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1 üRCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2 ýRCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4 þRCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8 ÿRCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16 RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64 RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128 RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256 RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512 RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1 RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2 RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4 RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8 RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16 «RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1 ¬RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2 RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4 ®RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8 ¯RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16 ÀRCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1 ÁRCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2 ÂRCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4 ÃRCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8 ÄRCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16 ÔRCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1 ÕRCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2 ÖRCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4 ×RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8 ØRCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16 çRCC_RTCCLKSOURCE_NO_CLK (0x00000000U) èRCC_RTCCLKSOURCE_LSE (0x00000100U) éRCC_RTCCLKSOURCE_LSI (0x00000200U) êRCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) ëRCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) ìRCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) íRCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) îRCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) ïRCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) ðRCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) ñRCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) òRCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) óRCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) ôRCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) õRCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) öRCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) ÷RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) øRCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) ùRCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) úRCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) ûRCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) üRCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) ýRCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) þRCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) ÿRCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) ¡RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) ¢RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) £RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) ¤RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) ¥RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) ¦RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) §RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) ²RCC_MCO1 (0x00000000U) ³RCC_MCO2 (0x00000001U) ¼RCC_MCO1SOURCE_HSI (0x00000000U) ½RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 ¾RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 ¿RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1) ÀRCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2 ÉRCC_MCO2SOURCE_SYSCLK (0x00000000U) ÊRCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0 ËRCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 ÌRCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1) ÍRCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2 ÎRCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2) ×RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0 ØRCC_MCODIV_2 RCC_CFGR_MCO1PRE_1 ÙRCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) ÚRCC_MCODIV_4 RCC_CFGR_MCO1PRE_2 ÛRCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) ÜRCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) ÝRCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) ÞRCC_MCODIV_8 RCC_CFGR_MCO1PRE_3 ßRCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) àRCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) áRCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) âRCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) ãRCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) äRCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) åRCC_MCODIV_15 RCC_CFGR_MCO1PRE ïRCC_IT_LSIRDY (0x00000001U) ðRCC_IT_LSERDY (0x00000002U) ñRCC_IT_HSIRDY (0x00000004U) òRCC_IT_HSERDY (0x00000008U) óRCC_IT_CSIRDY (0x00000010U) ôRCC_IT_HSI48RDY (0x00000020U) õRCC_IT_PLLRDY (0x00000040U) öRCC_IT_PLL2RDY (0x00000080U) ÷RCC_IT_PLL3RDY (0x00000100U) øRCC_IT_LSECSS (0x00000200U) ùRCC_IT_CSS (0x00000400U) RCC_FLAG_HSIRDY ((uint8_t)0x22) RCC_FLAG_HSIDIV ((uint8_t)0x25) RCC_FLAG_CSIRDY ((uint8_t)0x28) RCC_FLAG_HSI48RDY ((uint8_t)0x2D) RCC_FLAG_D1CKRDY ((uint8_t)0x2E) RCC_FLAG_D2CKRDY ((uint8_t)0x2F) RCC_FLAG_HSERDY ((uint8_t)0x31) RCC_FLAG_PLLRDY ((uint8_t)0x39) RCC_FLAG_PLL2RDY ((uint8_t)0x3B) RCC_FLAG_PLL3RDY ((uint8_t)0x3D) RCC_FLAG_LSERDY ((uint8_t)0x41) ¡RCC_FLAG_LSIRDY ((uint8_t)0x61) ¥RCC_FLAG_CPURST ((uint8_t)0x91) ©RCC_FLAG_D1RST ((uint8_t)0x93) ®RCC_FLAG_D2RST ((uint8_t)0x94) °RCC_FLAG_BORRST ((uint8_t)0x95) ±RCC_FLAG_PINRST ((uint8_t)0x96) ²RCC_FLAG_PORRST ((uint8_t)0x97) ³RCC_FLAG_SFTRST ((uint8_t)0x98) ´RCC_FLAG_IWDG1RST ((uint8_t)0x9A) µRCC_FLAG_WWDG1RST ((uint8_t)0x9C) ¶RCC_FLAG_LPWR1RST ((uint8_t)0x9E) ·RCC_FLAG_LPWR2RST ((uint8_t)0x9F) ÊRCC_LSEDRIVE_LOW (0x00000000U) ËRCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 ÌRCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 ÍRCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV ÕRCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) ÖRCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK ßRCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) àRCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK èHAL_RCC_REV_Y_HSITRIM_Pos (12U) éHAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U) êHAL_RCC_REV_Y_CSITRIM_Pos (26U) ëHAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U) ý__HAL_RCC_MDMA_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN); UNUSED(tmpreg); } while(0)
__HAL_RCC_DMA2D_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN); UNUSED(tmpreg); } while(0) __HAL_RCC_JPGDECEN_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN); UNUSED(tmpreg); } while(0) __HAL_RCC_FMC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); UNUSED(tmpreg); } while(0) __HAL_RCC_QSPI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); UNUSED(tmpreg); } while(0) Þ__HAL_RCC_SDMMC1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN); UNUSED(tmpreg); } while(0) ç__HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) è__HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) ê__HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) ì__HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) ï__HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) ÷__HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) ¨__HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) ©__HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) «__HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) ¯__HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) ±__HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) Ê__HAL_RCC_DMA1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); UNUSED(tmpreg); } while(0) Ò__HAL_RCC_DMA2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); UNUSED(tmpreg); } while(0) Ú__HAL_RCC_ADC12_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN); UNUSED(tmpreg); } while(0) ÷__HAL_RCC_ETH1MAC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN); UNUSED(tmpreg); } while(0) ÿ__HAL_RCC_ETH1TX_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN); UNUSED(tmpreg); } while(0) __HAL_RCC_ETH1RX_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN); UNUSED(tmpreg); } while(0) __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN); UNUSED(tmpreg); } while(0) __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN); UNUSED(tmpreg); } while(0) ¡__HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN); UNUSED(tmpreg); } while(0) ©__HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN); UNUSED(tmpreg); } while(0) ²__HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) ³__HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) ´__HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) ¼__HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) ½__HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) ¾__HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) À__HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) Á__HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) Ã__HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) Ä__HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) Í__HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) Î__HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) Ï__HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) ×__HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) Ø__HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) Ù__HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) Û__HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) Ü__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) Þ__HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) ß__HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) â__HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) ã__HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) ä__HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) ì__HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) í__HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) î__HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) ð__HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) ñ__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) ó__HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) ô__HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) __HAL_RCC_DCMI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); UNUSED(tmpreg); } while(0) ¥ __HAL_RCC_RNG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); UNUSED(tmpreg); } while(0) __HAL_RCC_SDMMC2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); UNUSED(tmpreg); } while(0) Ê __HAL_RCC_D2SRAM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN); UNUSED(tmpreg); } while(0) Ü __HAL_RCC_D2SRAM2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN); UNUSED(tmpreg); } while(0) î __HAL_RCC_D2SRAM3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN); UNUSED(tmpreg); } while(0)
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__HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
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__HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
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__HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
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__HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) ¥
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__HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) ª
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__HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) ½
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__HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) Å
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__HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) Æ
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__HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) Î
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__HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) Ó
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__HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) Ø
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__HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) å
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__HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) í
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__HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) î
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__HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) ö
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__HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) û
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__HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) __HAL_RCC_GPIOA_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN); UNUSED(tmpreg); } while(0) __HAL_RCC_GPIOB_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN); UNUSED(tmpreg); } while(0) __HAL_RCC_GPIOC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN); UNUSED(tmpreg); } while(0) § __HAL_RCC_GPIOD_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN); UNUSED(tmpreg); } while(0) ¯ __HAL_RCC_GPIOE_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN); UNUSED(tmpreg); } while(0) · __HAL_RCC_GPIOF_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN); UNUSED(tmpreg); } while(0) ¿ __HAL_RCC_GPIOG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN); UNUSED(tmpreg); } while(0) Ç __HAL_RCC_GPIOH_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN); UNUSED(tmpreg); } while(0) Ð __HAL_RCC_GPIOI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN); UNUSED(tmpreg); } while(0) Ù __HAL_RCC_GPIOJ_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN); UNUSED(tmpreg); } while(0) á __HAL_RCC_GPIOK_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN); UNUSED(tmpreg); } while(0) ê __HAL_RCC_CRC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN); UNUSED(tmpreg); } while(0) þ __HAL_RCC_BDMA_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN); UNUSED(tmpreg); } while(0) __HAL_RCC_ADC3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN); UNUSED(tmpreg); } while(0) __HAL_RCC_HSEM_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN); UNUSED(tmpreg); } while(0) ¥ __HAL_RCC_BKPRAM_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN); tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN); UNUSED(tmpreg); } while(0) ® __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) ¯ __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) ° __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) ± __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) ² __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) ³ __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) ´ __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) µ __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) · __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) ¹ __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) º __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) ¼ __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) Â __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) Å __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) È __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) Í __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) Ö __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) × __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) Ø __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) Ù __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) Ú __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) Û __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) Ü __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) Ý __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) ß __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) á __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) â __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) ä __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) ê __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) í __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) ð __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) õ __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) ÷ __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) ø __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) ù __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) ú __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) û __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) ü __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) ý __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) þ __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) ¡ __HAL_RCC_LTDC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN); tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN); UNUSED(tmpreg); } while(0) ´ __HAL_RCC_WWDG1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN); tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN); UNUSED(tmpreg); } while(0) ½ __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) Â __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) Ë __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) Ð __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) Ò __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) × __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) à __HAL_RCC_TIM2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); UNUSED(tmpreg); } while(0) è __HAL_RCC_TIM3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); UNUSED(tmpreg); } while(0) ð __HAL_RCC_TIM4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); UNUSED(tmpreg); } while(0) ø __HAL_RCC_TIM5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM6_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM7_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM12_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM13_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM14_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); UNUSED(tmpreg); } while(0) ¨__HAL_RCC_LPTIM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN); UNUSED(tmpreg); } while(0) º__HAL_RCC_SPI2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); UNUSED(tmpreg); } while(0) Â__HAL_RCC_SPI3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); UNUSED(tmpreg); } while(0) Ê__HAL_RCC_SPDIFRX_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN); UNUSED(tmpreg); } while(0) Ò__HAL_RCC_USART2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); UNUSED(tmpreg); } while(0) Ú__HAL_RCC_USART3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); UNUSED(tmpreg); } while(0) â__HAL_RCC_UART4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); UNUSED(tmpreg); } while(0) ê__HAL_RCC_UART5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); UNUSED(tmpreg); } while(0) ò__HAL_RCC_I2C1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); UNUSED(tmpreg); } while(0) ú__HAL_RCC_I2C2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); UNUSED(tmpreg); } while(0) __HAL_RCC_I2C3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN); UNUSED(tmpreg); } while(0) __HAL_RCC_CEC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); UNUSED(tmpreg); } while(0) __HAL_RCC_DAC12_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN); UNUSED(tmpreg); } while(0) ¤__HAL_RCC_UART7_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); UNUSED(tmpreg); } while(0) ¬__HAL_RCC_UART8_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); UNUSED(tmpreg); } while(0) ´__HAL_RCC_CRS_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN); tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN); UNUSED(tmpreg); } while(0) ¼__HAL_RCC_SWPMI1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN); tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN); UNUSED(tmpreg); } while(0) Ä__HAL_RCC_OPAMP_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN); tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN); UNUSED(tmpreg); } while(0) Ì__HAL_RCC_MDIOS_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN); tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN); UNUSED(tmpreg); } while(0) Ô__HAL_RCC_FDCAN_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); UNUSED(tmpreg); } while(0) ð__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) ñ__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) ò__HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) ó__HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) ô__HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) õ__HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) ö__HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) ÷__HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) ø__HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) ù__HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) ÿ__HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
__HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) £__HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) ¤__HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) ¥__HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) ¦__HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) §__HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) ¨__HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) ©__HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) ª__HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) «__HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) ¬__HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) °__HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) ±__HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) ²__HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) ³__HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) ´__HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) µ__HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) ¶__HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) ·__HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) ¸__HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) ¹__HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) ½__HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) ¾__HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) ¿__HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) À__HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) Á__HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) Â__HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) Ã__HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) Ä__HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) Å__HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) Í__HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) Î__HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) Ï__HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) Ð__HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) Ñ__HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) Ò__HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) Ó__HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) Ô__HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) Õ__HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) Ö__HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) Ú__HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) Û__HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) Ü__HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) Ý__HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) Þ__HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) ß__HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) à__HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) á__HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) â__HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) ã__HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) ç__HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) è__HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) é__HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) ê__HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) ë__HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) ì__HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) í__HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) î__HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) ï__HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) þ__HAL_RCC_TIM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM8_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); UNUSED(tmpreg); } while(0) __HAL_RCC_USART1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); UNUSED(tmpreg); } while(0) __HAL_RCC_USART6_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN); UNUSED(tmpreg); } while(0) ²__HAL_RCC_SPI1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); UNUSED(tmpreg); } while(0) º__HAL_RCC_SPI4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); UNUSED(tmpreg); } while(0) Â__HAL_RCC_TIM15_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); UNUSED(tmpreg); } while(0) Ê__HAL_RCC_TIM16_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); UNUSED(tmpreg); } while(0) Ò__HAL_RCC_TIM17_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); UNUSED(tmpreg); } while(0) Ú__HAL_RCC_SPI5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN); UNUSED(tmpreg); } while(0) â__HAL_RCC_SAI1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); UNUSED(tmpreg); } while(0) ë__HAL_RCC_SAI2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); UNUSED(tmpreg); } while(0) õ__HAL_RCC_SAI3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN); UNUSED(tmpreg); } while(0) þ__HAL_RCC_DFSDM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); UNUSED(tmpreg); } while(0) __HAL_RCC_HRTIM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN); UNUSED(tmpreg); } while(0) __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) ¢__HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) ¥__HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) §__HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) ©__HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) ²__HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) ³__HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) ´__HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) µ__HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) ¼__HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) ½__HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) ¾__HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) ¿__HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) À__HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) Á__HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) Â__HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) Ä__HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) Ç__HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) É__HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) Ë__HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) Î__HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) Ï__HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) Ð__HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) Ñ__HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) Ø__HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) Ù__HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) Ú__HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) Û__HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) Ü__HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) Ý__HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) Þ__HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) à__HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) ã__HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) å__HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) ç__HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) ð__HAL_RCC_SYSCFG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN); UNUSED(tmpreg); } while(0) ø__HAL_RCC_LPUART1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN); UNUSED(tmpreg); } while(0) __HAL_RCC_SPI6_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN); UNUSED(tmpreg); } while(0) __HAL_RCC_I2C4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN); UNUSED(tmpreg); } while(0) __HAL_RCC_LPTIM2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN); UNUSED(tmpreg); } while(0) __HAL_RCC_LPTIM3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN); UNUSED(tmpreg); } while(0) ¡__HAL_RCC_LPTIM4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN); UNUSED(tmpreg); } while(0) «__HAL_RCC_LPTIM5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN); UNUSED(tmpreg); } while(0) ¾__HAL_RCC_COMP12_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN); UNUSED(tmpreg); } while(0) Æ__HAL_RCC_VREF_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN); UNUSED(tmpreg); } while(0) Ï__HAL_RCC_SAI4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN); UNUSED(tmpreg); } while(0) Ø__HAL_RCC_RTC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN); tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN); UNUSED(tmpreg); } while(0) ô__HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) õ__HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) ö__HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) ÷__HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) ø__HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) ù__HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) û__HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) þ__HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
__HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) ¥__HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) ¦__HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) §__HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) ©__HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) ²__HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) ³__HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) ´__HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) µ__HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) ¶__HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) ·__HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) ¹__HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) ¼__HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) Á__HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) Â__HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) Ã__HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) Å__HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) ·$__HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) ½$__HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) ¾$__HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) À$__HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) Â$__HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) Ä$__HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) É$__HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) Ú$__HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) Û$__HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) Ü$__HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) Þ$__HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) à$__HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) â$__HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) ç$__HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) ý$__HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) %__HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) %__HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
%__HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) %__HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) %__HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) %__HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) %__HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) %__HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) %__HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) %__HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) %__HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) ¡%__HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) £%__HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) ©%__HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) ³%__HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) »%__HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) ¼%__HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) Ê%__HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) Ï%__HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) ×%__HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) Ø%__HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) ë%__HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) ñ%__HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) ò%__HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) ó%__HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) ô%__HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) õ%__HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) ö%__HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) ÷%__HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) ø%__HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) ú%__HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) ü%__HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) ý%__HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) ÿ%__HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
&__HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) &__HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) &__HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) &__HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) &__HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) &__HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) &__HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) &__HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) &__HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) &__HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) &__HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) &__HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) &__HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) &__HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) &__HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) &__HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) £&__HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) ¦&__HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) ©&__HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) ¯&__HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) ´&__HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) º&__HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) ¼&__HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) Å&__HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) Ê&__HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) Î&__HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) Ï&__HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) Ð&__HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) Ñ&__HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) Ò&__HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) Ó&__HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) Ô&__HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) Õ&__HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) Ö&__HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) ×&__HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) Ø&__HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) Ù&__HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) Ú&__HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) Û&__HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) Ü&__HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) Ý&__HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) Þ&__HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) ß&__HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) à&__HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) á&__HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) å&__HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) æ&__HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) ç&__HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) è&__HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) é&__HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) ê&__HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) ë&__HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) ì&__HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) í&__HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) õ&__HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) ö&__HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) ÷&__HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) ø&__HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) ù&__HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) ú&__HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) û&__HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) ü&__HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) ý&__HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) þ&__HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) ÿ&__HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) '__HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) '__HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) '__HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) '__HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) '__HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
'__HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) '__HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) '__HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) '__HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) '__HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) '__HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) '__HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) '__HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) '__HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) '__HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) '__HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) '__HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) '__HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) '__HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) '__HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) ¡'__HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) §'__HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) ¨'__HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) ©'__HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) ª'__HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) ±'__HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) ²'__HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) ³'__HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) ´'__HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) µ'__HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) ¶'__HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) ·'__HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) ¹'__HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) ¼'__HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) ¾'__HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) À'__HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) Ã'__HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) Ä'__HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) Å'__HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) Æ'__HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) Ç'__HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) Î'__HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) Ï'__HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) Ð'__HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) Ñ'__HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) Ò'__HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) Ó'__HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) Ô'__HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) Ö'__HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) Ù'__HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) Û'__HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) Ý'__HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) ä'__HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) ê'__HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) ë'__HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) ì'__HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) í'__HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) î'__HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) ï'__HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) ñ'__HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) ô'__HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) ù'__HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) ú'__HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) ü'__HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
(__HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) (__HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) (__HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) (__HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) (__HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) (__HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) (__HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) (__HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) (__HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) (__HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) (__HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) (__HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) ©(__HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) ª(__HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) ¬(__HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) ®(__HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) ¯(__HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) ±(__HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) ³(__HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) Ì(__HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) Í(__HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) Î(__HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) Ð(__HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) Ñ(__HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE ×(__HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) Ø(__HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) Ú(__HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) Ü(__HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) Ý(__HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) ß(__HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) á(__HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) ú(__HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) û(__HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) ü(__HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) þ(__HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) ÿ(__HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE )__HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) )__HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) )__HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) )__HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) )__HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) )__HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) )__HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) ¯)__HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) °)__HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) ±)__HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) ³)__HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) ¸)__HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) ¹)__HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) »)__HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) ½)__HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) ¾)__HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) À)__HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) Â)__HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) Û)__HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) Ü)__HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) Ý)__HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) ß)__HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) ë)__HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) ì)__HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) í)__HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) ò)__HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) ø)__HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) ù)__HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) û)__HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) ü)__HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) þ)__HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) ÿ)__HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) *__HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) *__HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) *__HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) *__HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) *__HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) *__HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) *__HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) *__HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) *__HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) *__HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) *__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) ¡*__HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) ¢*__HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) §*__HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) *__HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) ®*__HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) °*__HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) ±*__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) ³*__HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) ´*__HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) ·*__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) ¸*__HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) ¹*__HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) ¾*__HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) Ä*__HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) Å*__HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) Ç*__HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) È*__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) Ê*__HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) Ë*__HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) Ú*__HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) â*__HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) ã*__HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) î*__HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) ó*__HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) ø*__HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) ÿ*__HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +__HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +__HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +__HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +__HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +__HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) «+__HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) ³+__HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) ´+__HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) ¿+__HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) Ä+__HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) É+__HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) Ð+__HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) Ø+__HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) Ü+__HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) ä+__HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) é+__HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) î+__HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) ù+__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) ú+__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) û+__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) ü+__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) ý+__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) þ+__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) ÿ+__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) ,__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) ,__HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) ,__HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
,__HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) ,__HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) ,__HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) ,__HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) ,__HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) ,__HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) ,__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) ,__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) ,__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) ,__HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) ,__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) ,__HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) ,__HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) ¡,__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) £,__HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) ¥,__HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) ¦,__HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) ¨,__HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) ®,__HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) ±,__HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) ³,__HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) ¸,__HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) Ã,__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) Ä,__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) Å,__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) Æ,__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) Ç,__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) È,__HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) É,__HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) Ê,__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) Ì,__HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) Î,__HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) Ï,__HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) Ñ,__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) ×,__HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) Ú,__HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) Ü,__HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) á,__HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) ä,__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) å,__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) æ,__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) ç,__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) è,__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) é,__HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) ê,__HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) ë,__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) í,__HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) ï,__HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) ð,__HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) ò,__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) ø,__HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) û,__HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) ý,__HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) -__HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) -__HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) -__HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) -__HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) -__HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) ¦-__HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) «-__HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) ®-__HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) ³-__HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) ½-__HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) ¾-__HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) ¿-__HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) À-__HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) Á-__HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) Â-__HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) Ã-__HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) Ä-__HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) Å-__HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) Æ-__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) Ì-__HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) Í-__HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) Î-__HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) Ï-__HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) Ð-__HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) Ñ-__HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) Ò-__HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) Ó-__HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) Ô-__HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) Õ-__HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) Ù-__HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) Ú-__HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) Û-__HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) Ü-__HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) Ý-__HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) Þ-__HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) ß-__HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) à-__HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) á-__HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) ê-__HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) ë-__HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) ì-__HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) í-__HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) î-__HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) ï-__HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) ð-__HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) ñ-__HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) ò-__HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) ó-__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) ù-__HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) ú-__HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) û-__HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) ü-__HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) ý-__HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) þ-__HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) ÿ-__HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) .__HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) .__HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) .__HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) .__HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) .__HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) .__HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) .__HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) .__HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) .__HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) .__HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) .__HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) .__HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) .__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) .__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) .__HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) ¡.__HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) ¢.__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) £.__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) ¤.__HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) ¥.__HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) ¦.__HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) §.__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) «.__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) ¬.__HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) .__HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) ®.__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) ¯.__HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) °.__HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) ±.__HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) ².__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) ³.__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) ´.__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) ¸.__HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) ¹.__HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) º.__HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) ».__HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) ¼.__HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) ½.__HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) ¾.__HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) ¿.__HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) À.__HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) È.__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) É.__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) Ê.__HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) Ë.__HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) Ì.__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) Í.__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) Î.__HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) Ï.__HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) Ð.__HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) Ñ.__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) Õ.__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) Ö.__HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) ×.__HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) Ø.__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) Ù.__HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) Ú.__HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) Û.__HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) Ü.__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) Ý.__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) Þ.__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) â.__HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) ã.__HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) ä.__HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) å.__HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) æ.__HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) ç.__HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) è.__HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) é.__HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) ê.__HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) ú.__HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) û.__HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) ü.__HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) ý.__HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) /__HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
/__HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) /__HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) /__HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) /__HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) /__HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) /__HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) /__HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) /__HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) /__HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) /__HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) /__HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) /__HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) /__HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) /__HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) /__HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) ¡/__HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) ¢/__HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) £/__HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) ¤/__HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) ¥/__HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) ¦/__HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) ¨/__HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) «/__HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) /__HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) ¯/__HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) º/__HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) »/__HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) ¼/__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) ½/__HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) Ä/__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) Å/__HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) Æ/__HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) Ç/__HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) È/__HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) É/__HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) Ê/__HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) Ì/__HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) Ï/__HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) Ñ/__HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) Ó/__HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) Ö/__HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) ×/__HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) Ø/__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) Ù/__HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) à/__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) á/__HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) â/__HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) ã/__HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) ä/__HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) å/__HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) æ/__HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) è/__HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) ë/__HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) í/__HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) ï/__HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) ù/__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) ú/__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) û/__HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) ü/__HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) ý/__HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) þ/__HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 0__HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 0__HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 0__HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 0__HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 0__HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 0__HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 0__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 0__HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 0__HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 0__HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 0__HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 0__HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 0__HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 0__HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) ¤0__HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) ¥0__HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) ¦0__HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) ¨0__HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) ¹0__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) º0__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) »0__HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) ¼0__HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) ½0__HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) ¾0__HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) À0__HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) Ã0__HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) È0__HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) É0__HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) Ê0__HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) Ì0__HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) Õ0__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) Ö0__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) ×0__HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) Ø0__HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) Ù0__HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) Ú0__HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) Ü0__HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) ß0__HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) ä0__HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) å0__HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) æ0__HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) è0__HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) Î5__HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) Ñ5__HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) Ô5__HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) ×5__HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) Ú5__HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) Ý5__HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) à5__HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) ã5__HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) æ5__HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) é5__HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) ì5__HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) ï5__HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) ò5__HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) õ5__HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) û5__HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) þ5__HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) °6__HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) ³6__HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) ¶6__HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) ¹6__HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) ¼6__HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) ¿6__HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) Â6__HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) Å6__HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) È6__HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) Ë6__HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) Î6__HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) Ñ6__HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) Ô6__HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) ×6__HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) Ý6__HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) à6__HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) Û7__HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) ç7__HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) ø7__HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) ù7__HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 8__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) do { if(HAL_GetREVID() <= REV_ID_Y) { if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) { MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); } else { MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); } } else { MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); } } while(0) £8__HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) ¤8__HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) ®8__HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); °8__HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); Â8__HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) Ã8__HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) Ì8__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) do { if(HAL_GetREVID() <= REV_ID_Y) { if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) { MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); } else { MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); } } else { MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); } } while(0) ï8__HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) ð8__HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) û8__HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) ü8__HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) µ9__HAL_RCC_HSE_CONFIG(__STATE__) do { if ((__STATE__) == RCC_HSE_ON) { SET_BIT(RCC->CR, RCC_CR_HSEON); } else if ((__STATE__) == RCC_HSE_OFF) { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } else if ((__STATE__) == RCC_HSE_BYPASS) { SET_BIT(RCC->CR, RCC_CR_HSEBYP); SET_BIT(RCC->CR, RCC_CR_HSEON); } else { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } } while(0) :__HAL_RCC_LSE_CONFIG(__STATE__) do { if((__STATE__) == RCC_LSE_ON) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); } else if((__STATE__) == RCC_LSE_OFF) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } else if((__STATE__) == RCC_LSE_BYPASS) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); } else { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } } while(0) ª:__HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) «:__HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) Â:__HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) Å:__HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); } while (0) É:__HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) Ñ:__HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) Ò:__HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) Û:__HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) Ü:__HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) ï:__HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) ñ:__HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) ù:__HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) û:__HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) §;__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__,__PLLM1__,__PLLN1__,__PLLP1__,__PLLQ1__,__PLLR1__) do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); } while(0) ·;__HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) Ê;__HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) Ö;__HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) ä;__HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) ñ;__HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) ý;__HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) <__HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) <__HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__,__MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) ©<__HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__,__MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); À<__HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) do{ if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) { MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); } else { MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); } } while(0) ×<__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) â<__HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) ÷<__HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) =__HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) =__HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) ª=__HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) ®=__HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) >RCC_FLAG_MASK ((uint8_t)0x1F) >__HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) >RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) >Ê>HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT Ë>HSI_TIMEOUT_VALUE (2U) Ì>HSI48_TIMEOUT_VALUE (2U) Í>CSI_TIMEOUT_VALUE (2U) Î>LSI_TIMEOUT_VALUE (2U) Ï>PLL_TIMEOUT_VALUE (2U) Ð>PLL_FRAC_TIMEOUT_VALUE (1U) Ñ>CLOCKSWITCH_TIMEOUT_VALUE (5000U) Ò>RCC_DBP_TIMEOUT_VALUE (100U) Ó>RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT â>IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) î>IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_BYPASS)) ö>IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_BYPASS)) ú>IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) þ>IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) ?IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) ?IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) ?IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) ?IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || ((SOURCE) == RCC_PLLSOURCE_HSI) || ((SOURCE) == RCC_PLLSOURCE_NONE) || ((SOURCE) == RCC_PLLSOURCE_HSE)) ?IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || ((VALUE) == RCC_PLL1VCIRANGE_1) || ((VALUE) == RCC_PLL1VCIRANGE_2) || ((VALUE) == RCC_PLL1VCIRANGE_3)) ?IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) ?IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) ?IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) ?IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) ?IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) ?IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) ?IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) ?IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || ((VALUE) == RCC_PLL1_DIVQ) || ((VALUE) == RCC_PLL1_DIVR)) £?IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) ¥?IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) ª?IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || ((SYSCLK) == RCC_SYSCLK_DIV512)) ±?IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || ((HCLK) == RCC_HCLK_DIV512)) ·?IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || ((CDPCLK1) == RCC_APB3_DIV16)) »?IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 ½?IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || ((PCLK1) == RCC_APB1_DIV16)) Á?IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || ((PCLK2) == RCC_APB2_DIV16)) Å?IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || ((SRDPCLK1) == RCC_APB4_DIV16)) É?IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 Ë?IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) ì?IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) î?IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || ((SOURCE) == RCC_MCO1SOURCE_HSI48)) ò?IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) ö?IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || ((DIV) == RCC_MCODIV_15)) @IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) ®@IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) ¯@IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) ±@IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) ´@IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_rcc.h stm32h7xx_hal_def.h stm32h7xx_hal_rcc_ex.h D
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *è( PLLState Y # PLLSource Y # PLLM Y # PLLN Y # PLLP Y # PLLQ Y # PLLR Y # PLLRGE Y # PLLVCOSEL Y # PLLFRACN Y #$ PRCC_PLLInitTypeDef à O*ÒL OscillatorType Y # HSEState Y # LSEState Y # HSIState Y # HSICalibrationValue Y # LSIState Y # HSI48State Y # CSIState Y # CSICalibrationValue Y # PLL h#$ PRCC_OscInitTypeDef u*¨ ClockType Y # SYSCLKSource Y # SYSCLKDivider Y # AHBCLKDivider Y # APB3CLKDivider Y # APB1CLKDivider Y # APB2CLKDivider Y # APB4CLKDivider Y # PRCC_ClkInitTypeDef l Ó Ô Õ STM32H7xx_HAL_GPIO_EX_H 4GPIO_AF0_RTC_50Hz ((uint8_t)0x00) 5GPIO_AF0_MCO ((uint8_t)0x00) 6GPIO_AF0_SWJ ((uint8_t)0x00) 7GPIO_AF0_LCDBIAS ((uint8_t)0x00) 8GPIO_AF0_TRACE ((uint8_t)0x00) ?GPIO_AF0_C1DSLEEP ((uint8_t)0x00) @GPIO_AF0_C1SLEEP ((uint8_t)0x00) AGPIO_AF0_D1PWREN ((uint8_t)0x00) BGPIO_AF0_D2PWREN ((uint8_t)0x00) LGPIO_AF1_TIM1 ((uint8_t)0x01) MGPIO_AF1_TIM2 ((uint8_t)0x01) NGPIO_AF1_TIM16 ((uint8_t)0x01) OGPIO_AF1_TIM17 ((uint8_t)0x01) PGPIO_AF1_LPTIM1 ((uint8_t)0x01) RGPIO_AF1_HRTIM1 ((uint8_t)0x01) UGPIO_AF1_SAI4 ((uint8_t)0x01) WGPIO_AF1_FMC ((uint8_t)0x01) ]GPIO_AF2_TIM3 ((uint8_t)0x02) ^GPIO_AF2_TIM4 ((uint8_t)0x02) _GPIO_AF2_TIM5 ((uint8_t)0x02) `GPIO_AF2_TIM12 ((uint8_t)0x02) aGPIO_AF2_SAI1 ((uint8_t)0x02) cGPIO_AF2_HRTIM1 ((uint8_t)0x02) eGPIO_AF2_TIM15 ((uint8_t)0x02) mGPIO_AF3_TIM8 ((uint8_t)0x03) nGPIO_AF3_LPTIM2 ((uint8_t)0x03) oGPIO_AF3_DFSDM1 ((uint8_t)0x03) pGPIO_AF3_LPTIM3 ((uint8_t)0x03) qGPIO_AF3_LPTIM4 ((uint8_t)0x03) rGPIO_AF3_LPTIM5 ((uint8_t)0x03) sGPIO_AF3_LPUART ((uint8_t)0x03) yGPIO_AF3_HRTIM1 ((uint8_t)0x03) {GPIO_AF3_LTDC ((uint8_t)0x03) GPIO_AF4_I2C1 ((uint8_t)0x04) GPIO_AF4_I2C2 ((uint8_t)0x04) GPIO_AF4_I2C3 ((uint8_t)0x04) GPIO_AF4_I2C4 ((uint8_t)0x04) GPIO_AF4_TIM15 ((uint8_t)0x04) GPIO_AF4_CEC ((uint8_t)0x04) GPIO_AF4_LPTIM2 ((uint8_t)0x04) GPIO_AF4_USART1 ((uint8_t)0x04) GPIO_AF4_DFSDM1 ((uint8_t)0x04) GPIO_AF4_DCMI ((uint8_t)0x04) GPIO_AF5_SPI1 ((uint8_t)0x05) GPIO_AF5_SPI2 ((uint8_t)0x05) GPIO_AF5_SPI3 ((uint8_t)0x05) GPIO_AF5_SPI4 ((uint8_t)0x05) ¡GPIO_AF5_SPI5 ((uint8_t)0x05) ¢GPIO_AF5_SPI6 ((uint8_t)0x05) £GPIO_AF5_CEC ((uint8_t)0x05) «GPIO_AF6_SPI2 ((uint8_t)0x06) ¬GPIO_AF6_SPI3 ((uint8_t)0x06) GPIO_AF6_SAI1 ((uint8_t)0x06) ®GPIO_AF6_I2C4 ((uint8_t)0x06) ²GPIO_AF6_DFSDM1 ((uint8_t)0x06) ³GPIO_AF6_UART4 ((uint8_t)0x06) ¸GPIO_AF6_SAI3 ((uint8_t)0x06) ÁGPIO_AF7_SPI2 ((uint8_t)0x07) ÂGPIO_AF7_SPI3 ((uint8_t)0x07) ÃGPIO_AF7_SPI6 ((uint8_t)0x07) ÄGPIO_AF7_USART1 ((uint8_t)0x07) ÅGPIO_AF7_USART2 ((uint8_t)0x07) ÆGPIO_AF7_USART3 ((uint8_t)0x07) ÇGPIO_AF7_USART6 ((uint8_t)0x07) ÈGPIO_AF7_UART7 ((uint8_t)0x07) ÉGPIO_AF7_SDMMC1 ((uint8_t)0x07) ÎGPIO_AF8_SPI6 ((uint8_t)0x08) ÐGPIO_AF8_SAI2 ((uint8_t)0x08) ÒGPIO_AF8_UART4 ((uint8_t)0x08) ÓGPIO_AF8_UART5 ((uint8_t)0x08) ÔGPIO_AF8_UART8 ((uint8_t)0x08) ÕGPIO_AF8_SPDIF ((uint8_t)0x08) ÖGPIO_AF8_LPUART ((uint8_t)0x08) ×GPIO_AF8_SDMMC1 ((uint8_t)0x08) ÙGPIO_AF8_SAI4 ((uint8_t)0x08) ßGPIO_AF9_FDCAN1 ((uint8_t)0x09) àGPIO_AF9_FDCAN2 ((uint8_t)0x09) áGPIO_AF9_TIM13 ((uint8_t)0x09) âGPIO_AF9_TIM14 ((uint8_t)0x09) ãGPIO_AF9_SDMMC2 ((uint8_t)0x09) äGPIO_AF9_LTDC ((uint8_t)0x09) åGPIO_AF9_SPDIF ((uint8_t)0x09) æGPIO_AF9_FMC ((uint8_t)0x09) èGPIO_AF9_QUADSPI ((uint8_t)0x09) ëGPIO_AF9_SAI4 ((uint8_t)0x09) öGPIO_AF10_SAI2 ((uint8_t)0x0A) øGPIO_AF10_SDMMC2 ((uint8_t)0x0A) úGPIO_AF10_OTG2_FS ((uint8_t)0x0A) üGPIO_AF10_COMP1 ((uint8_t)0x0A) ýGPIO_AF10_COMP2 ((uint8_t)0x0A) ÿGPIO_AF10_LTDC ((uint8_t)0x0A) GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) GPIO_AF10_QUADSPI ((uint8_t)0x0A) GPIO_AF10_SAI4 ((uint8_t)0x0A) GPIO_AF10_OTG1_HS ((uint8_t)0x0A) GPIO_AF10_TIM8 ((uint8_t)0x0A) GPIO_AF10_FMC ((uint8_t)0x0A) GPIO_AF11_SWP ((uint8_t)0x0B) GPIO_AF11_MDIOS ((uint8_t)0x0B) GPIO_AF11_UART7 ((uint8_t)0x0B) GPIO_AF11_SDMMC2 ((uint8_t)0x0B) GPIO_AF11_DFSDM1 ((uint8_t)0x0B) GPIO_AF11_COMP1 ((uint8_t)0x0B) GPIO_AF11_COMP2 ((uint8_t)0x0B) GPIO_AF11_TIM1 ((uint8_t)0x0B) GPIO_AF11_TIM8 ((uint8_t)0x0B) GPIO_AF11_I2C4 ((uint8_t)0x0B) ©GPIO_AF11_ETH ((uint8_t)0x0B) ¬GPIO_AF11_LTDC ((uint8_t)0x0B) µGPIO_AF12_FMC ((uint8_t)0x0C) ¶GPIO_AF12_SDMMC1 ((uint8_t)0x0C) ·GPIO_AF12_MDIOS ((uint8_t)0x0C) ¸GPIO_AF12_COMP1 ((uint8_t)0x0C) ¹GPIO_AF12_COMP2 ((uint8_t)0x0C) ºGPIO_AF12_TIM1 ((uint8_t)0x0C) »GPIO_AF12_TIM8 ((uint8_t)0x0C) ½GPIO_AF12_LTDC ((uint8_t)0x0C) ÀGPIO_AF12_OTG1_FS ((uint8_t)0x0C) ÉGPIO_AF13_DCMI ((uint8_t)0x0D) ÊGPIO_AF13_COMP1 ((uint8_t)0x0D) ËGPIO_AF13_COMP2 ((uint8_t)0x0D) ÍGPIO_AF13_LTDC ((uint8_t)0x0D) ÕGPIO_AF13_TIM1 ((uint8_t)0x0D) ÝGPIO_AF14_LTDC ((uint8_t)0x0E) ÞGPIO_AF14_UART5 ((uint8_t)0x0E) æGPIO_AF15_EVENTOUT ((uint8_t)0x0F) èIS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) GPIOA_PIN_AVAILABLE GPIO_PIN_All GPIOB_PIN_AVAILABLE GPIO_PIN_All GPIOC_PIN_AVAILABLE GPIO_PIN_All GPIOD_PIN_AVAILABLE GPIO_PIN_All GPIOE_PIN_AVAILABLE GPIO_PIN_All GPIOF_PIN_AVAILABLE GPIO_PIN_All GPIOG_PIN_AVAILABLE GPIO_PIN_All GPIOI_PIN_AVAILABLE GPIO_PIN_All GPIOJ_PIN_AVAILABLE GPIO_PIN_All GPIOH_PIN_AVAILABLE GPIO_PIN_All GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) ±GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL : ((__GPIOx__) == (GPIOB))? 1UL : ((__GPIOx__) == (GPIOC))? 2UL : ((__GPIOx__) == (GPIOD))? 3UL : ((__GPIOx__) == (GPIOE))? 4UL : ((__GPIOx__) == (GPIOF))? 5UL : ((__GPIOx__) == (GPIOG))? 6UL : ((__GPIOx__) == (GPIOH))? 7UL : ((__GPIOx__) == (GPIOI))? 8UL : ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) t j ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_gpio_ex.h stm32h7xx_hal_def.h È
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM × Ø Ù STM32H7xx_HAL_GPIO_H UGPIO_PIN_0 ((uint16_t)0x0001) VGPIO_PIN_1 ((uint16_t)0x0002) WGPIO_PIN_2 ((uint16_t)0x0004) XGPIO_PIN_3 ((uint16_t)0x0008) YGPIO_PIN_4 ((uint16_t)0x0010) ZGPIO_PIN_5 ((uint16_t)0x0020) [GPIO_PIN_6 ((uint16_t)0x0040) \GPIO_PIN_7 ((uint16_t)0x0080) ]GPIO_PIN_8 ((uint16_t)0x0100) ^GPIO_PIN_9 ((uint16_t)0x0200) _GPIO_PIN_10 ((uint16_t)0x0400) `GPIO_PIN_11 ((uint16_t)0x0800) aGPIO_PIN_12 ((uint16_t)0x1000) bGPIO_PIN_13 ((uint16_t)0x2000) cGPIO_PIN_14 ((uint16_t)0x4000) dGPIO_PIN_15 ((uint16_t)0x8000) eGPIO_PIN_All ((uint16_t)0xFFFF) gGPIO_PIN_MASK (0x0000FFFFU) uGPIO_MODE_INPUT MODE_INPUT vGPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) wGPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) xGPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) yGPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) zGPIO_MODE_ANALOG MODE_ANALOG {GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) |GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) }GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) GPIO_SPEED_FREQ_LOW (0x00000000U) GPIO_SPEED_FREQ_MEDIUM (0x00000001U) GPIO_SPEED_FREQ_HIGH (0x00000002U) GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) GPIO_NOPULL (0x00000000U) GPIO_PULLUP (0x00000001U) GPIO_PULLDOWN (0x00000002U) ¬__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) ´__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) ¼__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) Ä__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) î__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) ôGPIO_MODE_Pos 0u GPIO_MODE (0x3uL << GPIO_MODE_Pos) MODE_INPUT (0x0uL << GPIO_MODE_Pos) MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) ¡MODE_AF (0x2uL << GPIO_MODE_Pos) ¢MODE_ANALOG (0x3uL << GPIO_MODE_Pos) £OUTPUT_TYPE_Pos 4u ¤OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) ¥OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) ¦OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) §EXTI_MODE_Pos 16u ¨EXTI_MODE (0x3uL << EXTI_MODE_Pos) ©EXTI_IT (0x1uL << EXTI_MODE_Pos) ªEXTI_EVT (0x2uL << EXTI_MODE_Pos) «TRIGGER_MODE_Pos 20u ¬TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) ®TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) ¯TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) ¸IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) ¹IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) && (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) »IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || ((MODE) == GPIO_MODE_ANALOG)) ÇIS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) ÊIS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN)) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_gpio.h stm32h7xx_hal_def.h stm32h7xx_hal_gpio_ex.h h
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM * Pin Y # Mode Y # Pull Y # Speed Y # Alternate Y # PGPIO_InitTypeDef Ä >ÓGPIO_PIN_RESET GPIO_PIN_SET PGPIO_PinState ,G Û Ü Ý STM32H7xx_HAL_DMA_EX_H mHAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U nHAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U oHAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U pHAL_DMAMUX1_SYNC_LPTIM1_OUT 3U qHAL_DMAMUX1_SYNC_LPTIM2_OUT 4U rHAL_DMAMUX1_SYNC_LPTIM3_OUT 5U sHAL_DMAMUX1_SYNC_EXTI0 6U tHAL_DMAMUX1_SYNC_TIM12_TRGO 7U vHAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U wHAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U xHAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U yHAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U zHAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U {HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U |HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U }HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U ~HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U HAL_DMAMUX2_SYNC_I2C4_WKUP 10U HAL_DMAMUX2_SYNC_SPI6_WKUP 11U HAL_DMAMUX2_SYNC_COMP1_OUT 12U HAL_DMAMUX2_SYNC_RTC_WKUP 13U HAL_DMAMUX2_SYNC_EXTI0 14U
HAL_DMAMUX2_SYNC_EXTI2 15U HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U ¡HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U ¢HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U £HAL_DMAMUX1_REQ_GEN_EXTI0 6U ¤HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U ¦HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U §HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U ¨HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U ©HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U ªHAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U «HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U ¬HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U ®HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U ¯HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U °HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U ±HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U ²HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U ´HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U ·HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U ¹HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U ºHAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U »HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U ¼HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U ½HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U ¾HAL_DMAMUX2_REQ_GEN_EXTI0 20U ¿HAL_DMAMUX2_REQ_GEN_EXTI2 21U ÀHAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U ÁHAL_DMAMUX2_REQ_GEN_SPI6_IT 23U ÂHAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U ÃHAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U ÅHAL_DMAMUX2_REQ_GEN_ADC3_IT 26U ÆHAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U ÈHAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U ÉHAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U ÔHAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U ÕHAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 ÖHAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 ×HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO) IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2) IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || ((EVENT) == ENABLE)) IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO) IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT) IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) t i ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_dma_ex.h stm32h7xx_hal_def.h
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM áMEMORY0 MEMORY1 PHAL_DMA_MemoryTypeDef Æ 4*ï SyncSignalID Y # SyncPolarity Y # SyncEnable # EventEnable # RequestNumber Y # PHAL_DMA_MuxSyncConfigTypeDef þ K*Ó SignalID Y # Polarity Y # RequestNumber Y # PHAL_DMA_MuxRequestGeneratorConfigTypeDef \ ß à á STM32H7xx_HAL_DMA_H ÅHAL_DMA_ERROR_NONE (0x00000000U) ÆHAL_DMA_ERROR_TE (0x00000001U) ÇHAL_DMA_ERROR_FE (0x00000002U) ÈHAL_DMA_ERROR_DME (0x00000004U) ÉHAL_DMA_ERROR_TIMEOUT (0x00000020U) ÊHAL_DMA_ERROR_PARAM (0x00000040U) ËHAL_DMA_ERROR_NO_XFER (0x00000080U) ÌHAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) ÍHAL_DMA_ERROR_SYNC (0x00000200U) ÎHAL_DMA_ERROR_REQGEN (0x00000400U) ÏHAL_DMA_ERROR_BUSY (0x00000800U) ÚDMA_REQUEST_MEM2MEM 0U ÜDMA_REQUEST_GENERATOR0 1U ÝDMA_REQUEST_GENERATOR1 2U ÞDMA_REQUEST_GENERATOR2 3U ßDMA_REQUEST_GENERATOR3 4U àDMA_REQUEST_GENERATOR4 5U áDMA_REQUEST_GENERATOR5 6U âDMA_REQUEST_GENERATOR6 7U ãDMA_REQUEST_GENERATOR7 8U åDMA_REQUEST_ADC1 9U æDMA_REQUEST_ADC2 10U èDMA_REQUEST_TIM1_CH1 11U éDMA_REQUEST_TIM1_CH2 12U êDMA_REQUEST_TIM1_CH3 13U ëDMA_REQUEST_TIM1_CH4 14U ìDMA_REQUEST_TIM1_UP 15U íDMA_REQUEST_TIM1_TRIG 16U îDMA_REQUEST_TIM1_COM 17U ðDMA_REQUEST_TIM2_CH1 18U ñDMA_REQUEST_TIM2_CH2 19U òDMA_REQUEST_TIM2_CH3 20U óDMA_REQUEST_TIM2_CH4 21U ôDMA_REQUEST_TIM2_UP 22U öDMA_REQUEST_TIM3_CH1 23U ÷DMA_REQUEST_TIM3_CH2 24U øDMA_REQUEST_TIM3_CH3 25U ùDMA_REQUEST_TIM3_CH4 26U úDMA_REQUEST_TIM3_UP 27U ûDMA_REQUEST_TIM3_TRIG 28U ýDMA_REQUEST_TIM4_CH1 29U þDMA_REQUEST_TIM4_CH2 30U ÿDMA_REQUEST_TIM4_CH3 31U DMA_REQUEST_TIM4_UP 32U DMA_REQUEST_I2C1_RX 33U DMA_REQUEST_I2C1_TX 34U DMA_REQUEST_I2C2_RX 35U
DMA_REQUEST_I2C2_TX 36U DMA_REQUEST_SPI1_RX 37U DMA_REQUEST_SPI1_TX 38U DMA_REQUEST_SPI2_RX 39U DMA_REQUEST_SPI2_TX 40U DMA_REQUEST_USART1_RX 41U DMA_REQUEST_USART1_TX 42U DMA_REQUEST_USART2_RX 43U DMA_REQUEST_USART2_TX 44U DMA_REQUEST_USART3_RX 45U DMA_REQUEST_USART3_TX 46U DMA_REQUEST_TIM8_CH1 47U DMA_REQUEST_TIM8_CH2 48U DMA_REQUEST_TIM8_CH3 49U DMA_REQUEST_TIM8_CH4 50U DMA_REQUEST_TIM8_UP 51U DMA_REQUEST_TIM8_TRIG 52U DMA_REQUEST_TIM8_COM 53U DMA_REQUEST_TIM5_CH1 55U DMA_REQUEST_TIM5_CH2 56U DMA_REQUEST_TIM5_CH3 57U DMA_REQUEST_TIM5_CH4 58U DMA_REQUEST_TIM5_UP 59U DMA_REQUEST_TIM5_TRIG 60U ¢DMA_REQUEST_SPI3_RX 61U £DMA_REQUEST_SPI3_TX 62U ¥DMA_REQUEST_UART4_RX 63U ¦DMA_REQUEST_UART4_TX 64U §DMA_REQUEST_UART5_RX 65U ¨DMA_REQUEST_UART5_TX 66U ªDMA_REQUEST_DAC1_CH1 67U «DMA_REQUEST_DAC1_CH2 68U DMA_REQUEST_TIM6_UP 69U ®DMA_REQUEST_TIM7_UP 70U °DMA_REQUEST_USART6_RX 71U ±DMA_REQUEST_USART6_TX 72U ³DMA_REQUEST_I2C3_RX 73U ´DMA_REQUEST_I2C3_TX 74U ºDMA_REQUEST_DCMI 75U ½DMA_REQUEST_CRYP_IN 76U ¾DMA_REQUEST_CRYP_OUT 77U ÀDMA_REQUEST_HASH_IN 78U ÂDMA_REQUEST_UART7_RX 79U ÃDMA_REQUEST_UART7_TX 80U ÄDMA_REQUEST_UART8_RX 81U ÅDMA_REQUEST_UART8_TX 82U ÇDMA_REQUEST_SPI4_RX 83U ÈDMA_REQUEST_SPI4_TX 84U ÉDMA_REQUEST_SPI5_RX 85U ÊDMA_REQUEST_SPI5_TX 86U ÌDMA_REQUEST_SAI1_A 87U ÍDMA_REQUEST_SAI1_B 88U ÐDMA_REQUEST_SAI2_A 89U ÑDMA_REQUEST_SAI2_B 90U ÔDMA_REQUEST_SWPMI_RX 91U ÕDMA_REQUEST_SWPMI_TX 92U ×DMA_REQUEST_SPDIF_RX_DT 93U ØDMA_REQUEST_SPDIF_RX_CS 94U ÛDMA_REQUEST_HRTIM_MASTER 95U ÜDMA_REQUEST_HRTIM_TIMER_A 96U ÝDMA_REQUEST_HRTIM_TIMER_B 97U ÞDMA_REQUEST_HRTIM_TIMER_C 98U ßDMA_REQUEST_HRTIM_TIMER_D 99U àDMA_REQUEST_HRTIM_TIMER_E 100U ãDMA_REQUEST_DFSDM1_FLT0 101U äDMA_REQUEST_DFSDM1_FLT1 102U åDMA_REQUEST_DFSDM1_FLT2 103U æDMA_REQUEST_DFSDM1_FLT3 104U èDMA_REQUEST_TIM15_CH1 105U éDMA_REQUEST_TIM15_UP 106U êDMA_REQUEST_TIM15_TRIG 107U ëDMA_REQUEST_TIM15_COM 108U íDMA_REQUEST_TIM16_CH1 109U îDMA_REQUEST_TIM16_UP 110U ðDMA_REQUEST_TIM17_CH1 111U ñDMA_REQUEST_TIM17_UP 112U ôDMA_REQUEST_SAI3_A 113U õDMA_REQUEST_SAI3_B 114U ùDMA_REQUEST_ADC3 115U ¨BDMA_REQUEST_MEM2MEM 0U ©BDMA_REQUEST_GENERATOR0 1U ªBDMA_REQUEST_GENERATOR1 2U «BDMA_REQUEST_GENERATOR2 3U ¬BDMA_REQUEST_GENERATOR3 4U BDMA_REQUEST_GENERATOR4 5U ®BDMA_REQUEST_GENERATOR5 6U ¯BDMA_REQUEST_GENERATOR6 7U °BDMA_REQUEST_GENERATOR7 8U ±BDMA_REQUEST_LPUART1_RX 9U ²BDMA_REQUEST_LPUART1_TX 10U ³BDMA_REQUEST_SPI6_RX 11U ´BDMA_REQUEST_SPI6_TX 12U µBDMA_REQUEST_I2C4_RX 13U ¶BDMA_REQUEST_I2C4_TX 14U ¸BDMA_REQUEST_SAI4_A 15U ¹BDMA_REQUEST_SAI4_B 16U ¼BDMA_REQUEST_ADC3 17U ÍDMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) ÎDMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) ÏDMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) ØDMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) ÙDMA_PINC_DISABLE ((uint32_t)0x00000000U) âDMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) ãDMA_MINC_DISABLE ((uint32_t)0x00000000U) ìDMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) íDMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) îDMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) ÷DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) øDMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) ùDMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) DMA_NORMAL ((uint32_t)0x00000000U) DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) DMA_PRIORITY_LOW ((uint32_t)0x00000000U) DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) ¥DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) ¦DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) §DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) ¨DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) ±DMA_MBURST_SINGLE ((uint32_t)0x00000000U) ²DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) ³DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) ´DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) ½DMA_PBURST_SINGLE ((uint32_t)0x00000000U) ¾DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) ¿DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) ÀDMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) ÉDMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) ÊDMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) ËDMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) ÌDMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) ÍDMA_IT_FE ((uint32_t)0x00000080U) ÖDMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) ×DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) ØDMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) ÙDMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) ÚDMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) ÛDMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) ÜDMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) ÝDMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) ÞDMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) ßDMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) àDMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) áDMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) âDMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) ãDMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) äDMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) åDMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) æDMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) çDMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) èDMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) éDMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) òBDMA_FLAG_GL0 ((uint32_t)0x00000001) óBDMA_FLAG_TC0 ((uint32_t)0x00000002) ôBDMA_FLAG_HT0 ((uint32_t)0x00000004) õBDMA_FLAG_TE0 ((uint32_t)0x00000008) öBDMA_FLAG_GL1 ((uint32_t)0x00000010) ÷BDMA_FLAG_TC1 ((uint32_t)0x00000020) øBDMA_FLAG_HT1 ((uint32_t)0x00000040) ùBDMA_FLAG_TE1 ((uint32_t)0x00000080) úBDMA_FLAG_GL2 ((uint32_t)0x00000100) ûBDMA_FLAG_TC2 ((uint32_t)0x00000200) üBDMA_FLAG_HT2 ((uint32_t)0x00000400) ýBDMA_FLAG_TE2 ((uint32_t)0x00000800) þBDMA_FLAG_GL3 ((uint32_t)0x00001000) ÿBDMA_FLAG_TC3 ((uint32_t)0x00002000) BDMA_FLAG_HT3 ((uint32_t)0x00004000) BDMA_FLAG_TE3 ((uint32_t)0x00008000) BDMA_FLAG_GL4 ((uint32_t)0x00010000) BDMA_FLAG_TC4 ((uint32_t)0x00020000) BDMA_FLAG_HT4 ((uint32_t)0x00040000)
BDMA_FLAG_TE4 ((uint32_t)0x00080000) BDMA_FLAG_GL5 ((uint32_t)0x00100000) BDMA_FLAG_TC5 ((uint32_t)0x00200000) BDMA_FLAG_HT5 ((uint32_t)0x00400000) BDMA_FLAG_TE5 ((uint32_t)0x00800000) BDMA_FLAG_GL6 ((uint32_t)0x01000000) BDMA_FLAG_TC6 ((uint32_t)0x02000000) BDMA_FLAG_HT6 ((uint32_t)0x04000000) BDMA_FLAG_TE6 ((uint32_t)0x08000000) BDMA_FLAG_GL7 ((uint32_t)0x10000000) BDMA_FLAG_TC7 ((uint32_t)0x20000000) BDMA_FLAG_HT7 ((uint32_t)0x40000000) BDMA_FLAG_TE7 ((uint32_t)0x80000000) ¤__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) ²__HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) ¹__HAL_DMA_ENABLE(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN)) Â__HAL_DMA_DISABLE(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN)) ñ__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 : (uint32_t)0x00000000) ¶__HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 : (uint32_t)0x00000000) û__HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 : (uint32_t)0x00000000) __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 : (uint32_t)0x00000000) ´__HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 : (uint32_t)0x00000000) à__HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 : (uint32_t)0x00000000) __HAL_DMA_GET_FLAG(__HANDLE__,__FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) __HAL_DMA_CLEAR_FLAG(__HANDLE__,__FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) ¤DMA_TO_BDMA_IT(__DMA_IT__) ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) : (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) : (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) : (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) : ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE : ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE : ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE : (uint32_t)0x00000000) ¯__HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) ²__HAL_DMA_STREAM_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) Á__HAL_DMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) : (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__)))) Æ__HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) È__HAL_DMA_STREAM_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) ×__HAL_DMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) : (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__)))) Ü__HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) Þ__HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) î__HAL_DMA_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) : (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) __HAL_DMA_SET_COUNTER(__HANDLE__,__COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) : (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__))) __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) : (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR)) à IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) æ IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) ë IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) ï IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) ñ IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE)) ô IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE)) ÷ IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD)) û IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD )) ÿ IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || ((MODE) == DMA_CIRCULAR) || ((MODE) == DMA_PFCTRL) || ((MODE) == DMA_DOUBLE_BUFFER_M0) || ((MODE) == DMA_DOUBLE_BUFFER_M1))
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IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
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IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || ((STATE) == DMA_FIFOMODE_ENABLE))
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IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
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IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || ((BURST) == DMA_MBURST_INC4) || ((BURST) == DMA_MBURST_INC8) || ((BURST) == DMA_MBURST_INC16))
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IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || ((BURST) == DMA_PBURST_INC4) || ((BURST) == DMA_PBURST_INC8) || ((BURST) == DMA_PBURST_INC16)) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_dma.h stm32h7xx_hal_def.h stm32h7xx_hal_dma_ex.h $
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM uvoid "Ã t
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"ötY " "Ù " "O PDMA_InitTypeDef `PHAL_DMA_StateTypeDef ylPHAL_DMA_LevelCompleteTypeDef ðuPHAL_DMA_CallbackIDTypeDef 'PDMA_HandleTypeDef ö³*ù0 Request Y # Direction Y # PeriphInc Y # MemInc Y # PeriphDataAlignment Y # MemDataAlignment Y # Mode Y # Priority Y # FIFOMode Y # FIFOThreshold Y #$ MemBurst Y #( PeriphBurst Y #, ðHAL_DMA_STATE_RESET HAL_DMA_STATE_READY HAL_DMA_STATE_BUSY HAL_DMA_STATE_ERROR HAL_DMA_STATE_ABORT §HAL_DMA_FULL_TRANSFER HAL_DMA_HALF_TRANSFER öHAL_DMA_XFER_CPLT_CB_ID HAL_DMA_XFER_HALFCPLT_CB_ID HAL_DMA_XFER_M1CPLT_CB_ID HAL_DMA_XFER_M1HALFCPLT_CB_ID HAL_DMA_XFER_ERROR_CB_ID HAL_DMA_XFER_ABORT_CB_ID HAL_DMA_XFER_ALL_CB_ID )¦ __DMA_HandleTypeDef x Instance É # Init ó # Lock 6 #4 State Í #5 Parent É #8OÛ%Ñ "S XferCpltCallback [#<Oÿ%Ñ "w XferHalfCpltCallback #@O§ %Ñ " XferM1CpltCallback §#DOÍ %Ñ "Å XferM1HalfCpltCallback Í#HO÷ %Ñ "ï XferErrorCallback ÷#LO
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%Ñ " XferAbortCallback #P ErrorCode Õ #T StreamBaseAddress Y #X StreamIndex Y #\ DMAmuxChannel Û #` DMAmuxChannelStatus á #d DMAmuxChannelStatusMask Y #h DMAmuxRequestGen ç #l DMAmuxRequestGenStatus í #p DMAmuxRequestGenStatusMask Y #t ã ä å STM32H7xx_HAL_MDMA_H HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U)
HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) ¡MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) ¢MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) £MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) ¤MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) ¥MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) §MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) ªMDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) «MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) ¬MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) ®MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) µMDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) ¶MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) ¸MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) ¹MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) ºMDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) ÁMDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) ÃMDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) ÄMDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) ËMDMA_REQUEST_SW ((uint32_t)0x40000000U) ÕMDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) ÖMDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) ×MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) ØMDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) âMDMA_PRIORITY_LOW ((uint32_t)0x00000000U) ãMDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) äMDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) åMDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) ðMDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) ñMDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) òMDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) óMDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) ýMDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) þMDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) ÿMDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)
MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) ¡MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) ¢MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) £MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) ¤MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) ®MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) ¯MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) °MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) ±MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) »MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) ½MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) ¾MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) ÀMDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) ÊMDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) ËMDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) ÌMDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) ÍMDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) ÎMDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) ÏMDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) ÐMDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) ÑMDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) ÛMDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) ÜMDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) ÝMDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) ÞMDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) ßMDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) àMDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) áMDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) âMDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) ìMDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) íMDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) îMDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) ïMDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) ðMDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) úMDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) ûMDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) üMDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) ýMDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) þMDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) ÿMDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN) ª__HAL_MDMA_GET_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) ¸__HAL_MDMA_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) Æ__HAL_MDMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) Ô__HAL_MDMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) á__HAL_MDMA_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) é__HAL_MDMA_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) ð__HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) æIS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) ìIS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) ñIS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) úIS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END)) ýIS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || ((__INC__) == MDMA_SRC_INC_BYTE ) || ((__INC__) == MDMA_SRC_INC_HALFWORD ) || ((__INC__) == MDMA_SRC_INC_WORD ) || ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || ((__INC__) == MDMA_SRC_DEC_BYTE) || ((__INC__) == MDMA_SRC_DEC_HALFWORD) || ((__INC__) == MDMA_SRC_DEC_WORD) || ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD)) IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || ((__INC__) == MDMA_DEST_INC_BYTE ) || ((__INC__) == MDMA_DEST_INC_HALFWORD ) || ((__INC__) == MDMA_DEST_INC_WORD ) || ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || ((__INC__) == MDMA_DEST_DEC_BYTE) || ((__INC__) == MDMA_DEST_DEC_HALFWORD) || ((__INC__) == MDMA_DEST_DEC_WORD) || ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD)) IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD)) IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) ¡IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) «IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || ((__BURST__) == MDMA_DEST_BURST_8BEATS) || ((__BURST__) == MDMA_DEST_BURST_16BEATS) || ((__BURST__) == MDMA_DEST_BURST_32BEATS) || ((__BURST__) == MDMA_DEST_BURST_64BEATS) || ((__BURST__) == MDMA_DEST_BURST_128BEATS)) ´IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || ((__MODE__) == MDMA_BLOCK_TRANSFER ) || ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || ((__MODE__) == MDMA_FULL_TRANSFER)) ¹IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) »IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) ½IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) ¿IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) p g ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_mdma.h stm32h7xx_hal_def.h È
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM uvoid "Ä "ý"î PMDMA_InitTypeDef ®pPMDMA_LinkNodeTypeDef ÿPMDMA_LinkNodeConfTypeDef PHAL_MDMA_StateTypeDef ,©PHAL_MDMA_LevelCompleteTypeDef ¨µPHAL_MDMA_CallbackIDTypeDef ÄPMDMA_HandleTypeDef ýñ*ÿ8 Request Y # TransferTriggerMode Y # Priority Y # Endianness Y # SourceInc Y # DestinationInc Y # SourceDataSize Y # DestDataSize Y # DataAlignment Y # BufferTransferLength Y #$ SourceBurst Y #( DestBurst Y #, SourceBlockAddressOffset #0 DestBlockAddressOffset #4 *( CTCR # CBNDTR # CSAR # CDAR # CBRUR # CLAR # CTBR # Reserved # CMAR # CMDR #$ tY *¬P Init Ö # SrcAddress Y #8 DstAddress Y #< BlockDataLength Y #@ BlockCount Y #D PostRequestMaskAddress Y #H PostRequestMaskData Y #L ¨ HAL_MDMA_STATE_RESET HAL_MDMA_STATE_READY HAL_MDMA_STATE_BUSY HAL_MDMA_STATE_ERROR HAL_MDMA_STATE_ABORT
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HAL_MDMA_FULL_TRANSFER HAL_MDMA_BUFFER_TRANSFER HAL_MDMA_BLOCK_TRANSFER HAL_MDMA_REPEAT_BLOCK_TRANSFER ý HAL_MDMA_XFER_CPLT_CB_ID HAL_MDMA_XFER_BUFFERCPLT_CB_ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID HAL_MDMA_XFER_ERROR_CB_ID HAL_MDMA_XFER_ABORT_CB_ID HAL_MDMA_XFER_ALL_CB_ID )¿__MDMA_HandleTypeDef l Instance ¿# Init Ö # Lock 6 #< State Å#= Parent Ê #@Oã %Î "[ XferCpltCallback c#DO %Î " XferBufferCpltCallback #HO± %Î "© XferBlockCpltCallback ±#LOÚ %Î "Ò XferRepeatBlockCpltCallback Ú#PO%Î " XferErrorCallback #TO®%Î "& XferAbortCallback .#X FirstLinkedListNodeAddress Ò #\ LastLinkedListNodeAddress Ò #` LinkedListNodeCounter Y #d ErrorCode #h "U t, ç è é STM32H7xx_HAL_EXTI_H \EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U) ]EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U) ^EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U) _EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U) `EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U) aEXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U) bEXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U) cEXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U) dEXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U) eEXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U) fEXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU) gEXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU) hEXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU) iEXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU) jEXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU) kEXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU) lEXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U) mEXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U) nEXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U) oEXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U) pEXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U) qEXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U) rEXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) sEXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) tEXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) uEXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U) vEXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) wEXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) xEXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) yEXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) zEXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) {EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) |EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) }EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) ~EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U) EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U) EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U) EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU) EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU) EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU) EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U) EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U) EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U) EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U) EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U) EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U) ¢EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) £EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) ¤EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) ¦EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) ªEXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) ¬EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) °EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) ±EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) ²EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) ³EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) ´EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) µEXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) ¶EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U) ·EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U) ¸EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) ¹EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) ºEXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) »EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) ¼EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) ½EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U) ¾EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) ÀEXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) ÅEXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) ÏEXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU) ÐEXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU) ÑEXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU) ÒEXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U) ÔEXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U) ØEXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U) ÚEXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U) ÞEXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U) àEXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) âEXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) æEXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) ûEXTI_MODE_NONE 0x00000000U üEXTI_MODE_INTERRUPT 0x00000001U ýEXTI_MODE_EVENT 0x00000002U EXTI_TRIGGER_NONE 0x00000000U EXTI_TRIGGER_RISING 0x00000001U EXTI_TRIGGER_FALLING 0x00000002U EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) EXTI_GPIOA 0x00000000U EXTI_GPIOB 0x00000001U EXTI_GPIOC 0x00000002U EXTI_GPIOD 0x00000003U EXTI_GPIOE 0x00000004U EXTI_GPIOF 0x00000005U EXTI_GPIOG 0x00000006U EXTI_GPIOH 0x00000007U EXTI_GPIOI 0x00000008U ¢EXTI_GPIOJ 0x00000009U £EXTI_GPIOK 0x0000000AU EXTI_D3_PENDCLR_SRC_NONE 0x00000000U ®EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U ¯EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U ±EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U ¶EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U ÒEXTI_PROPERTY_SHIFT 24U ÓEXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) ÔEXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) ÕEXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) ÖEXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) ×EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) ÜEXTI_EVENT_PRESENCE_SHIFT 28U ÝEXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) ÞEXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) ãEXTI_REG_SHIFT 16U äEXTI_REG1 (0x00UL << EXTI_REG_SHIFT) åEXTI_REG2 (0x01UL << EXTI_REG_SHIFT) æEXTI_REG3 (0x02UL << EXTI_REG_SHIFT) çEXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) èEXTI_PIN_MASK 0x0000001FUL íEXTI_TARGET_SHIFT 20U îEXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT) ïEXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT) ðEXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT) öEXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1) ÷EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1 ùEXTI_TARGET_MSK_ALL EXTI_TARGET_MASK EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) EXTI_LINE_NB 88UL IS_EXTI_PROPERTY(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) ¥IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) ©IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && IS_EXTI_PROPERTY(__EXTI_LINE__) && IS_EXTI_TARGET(__EXTI_LINE__) && (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL)))) ¯IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL) ±IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL) ³IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)|| ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) ·IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00UL) ºIS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) || ((__PORT__) == EXTI_GPIOG) || ((__PORT__) == EXTI_GPIOH) || ((__PORT__) == EXTI_GPIOI) || ((__PORT__) == EXTI_GPIOJ) || ((__PORT__) == EXTI_GPIOK)) ÒIS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL) ÔIS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5)) p g ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_exti.h stm32h7xx_hal_def.h À
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM âHAL_EXTI_COMMON_CB_ID PEXTI_CallbackIDTypeDef Ä /*² Line Y # O " PendingCallback # PEXTI_HandleTypeDef 9*¨ Line Y # Mode Y # Trigger Y # GPIOSel Y # PendClearSource Y # PEXTI_ConfigTypeDef LN ë ì í STM32H7xx_HAL_CORTEX_H YNVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) [NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) ]NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) _NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) aNVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) jSYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) kSYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) uMPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) vMPU_HARDFAULT_NMI ((uint32_t)0x00000002) wMPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) xMPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) MPU_REGION_ENABLE ((uint8_t)0x01) MPU_REGION_DISABLE ((uint8_t)0x00) MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) MPU_ACCESS_SHAREABLE ((uint8_t)0x01) MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) MPU_ACCESS_CACHEABLE ((uint8_t)0x01) MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) ¤MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) ¥MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) MPU_TEX_LEVEL0 ((uint8_t)0x00) ®MPU_TEX_LEVEL1 ((uint8_t)0x01) ¯MPU_TEX_LEVEL2 ((uint8_t)0x02) ·MPU_REGION_SIZE_32B ((uint8_t)0x04) ¸MPU_REGION_SIZE_64B ((uint8_t)0x05) ¹MPU_REGION_SIZE_128B ((uint8_t)0x06) ºMPU_REGION_SIZE_256B ((uint8_t)0x07) »MPU_REGION_SIZE_512B ((uint8_t)0x08) ¼MPU_REGION_SIZE_1KB ((uint8_t)0x09) ½MPU_REGION_SIZE_2KB ((uint8_t)0x0A) ¾MPU_REGION_SIZE_4KB ((uint8_t)0x0B) ¿MPU_REGION_SIZE_8KB ((uint8_t)0x0C) ÀMPU_REGION_SIZE_16KB ((uint8_t)0x0D) ÁMPU_REGION_SIZE_32KB ((uint8_t)0x0E) ÂMPU_REGION_SIZE_64KB ((uint8_t)0x0F) ÃMPU_REGION_SIZE_128KB ((uint8_t)0x10) ÄMPU_REGION_SIZE_256KB ((uint8_t)0x11) ÅMPU_REGION_SIZE_512KB ((uint8_t)0x12) ÆMPU_REGION_SIZE_1MB ((uint8_t)0x13) ÇMPU_REGION_SIZE_2MB ((uint8_t)0x14) ÈMPU_REGION_SIZE_4MB ((uint8_t)0x15) ÉMPU_REGION_SIZE_8MB ((uint8_t)0x16) ÊMPU_REGION_SIZE_16MB ((uint8_t)0x17) ËMPU_REGION_SIZE_32MB ((uint8_t)0x18) ÌMPU_REGION_SIZE_64MB ((uint8_t)0x19) ÍMPU_REGION_SIZE_128MB ((uint8_t)0x1A) ÎMPU_REGION_SIZE_256MB ((uint8_t)0x1B) ÏMPU_REGION_SIZE_512MB ((uint8_t)0x1C) ÐMPU_REGION_SIZE_1GB ((uint8_t)0x1D) ÑMPU_REGION_SIZE_2GB ((uint8_t)0x1E) ÒMPU_REGION_SIZE_4GB ((uint8_t)0x1F) ÚMPU_REGION_NO_ACCESS ((uint8_t)0x00) ÛMPU_REGION_PRIV_RW ((uint8_t)0x01) ÜMPU_REGION_PRIV_RW_URO ((uint8_t)0x02) ÝMPU_REGION_FULL_ACCESS ((uint8_t)0x03) ÞMPU_REGION_PRIV_RO ((uint8_t)0x05) ßMPU_REGION_PRIV_RO_URO ((uint8_t)0x06) çMPU_REGION_NUMBER0 ((uint8_t)0x00) èMPU_REGION_NUMBER1 ((uint8_t)0x01) éMPU_REGION_NUMBER2 ((uint8_t)0x02) êMPU_REGION_NUMBER3 ((uint8_t)0x03) ëMPU_REGION_NUMBER4 ((uint8_t)0x04) ìMPU_REGION_NUMBER5 ((uint8_t)0x05) íMPU_REGION_NUMBER6 ((uint8_t)0x06) îMPU_REGION_NUMBER7 ((uint8_t)0x07) ðMPU_REGION_NUMBER8 ((uint8_t)0x08) ñMPU_REGION_NUMBER9 ((uint8_t)0x09) òMPU_REGION_NUMBER10 ((uint8_t)0x0A) óMPU_REGION_NUMBER11 ((uint8_t)0x0B) ôMPU_REGION_NUMBER12 ((uint8_t)0x0C) õMPU_REGION_NUMBER13 ((uint8_t)0x0D) öMPU_REGION_NUMBER14 ((uint8_t)0x0E) ÷MPU_REGION_NUMBER15 ((uint8_t)0x0F) CM7_CPUID ((uint32_t)0x00000003) ÕIS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4)) ÛIS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) ÝIS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) ßIS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00) áIS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) åIS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE)) èIS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) ëIS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) îIS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) ñIS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) ôIS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2)) øIS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) || ((TYPE) == MPU_REGION_PRIV_RO_URO)) IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7) || ((NUMBER) == MPU_REGION_NUMBER8) || ((NUMBER) == MPU_REGION_NUMBER9) || ((NUMBER) == MPU_REGION_NUMBER10) || ((NUMBER) == MPU_REGION_NUMBER11) || ((NUMBER) == MPU_REGION_NUMBER12) || ((NUMBER) == MPU_REGION_NUMBER13) || ((NUMBER) == MPU_REGION_NUMBER14) || ((NUMBER) == MPU_REGION_NUMBER15)) IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB)) ¸IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) t i ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_cortex.h stm32h7xx_hal_def.h Ì
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM * Enable : # Number : # BaseAddress Y # Size : # SubRegionDisable : # TypeExtField : #
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AccessPermission : # DisableExec : # IsShareable : # IsCacheable : # IsBufferable : # PMPU_Region_InitTypeDef Æ F ï ð ñ STM32H7xx_HAL_FLASH_EX_H ÍFLASH_TYPEERASE_SECTORS 0x00U ÎFLASH_TYPEERASE_MASSERASE 0x01U ×FLASH_VOLTAGE_RANGE_1 0x00000000U ØFLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 ÙFLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 ÚFLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE ãOB_WRPSTATE_DISABLE 0x00000000U äOB_WRPSTATE_ENABLE 0x00000001U øOPTIONBYTE_WRP 0x01U ùOPTIONBYTE_RDP 0x02U úOPTIONBYTE_USER 0x04U ûOPTIONBYTE_PCROP 0x08U üOPTIONBYTE_BOR 0x10U ýOPTIONBYTE_SECURE_AREA 0x20U OPTIONBYTE_BOOTADD 0x40U OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA | OPTIONBYTE_BOOTADD) §OB_RDP_LEVEL_0 0xAA00U ¨OB_RDP_LEVEL_1 0x5500U ©OB_RDP_LEVEL_2 0xCC00U ²OB_IWDG_SW OB_IWDG1_SW ³OB_IWDG_HW OB_IWDG1_HW »OB_STOP_NO_RST 0x40U ¼OB_STOP_RST 0x00U ÄOB_STDBY_NO_RST 0x80U ÅOB_STDBY_RST 0x00U ÍOB_IWDG_STOP_FREEZE 0x00000000U ÎOB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP ÖOB_IWDG_STDBY_FREEZE 0x00000000U ×OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY ßOB_BOR_LEVEL0 0x00000000U àOB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 áOB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 âOB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) ìOB_BOOTADDR_ITCM_RAM 0x0000U íOB_BOOTADDR_SYSTEM 0x0040U îOB_BOOTADDR_ITCM_FLASH 0x0080U ïOB_BOOTADDR_AXIM_FLASH 0x2000U ðOB_BOOTADDR_DTCM_RAM 0x8000U ñOB_BOOTADDR_SRAM1 0x8004U òOB_BOOTADDR_SRAM2 0x8013U úFLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS ûFLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS üFLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS ýFLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS þFLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS ÿFLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS FLASH_BANK_1 0x01U FLASH_BANK_2 0x02U FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) OB_PCROP_RDP_NOT_ERASE 0x00000000U ¡OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP ÎOB_WRP_SECTOR_0 0x00000001U ÏOB_WRP_SECTOR_1 0x00000002U ÐOB_WRP_SECTOR_2 0x00000004U ÑOB_WRP_SECTOR_3 0x00000008U ÒOB_WRP_SECTOR_4 0x00000010U ÓOB_WRP_SECTOR_5 0x00000020U ÔOB_WRP_SECTOR_6 0x00000040U ÕOB_WRP_SECTOR_7 0x00000080U ÖOB_WRP_SECTOR_ALL 0x000000FFU ßOB_SECURITY_DISABLE 0x00000000U àOB_SECURITY_ENABLE FLASH_OPTSR_SECURITY èOB_ST_RAM_SIZE_2KB 0x00000000U éOB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 êOB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 ëOB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW OB_IWDG1_HW 0x00000000U OB_STOP_RST_D1 0x00000000U OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 ¥OB_STDBY_RST_D1 0x00000000U ¦OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 ÃOB_SWAP_BANK_DISABLE 0x00000000U ÄOB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT ÍOB_IOHSLV_DISABLE 0x00000000U ÎOB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV ùOB_USER_IWDG1_SW 0x0001U úOB_USER_NRST_STOP_D1 0x0002U ûOB_USER_NRST_STDBY_D1 0x0004U üOB_USER_IWDG_STOP 0x0008U ýOB_USER_IWDG_STDBY 0x0010U þOB_USER_ST_RAM_SIZE 0x0020U ÿOB_USER_SECURITY 0x0040U OB_USER_IOHSLV 0x0080U OB_USER_SWAP_BANK 0x0100U ªOB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 | OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE | OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) ºOB_BOOT_ADD0 0x01U »OB_BOOT_ADD1 0x02U ¼OB_BOOT_ADD_BOTH 0x03U ÄOB_SECURE_RDP_NOT_ERASE 0x00000000U ÆOB_SECURE_RDP_ERASE FLASH_SCAR_DMES ÏFLASH_CRC_ADDR 0x00000000U ÐFLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT ÑFLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) ÙFLASH_CRC_BURST_SIZE_4 0x00000000U ÚFLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 ÛFLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 ÜFLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST äFLASH_PROGRAMMING_DELAY_0 0x00000000U åFLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 æFLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 çFLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) __HAL_FLASH_SET_PSIZE(__PSIZE__,__BANK__) (((__BANK__) == FLASH_BANK_1) ? MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) ¬__HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) »__HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) Â__HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || ((RANGE) == FLASH_VOLTAGE_RANGE_2) || ((RANGE) == FLASH_VOLTAGE_RANGE_3) || ((RANGE) == FLASH_VOLTAGE_RANGE_4)) IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) ¡IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) £IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1) || ((LEVEL) == OB_RDP_LEVEL_2)) §IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) ©IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) «IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) ¯IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) ±IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) ´IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) ÅIS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) ÈIS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) ÍIS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || ((CONFIG) == OB_PCROP_RDP_ERASE)) ÐIS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || ((CONFIG) == OB_SECURE_RDP_ERASE)) ÔIS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) ×IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) ÝIS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) áIS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) ãIS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) åIS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) çIS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) éIS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) ìIS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && (((TYPE) & ~OB_USER_ALL) == 0U)) IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || ((VALUE) == OB_BOOT_ADD1) || ((VALUE) == OB_BOOT_ADD_BOTH)) IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || ((VALUE) == FLASH_CRC_SECTORS) || ((VALUE) == FLASH_CRC_BANK)) t k ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_flash_ex.h stm32h7xx_hal_def.h p
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *¨ TypeErase Y # Banks Y # Sector Y # NbSectors Y # VoltageRange Y # PFLASH_EraseInitTypeDef È >*¬D OptionType Y # WRPState Y # WRPSector Y # RDPLevel Y # BORLevel Y # USERType Y # USERConfig Y # Banks Y # PCROPConfig Y # PCROPStartAddr Y #$ PCROPEndAddr Y #( BootConfig Y #, BootAddr0 Y #0 BootAddr1 Y #4 SecureAreaConfig Y #8 SecureAreaStartAddr Y #< SecureAreaEndAddr Y #@ PFLASH_OBProgramInitTypeDef F*Ó TypeCRC Y # BurstSize Y # Bank Y # Sector Y # NbSectors Y # CRCStartAddr Y # CRCEndAddr Y # PFLASH_CRCInitTypeDef ϱ ó ô õ ö STM32H7xx_HAL_FLASH_H \HAL_FLASH_ERROR_NONE 0x00000000U ^HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR _HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR `HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR aHAL_FLASH_ERROR_INC FLASH_FLAG_INCERR cHAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR eHAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR fHAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR gHAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR hHAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR iHAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR kHAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 lHAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 mHAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 nHAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 pHAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 rHAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 sHAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 tHAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 uHAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 vHAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 xHAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2 yHAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 zHAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 {HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 }HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2 HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2
HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR FLASH_TYPEPROGRAM_FLASHWORD 0x01U FLASH_FLAG_BSY FLASH_SR_BSY FLASH_FLAG_WBNE FLASH_SR_WBNE FLASH_FLAG_QW FLASH_SR_QW FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY FLASH_FLAG_EOP FLASH_SR_EOP FLASH_FLAG_WRPERR FLASH_SR_WRPERR FLASH_FLAG_PGSERR FLASH_SR_PGSERR FLASH_FLAG_STRBERR FLASH_SR_STRBERR ¡FLASH_FLAG_INCERR FLASH_SR_INCERR £FLASH_FLAG_OPERR FLASH_SR_OPERR ¥FLASH_FLAG_RDPERR FLASH_SR_RDPERR ¦FLASH_FLAG_RDSERR FLASH_SR_RDSERR §FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR ¨FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR ©FLASH_FLAG_CRCEND FLASH_SR_CRCEND ªFLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR ¬FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE ®FLASH_FLAG_QW_BANK1 FLASH_SR_QW ¯FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY °FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP ±FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR ²FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR ³FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR ´FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR ¶FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR ¸FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR ¹FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR ºFLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR »FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR ¼FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND ½FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR ÀFLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) ÍFLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1) ÒFLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) ÓFLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) ÔFLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) ÕFLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) ÖFLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) ×FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) ØFLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) ÙFLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) ÚFLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) ÜFLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) ÞFLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) ßFLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) àFLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) áFLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) âFLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) ãFLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) æFLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) óFLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2) ÿFLASH_IT_EOP_BANK1 FLASH_CR_EOPIE FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE
FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) ¡FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) ¢FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) ¤FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) ¦FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) §FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) ¨FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) ©FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) ªFLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) «FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) ®FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) ÄFLASH_PSIZE_BYTE 0x00000000U ÅFLASH_PSIZE_HALF_WORD FLASH_CR_PSIZE_0 ÆFLASH_PSIZE_WORD FLASH_CR_PSIZE_1 ÇFLASH_PSIZE_DOUBLE_WORD FLASH_CR_PSIZE ÑFLASH_KEY1 0x45670123U ÒFLASH_KEY2 0xCDEF89ABU ÓFLASH_OPT_KEY1 0x08192A3BU ÔFLASH_OPT_KEY2 0x4C5D6E7FU ÜFLASH_SECTOR_0 0U ÝFLASH_SECTOR_1 1U ÞFLASH_SECTOR_2 2U ßFLASH_SECTOR_3 3U àFLASH_SECTOR_4 4U áFLASH_SECTOR_5 5U âFLASH_SECTOR_6 6U ãFLASH_SECTOR_7 7U ð__HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) ø__HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__)) __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU)) ¢__HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)) Í__HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__)) Ï__HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU)) Ò__HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__)) __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU))) __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)) ³__HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__)) µ__HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU)) ¸__HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)) ÃIS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT)) IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT)) IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG)) IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG)) IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE)) IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END)) ¨IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS)) µIS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U)) ¸IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH)) »IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2)) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_flash.h stm32h7xx_hal_def.h stm32h7xx_hal_flash_ex.h
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM FLASH_PROC_NONE FLASH_PROC_SECTERASE_BANK1 FLASH_PROC_MASSERASE_BANK1 FLASH_PROC_PROGRAM_BANK1 FLASH_PROC_SECTERASE_BANK2 FLASH_PROC_MASSERASE_BANK2 FLASH_PROC_PROGRAM_BANK2 FLASH_PROC_ALLBANK_MASSERASE PFLASH_ProcedureTypeDef Å 7*Ó ProcedureOnGoing S# NbSectorsToErase W# VoltageForErase W# Sector W# Address W# Lock 6 # ErrorCode W# ttY PFLASH_ProcessTypeDef ËMqpFlash ] y pFlash ø ù ú STM32H7xx_HAL_HSEM_H 0__HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) <__HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->C1IER |= (__SEM_MASK__)) H__HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->C1IER &= ~(__SEM_MASK__)) U__HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1MISR) b__HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1ISR) o__HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->C1ICR |= (__SEM_MASK__)) µIS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) ·IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) ¹IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) ¿IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID) p g ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_hsem.h stm32h7xx_hal_def.h Ä
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ü ý þ STM32H7xx_HAL_I2C_EX_H /I2C_ANALOGFILTER_ENABLE 0x00000000U 0I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 8I2C_FMP_NOT_SUPPORTED 0xAAAA0000U 9I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP :I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP ;I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP <I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP =I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP >I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP ?I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP @I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP DI2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || ((FILTER) == I2C_ANALOGFILTER_DISABLE)) IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) t i ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_i2c_ex.h stm32h7xx_hal_def.h Ä
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM STM32H7xx_HAL_I2C_H £HAL_I2C_ERROR_NONE (0x00000000U) ¤HAL_I2C_ERROR_BERR (0x00000001U) ¥HAL_I2C_ERROR_ARLO (0x00000002U) ¦HAL_I2C_ERROR_AF (0x00000004U) §HAL_I2C_ERROR_OVR (0x00000008U) ¨HAL_I2C_ERROR_DMA (0x00000010U) ©HAL_I2C_ERROR_TIMEOUT (0x00000020U) ªHAL_I2C_ERROR_SIZE (0x00000040U) «HAL_I2C_ERROR_DMA_PARAM (0x00000080U) ¯HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) ®I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) ¯I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) °I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) ±I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) ²I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) ·I2C_OTHER_FRAME (0x000000AAU) ¸I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) ÀI2C_ADDRESSINGMODE_7BIT (0x00000001U) ÁI2C_ADDRESSINGMODE_10BIT (0x00000002U) ÉI2C_DUALADDRESS_DISABLE (0x00000000U) ÊI2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN ÒI2C_OA2_NOMASK ((uint8_t)0x00U) ÓI2C_OA2_MASK01 ((uint8_t)0x01U) ÔI2C_OA2_MASK02 ((uint8_t)0x02U) ÕI2C_OA2_MASK03 ((uint8_t)0x03U) ÖI2C_OA2_MASK04 ((uint8_t)0x04U) ×I2C_OA2_MASK05 ((uint8_t)0x05U) ØI2C_OA2_MASK06 ((uint8_t)0x06U) ÙI2C_OA2_MASK07 ((uint8_t)0x07U) áI2C_GENERALCALL_DISABLE (0x00000000U) âI2C_GENERALCALL_ENABLE I2C_CR1_GCEN êI2C_NOSTRETCH_DISABLE (0x00000000U) ëI2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH óI2C_MEMADD_SIZE_8BIT (0x00000001U) ôI2C_MEMADD_SIZE_16BIT (0x00000002U) üI2C_DIRECTION_TRANSMIT (0x00000000U) ýI2C_DIRECTION_RECEIVE (0x00000001U)
I2C_RELOAD_MODE I2C_CR2_RELOAD I2C_AUTOEND_MODE I2C_CR2_AUTOEND I2C_SOFTEND_MODE (0x00000000U) I2C_NO_STARTSTOP (0x00000000U) I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) I2C_IT_ERRI I2C_CR1_ERRIE I2C_IT_TCI I2C_CR1_TCIE I2C_IT_STOPI I2C_CR1_STOPIE I2C_IT_NACKI I2C_CR1_NACKIE ¡I2C_IT_ADDRI I2C_CR1_ADDRIE ¢I2C_IT_RXI I2C_CR1_RXIE £I2C_IT_TXI I2C_CR1_TXIE «I2C_FLAG_TXE I2C_ISR_TXE ¬I2C_FLAG_TXIS I2C_ISR_TXIS I2C_FLAG_RXNE I2C_ISR_RXNE ®I2C_FLAG_ADDR I2C_ISR_ADDR ¯I2C_FLAG_AF I2C_ISR_NACKF °I2C_FLAG_STOPF I2C_ISR_STOPF ±I2C_FLAG_TC I2C_ISR_TC ²I2C_FLAG_TCR I2C_ISR_TCR ³I2C_FLAG_BERR I2C_ISR_BERR ´I2C_FLAG_ARLO I2C_ISR_ARLO µI2C_FLAG_OVR I2C_ISR_OVR ¶I2C_FLAG_PECERR I2C_ISR_PECERR ·I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT ¸I2C_FLAG_ALERT I2C_ISR_ALERT ¹I2C_FLAG_BUSY I2C_ISR_BUSY ºI2C_FLAG_DIR I2C_ISR_DIR Ô__HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) å__HAL_I2C_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) õ__HAL_I2C_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
__HAL_I2C_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) I2C_FLAG_MASK (0x0001FFFFU) __HAL_I2C_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) ´__HAL_I2C_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : ((__HANDLE__)->Instance->ICR = (__FLAG__))) ¼__HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) Â__HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) È__HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) ÎáIS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || ((MODE) == I2C_ADDRESSINGMODE_10BIT)) äIS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) çIS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || ((MASK) == I2C_OA2_MASK01) || ((MASK) == I2C_OA2_MASK02) || ((MASK) == I2C_OA2_MASK03) || ((MASK) == I2C_OA2_MASK04) || ((MASK) == I2C_OA2_MASK05) || ((MASK) == I2C_OA2_MASK06) || ((MASK) == I2C_OA2_MASK07)) ðIS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE)) óIS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE)) öIS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT)) ùIS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || ((MODE) == I2C_AUTOEND_MODE) || ((MODE) == I2C_SOFTEND_MODE)) ýIS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || ((REQUEST) == I2C_GENERATE_START_READ) || ((REQUEST) == I2C_GENERATE_START_WRITE) || ((REQUEST) == I2C_NO_STARTSTOP)) IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) ¡I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) ©I2C_CHECK_FLAG(__ISR__,__FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) «I2C_CHECK_IT_SOURCE(__CR1__,__IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_i2c.h stm32h7xx_hal_def.h stm32h7xx_hal_i2c_ex.h
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *ý Timing Y # OwnAddress1 Y # AddressingMode Y # DualAddressMode Y # OwnAddress2 Y # OwnAddress2Masks Y # GeneralCallMode Y # NoStretchMode Y # PI2C_InitTypeDef à KþHAL_I2C_STATE_RESET HAL_I2C_STATE_READY HAL_I2C_STATE_BUSY $HAL_I2C_STATE_BUSY_TX !HAL_I2C_STATE_BUSY_RX "HAL_I2C_STATE_LISTEN (HAL_I2C_STATE_BUSY_TX_LISTEN )HAL_I2C_STATE_BUSY_RX_LISTEN *HAL_I2C_STATE_ABORT ` PHAL_I2C_StateTypeDef zõHAL_I2C_MODE_NONE HAL_I2C_MODE_MASTER HAL_I2C_MODE_SLAVE HAL_I2C_MODE_MEM @ PHAL_I2C_ModeTypeDef )Û__I2C_HandleTypeDef T Instance [# Init }# pBuffPtr a#$ XferSize I #( XferCount g#* XferOptions m#, PreviousState m#0N¹ú %s%Y %Y " XferISR ¹#4 hdmatx w#8 hdmarx w#< Lock 6 #@ State }#A Mode #B ErrorCode m#D AddrEventCount m#H Devaddress m#L Memaddress m#P "73 ": tI tY ""l t~tõPI2C_HandleTypeDef ü STM32H7xx_HAL_PWR_EX_H gPWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 iPWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 kPWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 mPWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 oPWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 pPWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 sPWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 uPWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 wPWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 yPWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 {PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 |PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) PWR_PIN_POLARITY_HIGH (0x00000000U) PWR_PIN_POLARITY_LOW (0x00000001U) PWR_PIN_NO_PULL (0x00000000U) PWR_PIN_PULL_UP (0x00000001U) PWR_PIN_PULL_DOWN (0x00000002U) £PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 ¤PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 ¦PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 ¨PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 ªPWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 ¬PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 ®PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 | PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) ÇPWR_D1_DOMAIN (0x00000000U) ÉPWR_D2_DOMAIN (0x00000001U) ËPWR_D3_DOMAIN (0x00000002U) ØPWR_CPU_FLAGS (0x00000000U) áPWR_D3_DOMAIN_STOP (0x00000000U) âPWR_D3_DOMAIN_RUN (0x00000800U) ëPWR_LDO_SUPPLY PWR_CR3_LDOEN õPWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS ûPWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 PWR_AVD_MODE_NORMAL (0x00000000U) PWR_AVD_MODE_IT_RISING (0x00010001U) PWR_AVD_MODE_IT_FALLING (0x00010002U) PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) PWR_AVD_MODE_EVENT_RISING (0x00020001U) PWR_AVD_MODE_EVENT_FALLING (0x00020002U) PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) ¢PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) £PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) ¤PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) ¬PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS µPWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) ¶PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL ·PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH ¿PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) ÀPWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL ÁPWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH ÈPWR_EXTI_LINE_AVD EXTI_IMR1_IM16 ï__HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) ý__HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) §__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) ³__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) ¹__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) ¿__HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); } while(0); É__HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); } while(0); Ó__HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) á__HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) ï__HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) ÿIS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || ((DOMAIN) == PWR_D2_DOMAIN) || ((DOMAIN) == PWR_D3_DOMAIN)) IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN)) IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) || ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN6) || ((PIN) == PWR_WAKEUP_PIN1_HIGH) || ((PIN) == PWR_WAKEUP_PIN2_HIGH) || ((PIN) == PWR_WAKEUP_PIN3_HIGH) || ((PIN) == PWR_WAKEUP_PIN4_HIGH) || ((PIN) == PWR_WAKEUP_PIN5_HIGH) || ((PIN) == PWR_WAKEUP_PIN6_HIGH) || ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) || ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) || ((PIN) == PWR_WAKEUP_PIN5_LOW) || ((PIN) == PWR_WAKEUP_PIN6_LOW)) ºIS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || ((POLARITY) == PWR_PIN_POLARITY_LOW)) ¾IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || ((PULL) == PWR_PIN_PULL_UP) || ((PULL) == PWR_PIN_PULL_DOWN)) ÄIS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || ((FLAG) == PWR_WAKEUP_FLAG2) || ((FLAG) == PWR_WAKEUP_FLAG3) || ((FLAG) == PWR_WAKEUP_FLAG4) || ((FLAG) == PWR_WAKEUP_FLAG5) || ((FLAG) == PWR_WAKEUP_FLAG6) || ((FLAG) == PWR_WAKEUP_FLAG_ALL)) ÔIS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3)) ÚIS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) || ((MODE) == PWR_AVD_MODE_IT_FALLING) || ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_NORMAL) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) ãIS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) || ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) æIS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) t i ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_pwr_ex.h stm32h7xx_hal_def.h `
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *ë AVDLevel Y # Mode Y # PPWREx_AVDTypeDef Æ 8*Á WakeUpPin Y # PinPolarity Y # PinPull Y # PPWREx_WakeupPinTypeDef M
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STM32H7xx_HAL_PWR_H HPWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 JPWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 LPWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 NPWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 PPWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 RPWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 TPWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 VPWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 _PWR_PVD_MODE_NORMAL (0x00000000U) `PWR_PVD_MODE_IT_RISING (0x00010001U) aPWR_PVD_MODE_IT_FALLING (0x00010002U) bPWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) cPWR_PVD_MODE_EVENT_RISING (0x00020001U) dPWR_PVD_MODE_EVENT_FALLING (0x00020002U) ePWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) mPWR_MAINREGULATOR_ON (0U) nPWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS vPWR_SLEEPENTRY_WFI (0x01U) wPWR_SLEEPENTRY_WFE (0x02U) PWR_STOPENTRY_WFI (0x01U) PWR_STOPENTRY_WFE (0x02U) PWR_REGULATOR_VOLTAGE_SCALE0 (0U) PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) PWR_FLAG_STOP (0x01U) PWR_FLAG_SB_D1 (0x02U) PWR_FLAG_SB_D2 (0x03U) PWR_FLAG_SB (0x04U) ©PWR_FLAG_PVDO (0x0BU) ªPWR_FLAG_AVDO (0x0CU) «PWR_FLAG_ACTVOSRDY (0x0DU) ¬PWR_FLAG_ACTVOS (0x0EU) PWR_FLAG_BRR (0x0FU) ®PWR_FLAG_VOSRDY (0x10U) ²PWR_FLAG_SCUEN (0x11U) ·PWR_FLAG_USB33RDY (0x13U) ¸PWR_FLAG_TEMPH (0x14U) ¹PWR_FLAG_TEMPL (0x15U) ºPWR_FLAG_VBATH (0x16U) »PWR_FLAG_VBATL (0x17U) ¾PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 ¿PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 ÀPWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 ÁPWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 ÂPWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 ÃPWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 ËPWR_EWUP_MASK (0x0FFF3F3FU) __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { __IO uint32_t tmpreg = 0x00; if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) { MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); } else { CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); } UNUSED(tmpreg); } while(0) ¤__HAL_PWR_GET_FLAG(__FLAG__) (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) : ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) : ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) : ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) : ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) ç__HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) ¨__HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) ¶__HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) Ä__HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) Ò__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) Ø__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) Þ__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) ä__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) ê__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0); ô__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0); þ__HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) ßPWR_EXTI_LINE_PVD EXTI_IMR1_IM16 ñIS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) ûIS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL)) IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_pwr.h stm32h7xx_hal_def.h stm32h7xx_hal_pwr_ex.h ü
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *è PVDLevel Y # Mode Y # PPWR_PVDTypeDef à : STM32H7xx_HAL_TIM_EX_H [TIM_TIM1_ETR_GPIO 0x00000000U \TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 ]TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 ^TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) _TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) `TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) aTIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) bTIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) cTIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 eTIM_TIM8_ETR_GPIO 0x00000000U fTIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 gTIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 hTIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) iTIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) jTIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) kTIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) lTIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) mTIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 oTIM_TIM2_ETR_GPIO 0x00000000U pTIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) qTIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) rTIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) sTIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 tTIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) vTIM_TIM3_ETR_GPIO 0x00000000U wTIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 yTIM_TIM5_ETR_GPIO 0x00000000U zTIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 {TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 |TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 }TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 TIM_TIM23_ETR_GPIO 0x00000000U TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) TIM_TIM24_ETR_GPIO 0x00000000U TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0
TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 TIM_BREAKINPUT_BRK 0x00000001U TIM_BREAKINPUT_BRK2 0x00000002U TIM_BREAKINPUTSOURCE_BKIN 0x00000001U TIM_BREAKINPUTSOURCE_COMP1 0x00000002U TIM_BREAKINPUTSOURCE_COMP2 0x00000004U TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U ¤TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U ¥TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U ®TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U ·TIM_TIM1_TI1_GPIO 0x00000000U ¸TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 ºTIM_TIM8_TI1_GPIO 0x00000000U »TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 ½TIM_TIM2_TI4_GPIO 0x00000000U ¾TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 ¿TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 ÀTIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) ÂTIM_TIM3_TI1_GPIO 0x00000000U ÃTIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 ÄTIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 ÅTIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) ÇTIM_TIM5_TI1_GPIO 0x00000000U ÈTIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 ÉTIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 ËTIM_TIM12_TI1_GPIO 0x00000000U ÌTIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 ÎTIM_TIM15_TI1_GPIO 0x00000000U ÏTIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 ÐTIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 ÑTIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) ÒTIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) ÓTIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) ÔTIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) ÖTIM_TIM15_TI2_GPIO 0x00000000U ×TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) ØTIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) ÙTIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) ÛTIM_TIM16_TI1_GPIO 0x00000000U ÜTIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 ÝTIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 ÞTIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) àTIM_TIM17_TI1_GPIO 0x00000000U áTIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 âTIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 ãTIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) åTIM_TIM23_TI4_GPIO 0x00000000U æTIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 çTIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 èTIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) êTIM_TIM24_TI1_GPIO 0x00000000U ëTIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 ìTIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 íTIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) || ((__TISEL__) == TIM_TIM1_TI1_COMP1) || ((__TISEL__) == TIM_TIM8_TI1_GPIO) || ((__TISEL__) == TIM_TIM8_TI1_COMP2) || ((__TISEL__) == TIM_TIM2_TI4_GPIO) || ((__TISEL__) == TIM_TIM2_TI4_COMP1) || ((__TISEL__) == TIM_TIM2_TI4_COMP2) || ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) || ((__TISEL__) == TIM_TIM3_TI1_GPIO) || ((__TISEL__) == TIM_TIM3_TI1_COMP1) || ((__TISEL__) == TIM_TIM3_TI1_COMP2) || ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) || ((__TISEL__) == TIM_TIM5_TI1_GPIO) || ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) || ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) || ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) || ((__TISEL__) == TIM_TIM12_TI1_GPIO) || ((__TISEL__) == TIM_TIM15_TI1_GPIO) || ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) || ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) || ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) || ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) || ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) || ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) || ((__TISEL__) == TIM_TIM15_TI2_GPIO) || ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) || ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) || ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) || ((__TISEL__) == TIM_TIM16_TI1_GPIO) || ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) || ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) || ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) || ((__TISEL__) == TIM_TIM17_TI1_GPIO) || ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) || ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) || ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) || ((__TISEL__) == TIM_TIM23_TI4_GPIO) || ((__TISEL__) == TIM_TIM23_TI4_COMP1) || ((__TISEL__) == TIM_TIM23_TI4_COMP2) || ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) || ((__TISEL__) == TIM_TIM24_TI1_GPIO) || ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) || ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) || ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC)) ÀIS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) || ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) || ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) || ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) || ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) || ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) || ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) || ((__RREMAP__) == TIM_TIM1_ETR_COMP1) || ((__RREMAP__) == TIM_TIM1_ETR_COMP2) || ((__RREMAP__) == TIM_TIM8_ETR_GPIO) || ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) || ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) || ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) || ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) || ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) || ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) || ((__RREMAP__) == TIM_TIM8_ETR_COMP1) || ((__RREMAP__) == TIM_TIM8_ETR_COMP2) || ((__RREMAP__) == TIM_TIM2_ETR_GPIO) || ((__RREMAP__) == TIM_TIM2_ETR_COMP1) || ((__RREMAP__) == TIM_TIM2_ETR_COMP2) || ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) || ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) || ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) || ((__RREMAP__) == TIM_TIM3_ETR_GPIO) || ((__RREMAP__) == TIM_TIM3_ETR_COMP1) || ((__RREMAP__) == TIM_TIM5_ETR_GPIO) || ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) || ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) || ((__RREMAP__) == TIM_TIM23_ETR_GPIO) || ((__RREMAP__) == TIM_TIM23_ETR_COMP1) || ((__RREMAP__) == TIM_TIM23_ETR_COMP2) || ((__RREMAP__) == TIM_TIM24_ETR_GPIO) || ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) || ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) || ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) || ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB)) t i ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_tim_ex.h stm32h7xx_hal_def.h
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *¤ IC1Polarity Y # IC1Prescaler Y # IC1Filter Y # Commutation_Delay Y # PTIM_HallSensor_InitTypeDef Æ <*ý Source Y # Enable Y # Polarity Y # PTIMEx_BreakInputConfigTypeDef FK STM32H7xx_HAL_TIM_H ËTIM_CLEARINPUTSOURCE_NONE 0x00000000U ÌTIM_CLEARINPUTSOURCE_ETR 0x00000001U ÔTIM_DMABASE_CR1 0x00000000U ÕTIM_DMABASE_CR2 0x00000001U ÖTIM_DMABASE_SMCR 0x00000002U ×TIM_DMABASE_DIER 0x00000003U ØTIM_DMABASE_SR 0x00000004U ÙTIM_DMABASE_EGR 0x00000005U ÚTIM_DMABASE_CCMR1 0x00000006U ÛTIM_DMABASE_CCMR2 0x00000007U ÜTIM_DMABASE_CCER 0x00000008U ÝTIM_DMABASE_CNT 0x00000009U ÞTIM_DMABASE_PSC 0x0000000AU ßTIM_DMABASE_ARR 0x0000000BU àTIM_DMABASE_RCR 0x0000000CU áTIM_DMABASE_CCR1 0x0000000DU âTIM_DMABASE_CCR2 0x0000000EU ãTIM_DMABASE_CCR3 0x0000000FU äTIM_DMABASE_CCR4 0x00000010U åTIM_DMABASE_BDTR 0x00000011U æTIM_DMABASE_DCR 0x00000012U çTIM_DMABASE_DMAR 0x00000013U èTIM_DMABASE_CCMR3 0x00000015U éTIM_DMABASE_CCR5 0x00000016U êTIM_DMABASE_CCR6 0x00000017U ìTIM_DMABASE_AF1 0x00000018U íTIM_DMABASE_AF2 0x00000019U ïTIM_DMABASE_TISEL 0x0000001AU ÷TIM_EVENTSOURCE_UPDATE TIM_EGR_UG øTIM_EVENTSOURCE_CC1 TIM_EGR_CC1G ùTIM_EVENTSOURCE_CC2 TIM_EGR_CC2G úTIM_EVENTSOURCE_CC3 TIM_EGR_CC3G ûTIM_EVENTSOURCE_CC4 TIM_EGR_CC4G üTIM_EVENTSOURCE_COM TIM_EGR_COMG ýTIM_EVENTSOURCE_TRIGGER TIM_EGR_TG þTIM_EVENTSOURCE_BREAK TIM_EGR_BG ÿTIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP TIM_ETRPOLARITY_NONINVERTED 0x00000000U TIM_ETRPRESCALER_DIV1 0x00000000U TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS ¥TIM_COUNTERMODE_UP 0x00000000U ¦TIM_COUNTERMODE_DOWN TIM_CR1_DIR §TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 ¨TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 ©TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS ±TIM_UIFREMAP_DISABLE 0x00000000U ²TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP ºTIM_CLOCKDIVISION_DIV1 0x00000000U »TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 ¼TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 ÄTIM_OUTPUTSTATE_DISABLE 0x00000000U ÅTIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E ÍTIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U ÎTIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE ×TIM_OCFAST_DISABLE 0x00000000U ØTIM_OCFAST_ENABLE TIM_CCMR1_OC1FE àTIM_OUTPUTNSTATE_DISABLE 0x00000000U áTIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE éTIM_OCPOLARITY_HIGH 0x00000000U êTIM_OCPOLARITY_LOW TIM_CCER_CC1P òTIM_OCNPOLARITY_HIGH 0x00000000U óTIM_OCNPOLARITY_LOW TIM_CCER_CC1NP ûTIM_OCIDLESTATE_SET TIM_CR2_OIS1 üTIM_OCIDLESTATE_RESET 0x00000000U TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
TIM_OCNIDLESTATE_RESET 0x00000000U TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 ¡TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 ¢TIM_ICSELECTION_TRC TIM_CCMR1_CC1S ªTIM_ICPSC_DIV1 0x00000000U «TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 ¬TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC µTIM_OPMODE_SINGLE TIM_CR1_OPM ¶TIM_OPMODE_REPETITIVE 0x00000000U ¾TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 ¿TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 ÀTIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) ÈTIM_IT_UPDATE TIM_DIER_UIE ÉTIM_IT_CC1 TIM_DIER_CC1IE ÊTIM_IT_CC2 TIM_DIER_CC2IE ËTIM_IT_CC3 TIM_DIER_CC3IE ÌTIM_IT_CC4 TIM_DIER_CC4IE ÍTIM_IT_COM TIM_DIER_COMIE ÎTIM_IT_TRIGGER TIM_DIER_TIE ÏTIM_IT_BREAK TIM_DIER_BIE ×TIM_COMMUTATION_TRGI TIM_CR2_CCUS ØTIM_COMMUTATION_SOFTWARE 0x00000000U àTIM_DMA_UPDATE TIM_DIER_UDE áTIM_DMA_CC1 TIM_DIER_CC1DE âTIM_DMA_CC2 TIM_DIER_CC2DE ãTIM_DMA_CC3 TIM_DIER_CC3DE äTIM_DMA_CC4 TIM_DIER_CC4DE åTIM_DMA_COM TIM_DIER_COMDE æTIM_DMA_TRIGGER TIM_DIER_TDE îTIM_CCDMAREQUEST_CC 0x00000000U ïTIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS ÷TIM_FLAG_UPDATE TIM_SR_UIF øTIM_FLAG_CC1 TIM_SR_CC1IF ùTIM_FLAG_CC2 TIM_SR_CC2IF úTIM_FLAG_CC3 TIM_SR_CC3IF ûTIM_FLAG_CC4 TIM_SR_CC4IF üTIM_FLAG_CC5 TIM_SR_CC5IF ýTIM_FLAG_CC6 TIM_SR_CC6IF þTIM_FLAG_COM TIM_SR_COMIF ÿTIM_FLAG_TRIGGER TIM_SR_TIF TIM_FLAG_BREAK TIM_SR_BIF TIM_FLAG_BREAK2 TIM_SR_B2IF TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF TIM_FLAG_CC1OF TIM_SR_CC1OF TIM_FLAG_CC2OF TIM_SR_CC2OF
TIM_FLAG_CC3OF TIM_SR_CC3OF TIM_FLAG_CC4OF TIM_SR_CC4OF TIM_CHANNEL_1 0x00000000U TIM_CHANNEL_2 0x00000004U TIM_CHANNEL_3 0x00000008U TIM_CHANNEL_4 0x0000000CU TIM_CHANNEL_5 0x00000010U TIM_CHANNEL_6 0x00000014U TIM_CHANNEL_ALL 0x0000003CU TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 ¡TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 ¢TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 £TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 ¤TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 ¥TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 ¦TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 §TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 ¨TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 ©TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 ªTIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 ²TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED ³TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED ´TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING µTIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING ¶TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE ¾TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 ¿TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 ÀTIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 ÁTIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 ÉTIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED ÊTIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED ÒTIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 ÓTIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 ÔTIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 ÕTIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 ÝTIM_OSSR_ENABLE TIM_BDTR_OSSR ÞTIM_OSSR_DISABLE 0x00000000U æTIM_OSSI_ENABLE TIM_BDTR_OSSI çTIM_OSSI_DISABLE 0x00000000U îTIM_LOCKLEVEL_OFF 0x00000000U ïTIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 ðTIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 ñTIM_LOCKLEVEL_3 TIM_BDTR_LOCK ùTIM_BREAK_ENABLE TIM_BDTR_BKE úTIM_BREAK_DISABLE 0x00000000U TIM_BREAKPOLARITY_LOW 0x00000000U TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP TIM_BREAK2_DISABLE 0x00000000U TIM_BREAK2_ENABLE TIM_BDTR_BK2E TIM_BREAK2POLARITY_LOW 0x00000000U TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P ³TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U ´TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE ¼TIM_GROUPCH5_NONE 0x00000000U ½TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 ¾TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 ¿TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 ÇTIM_TRGO_RESET 0x00000000U ÈTIM_TRGO_ENABLE TIM_CR2_MMS_0 ÉTIM_TRGO_UPDATE TIM_CR2_MMS_1 ÊTIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) ËTIM_TRGO_OC1REF TIM_CR2_MMS_2 ÌTIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) ÍTIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) ÎTIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) ÖTIM_TRGO2_RESET 0x00000000U ×TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 ØTIM_TRGO2_UPDATE TIM_CR2_MMS2_1 ÙTIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) ÚTIM_TRGO2_OC1REF TIM_CR2_MMS2_2 ÛTIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) ÜTIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) ÝTIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) ÞTIM_TRGO2_OC5REF TIM_CR2_MMS2_3 ßTIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) àTIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) áTIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) âTIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) ãTIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) äTIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) åTIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) íTIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM îTIM_MASTERSLAVEMODE_DISABLE 0x00000000U öTIM_SLAVEMODE_DISABLE 0x00000000U ÷TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 øTIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) ùTIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) úTIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) ûTIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 TIM_OCMODE_TIMING 0x00000000U TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M TIM_TS_ITR0 0x00000000U TIM_TS_ITR1 TIM_SMCR_TS_0 TIM_TS_ITR2 TIM_SMCR_TS_1 TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) TIM_TS_ITR4 (TIM_SMCR_TS_3) TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) ¡TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) ¢TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) £TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) ¤TIM_TS_ITR12 (TIM_SMCR_TS_4) ¥TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) ¦TIM_TS_TI1F_ED TIM_SMCR_TS_2 §TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) ¨TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) ©TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) ªTIM_TS_NONE 0x0000FFFFU ²TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED ³TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED ´TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING µTIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING ¶TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE ¾TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 ¿TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 ÀTIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 ÁTIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 ÉTIM_TI1SELECTION_CH1 0x00000000U ÊTIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S ÒTIM_DMABURSTLENGTH_1TRANSFER 0x00000000U ÓTIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U ÔTIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U ÕTIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U ÖTIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U ×TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U ØTIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U ÙTIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U ÚTIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U ÛTIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U ÜTIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U ÝTIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U ÞTIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U ßTIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U àTIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U áTIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U âTIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U ãTIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U ëTIM_DMA_ID_UPDATE ((uint16_t) 0x0000) ìTIM_DMA_ID_CC1 ((uint16_t) 0x0001) íTIM_DMA_ID_CC2 ((uint16_t) 0x0002) îTIM_DMA_ID_CC3 ((uint16_t) 0x0003) ïTIM_DMA_ID_CC4 ((uint16_t) 0x0004) ðTIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) ñTIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) ùTIM_CCx_ENABLE 0x00000001U úTIM_CCx_DISABLE 0x00000000U ûTIM_CCxN_ENABLE 0x00000004U üTIM_CCxN_DISABLE 0x00000000U TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL ¸ __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { (__HANDLE__)->State = HAL_TIM_STATE_RESET; (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; } while(0) Í __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) Ô __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) Û __HAL_TIM_DISABLE(__HANDLE__) do { if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); } } } while(0) í __HAL_TIM_MOE_DISABLE(__HANDLE__) do { if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); } } } while(0) þ __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
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__HAL_TIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
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__HAL_TIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
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__HAL_TIM_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) ¼
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__HAL_TIM_DISABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) Ô
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__HAL_TIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) ì
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__HAL_TIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) ý
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__HAL_TIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) __HAL_TIM_CLEAR_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) ¨ __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) ± __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) ¹ __HAL_TIM_SET_PRESCALER(__HANDLE__,__PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) Ä __HAL_TIM_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) Ë __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) Ó __HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0) Þ __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) ê __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0) ù __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) __HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0) ¢ __HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) ¶ __HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) Ë __HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) : ((__HANDLE__)->Instance->CCR6)) à __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) : ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) õ __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) : ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) __HAL_TIM_ENABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) : ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) § __HAL_TIM_DISABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) : ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) · __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) Ä __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) Õ __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0) ã __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__,__CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) ñ TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) ò TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) ü IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) ÿ IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR) || ((__BASE__) == TIM_DMABASE_CCMR3) || ((__BASE__) == TIM_DMABASE_CCR5) || ((__BASE__) == TIM_DMABASE_CCR6) || ((__BASE__) == TIM_DMABASE_AF1) || ((__BASE__) == TIM_DMABASE_AF2) || ((__BASE__) == TIM_DMABASE_TISEL)) IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) ¡IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || ((__MODE__) == TIM_UIFREMAP_ENABLE)) ¤IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) ¨IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) «IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE)) ®IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW)) ±IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) ´IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || ((__STATE__) == TIM_OCIDLESTATE_RESET)) ·IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || ((__STATE__) == TIM_OCNIDLESTATE_RESET)) ºIS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) ½IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) ÁIS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC)) ÅIS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8)) ÊIS_TIM_CCX_CHANNEL(__INSTANCE__,__CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && ((__CHANNEL__) != (TIM_CHANNEL_5)) && ((__CHANNEL__) != (TIM_CHANNEL_6))) ÎIS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE)) ÑIS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12)) ÕIS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) ×IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || ((__CHANNEL__) == TIM_CHANNEL_5) || ((__CHANNEL__) == TIM_CHANNEL_6) || ((__CHANNEL__) == TIM_CHANNEL_ALL)) ßIS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2)) âIS_TIM_PERIOD(__HANDLE__,__PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) æIS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3)) êIS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) õIS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) ûIS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE)) IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE)) IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3)) IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE)) IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) ¥IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || ((__STATE__) == TIM_BREAK2_DISABLE)) ¨IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) ±IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) ´IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) ¶IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF)) ¿IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || ((__SOURCE__) == TIM_TRGO2_ENABLE) || ((__SOURCE__) == TIM_TRGO2_UPDATE) || ((__SOURCE__) == TIM_TRGO2_OC1) || ((__SOURCE__) == TIM_TRGO2_OC1REF) || ((__SOURCE__) == TIM_TRGO2_OC2REF) || ((__SOURCE__) == TIM_TRGO2_OC3REF) || ((__SOURCE__) == TIM_TRGO2_OC3REF) || ((__SOURCE__) == TIM_TRGO2_OC4REF) || ((__SOURCE__) == TIM_TRGO2_OC5REF) || ((__SOURCE__) == TIM_TRGO2_OC6REF) || ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) ÑIS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) ÔIS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || ((__MODE__) == TIM_SLAVEMODE_RESET) || ((__MODE__) == TIM_SLAVEMODE_GATED) || ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) ÛIS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2) || ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) âIS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) ëIS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR12) || ((__SELECTION__) == TIM_TS_ITR13) || ((__SELECTION__) == TIM_TS_TI1F_ED) || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF)) ûIS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR12) || ((__SELECTION__) == TIM_TS_ITR13) || ((__SELECTION__) == TIM_TS_NONE)) IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) «IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) ¯IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) ±IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) ¶IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) ¹TIM_SET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__,__ICPSC__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) ¿TIM_RESET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) ÅTIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) ËTIM_RESET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) ÑTIM_CHANNEL_STATE_GET(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] : ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] : ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] : (__HANDLE__)->ChannelState[5]) ÙTIM_CHANNEL_STATE_SET(__HANDLE__,__CHANNEL__,__CHANNEL_STATE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) áTIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__) do { (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); } while(0) ðTIM_CHANNEL_N_STATE_GET(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] : (__HANDLE__)->ChannelNState[3]) öTIM_CHANNEL_N_STATE_SET(__HANDLE__,__CHANNEL__,__CHANNEL_STATE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) üTIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__) do { (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); } while(0) ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_tim.h stm32h7xx_hal_def.h stm32h7xx_hal_tim_ex.h ü
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *Í Prescaler Y # CounterMode Y # Period Y # ClockDivision Y # RepetitionCounter Y # AutoReloadPreload Y # PTIM_Base_InitTypeDef à J*õ OCMode Y # Pulse Y # OCPolarity Y # OCNPolarity Y # OCFastMode Y # OCIdleState Y # OCNIdleState Y # PTIM_OC_InitTypeDef ij*Â$ OCMode Y # Pulse Y # OCPolarity Y # OCNPolarity Y # OCIdleState Y # OCNIdleState Y # ICPolarity Y # ICSelection Y # ICFilter Y # PTIM_OnePulse_InitTypeDef *¸ ICPolarity Y # ICSelection Y # ICPrescaler Y # ICFilter Y # PTIM_IC_InitTypeDef ã *$ EncoderMode Y # IC1Polarity Y # IC1Selection Y # IC1Prescaler Y # IC1Filter Y # IC2Polarity Y # IC2Selection Y # IC2Prescaler Y # IC2Filter Y # PTIM_Encoder_InitTypeDef SÁ* ClockSource Y # ClockPolarity Y # ClockPrescaler Y # ClockFilter Y # PTIM_ClockConfigTypeDef 5Ð*½
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ClearInputState Y # ClearInputSource Y # ClearInputPolarity Y # ClearInputPrescaler Y # ClearInputFilter Y # PTIM_ClearInputConfigTypeDef ²â*º MasterOutputTrigger Y # MasterOutputTrigger2 Y # MasterSlaveMode Y # PTIM_MasterConfigTypeDef aö*Ò SlaveMode Y # InputTrigger Y # TriggerPolarity Y # TriggerPrescaler Y # TriggerFilter Y # PTIM_SlaveConfigTypeDef Ú*ê, OffStateRunMode Y # OffStateIDLEMode Y # LockLevel Y # DeadTime Y # BreakState Y # BreakPolarity Y # BreakFilter Y # Break2State Y # Break2Polarity Y # Break2Filter Y #$ AutomaticOutput Y #( PTIM_BreakDeadTimeConfigTypeDef q¯HAL_TIM_STATE_RESET HAL_TIM_STATE_READY HAL_TIM_STATE_BUSY HAL_TIM_STATE_TIMEOUT HAL_TIM_STATE_ERROR PHAL_TIM_StateTypeDef »HAL_TIM_CHANNEL_STATE_RESET HAL_TIM_CHANNEL_STATE_READY HAL_TIM_CHANNEL_STATE_BUSY PHAL_TIM_ChannelStateTypeDef 'ÅHAL_DMA_BURST_STATE_RESET HAL_DMA_BURST_STATE_READY HAL_DMA_BURST_STATE_BUSY PHAL_TIM_DMABurstStateTypeDef ¬ÏûHAL_TIM_ACTIVE_CHANNEL_1 HAL_TIM_ACTIVE_CHANNEL_2 HAL_TIM_ACTIVE_CHANNEL_3 HAL_TIM_ACTIVE_CHANNEL_4 HAL_TIM_ACTIVE_CHANNEL_5 HAL_TIM_ACTIVE_CHANNEL_6 HAL_TIM_ACTIVE_CHANNEL_CLEARED PHAL_TIM_ActiveChannel , Ý*ÉL Instance É
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# Init M# Channel û # ÑÏ
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hdma H
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# Lock 6 #< State Õ
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#=Ù
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ChannelState x
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#>Ù
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ChannelNState
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#D DMABurstState Ý
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#H "'G "l t
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tt PTIM_HandleTypeDef
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STM32H7xx_HAL_UART_EX_H GUART_WORDLENGTH_7B USART_CR1_M1 HUART_WORDLENGTH_8B 0x00000000U IUART_WORDLENGTH_9B USART_CR1_M0 QUART_ADDRESS_DETECT_4B 0x00000000U RUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 [UART_FIFOMODE_DISABLE 0x00000000U \UART_FIFOMODE_ENABLE USART_CR1_FIFOEN eUART_TXFIFO_THRESHOLD_1_8 0x00000000U fUART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 gUART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 hUART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) iUART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 jUART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) sUART_RXFIFO_THRESHOLD_1_8 0x00000000U tUART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 uUART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 vUART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) wUART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 xUART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) üUART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_D2PCLK2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; break; case RCC_USART1CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_USART1CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_D2PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; break; case RCC_USART2CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_USART2CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART3) { switch(__HAL_RCC_GET_USART3_SOURCE()) { case RCC_USART3CLKSOURCE_D2PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; break; case RCC_USART3CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_USART3CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_USART3CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART3CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_USART3CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == UART4) { switch(__HAL_RCC_GET_UART4_SOURCE()) { case RCC_UART4CLKSOURCE_D2PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; break; case RCC_UART4CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_UART4CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_UART4CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART4CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_UART4CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if ((__HANDLE__)->Instance == UART5) { switch(__HAL_RCC_GET_UART5_SOURCE()) { case RCC_UART5CLKSOURCE_D2PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; break; case RCC_UART5CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_UART5CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_UART5CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART5CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_UART5CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART6) { switch(__HAL_RCC_GET_USART6_SOURCE()) { case RCC_USART6CLKSOURCE_D2PCLK2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; break; case RCC_USART6CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_USART6CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_USART6CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART6CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_USART6CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == UART7) { switch(__HAL_RCC_GET_UART7_SOURCE()) { case RCC_UART7CLKSOURCE_D2PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; break; case RCC_UART7CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_UART7CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_UART7CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART7CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_UART7CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == UART8) { switch(__HAL_RCC_GET_UART8_SOURCE()) { case RCC_UART8CLKSOURCE_D2PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; break; case RCC_UART8CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_UART8CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_UART8CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART8CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_UART8CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == LPUART1) { switch(__HAL_RCC_GET_LPUART1_SOURCE()) { case RCC_LPUART1CLKSOURCE_D3PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; break; case RCC_LPUART1CLKSOURCE_PLL2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; break; case RCC_LPUART1CLKSOURCE_PLL3: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; break; case RCC_LPUART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_LPUART1CLKSOURCE_CSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; break; case RCC_LPUART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; } } while(0U) UART_MASK_COMPUTATION(__HANDLE__) do { if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x01FFU ; } else { (__HANDLE__)->Mask = 0x00FFU ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x00FFU ; } else { (__HANDLE__)->Mask = 0x007FU ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x007FU ; } else { (__HANDLE__)->Mask = 0x003FU ; } } else { (__HANDLE__)->Mask = 0x0000U; } } while(0U) ¯IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || ((__LENGTH__) == UART_WORDLENGTH_8B) || ((__LENGTH__) == UART_WORDLENGTH_9B)) ¸IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) ÀIS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) ÌIS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) t j ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_uart_ex.h stm32h7xx_hal_def.h $
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM * WakeUpEvent Y # AddressLength I # Address : # PUART_WakeUpTypeDef Ç 9 STM32H7xx_HAL_UART_H ÒHAL_UART_STATE_RESET 0x00000000U ÔHAL_UART_STATE_READY 0x00000020U ÖHAL_UART_STATE_BUSY 0x00000024U ØHAL_UART_STATE_BUSY_TX 0x00000021U ÚHAL_UART_STATE_BUSY_RX 0x00000022U ÜHAL_UART_STATE_BUSY_TX_RX 0x00000023U ßHAL_UART_STATE_TIMEOUT 0x000000A0U áHAL_UART_STATE_ERROR 0x000000E0U êHAL_UART_ERROR_NONE (0x00000000U) ëHAL_UART_ERROR_PE (0x00000001U) ìHAL_UART_ERROR_NE (0x00000002U) íHAL_UART_ERROR_FE (0x00000004U) îHAL_UART_ERROR_ORE (0x00000008U) ïHAL_UART_ERROR_DMA (0x00000010U) ðHAL_UART_ERROR_RTO (0x00000020U) üUART_STOPBITS_0_5 USART_CR2_STOP_0 ýUART_STOPBITS_1 0x00000000U þUART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) ÿUART_STOPBITS_2 USART_CR2_STOP_1 UART_PARITY_NONE 0x00000000U UART_PARITY_EVEN USART_CR1_PCE UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) UART_HWCONTROL_NONE 0x00000000U UART_HWCONTROL_RTS USART_CR3_RTSE UART_HWCONTROL_CTS USART_CR3_CTSE UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) UART_MODE_RX USART_CR1_RE UART_MODE_TX USART_CR1_TE UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) ¦UART_STATE_DISABLE 0x00000000U §UART_STATE_ENABLE USART_CR1_UE ¯UART_OVERSAMPLING_16 0x00000000U °UART_OVERSAMPLING_8 USART_CR1_OVER8 ¸UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U ¹UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT ÁUART_PRESCALER_DIV1 0x00000000U ÂUART_PRESCALER_DIV2 0x00000001U ÃUART_PRESCALER_DIV4 0x00000002U ÄUART_PRESCALER_DIV6 0x00000003U ÅUART_PRESCALER_DIV8 0x00000004U ÆUART_PRESCALER_DIV10 0x00000005U ÇUART_PRESCALER_DIV12 0x00000006U ÈUART_PRESCALER_DIV16 0x00000007U ÉUART_PRESCALER_DIV32 0x00000008U ÊUART_PRESCALER_DIV64 0x00000009U ËUART_PRESCALER_DIV128 0x0000000AU ÌUART_PRESCALER_DIV256 0x0000000BU ÔUART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U ÖUART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 ØUART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 ÚUART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE ãUART_RECEIVER_TIMEOUT_DISABLE 0x00000000U äUART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN ìUART_LIN_DISABLE 0x00000000U íUART_LIN_ENABLE USART_CR2_LINEN õUART_LINBREAKDETECTLENGTH_10B 0x00000000U öUART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL þUART_DMA_TX_DISABLE 0x00000000U ÿUART_DMA_TX_ENABLE USART_CR3_DMAT UART_DMA_RX_DISABLE 0x00000000U UART_DMA_RX_ENABLE USART_CR3_DMAR UART_HALF_DUPLEX_DISABLE 0x00000000U UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL UART_WAKEUPMETHOD_IDLELINE 0x00000000U UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE ¢UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ £UART_SENDBREAK_REQUEST USART_RQR_SBKRQ ¤UART_MUTE_MODE_REQUEST USART_RQR_MMRQ ¥UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ ¦UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ ®UART_ADVFEATURE_NO_INIT 0x00000000U ¯UART_ADVFEATURE_TXINVERT_INIT 0x00000001U °UART_ADVFEATURE_RXINVERT_INIT 0x00000002U ±UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U ²UART_ADVFEATURE_SWAP_INIT 0x00000008U ³UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U ´UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U µUART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U ¶UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U ¾UART_ADVFEATURE_TXINV_DISABLE 0x00000000U ¿UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV ÇUART_ADVFEATURE_RXINV_DISABLE 0x00000000U ÈUART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV ÐUART_ADVFEATURE_DATAINV_DISABLE 0x00000000U ÑUART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV ÙUART_ADVFEATURE_SWAP_DISABLE 0x00000000U ÚUART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP âUART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U ãUART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS ëUART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U ìUART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN ôUART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U õUART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE ýUART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U ÿUART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME UART_CR2_ADDRESS_LSB_POS 24U ¢UART_WAKEUP_ON_ADDRESS 0x00000000U £UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 ¤UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS UART_DE_POLARITY_HIGH 0x00000000U ®UART_DE_POLARITY_LOW USART_CR3_DEP ¶UART_CR1_DEAT_ADDRESS_LSB_POS 21U ¿UART_CR1_DEDT_ADDRESS_LSB_POS 16U ÈUART_IT_MASK 0x001FU ÐHAL_UART_TIMEOUT_VALUE 0x1FFFFFFU ÚUART_FLAG_TXFT USART_ISR_TXFT ÛUART_FLAG_RXFT USART_ISR_RXFT ÜUART_FLAG_RXFF USART_ISR_RXFF ÝUART_FLAG_TXFE USART_ISR_TXFE ÞUART_FLAG_REACK USART_ISR_REACK ßUART_FLAG_TEACK USART_ISR_TEACK àUART_FLAG_WUF USART_ISR_WUF áUART_FLAG_RWU USART_ISR_RWU âUART_FLAG_SBKF USART_ISR_SBKF ãUART_FLAG_CMF USART_ISR_CMF äUART_FLAG_BUSY USART_ISR_BUSY åUART_FLAG_ABRF USART_ISR_ABRF æUART_FLAG_ABRE USART_ISR_ABRE çUART_FLAG_RTOF USART_ISR_RTOF èUART_FLAG_CTS USART_ISR_CTS éUART_FLAG_CTSIF USART_ISR_CTSIF êUART_FLAG_LBDF USART_ISR_LBDF ëUART_FLAG_TXE USART_ISR_TXE_TXFNF ìUART_FLAG_TXFNF USART_ISR_TXE_TXFNF íUART_FLAG_TC USART_ISR_TC îUART_FLAG_RXNE USART_ISR_RXNE_RXFNE ïUART_FLAG_RXFNE USART_ISR_RXNE_RXFNE ðUART_FLAG_IDLE USART_ISR_IDLE ñUART_FLAG_ORE USART_ISR_ORE òUART_FLAG_NE USART_ISR_NE óUART_FLAG_FE USART_ISR_FE ôUART_FLAG_PE USART_ISR_PE UART_IT_PE 0x0028U UART_IT_TXE 0x0727U UART_IT_TXFNF 0x0727U UART_IT_TC 0x0626U UART_IT_RXNE 0x0525U UART_IT_RXFNE 0x0525U UART_IT_IDLE 0x0424U UART_IT_LBD 0x0846U UART_IT_CTS 0x096AU UART_IT_CM 0x112EU UART_IT_WUF 0x1476U UART_IT_RXFF 0x183FU UART_IT_TXFE 0x173EU UART_IT_RXFT 0x1A7CU UART_IT_TXFT 0x1B77U UART_IT_RTO 0x0B3AU UART_IT_ERR 0x0060U UART_IT_ORE 0x0300U UART_IT_NE 0x0200U UART_IT_FE 0x0100U ¨UART_CLEAR_PEF USART_ICR_PECF ©UART_CLEAR_FEF USART_ICR_FECF ªUART_CLEAR_NEF USART_ICR_NECF «UART_CLEAR_OREF USART_ICR_ORECF ¬UART_CLEAR_IDLEF USART_ICR_IDLECF UART_CLEAR_TXFECF USART_ICR_TXFECF ®UART_CLEAR_TCF USART_ICR_TCCF ¯UART_CLEAR_LBDF USART_ICR_LBDCF °UART_CLEAR_CTSF USART_ICR_CTSCF ±UART_CLEAR_CMF USART_ICR_CMCF ²UART_CLEAR_WUF USART_ICR_WUCF ³UART_CLEAR_RTOF USART_ICR_RTOCF »HAL_UART_RECEPTION_STANDARD (0x00000000U) ¼HAL_UART_RECEPTION_TOIDLE (0x00000001U) ½HAL_UART_RECEPTION_TORTO (0x00000002U) ¾HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) ÆHAL_UART_RXEVENT_TC (0x00000000U) ÇHAL_UART_RXEVENT_HT (0x00000001U) ÈHAL_UART_RXEVENT_IDLE (0x00000002U) â__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U) ì__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); } while(0U) __HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) ¢__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) ¨__HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) Ê__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ã__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ( ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) __HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ( ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) ¥__HAL_UART_GET_IT(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) ¿__HAL_UART_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) Ú__HAL_UART_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) ç__HAL_UART_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) í__HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) ó__HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) ù__HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) ÿ__HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) do{ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; } while(0U) ¡ __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) do{ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); } while(0U) ´ __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) do{ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; } while(0U) Ç __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) do{ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); } while(0U) Ø UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) ë UART_DIV_LPUART(__PCLK__,__BAUD__,__CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) ) ö UART_DIV_SAMPLING8(__PCLK__,__BAUD__,__CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) ÿ UART_DIV_SAMPLING16(__PCLK__,__BAUD__,__CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
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UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
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IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
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IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
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IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) ¡
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IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || ((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_1_5) || ((__STOPBITS__) == UART_STOPBITS_2)) «
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IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_2)) ³
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IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || ((__PARITY__) == UART_PARITY_EVEN) || ((__PARITY__) == UART_PARITY_ODD)) ¼
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IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__) (((__CONTROL__) == UART_HWCONTROL_NONE) || ((__CONTROL__) == UART_HWCONTROL_RTS) || ((__CONTROL__) == UART_HWCONTROL_CTS) || ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) Ç
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IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) Î
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IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || ((__STATE__) == UART_STATE_ENABLE)) Ö
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IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || ((__SAMPLING__) == UART_OVERSAMPLING_8)) Þ
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IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) æ
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IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) ð
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IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) ø
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IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) ÿ
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IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || ((__LIN__) == UART_LIN_ENABLE)) IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || ((__DMATX__) == UART_DMA_TX_ENABLE)) IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || ((__DMARX__) == UART_DMA_RX_ENABLE)) IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) § IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) ¯ IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || ((__PARAM__) == UART_SENDBREAK_REQUEST) || ((__PARAM__) == UART_MUTE_MODE_REQUEST) || ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) º IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | UART_ADVFEATURE_TXINVERT_INIT | UART_ADVFEATURE_RXINVERT_INIT | UART_ADVFEATURE_DATAINVERT_INIT | UART_ADVFEATURE_SWAP_INIT | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | UART_ADVFEATURE_DMADISABLEONERROR_INIT | UART_ADVFEATURE_AUTOBAUDRATE_INIT | UART_ADVFEATURE_MSBFIRST_INIT)) É IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) Ñ IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) Ù IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) á IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) é IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) ñ IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) ú IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) £ IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || ((__POLARITY__) == UART_DE_POLARITY_LOW)) « IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) ½ ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_uart.h stm32h7xx_hal_def.h stm32h7xx_hal_uart_ex.h \
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../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM *ø$ BaudRate Y # WordLength Y # StopBits Y # Parity Y # Mode Y # HwFlowCtl Y # OverSampling Y # OneBitSampling Y # ClockPrescaler Y # PUART_InitTypeDef Ä a*( AdvFeatureInit Y # TxPinLevelInvert Y # RxPinLevelInvert Y # DataInvert Y # Swap Y # OverrunDisable Y # DMADisableonRxError Y # AutoBaudRateEnable Y # AutoBaudRateMode Y # MSBFirst Y #$ PUART_AdvFeatureInitTypeDef PHAL_UART_StateTypeDef Y ³´UART_CLOCKSOURCE_D2PCLK1 UART_CLOCKSOURCE_D2PCLK2 UART_CLOCKSOURCE_D3PCLK1 UART_CLOCKSOURCE_PLL2 UART_CLOCKSOURCE_PLL3 UART_CLOCKSOURCE_HSI UART_CLOCKSOURCE_CSI UART_CLOCKSOURCE_LSE @UART_CLOCKSOURCE_UNDEFINED PUART_ClockSourceTypeDef ÃÃPHAL_UART_RxTypeTypeDef Y ÎPHAL_UART_RxEventTypeTypeDef Y Ù)å __UART_HandleTypeDef Instance å# Init x# AdvancedInit #( pTxBuffPtr ñ#P TxXferSize I #T TxXferCount õ#V pRxBuffPtr û#X RxXferSize I #\ RxXferCount õ#^ Mask I #` FifoMode Y #d NbRxDataToProcess I #h NbTxDataToProcess I #j ReceptionType #l RxEventType #pOÝ
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% "U RxISR ]#tOö
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% "n TxISR v#x hdmatx #| hdmarx # Lock 6 # gState # RxState # ErrorCode # "ðH : "ëtI ": tÔtõ""l t£tY PUART_HandleTypeDef ¤I Ç 8 qUARTPrescTable > ! ` G UARTPrescTable STM32H7xx_HAL_CONF_H #HAL_MODULE_ENABLED MHAL_TIM_MODULE_ENABLED NHAL_UART_MODULE_ENABLED [HAL_GPIO_MODULE_ENABLED \HAL_DMA_MODULE_ENABLED ]HAL_MDMA_MODULE_ENABLED ^HAL_RCC_MODULE_ENABLED _HAL_FLASH_MODULE_ENABLED `HAL_EXTI_MODULE_ENABLED aHAL_PWR_MODULE_ENABLED bHAL_I2C_MODULE_ENABLED cHAL_CORTEX_MODULE_ENABLED dHAL_HSEM_MODULE_ENABLED mHSE_VALUE (25000000UL) qHSE_STARTUP_TIMEOUT (100UL) yCSI_VALUE (4000000UL) HSI_VALUE (64000000UL) LSE_VALUE (32768UL) LSE_STARTUP_TIMEOUT (5000UL) LSI_VALUE (32000UL) EXTERNAL_CLOCK_VALUE 12288000UL §VDD_VALUE (3300UL) ¨TICK_INT_PRIORITY (15UL) ©USE_RTOS 0 ªUSE_SD_TRANSCEIVER 0U «USE_SPI_CRC 0U USE_HAL_ADC_REGISTER_CALLBACKS 0U ®USE_HAL_CEC_REGISTER_CALLBACKS 0U ¯USE_HAL_COMP_REGISTER_CALLBACKS 0U °USE_HAL_CORDIC_REGISTER_CALLBACKS 0U ±USE_HAL_CRYP_REGISTER_CALLBACKS 0U ²USE_HAL_DAC_REGISTER_CALLBACKS 0U ³USE_HAL_DCMI_REGISTER_CALLBACKS 0U ´USE_HAL_DFSDM_REGISTER_CALLBACKS 0U µUSE_HAL_DMA2D_REGISTER_CALLBACKS 0U ¶USE_HAL_DSI_REGISTER_CALLBACKS 0U ·USE_HAL_DTS_REGISTER_CALLBACKS 0U ¸USE_HAL_ETH_REGISTER_CALLBACKS 0U ¹USE_HAL_FDCAN_REGISTER_CALLBACKS 0U ºUSE_HAL_FMAC_REGISTER_CALLBACKS 0U »USE_HAL_NAND_REGISTER_CALLBACKS 0U ¼USE_HAL_NOR_REGISTER_CALLBACKS 0U ½USE_HAL_SDRAM_REGISTER_CALLBACKS 0U ¾USE_HAL_SRAM_REGISTER_CALLBACKS 0U ¿USE_HAL_HASH_REGISTER_CALLBACKS 0U ÀUSE_HAL_HCD_REGISTER_CALLBACKS 0U ÁUSE_HAL_GFXMMU_REGISTER_CALLBACKS 0U ÂUSE_HAL_HRTIM_REGISTER_CALLBACKS 0U ÃUSE_HAL_I2C_REGISTER_CALLBACKS 0U ÄUSE_HAL_I2S_REGISTER_CALLBACKS 0U ÅUSE_HAL_IRDA_REGISTER_CALLBACKS 0U ÆUSE_HAL_JPEG_REGISTER_CALLBACKS 0U ÇUSE_HAL_LPTIM_REGISTER_CALLBACKS 0U ÈUSE_HAL_LTDC_REGISTER_CALLBACKS 0U ÉUSE_HAL_MDIOS_REGISTER_CALLBACKS 0U ÊUSE_HAL_MMC_REGISTER_CALLBACKS 0U ËUSE_HAL_OPAMP_REGISTER_CALLBACKS 0U ÌUSE_HAL_OSPI_REGISTER_CALLBACKS 0U ÍUSE_HAL_OTFDEC_REGISTER_CALLBACKS 0U ÎUSE_HAL_PCD_REGISTER_CALLBACKS 0U ÏUSE_HAL_QSPI_REGISTER_CALLBACKS 0U ÐUSE_HAL_RNG_REGISTER_CALLBACKS 0U ÑUSE_HAL_RTC_REGISTER_CALLBACKS 0U ÒUSE_HAL_SAI_REGISTER_CALLBACKS 0U ÓUSE_HAL_SD_REGISTER_CALLBACKS 0U ÔUSE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U ÕUSE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U ÖUSE_HAL_SMBUS_REGISTER_CALLBACKS 0U ×USE_HAL_SPI_REGISTER_CALLBACKS 0U ØUSE_HAL_SWPMI_REGISTER_CALLBACKS 0U ÙUSE_HAL_TIM_REGISTER_CALLBACKS 0U ÚUSE_HAL_UART_REGISTER_CALLBACKS 0U ÛUSE_HAL_USART_REGISTER_CALLBACKS 0U ÜUSE_HAL_WWDG_REGISTER_CALLBACKS 0U ßETH_TX_DESC_CNT 4U àETH_RX_DESC_CNT 4U âETH_MAC_ADDR0 (0x02UL) ãETH_MAC_ADDR1 (0x00UL) äETH_MAC_ADDR2 (0x00UL) åETH_MAC_ADDR3 (0x00UL) æETH_MAC_ADDR4 (0x00UL) çETH_MAC_ADDR5 (0x00UL) öúþ¦ªÎÞ î
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Ê Î ûassert_param(expr) ((void)0U) { ../Core/Inc/ ../Drivers/STM32H7xx_HAL_Driver/Inc/ stm32h7xx_hal_conf.h stm32h7xx_hal_rcc.h stm32h7xx_hal_gpio.h stm32h7xx_hal_dma.h stm32h7xx_hal_mdma.h stm32h7xx_hal_exti.h stm32h7xx_hal_cortex.h stm32h7xx_hal_flash.h stm32h7xx_hal_hsem.h stm32h7xx_hal_i2c.h stm32h7xx_hal_pwr.h stm32h7xx_hal_tim.h stm32h7xx_hal_uart.h ¬
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../Core/Inc/stm32h7xx_hal_conf.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM ! " # ¨HAL_TIMEOUT_MDMA_ABORT 5U ©HAL_MDMA_CHANNEL_SIZE 0x40U ../Drivers/STM32H7xx_HAL_Driver/Inc/ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c stm32h7xx_hal.h d
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../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\git-H7\Lawnmower_STM32H7\STM32H743\MDK-ARM _Complex long_double _Complex double _Complex float uvoid )¢__va_list __ap "# "P__builtin_va_list " " î "KtY "[ % ! / ! I $ > % % % % %C
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%C % % % % %C %C & I ( ( 1 1 1 1 I8 I I8 4 ! I8 " I #7 I $ I % I & I ' I ( I ) * + , - . /4 04 14 24 3 4 4 4 5.:;9? I 6.:;9? 7.:;9G 8.:;9? I 9.:;9? :.:;9G ;.:;9? I <.:;9? =.:;9G >.:;9? I@ ?.:;9? @ @.:;9G@ A.:;9? I@
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B.:;9? @
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D 1 E 1 F 1XYW G 1XYW H.1 I.1@ J.1@
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K.1 L.< 4 I? M.< 4 ? NI O P I:;9 Q I4 R S T U V W 1 X4 I , Y4 I Z4 I [4 I, \4 I ]4 I 4 ^4 I ,4 _4 I4 `4 I,4 a4 I4 b4 1 , c4 1 d4 1, e4 1 f 1 g 1 h I i I j I k I 4 l I ,4 m I4 n 1 o 1 p4 I ? q4 I? < r4 I , s4 I t5 I u; v= w% x<% Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M7.fp.dp --fpu=FPv5_D16 --output=stm32h743\stm32h7xx_hal_mdma.o --vfemode=force
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Input Comments: pd44c-3 Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M7.fp.dp --fpu=FPv5_D16 --apcs=/interwork/interwork --divide stm32h7xx_hal_mdma.o Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] ArmCC --c99 --split_sections --debug -c --gnu -ostm32h743\stm32h7xx_hal_mdma.o --depend=stm32h743\stm32h7xx_hal_mdma.d --cpu=Cortex-M7.fp.dp --apcs=interwork -O0 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../HIDOLibrary/Include -I../HAL -I../FML -I../APL -I../FML/Internet -I../FML/Internet/Module -I../FML/Internet/Module/EG800 -I.\RTE\_STM32H743 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION=530 -D_RTE_ -DSTM32H743xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H743xx -D_USE_OS_ -D_RTK_MODE_ -D__EC600S__ -D__APP_CODE__ -D__USE_UWB__ -D__USE_NTRIP__ --omf_browse=stm32h743\stm32h7xx_hal_mdma.crf ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c O7 O7 O7 O7 O7 O7 O7 O7 O7 O7
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ß Ï ¿ ^ Ã : Ù × ð × × Ï ¼ ] À 9 Ó × ç × ù × × × * × @ × X × p × ¥ × ¿ × Ù × í × û × × 0 × L × f × x × » × í × × × ½ × Þ × ð × × & × « Þ ç Ù í × ÷ × ý × ß × : × ñ Ï ¤ H ¨ $ Ï ¼ U À 1 A ê G ê M ê W × ] ê .ARM.attributes .strtab .shstrtab .rel.debug_pubnames .rel.debug_frame .rel.debug_line .rel.debug_info .reli.HAL_MDMA_Start_IT .reli.HAL_MDMA_Start .reli.HAL_MDMA_PollForTransfer .reli.HAL_MDMA_Init .reli.HAL_MDMA_IRQHandler .reli.HAL_MDMA_Abort .symtab .comment .arm_vfe_header __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000 __ARM_grp.stm32h7xx_hal_mdma.c.2_81T300_qUYAFbTncz8_j30000 __ARM_grp.stm32h7xx_hal_conf.h.2_QZ1000_QB2js7yNpPc_300000 __ARM_grp.stm32h7xx_hal_uart.h.2_Nt1800_xPIB0JvCUh3_x70000 __ARM_grp.stm32h7xx_hal_uart_ex.h.2_Ql5000_OQDVDO16k90_900000 __ARM_grp.stm32h7xx_hal_tim.h.2_wOc400_XV0TZeKCom9_e40000 __ARM_grp.stm32h7xx_hal_tim_ex.h.2_wo5000_NEHa7frknEc_d00000 __ARM_grp.stm32h7xx_hal_pwr.h.2_Yc4000_sKI00qOuRw7_800000 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i.HAL_MDMA_GetError i.HAL_MDMA_GenerateSWRequest i.HAL_MDMA_DeInit i.HAL_MDMA_ConfigPostRequestMask i.HAL_MDMA_Abort_IT BuildAttributes$$THM_ISAv4$E$P$D$K$B$S$7EM$VFPv5_D16$PE$PLD8$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2 i.HAL_MDMA_Abort BuildAttributes$$THM_ISAv4$E$P$D$K$B$S$7EM$VFPv5_D16$PE$PLD8$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2 ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c .rrx_text .revsh_text $v0 .rev16_text ..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c $d.realdata $d $t Aw aeabi 9 Cortex-M7.fp.dp Cortex-M7 M
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