// File: STM32H742_743_753_750.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32H742, STM32H743/753 and STM32H750 reference manual (RM0433)
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// refer to STM32H742xI/G STM32H743xI/G datasheets
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// refer to STM32H753xI datasheet
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// refer to STM32H750VB STM32H750IB STM32H750XB datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> DBGMCU configuration register (DBGMCU_CR)
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// <o.28> TRGOEN <i> External trigger output enable
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// <o.8> DBGSTBY_D3 <i> Allow debug in D3 Standby mode
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// <o.7> DBGSTOP_D3 <i> Allow debug in D3 Stop mode
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// <o.2> DBGSTBY_D1 <i> Allow D1 domain debug in Standby mode
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// <o.1> DBGSTOP_D1 <i> Allow D1 domain debug in Stop mode
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// <o.0> DBGSLEEP_D1 <i> Allow D1 domain debug in Sleep mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1)
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// <i> Reserved bits must be kept at reset value
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// <o.6> WWDG1 <i> WWDG1 stop in debug
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// </h>
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DbgMCU_APB3_Fz1 = 0x00000000;
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// <h> DBGMCU APB1L peripheral freeze register (DBGMCU_APB1LFZ1)
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// <i> Reserved bits must be kept at reset value
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// <o.23> DBG_I2C3 <i> I2C3 SMBUS timeout stop in debug
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// <o.22> DBG_I2C2 <i> I2C2 SMBUS timeout stop in debug
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// <o.21> DBG_I2C1 <i> I2C1 SMBUS timeout stop in debug
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// <o.9> DBG_LPTIM1 <i> LPTIM1 stop in debug
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// <o.8> DBG_TIM14 <i> TIM14 stop in debug
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// <o.7> DBG_TIM13 <i> TIM13 stop in debug
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// <o.6> DBG_TIM12 <i> TIM12 stop in debug
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// <o.5> DBG_TIM7 <i> TIM7 stop in debug
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// <o.4> DBG_TIM6 <i> TIM6 stop in debug
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// <o.3> DBG_TIM5 <i> TIM5 stop in debug
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// <o.2> DBG_TIM4 <i> TIM4 stop in debug
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// <o.1> DBG_TIM3 <i> TIM3 stop in debug
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// <o.0> DBG_TIM2 <i> TIM2 stop in debug
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// </h>
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DbgMCU_APB1L_Fz1 = 0x00000000;
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// <h> DBGMCU APB2 peripheral freeze register (DBGMCU_APB2FZ1)
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// <i> Reserved bits must be kept at reset value
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// <o.29> DBG_HRTIM <i> HRTIM stop in debug
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// <o.18> DBG_TIM17 <i> TIM17 stop in debug
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// <o.17> DBG_TIM16 <i> TIM16 stop in debug
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// <o.16> DBG_TIM15 <i> TIM15 stop in debug
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// <o.1> DBG_TIM8 <i> TIM8 stop in debug
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// <o.0> DBG_TIM1 <i> TIM1 stop in debug
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// </h>
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DbgMCU_APB2_Fz1 = 0x00000000;
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// <h> DBGMCU APB4 peripheral freeze register (DBGMCU_APB4FZ1)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_IIWDG1 <i> Independent watchdog for D1 stop in debug
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// <o.16> DBG_RTC <i> RTC stop in debug
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// <o.12> DBG_LPTIM5 <i> LPTIM5 stop in debug
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// <o.11> DBG_LPTIM4 <i> LPTIM4 stop in debug
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// <o.10> DBG_LPTIM3 <i> LPTIM2 stop in debug
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// <o.9> DBG_LPTIM2 <i> LPTIM2 stop in debug
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// <o.7> DBG_I2C4 <i> I2C4 SMBUS timeout stop in debug
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// </h>
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DbgMCU_APB4_Fz1 = 0x00000000;
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// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
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// <i> TRACECLK: Pin PE2
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// <o1> TRACED0
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// <i> ETM Trace Data 0
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// <0x00040003=> Pin PE3
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// <0x00020001=> Pin PC1
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// <0x0006000D=> Pin PG13
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// <o2> TRACED1
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// <i> ETM Trace Data 1
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// <0x00040004=> Pin PE4
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// <0x00020008=> Pin PC8
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// <0x0006000E=> Pin PG14
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// <o3> TRACED2
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// <i> ETM Trace Data 2
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// <0x00040005=> Pin PE5
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// <0x00030002=> Pin PD2
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// <o4> TRACED3
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// <i> ETM Trace Data 3
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// <0x00040006=> Pin PE6
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// <0x0002000C=> Pin PC12
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// </h>
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TraceClk_Pin = 0x00040002;
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TraceD0_Pin = 0x00040003;
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TraceD1_Pin = 0x00040004;
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TraceD2_Pin = 0x00040005;
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TraceD3_Pin = 0x00040006;
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// <<< end of configuration section >>>
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