/**
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******************************************************************************
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* @file stm3210e_eval_fsmc_nand.c
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* @author MCD Application Team
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* @version V4.5.0
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* @date 07-March-2011
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* @brief This file provides a set of functions needed to drive the
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* NAND512W3A2 memory mounted on STM3210E-EVAL board.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm3210e_eval_fsmc_nand.h"
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/** @addtogroup Utilities
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* @{
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*/
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/** @addtogroup STM32_EVAL
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* @{
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*/
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/** @addtogroup STM3210E_EVAL
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* @{
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*/
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/** @addtogroup STM3210E_EVAL_FSMC_NAND
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* @brief This file provides a set of functions needed to drive the
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* NAND512W3A2 memory mounted on STM3210E-EVAL board.
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* @{
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*/
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/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines
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* @{
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*/
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/**
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* @brief FSMC Bank 2
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*/
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#define FSMC_Bank_NAND FSMC_Bank2_NAND
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#define Bank_NAND_ADDR Bank2_NAND_ADDR
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#define Bank2_NAND_ADDR ((uint32_t)0x70000000)
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros
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* @{
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*/
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#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions
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* @{
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*/
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/**
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* @brief Configures the FSMC and GPIOs to interface with the NAND memory.
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* This function must be called before any write/read operation on the
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* NAND.
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* @param None
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* @retval None
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*/
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void NAND_Init(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
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FSMC_NAND_PCCARDTimingInitTypeDef p;
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
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RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
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/*-- GPIO Configuration ------------------------------------------------------*/
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/*!< CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
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GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
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GPIO_Pin_7;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*!< D4->D7 NAND pin configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
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GPIO_Init(GPIOE, &GPIO_InitStructure);
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/*!< NWAIT NAND pin configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*!< INT2 NAND pin configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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GPIO_Init(GPIOG, &GPIO_InitStructure);
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/*-- FSMC Configuration ------------------------------------------------------*/
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p.FSMC_SetupTime = 0x0;
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p.FSMC_WaitSetupTime = 0x2;
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p.FSMC_HoldSetupTime = 0x1;
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p.FSMC_HiZSetupTime = 0x0;
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FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
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FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
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FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
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FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
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FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
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FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
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FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
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FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
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FSMC_NANDInit(&FSMC_NANDInitStructure);
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/*!< FSMC NAND Bank Cmd Test */
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FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
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}
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/**
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* @brief Reads NAND memory's ID.
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* @param NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
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* the Manufacturer and Device ID.
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* @retval None
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*/
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void NAND_ReadID(NAND_IDTypeDef* NAND_ID)
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{
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uint32_t data = 0;
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/*!< Send Command to the command area */
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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/*!< Sequence to read ID from NAND flash */
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data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
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NAND_ID->Maker_ID = ADDR_1st_CYCLE (data);
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NAND_ID->Device_ID = ADDR_2nd_CYCLE (data);
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NAND_ID->Third_ID = ADDR_3rd_CYCLE (data);
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NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data);
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}
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/**
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* @brief This routine is for writing one or several 512 Bytes Page size.
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* @param pBuffer: pointer on the Buffer containing data to be written
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* @param Address: First page address
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* @param NumPageToWrite: Number of page to write
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* @retval New status of the NAND operation. This parameter can be:
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* - NAND_TIMEOUT_ERROR: when the previous operation generate
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* a Timeout error
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* - NAND_READY: when memory is ready for the next operation
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* And the new status of the increment address operation. It can be:
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* - NAND_VALID_ADDRESS: When the new address is valid address
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* - NAND_INVALID_ADDRESS: When the new address is invalid address
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*/
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uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
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{
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uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
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uint32_t status = NAND_READY, size = 0x00;
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while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
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{
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/*!< Page write command and address */
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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/*!< Calculate the size */
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size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
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/*!< Write data */
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for(; index < size; index++)
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{
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*(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
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}
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
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/*!< Check status for successful operation */
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status = NAND_GetStatus();
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if(status == NAND_READY)
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{
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numpagewritten++;
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NumPageToWrite--;
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/*!< Calculate Next small page Address */
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addressstatus = NAND_AddressIncrement(&Address);
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}
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}
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return (status | addressstatus);
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}
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/**
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* @brief This routine is for sequential read from one or several 512 Bytes Page size.
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* @param pBuffer: pointer on the Buffer to fill
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* @param Address: First page address
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* @param NumPageToRead: Number of page to read
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* @retval New status of the NAND operation. This parameter can be:
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* - NAND_TIMEOUT_ERROR: when the previous operation generate
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* a Timeout error
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* - NAND_READY: when memory is ready for the next operation
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* And the new status of the increment address operation. It can be:
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* - NAND_VALID_ADDRESS: When the new address is valid address
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* - NAND_INVALID_ADDRESS: When the new address is invalid address
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*/
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uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
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{
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uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
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uint32_t status = NAND_READY, size = 0x00;
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while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
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{
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/*!< Page Read command and page address */
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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/*!< Calculate the size */
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size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
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/*!< Get Data into Buffer */
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for(; index < size; index++)
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{
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pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
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}
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numpageread++;
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NumPageToRead--;
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/*!< Calculate page address */
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addressstatus = NAND_AddressIncrement(&Address);
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}
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status = NAND_GetStatus();
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return (status | addressstatus);
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}
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/**
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* @brief This routine write the spare area information for the specified
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* pages addresses.
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* @param pBuffer: pointer on the Buffer containing data to be written
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* @param Address: First page address
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* @param NumSpareAreaTowrite: Number of Spare Area to write
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* @retval New status of the NAND operation. This parameter can be:
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* - NAND_TIMEOUT_ERROR: when the previous operation generate
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* a Timeout error
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* - NAND_READY: when memory is ready for the next operation
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* And the new status of the increment address operation. It can be:
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* - NAND_VALID_ADDRESS: When the new address is valid address
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* - NAND_INVALID_ADDRESS: When the new address is invalid address
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*/
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uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
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{
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uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
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uint32_t status = NAND_READY, size = 0x00;
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while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
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{
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/*!< Page write Spare area command and address */
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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/*!< Calculate the size */
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size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
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/*!< Write the data */
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for(; index < size; index++)
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{
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*(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
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}
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
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/*!< Check status for successful operation */
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status = NAND_GetStatus();
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if(status == NAND_READY)
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{
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numsparesreawritten++;
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NumSpareAreaTowrite--;
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/*!< Calculate Next page Address */
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addressstatus = NAND_AddressIncrement(&Address);
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}
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}
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return (status | addressstatus);
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}
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/**
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* @brief This routine read the spare area information from the specified
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* pages addresses.
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* @param pBuffer: pointer on the Buffer to fill
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* @param Address: First page address
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* @param NumSpareAreaToRead: Number of Spare Area to read
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* @retval New status of the NAND operation. This parameter can be:
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* - NAND_TIMEOUT_ERROR: when the previous operation generate
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* a Timeout error
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* - NAND_READY: when memory is ready for the next operation
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* And the new status of the increment address operation. It can be:
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* - NAND_VALID_ADDRESS: When the new address is valid address
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* - NAND_INVALID_ADDRESS: When the new address is invalid address
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*/
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uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
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{
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uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
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uint32_t status = NAND_READY, size = 0x00;
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while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
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{
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/*!< Page Read command and page address */
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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/*!< Data Read */
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size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead);
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/*!< Get Data into Buffer */
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for ( ;index < size; index++)
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{
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pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
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}
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numsparearearead++;
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NumSpareAreaToRead--;
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/*!< Calculate page address */
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addressstatus = NAND_AddressIncrement(&Address);
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}
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status = NAND_GetStatus();
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return (status | addressstatus);
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}
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/**
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* @brief This routine erase complete block from NAND FLASH
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* @param Address: Any address into block to be erased
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* @retval New status of the NAND operation. This parameter can be:
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* - NAND_TIMEOUT_ERROR: when the previous operation generate
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* a Timeout error
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* - NAND_READY: when memory is ready for the next operation
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*/
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uint32_t NAND_EraseBlock(NAND_ADDRESS Address)
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{
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
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return (NAND_GetStatus());
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}
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/**
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* @brief This routine reset the NAND FLASH.
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* @param None
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* @retval NAND_READY
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*/
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uint32_t NAND_Reset(void)
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{
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
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return (NAND_READY);
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}
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/**
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* @brief Get the NAND operation status.
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* @param None
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* @retval New status of the NAND operation. This parameter can be:
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* - NAND_TIMEOUT_ERROR: when the previous operation generate
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* a Timeout error
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* - NAND_READY: when memory is ready for the next operation
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*/
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uint32_t NAND_GetStatus(void)
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{
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uint32_t timeout = 0x1000000, status = NAND_READY;
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status = NAND_ReadStatus();
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/*!< Wait for a NAND operation to complete or a TIMEOUT to occur */
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while ((status != NAND_READY) &&( timeout != 0x00))
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{
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status = NAND_ReadStatus();
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timeout --;
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}
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if(timeout == 0x00)
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{
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status = NAND_TIMEOUT_ERROR;
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}
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/*!< Return the operation status */
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return (status);
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}
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/**
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* @brief Reads the NAND memory status using the Read status command.
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* @param None
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* @retval The status of the NAND memory. This parameter can be:
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* - NAND_BUSY: when memory is busy
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* - NAND_READY: when memory is ready for the next operation
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* - NAND_ERROR: when the previous operation gererates error
|
*/
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uint32_t NAND_ReadStatus(void)
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{
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uint32_t data = 0x00, status = NAND_BUSY;
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/*!< Read status operation ------------------------------------ */
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*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
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data = *(__IO uint8_t *)(Bank_NAND_ADDR);
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if((data & NAND_ERROR) == NAND_ERROR)
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{
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status = NAND_ERROR;
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}
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else if((data & NAND_READY) == NAND_READY)
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{
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status = NAND_READY;
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}
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else
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{
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status = NAND_BUSY;
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}
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return (status);
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}
|
|
/**
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* @brief Increment the NAND memory address.
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* @param Address: address to be incremented.
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* @retval The new status of the increment address operation. It can be:
|
* - NAND_VALID_ADDRESS: When the new address is valid address
|
* - NAND_INVALID_ADDRESS: When the new address is invalid address
|
*/
|
uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address)
|
{
|
uint32_t status = NAND_VALID_ADDRESS;
|
|
Address->Page++;
|
|
if(Address->Page == NAND_BLOCK_SIZE)
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{
|
Address->Page = 0;
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Address->Block++;
|
|
if(Address->Block == NAND_ZONE_SIZE)
|
{
|
Address->Block = 0;
|
Address->Zone++;
|
|
if(Address->Zone == NAND_MAX_ZONE)
|
{
|
status = NAND_INVALID_ADDRESS;
|
}
|
}
|
}
|
|
return (status);
|
}
|
|
/**
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* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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