/**
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******************************************************************************
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* @file stm3210e_eval_fsmc_sram.c
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* @author MCD Application Team
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* @version V4.5.0
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* @date 07-March-2011
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* @brief This file provides a set of functions needed to drive the
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* IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
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******************************************************************************
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* @attention
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*
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* modefied by www.armjishu.com
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm3210e_eval_fsmc_sram.h"
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/** @addtogroup Utilities
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* @{
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*/
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/** @addtogroup STM32_EVAL
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* @{
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*/
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/** @addtogroup STM3210E_EVAL
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* @{
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*/
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/** @addtogroup STM3210E_EVAL_FSMC_SRAM
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* @brief This file provides a set of functions needed to drive the
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* IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
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* @{
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*/
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/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Defines
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* @{
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*/
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/**
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* @brief FSMC Bank 1 NOR/SRAM3
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*/
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#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Functions
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* @{
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*/
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/**
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* @brief Configures the FSMC and GPIOs to interface with the SRAM memory.
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* This function must be called before any write/read operation
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* on the SRAM.
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* @param None
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* @retval None
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*/
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void SRAM_Init(void)
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{
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FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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FSMC_NORSRAMTimingInitTypeDef p;
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
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RCC_APB2Periph_GPIOF, ENABLE);
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/*-- GPIO Configuration ------------------------------------------------------*/
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/*FSMCÊý¾ÝÏßFSMC_D[0:15]³õʼ»¯£¬ÍÆÍ츴ÓÃÊä³ö*/
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/*!< SRAM Data lines configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
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GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
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GPIO_Pin_15;
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GPIO_Init(GPIOE, &GPIO_InitStructure);
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/*!< SRAM Address lines configuration */
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/*FSMCµØÖ·ÏßFSMC_A[0:17]³õʼ»¯£¬ÍÆÍ츴ÓÃÊä³ö*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
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GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOF, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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GPIO_Pin_4 | GPIO_Pin_5;
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GPIO_Init(GPIOG, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*!< NOE and NWE configuration */
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/*FSMC NOEºÍNWE³õÊÔ»¯£¬ÍÆÍ츴ÓÃÊä³ö*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*!< NE3 configuration */
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/*FSMC NE3³õÊÔ»¯£¬ÍÆÍ츴ÓÃÊä³ö*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
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GPIO_Init(GPIOG, &GPIO_InitStructure);
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/*!< NBL0, NBL1 configuration */
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/*FSMC NBL0ºÍNBL1³õÊÔ»¯£¬ÍÆÍ츴ÓÃÊä³ö*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
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GPIO_Init(GPIOE, &GPIO_InitStructure);
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/*-- FSMC Configuration ------------------------------------------------------*/
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/*--------------FSMC ×ÜÏß ´æ´¢Æ÷²ÎÊýÅäÖÃ------------------------------*/
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p.FSMC_AddressSetupTime = 0; //µØÖ·½¨Á¢Ê±¼ä
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p.FSMC_AddressHoldTime = 0; //µØÖ·±£³Öʱ¼ä
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p.FSMC_DataSetupTime = 1; //Êý¾Ý½¨Á¢Ê±¼ä
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p.FSMC_BusTurnAroundDuration = 0; //×ÜÏ߻ָ´Ê±¼ä
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p.FSMC_CLKDivision = 0; // ʱÖÓ·ÖƵÒò×Ó
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p.FSMC_DataLatency = 0; //Êý¾Ý²úÉúʱ¼ä
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p.FSMC_AccessMode = FSMC_AccessMode_A; //FSMC NOR¿ØÖÆÆ÷ʱÐò
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/*--------------FSMC ×ÜÏß ²ÎÊýÅäÖÃ------------------------------*/
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FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; //ʹÓÃÁËFSMCµÄBANK1µÄ×Ó°å¿é3
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FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; //½ûÖ¹µØÖ·Êý¾ÝÏ߸´ÓÃ
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FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; //´æ´¢Æ÷ÀàÐÍΪSRAM
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FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; //´æ´¢Æ÷Êý¾Ý¿í¶ÈΪ16λ
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FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; //¹Ø±ÕÍ»·¢Ä£Ê½·ÃÎÊ
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FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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//µÈ´ýÐźÅÓÅÏȼ¶£¬Ö»ÓÐÔÚʹÄÜÍ»·¢·ÃÎÊģʽ²ÅÓÐЧ
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; //ʹÄÜÕâ¸öBANKµÄд²Ù×÷
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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//ʹÄÜ/¹Ø±ÕµÈ´ýÐÅÏ¢ÉèÖã¬Ö»ÔÚʹÄÜÍ»·¢·ÃÎÊģʽ²ÅÓÐЧ
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FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; //¹Ø±ÕExtend Mode
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FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; //¹Ø±ÕWrite Burst Mode
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FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; //¶Á²Ù×÷ʱÐò²ÎÊý
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FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; //д²Ù×÷ʱÐò²ÎÊý
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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/*!< Enable FSMC Bank1_SRAM Bank */
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/*--------------ʹÄÜBANK1µÄ×Ó°å¿é3------------------------------*/
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
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}
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/**
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* @brief Writes a Half-word buffer to the FSMC SRAM memory.
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* @param pBuffer : pointer to buffer.
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* @param WriteAddr : SRAM memory internal address from which the data will be
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* written.
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* @param NumHalfwordToWrite : number of half-words to write.
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* @retval None
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*/
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void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
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{
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for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
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{
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/*!< Transfer data to the memory */
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*(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
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/*!< Increment the address*/
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WriteAddr += 2;
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}
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}
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/**
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* @brief Reads a block of data from the FSMC SRAM memory.
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* @param pBuffer : pointer to the buffer that receives the data read from the
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* SRAM memory.
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* @param ReadAddr : SRAM memory internal address to read from.
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* @param NumHalfwordToRead : number of half-words to read.
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* @retval None
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*/
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void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
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{
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for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
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{
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/*!< Read a half-word from the memory */
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*pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
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/*!< Increment the address*/
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ReadAddr += 2;
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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