/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
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* File Name : otgd_fs_regs.h
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* Author : STMicroelectronics
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* Version : V3.3.0
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* Date : 21-March-2011
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* Description : USB OTG IP hardware registers.
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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#ifndef __USB_OTG_REGS_H__
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#define __USB_OTG_REGS_H__
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#ifdef STM32F10X_CL
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#include "stm32f10x.h"
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#include "usb_type.h"
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#define USB_OTG_FS_BASE_ADDR 0x50000000
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#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x0000
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#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x0800
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#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x0900
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#define USB_OTG_EP_REG_OFFSET 0x0020
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#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0x0B00
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#define USB_OTG_PCGCCTL_OFFSET 0x0E00
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#define USB_OTG_DATA_FIFO_OFFSET 0x1000
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#define USB_OTG_DATA_FIFO_SIZE 0x1000
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#define NUM_TX_FIFOS 4
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/*******************************************************************************
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* USB_OTG Core registers .
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* The USB_OTG_USB_OTG_FS_REGS structure defines the size
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* and relative field offsets for the Core Global registers.
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******************************************************************************/
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typedef struct _USB_OTG_GREGS //000h
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{
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__IO uint32_t GOTGCTL; /* USB_OTG Control and Status reg 000h*/
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__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
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__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
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__IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
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__IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
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__IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
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__IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
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__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
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__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
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__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
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__IO uint32_t DIEPTXF0; /* EP0 Tx FIFO Size Register 028h*/
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__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
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uint32_t Reserved30[2]; /* Reserved 030h*/
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__IO uint32_t GCCFG; /* General Core configuration reg 038h*/
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__IO uint32_t CID; /* User ID Register 03Ch*/
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uint32_t reserved[48]; /* Reserved 040h-0FFh*/
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__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
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__IO uint32_t DIEPTXFx[NUM_TX_FIFOS - 1]; /* dev Transmit FIFO */
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}
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USB_OTG_GREGS;
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/*******************************************************************************
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* dev Registers
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* dev Global Registers : Offsets 800h-BFFh
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* The following structures define the size and relative field offsets
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* for the dev Mode Registers.
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* These registers are visible only in dev mode and must not be
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* accessed in Host mode, as the results are unknown
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******************************************************************************/
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typedef struct _USB_OTG_DEV // 800h
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{
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__IO uint32_t DCFG; /* dev Configuration Register 800h*/
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__IO uint32_t DCTL; /* dev Control Register 804h*/
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__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
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uint32_t reservedC; /* Reserved 80Ch*/
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__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
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__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
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__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
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__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
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uint32_t Reserved20[2]; /* Reserved 820h-824h*/
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__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
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__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
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__IO uint32_t Reserved30; /* Reserved 830h*/
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__IO uint32_t DIEPEMPMSK; /* IN EP FIFO empty int mask 834h*/
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}
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USB_OTG_DEV;
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/*******************************************************************************
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* dev Logical IN Endpoint-Specific Registers: Offsets 900h-AFCh
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* There will be one set of endpoint registers per logical endpoint implemented.
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* These registers are visible only in dev mode and must not be
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* accessed in Host mode, as the results are unknown
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*******************************************************************************/
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typedef struct _USB_OTG_DINEPS
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{
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__IO uint32_t DIEPCTLx; /* dev IN EP Ctl Reg 900h + (ep_num * 20h) + 00h*/
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uint32_t reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
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__IO uint32_t DIEPINTx; /* dev IN EP Itr Reg 900h + (ep_num * 20h) + 08h*/
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uint32_t reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
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__IO uint32_t DIEPTSIZx; /* dev IN EP Tx Size 900h + (ep_num * 20h) + 10h*/
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uint32_t reserved14; /* Reserved 900h + (ep_num * 20h) + 14h*/
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__IO uint32_t DTXFSTSx; /* IN EP TxFIFO Sts 900h + (ep_num * 20h) + 18h*/
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uint32_t reserved18; /* Reserved 900h + (ep_num * 20h) + 1Ch*/
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}
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USB_OTG_DINEPS;
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/*******************************************************************************
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* dev Logical OUT Endpoint-Specific Registers Offsets: B00h-CFCh
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* There will be one set of endpoint registers per logical endpoint
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* implemented.
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* These registers are visible only in dev mode and must not be
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* accessed in Host mode, as the results are unknown
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******************************************************************************/
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typedef struct _USB_OTG_DOUTEPS
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{
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__IO uint32_t DOEPCTLx; /* OUT EP Ctl Reg B00h + (ep_num * 20h) + 00h*/
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uint32_t reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
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__IO uint32_t DOEPINTx; /* OUT EP Itr Reg B00h + (ep_num * 20h) + 08h*/
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uint32_t reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
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__IO uint32_t DOEPTSIZx; /* OUT EP Tx Size B00h + (ep_num * 20h) + 10h*/
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__IO uint32_t Reserved14[3]; /* Reserved B00h + (ep_num * 20h) + 14h*/
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}
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USB_OTG_DOUTEPS;
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/*******************************************************************************
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* otg Core registers .
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* The USB_OTG_USB_OTG_FS_REGS structure defines the size
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* and relative field offsets for the Core Global registers.
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******************************************************************************/
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typedef struct USB_OTG_USB_OTG_FS_REGS //000h
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{
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USB_OTG_GREGS *GREGS;
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USB_OTG_DEV *DEV;
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USB_OTG_DINEPS *DINEPS[NUM_TX_FIFOS];
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USB_OTG_DOUTEPS *DOUTEPS[NUM_TX_FIFOS];
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__IO uint32_t *FIFO[NUM_TX_FIFOS];
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__IO uint32_t *PCGCCTL;
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}
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USB_OTG_CORE_REGS , *pUSB_OTG_CORE_REGS;
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/******************************************************************************/
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typedef union _USB_OTG_GAHBCFG_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t gintmsk :
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1;
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uint32_t reserved1 :
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6;
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uint32_t txfemplvl :
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1;
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uint32_t reserved8_31 :
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24;
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}
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b;
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}
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USB_OTG_GAHBCFG_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_GUSBCFG_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t toutcal :
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3;
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uint32_t Reserved3_5 :
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3;
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uint32_t physel : /* MUST be always 1 because the phy is embedded*/
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1;
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uint32_t Reserved7 :
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1;
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uint32_t srpcap :
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1;
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uint32_t hnpcap :
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1;
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uint32_t usbtrdtim :
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4;
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uint32_t reserved15_30 :
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15;
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uint32_t force_host :
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1;
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uint32_t force_dev :
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1;
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uint32_t corrupt_tx :
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1;
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}
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b;
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} USB_OTG_GUSBCFG_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_GRSTCTL_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t csftrst :
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1;
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uint32_t hsftrst :
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1;
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uint32_t hstfrm :
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1;
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uint32_t reserved3 :
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1;
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uint32_t rxfflsh :
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1;
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uint32_t txfflsh :
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1;
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uint32_t txfnum :
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5;
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uint32_t reserved11_30 :
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20;
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uint32_t ahbidle :
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1;
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}
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b;
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} USB_OTG_GRSTCTL_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_GINTMSK_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t reserved0 :
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1;
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uint32_t modemismatch :
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1;
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uint32_t otgintr :
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1;
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uint32_t sofintr :
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1;
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uint32_t rxstsqlvl :
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1;
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uint32_t reserved5 :
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1;
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uint32_t ginnakeff :
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1;
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uint32_t goutnakeff :
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1;
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uint32_t reserved8_9 :
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2;
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uint32_t erlysuspend :
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1;
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uint32_t usbsuspend :
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1;
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uint32_t usbreset :
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1;
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uint32_t enumdone :
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1;
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uint32_t isooutdrop :
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1;
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uint32_t eopframe :
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1;
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uint32_t reserved16 :
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1;
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uint32_t epmismatch :
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1;
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uint32_t inepintr :
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1;
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uint32_t outepintr :
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1;
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uint32_t incomplisoin :
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1;
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uint32_t incomplisoout :
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1;
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uint32_t reserved22_23 :
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2;
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uint32_t portintr :
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1;
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uint32_t hcintr :
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1;
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uint32_t ptxfempty :
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1;
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uint32_t reserved27 :
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1;
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uint32_t conidstschng :
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1;
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uint32_t disconnect :
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1;
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uint32_t sessreqintr :
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1;
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uint32_t wkupintr :
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1;
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}
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b;
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} USB_OTG_GINTMSK_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_GINTSTS_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t curmode :
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1;
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uint32_t modemismatch :
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1;
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uint32_t otgintr :
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1;
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uint32_t sofintr :
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1;
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uint32_t rxstsqlvl :
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1;
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uint32_t reserved5 :
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1;
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uint32_t ginnakeff :
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1;
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uint32_t goutnakeff :
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1;
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uint32_t reserved8_9 :
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2;
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uint32_t erlysuspend :
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1;
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uint32_t usbsuspend :
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1;
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uint32_t usbreset :
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1;
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uint32_t enumdone :
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1;
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uint32_t isooutdrop :
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1;
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uint32_t eopframe :
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1;
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uint32_t Reserved16_17 :
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2;
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uint32_t inepint:
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1;
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uint32_t outepintr :
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1;
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uint32_t incomplisoin :
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1;
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uint32_t incomplisoout :
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1;
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uint32_t reserved22_23 :
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2;
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uint32_t portintr :
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1;
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uint32_t hcintr :
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1;
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uint32_t ptxfempty :
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1;
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uint32_t reserved27 :
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1;
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uint32_t conidstschng :
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1;
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uint32_t disconnect :
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1;
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uint32_t sessreqintr :
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1;
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uint32_t wkupintr :
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1;
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}
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b;
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} USB_OTG_GINTSTS_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_GRXSTSP_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t epnum :
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4;
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uint32_t bcnt :
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11;
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uint32_t dpid :
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2;
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uint32_t pktsts :
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4;
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uint32_t frmnum :
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4;
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uint32_t reserved :
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7;
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}
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b;
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} USB_OTG_GRXSTSP_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_FIFOSIZ_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t startaddr :
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16;
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uint32_t depth :
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16;
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}
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b;
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} USB_OTG_FIFOSIZ_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DTXFSTS_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t txfspcavail :
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16;
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uint32_t reserved :
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16;
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}
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b;
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} USB_OTG_DTXFSTS_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_GCCFG_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t reserved0 :
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16;
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uint32_t pwdn :
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1;
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uint32_t reserved17 :
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1;
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uint32_t vbussensingA :
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1;
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uint32_t vbussensingB :
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1;
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uint32_t SOFouten :
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1;
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uint32_t reserved21 :
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11;
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}
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b;
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} USB_OTG_GCCFG_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DCFG_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t devspd :
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2;
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uint32_t nzstsouthshk :
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1;
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uint32_t reserved3 :
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1;
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uint32_t devaddr :
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7;
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uint32_t perfrint :
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2;
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uint32_t reserved13_31 :
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19;
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}
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b;
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} USB_OTG_DCFG_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DCTL_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t rmtwkupsig :
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1;
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uint32_t sftdiscon :
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1;
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uint32_t gnpinnaksts :
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1;
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uint32_t goutnaksts :
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1;
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uint32_t tstctl :
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3;
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uint32_t sgnpinnak :
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1;
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uint32_t cgnpinnak :
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1;
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uint32_t sgoutnak :
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1;
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uint32_t cgoutnak :
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1;
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uint32_t pwronprgdone :
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1;
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uint32_t reserved :
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20;
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}
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b;
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} USB_OTG_DCTL_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DSTS_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t suspsts :
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1;
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uint32_t enumspd :
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2;
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uint32_t errticerr :
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1;
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uint32_t reserved4_7:
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4;
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uint32_t soffn :
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14;
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uint32_t reserved22_31 :
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10;
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}
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b;
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} USB_OTG_DSTS_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DIEPINTx_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t xfercompl :
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1;
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uint32_t epdis :
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1;
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uint32_t Reserved2 :
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1;
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uint32_t timeout :
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1;
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uint32_t intktxfemp :
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1;
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uint32_t reserved5 :
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1;
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uint32_t inepnakeff :
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1;
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uint32_t txfempty :
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1;
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uint32_t reserved08_31 :
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24;
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}
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b;
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} USB_OTG_DIEPINTx_TypeDef;
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typedef union _USB_OTG_DIEPINTx_TypeDef USB_OTG_DIEPMSKx_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DOEPINTx_TypeDef
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{
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uint32_t d32;
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struct
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{
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uint32_t xfercompl :
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1;
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uint32_t epdis :
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1;
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uint32_t reserved2 :
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1;
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uint32_t setup : /* for EP0 only */
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1;
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uint32_t outtokenepdis :
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1;
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uint32_t reserved5 :
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1;
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uint32_t b2bsetup :
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1;
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uint32_t reserved07_31 :
|
25;
|
}
|
b;
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} USB_OTG_DOEPINTx_TypeDef;
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|
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typedef union _USB_OTG_DOEPINTx_TypeDef USB_OTG_DOEPMSKx_TypeDef;
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/******************************************************************************/
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typedef union _USB_OTG_DAINT_TypeDef
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{
|
|
uint32_t d32;
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struct
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{
|
uint32_t in :
|
16;
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uint32_t out :
|
16;
|
}
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ep;
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} USB_OTG_DAINT_TypeDef;
|
|
/******************************************************************************/
|
typedef union _USB_OTG_DEPCTLx_TypeDef
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{
|
|
uint32_t d32;
|
struct
|
{
|
uint32_t mps :
|
11;
|
uint32_t Reserved11_14 :
|
4;
|
uint32_t usbactep :
|
1;
|
uint32_t dpid :
|
1;
|
uint32_t naksts :
|
1;
|
uint32_t eptype :
|
2;
|
uint32_t Reserved20 :
|
1;
|
uint32_t stall :
|
1;
|
uint32_t txfnum :
|
4;
|
uint32_t cnak :
|
1;
|
uint32_t snak :
|
1;
|
uint32_t setd0pid :
|
1;
|
uint32_t setoddfrm :
|
1;
|
uint32_t epdis :
|
1;
|
uint32_t epena :
|
1;
|
}
|
b;
|
} USB_OTG_DEPCTLx_TypeDef;
|
|
/******************************************************************************/
|
|
typedef union _OTG_FS_DEPTSIZx_TypeDef
|
{
|
|
uint32_t d32;
|
struct
|
{
|
uint32_t xfersize :
|
19;
|
uint32_t pktcnt :
|
10;
|
uint32_t mcount :
|
2;
|
uint32_t reserved :
|
1;
|
}
|
b;
|
}
|
OTG_FS_DEPTSIZx_TypeDef;
|
|
/******************************************************************************/
|
|
typedef union _USB_OTG_DOEPTSIZ0_TypeDef
|
{
|
|
uint32_t d32;
|
struct
|
{
|
uint32_t xfersize :
|
7;
|
uint32_t reserved7_18 :
|
12;
|
uint32_t pktcnt :
|
1;
|
uint32_t reserved20_28 :
|
9;
|
uint32_t supcnt :
|
2;
|
uint32_t reserved31;
|
}
|
b;
|
} USB_OTG_DOEPTSIZ0_TypeDef;
|
|
/******************************************************************************/
|
|
typedef union _OTG_FS_PCGCCTL_TypeDef
|
{
|
uint32_t d32;
|
struct
|
{
|
uint32_t stoppclk :
|
1;
|
uint32_t gatehclk :
|
1;
|
uint32_t reserved3 :
|
30;
|
}
|
b;
|
} OTG_FS_PCGCCTL_TypeDef;
|
|
#endif /* STM32F10X_CL */
|
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
|
#endif
|
