/**
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******************************************************************************
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* @file stm32100e_eval_fsmc_onenand.c
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* @author MCD Application Team
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* @version V4.5.0
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* @date 07-March-2011
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* @brief This file provides a set of functions needed to drive the
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* KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32100e_eval_fsmc_onenand.h"
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/** @addtogroup Utilities
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* @{
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*/
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/** @addtogroup STM32_EVAL
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* @{
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*/
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/** @addtogroup STM32100E_EVAL
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* @{
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*/
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/** @addtogroup STM32100E_EVAL_FSMC_ONENAND
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* @brief This file provides a set of functions needed to drive the
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* KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
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* @{
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*/
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/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
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* @{
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*/
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#define BANK1_ONENAND1_ADDR ((uint32_t)0x60000000)
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#define ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR)
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/**
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* @}
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*/
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/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
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* @{
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*/
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#define OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))
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/**
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* @}
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*/
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/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
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* @{
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*/
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/**
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* @brief Configures the FSMC and GPIOs to interface with the OneNAND memory.
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* This function must be called before any write/read operation on the
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* OneNAND.
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* @param None
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* @retval None
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*/
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void OneNAND_Init(void)
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{
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FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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FSMC_NORSRAMTimingInitTypeDef p;
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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/*-- GPIO Configuration ------------------------------------------------------*/
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/* OneNAND Data lines configuration */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
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RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
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/*-- GPIO Configuration ------------------------------------------------------*/
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/*!< OneNAND Data lines configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
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GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
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GPIO_Pin_15;
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GPIO_Init(GPIOE, &GPIO_InitStructure);
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/*!< OneNAND Address lines configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
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GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOF, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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GPIO_Pin_4 | GPIO_Pin_5;
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GPIO_Init(GPIOG, &GPIO_InitStructure);
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/*!< CLK, NOE and NWE configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*!< NE1 configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*!< NL configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE);
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/*!< NWAIT configuration */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/*-- FSMC Configuration ----------------------------------------------------*/
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p.FSMC_AddressSetupTime = 0x01;
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p.FSMC_AddressHoldTime = 0x00;
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p.FSMC_DataSetupTime = 0x05;
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p.FSMC_BusTurnAroundDuration = 0x02;
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p.FSMC_CLKDivision = 0x1;
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p.FSMC_DataLatency = 0x01;
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p.FSMC_AccessMode = FSMC_AccessMode_B;
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FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
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FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
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FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
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FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable;
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FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
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}
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/**
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* @brief Resets the OneNAND memory.
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* @param None
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* @retval None
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*/
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void OneNAND_Reset(void)
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{
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OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET);
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}
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/**
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* @brief Reads OneNAND memory's Manufacturer and Device Code.
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* @param OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
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* the Manufacturer and Device Code.
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* @retval None
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*/
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void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
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{
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uint16_t status = 0x0;
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/* Wait till no ongoing operation */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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while((status & 0x8000) == 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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}
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/* Read ID data */
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OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID);
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OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID);
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0;
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}
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/**
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* @brief Unlocks the specified OneNAND memory block (128Kb).
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* @param BlockNumber: specifies the block number to be erased. This parameter
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* should be between 0 and 511.
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* @retval OneNAND memory Interrupt Status.
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*/
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uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber)
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{
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uint16_t status = 0;
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/* Wait till no ongoing operation */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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while((status & 0x8000) == 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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}
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK;
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/* Wait till the command is completed */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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while((status & 0x8000) != 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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}
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/* Get the Controller Status */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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return (status);
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}
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/**
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* @brief Erases the specified OneNAND memory block (128Kb).
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* @param BlockNumber: specifies the block number to be erased. This parameter
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* should be between 0 and 511.
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* @retval OneNAND memory Interrupt Status.
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*/
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uint16_t OneNAND_EraseBlock(uint32_t BlockNumber)
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{
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uint16_t status = 0x0;
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/* Wait till no ongoing operation */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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while((status & 0x8000) == 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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}
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/* Erase operation */
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE;
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/* Wait till no error is generated */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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while((status & 0x0400) == 0x0400)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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}
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/* Wait till the command is completed */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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while((status & 0x8000) != 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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}
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/* Get the Controller Status */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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return (status);
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}
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/**
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* @brief Writes a Half-word buffer to the OneNAND memory.
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* @param pBuffer: pointer to buffer.
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* @param WriteAddr: OneNAND memory internal address from which the data will be
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* written.
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* @param NumHalfwordToWrite: number of half-words to write.
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* @retval OneNAND memory Controller Status.
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*/
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uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
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{
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uint32_t datacounter = 0;
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uint16_t status = 0;
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/* Load the buffer to be written into the DATA RAM0*/
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for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
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{
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*(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter];
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}
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/* Write operation from DATA RAM0 to NAND address*/
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); /* NAND Flash start page address */
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */
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/* Wait till the command is completed */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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while((status & 0x8000) != 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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}
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/* Wait till the write interrupt is set */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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while((status & 0x40) != 0x40)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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}
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/* Get the Controller Status */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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return (status);
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}
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/**
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* @brief Reads a block of data from the OneNAND memory using asynchronous mode.
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* @param pBuffer: pointer to the buffer that receives the data read from the
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* OneNAND memory.
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* @param ReadAddr: OneNAND memory internal address to read from.
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* @param NumHalfwordToRead: number of half-words to read.
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* @retval None
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*/
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void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
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{
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uint16_t datatmp = 0x0, index = 0;
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uint16_t status = 0;
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datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION);
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/* Set the asynchronous read mode */
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OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF));
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/* Load data from the read address to the DATA RAM 1 setor 1 */
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
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/* Wait till the command is completed */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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while((status & 0x8000) != 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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}
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/* Read Controller status */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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/* Read data */
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for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
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{
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/* Read a Halfword from the memory */
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*pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index);
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index++;
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}
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}
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/**
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* @brief Reads a block of data from the OneNAND memory using synchronous mode.
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* @param pBuffer: pointer to the buffer that receives the data read from the
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* OneNAND memory.
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* @param ReadAddr: OneNAND memory internal address to read from.
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* @param NumHalfwordToRead: number of half-words to read.
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* @retval None
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*/
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void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
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{
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uint16_t index = 0;
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uint16_t status = 0;
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/* Set the asynchronous read mode */
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OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0);
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/* Load data from the read address to the DATA RAM 1 setor 1 */
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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*(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
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/* Wait till the command is completed */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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while((status & 0x8000) != 0x8000)
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{
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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}
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/* Read Controller status */
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status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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/* Read data */
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for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
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{
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*pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index));
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index++;
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}
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}
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/**
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* @brief Reads the OneNAND memory Interrupt status.
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* @param None
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* @retval OneNAND memory Interrupt Status.
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*/
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uint16_t OneNAND_ReadStatus(void)
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{
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__IO uint16_t status = 0x0;
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/* Read Status */
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return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT));
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}
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/**
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* @brief Reads the OneNAND Controller status.
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* @param None
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* @retval OneNAND Controller Status.
|
*/
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uint16_t OneNAND_ReadControllerStatus(void)
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{
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__IO uint16_t status = 0x0;
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/* Read Controller Status */
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return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS));
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}
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/**
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* @}
|
*/
|
|
/**
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* @}
|
*/
|
|
/**
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* @}
|
*/
|
|
/**
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* @}
|
*/
|
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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