/*
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******************************************************************************
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* @file lis3dh_reg.h
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* @author Sensors Software Solution Team
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* @brief This file contains all the functions prototypes for the
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* lis3dh_reg.c driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef LIS3DH_REGS_H
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#define LIS3DH_REGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include <stdint.h>
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#include <math.h>
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/** @addtogroup LIS3DH
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* @{
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*
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*/
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/** @defgroup STMicroelectronics sensors common types
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* @{
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*
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*/
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#ifndef MEMS_SHARED_TYPES
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#define MEMS_SHARED_TYPES
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typedef struct{
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uint8_t bit0 : 1;
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uint8_t bit1 : 1;
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uint8_t bit2 : 1;
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uint8_t bit3 : 1;
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uint8_t bit4 : 1;
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uint8_t bit5 : 1;
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uint8_t bit6 : 1;
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uint8_t bit7 : 1;
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} bitwise_t;
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#define PROPERTY_DISABLE (0U)
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#define PROPERTY_ENABLE (1U)
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/** @addtogroup Interfaces_Functions
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* @brief This section provide a set of functions used to read and
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* write a generic register of the device.
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* MANDATORY: return 0 -> no Error.
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* @{
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*
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*/
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typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
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typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
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typedef struct {
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/** Component mandatory fields **/
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stmdev_write_ptr write_reg;
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stmdev_read_ptr read_reg;
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/** Customizable optional pointer **/
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void *handle;
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} stmdev_ctx_t;
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/**
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* @}
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*
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*/
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#endif /* MEMS_SHARED_TYPES */
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#ifndef MEMS_UCF_SHARED_TYPES
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#define MEMS_UCF_SHARED_TYPES
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/** @defgroup Generic address-data structure definition
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* @brief This structure is useful to load a predefined configuration
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* of a sensor.
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* You can create a sensor configuration by your own or using
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* Unico / Unicleo tools available on STMicroelectronics
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* web site.
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*
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* @{
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*
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*/
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typedef struct {
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uint8_t address;
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uint8_t data;
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} ucf_line_t;
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/**
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* @}
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*
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*/
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#endif /* MEMS_UCF_SHARED_TYPES */
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/**
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* @}
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*
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*/
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/** @defgroup LIS3DH_Infos
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* @{
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*
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*/
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/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/
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#define LIS3DH_I2C_ADD_L 0x31U
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#define LIS3DH_I2C_ADD_H 0x33U
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/** Device Identification (Who am I) **/
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#define LIS3DH_ID 0x33U
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/**
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* @}
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*
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*/
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#define LIS3DH_STATUS_REG_AUX 0x07U
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typedef struct {
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uint8_t _1da : 1;
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uint8_t _2da : 1;
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uint8_t _3da : 1;
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uint8_t _321da : 1;
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uint8_t _1or : 1;
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uint8_t _2or : 1;
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uint8_t _3or : 1;
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uint8_t _321or : 1;
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} lis3dh_status_reg_aux_t;
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#define LIS3DH_OUT_ADC1_L 0x08U
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#define LIS3DH_OUT_ADC1_H 0x09U
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#define LIS3DH_OUT_ADC2_L 0x0AU
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#define LIS3DH_OUT_ADC2_H 0x0BU
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#define LIS3DH_OUT_ADC3_L 0x0CU
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#define LIS3DH_OUT_ADC3_H 0x0DU
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#define LIS3DH_WHO_AM_I 0x0FU
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#define LIS3DH_CTRL_REG0 0x1EU
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typedef struct {
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uint8_t not_used_01 : 7;
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uint8_t sdo_pu_disc : 1;
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} lis3dh_ctrl_reg0_t;
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#define LIS3DH_TEMP_CFG_REG 0x1FU
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typedef struct {
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uint8_t not_used_01 : 6;
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uint8_t adc_pd : 1;
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uint8_t temp_en : 1;
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} lis3dh_temp_cfg_reg_t;
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#define LIS3DH_CTRL_REG1 0x20U
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typedef struct {
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uint8_t xen : 1;
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uint8_t yen : 1;
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uint8_t zen : 1;
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uint8_t lpen : 1;
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uint8_t odr : 4;
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} lis3dh_ctrl_reg1_t;
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#define LIS3DH_CTRL_REG2 0x21U
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typedef struct {
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uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
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uint8_t fds : 1;
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uint8_t hpcf : 2;
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uint8_t hpm : 2;
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} lis3dh_ctrl_reg2_t;
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#define LIS3DH_CTRL_REG3 0x22U
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typedef struct {
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uint8_t not_used_01 : 1;
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uint8_t i1_overrun : 1;
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uint8_t i1_wtm : 1;
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uint8_t i1_321da : 1;
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uint8_t i1_zyxda : 1;
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uint8_t i1_ia2 : 1;
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uint8_t i1_ia1 : 1;
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uint8_t i1_click : 1;
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} lis3dh_ctrl_reg3_t;
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#define LIS3DH_CTRL_REG4 0x23U
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typedef struct {
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uint8_t sim : 1;
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uint8_t st : 2;
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uint8_t hr : 1;
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uint8_t fs : 2;
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uint8_t ble : 1;
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uint8_t bdu : 1;
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} lis3dh_ctrl_reg4_t;
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#define LIS3DH_CTRL_REG5 0x24U
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typedef struct {
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uint8_t d4d_int2 : 1;
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uint8_t lir_int2 : 1;
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uint8_t d4d_int1 : 1;
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uint8_t lir_int1 : 1;
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uint8_t not_used_01 : 2;
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uint8_t fifo_en : 1;
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uint8_t boot : 1;
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} lis3dh_ctrl_reg5_t;
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#define LIS3DH_CTRL_REG6 0x25U
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typedef struct {
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uint8_t not_used_01 : 1;
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uint8_t int_polarity : 1;
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uint8_t not_used_02 : 1;
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uint8_t i2_act : 1;
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uint8_t i2_boot : 1;
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uint8_t i2_ia2 : 1;
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uint8_t i2_ia1 : 1;
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uint8_t i2_click : 1;
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} lis3dh_ctrl_reg6_t;
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#define LIS3DH_REFERENCE 0x26U
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#define LIS3DH_STATUS_REG 0x27U
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typedef struct {
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uint8_t xda : 1;
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uint8_t yda : 1;
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uint8_t zda : 1;
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uint8_t zyxda : 1;
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uint8_t _xor : 1;
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uint8_t yor : 1;
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uint8_t zor : 1;
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uint8_t zyxor : 1;
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} lis3dh_status_reg_t;
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#define LIS3DH_OUT_X_L 0x28U
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#define LIS3DH_OUT_X_H 0x29U
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#define LIS3DH_OUT_Y_L 0x2AU
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#define LIS3DH_OUT_Y_H 0x2BU
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#define LIS3DH_OUT_Z_L 0x2CU
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#define LIS3DH_OUT_Z_H 0x2DU
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#define LIS3DH_FIFO_CTRL_REG 0x2EU
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typedef struct {
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uint8_t fth : 5;
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uint8_t tr : 1;
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uint8_t fm : 2;
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} lis3dh_fifo_ctrl_reg_t;
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#define LIS3DH_FIFO_SRC_REG 0x2FU
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typedef struct {
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uint8_t fss : 5;
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uint8_t empty : 1;
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uint8_t ovrn_fifo : 1;
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uint8_t wtm : 1;
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} lis3dh_fifo_src_reg_t;
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#define LIS3DH_INT1_CFG 0x30U
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typedef struct {
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uint8_t xlie : 1;
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uint8_t xhie : 1;
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uint8_t ylie : 1;
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uint8_t yhie : 1;
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uint8_t zlie : 1;
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uint8_t zhie : 1;
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uint8_t _6d : 1;
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uint8_t aoi : 1;
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} lis3dh_int1_cfg_t;
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#define LIS3DH_INT1_SRC 0x31U
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typedef struct {
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uint8_t xl : 1;
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uint8_t xh : 1;
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uint8_t yl : 1;
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uint8_t yh : 1;
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uint8_t zl : 1;
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uint8_t zh : 1;
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uint8_t ia : 1;
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uint8_t not_used_01 : 1;
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} lis3dh_int1_src_t;
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#define LIS3DH_INT1_THS 0x32U
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typedef struct {
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uint8_t ths : 7;
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uint8_t not_used_01 : 1;
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} lis3dh_int1_ths_t;
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#define LIS3DH_INT1_DURATION 0x33U
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typedef struct {
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uint8_t d : 7;
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uint8_t not_used_01 : 1;
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} lis3dh_int1_duration_t;
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#define LIS3DH_INT2_CFG 0x34U
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typedef struct {
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uint8_t xlie : 1;
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uint8_t xhie : 1;
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uint8_t ylie : 1;
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uint8_t yhie : 1;
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uint8_t zlie : 1;
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uint8_t zhie : 1;
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uint8_t _6d : 1;
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uint8_t aoi : 1;
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} lis3dh_int2_cfg_t;
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#define LIS3DH_INT2_SRC 0x35U
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typedef struct {
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uint8_t xl : 1;
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uint8_t xh : 1;
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uint8_t yl : 1;
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uint8_t yh : 1;
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uint8_t zl : 1;
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uint8_t zh : 1;
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uint8_t ia : 1;
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uint8_t not_used_01 : 1;
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} lis3dh_int2_src_t;
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#define LIS3DH_INT2_THS 0x36U
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typedef struct {
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uint8_t ths : 7;
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uint8_t not_used_01 : 1;
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} lis3dh_int2_ths_t;
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#define LIS3DH_INT2_DURATION 0x37U
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typedef struct {
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uint8_t d : 7;
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uint8_t not_used_01 : 1;
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} lis3dh_int2_duration_t;
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#define LIS3DH_CLICK_CFG 0x38U
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typedef struct {
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uint8_t xs : 1;
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uint8_t xd : 1;
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uint8_t ys : 1;
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uint8_t yd : 1;
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uint8_t zs : 1;
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uint8_t zd : 1;
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uint8_t not_used_01 : 2;
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} lis3dh_click_cfg_t;
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#define LIS3DH_CLICK_SRC 0x39U
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typedef struct {
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uint8_t x : 1;
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uint8_t y : 1;
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uint8_t z : 1;
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uint8_t sign : 1;
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uint8_t sclick : 1;
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uint8_t dclick : 1;
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uint8_t ia : 1;
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uint8_t not_used_01 : 1;
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} lis3dh_click_src_t;
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#define LIS3DH_CLICK_THS 0x3AU
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typedef struct {
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uint8_t ths : 7;
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uint8_t lir_click : 1;
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} lis3dh_click_ths_t;
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#define LIS3DH_TIME_LIMIT 0x3BU
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typedef struct {
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uint8_t tli : 7;
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uint8_t not_used_01 : 1;
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} lis3dh_time_limit_t;
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#define LIS3DH_TIME_LATENCY 0x3CU
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typedef struct {
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uint8_t tla : 8;
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} lis3dh_time_latency_t;
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#define LIS3DH_TIME_WINDOW 0x3DU
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typedef struct {
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uint8_t tw : 8;
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} lis3dh_time_window_t;
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#define LIS3DH_ACT_THS 0x3EU
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typedef struct {
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uint8_t acth : 7;
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uint8_t not_used_01 : 1;
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} lis3dh_act_ths_t;
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#define LIS3DH_ACT_DUR 0x3FU
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typedef struct {
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uint8_t actd : 8;
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} lis3dh_act_dur_t;
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/**
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* @defgroup LIS3DH_Register_Union
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* @brief This union group all the registers that has a bitfield
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* description.
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* This union is usefull but not need by the driver.
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*
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* REMOVING this union you are complient with:
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* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
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*
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* @{
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*
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*/
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typedef union{
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lis3dh_status_reg_aux_t status_reg_aux;
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lis3dh_ctrl_reg0_t ctrl_reg0;
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lis3dh_temp_cfg_reg_t temp_cfg_reg;
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lis3dh_ctrl_reg1_t ctrl_reg1;
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lis3dh_ctrl_reg2_t ctrl_reg2;
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lis3dh_ctrl_reg3_t ctrl_reg3;
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lis3dh_ctrl_reg4_t ctrl_reg4;
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lis3dh_ctrl_reg5_t ctrl_reg5;
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lis3dh_ctrl_reg6_t ctrl_reg6;
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lis3dh_status_reg_t status_reg;
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lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
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lis3dh_fifo_src_reg_t fifo_src_reg;
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lis3dh_int1_cfg_t int1_cfg;
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lis3dh_int1_src_t int1_src;
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lis3dh_int1_ths_t int1_ths;
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lis3dh_int1_duration_t int1_duration;
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lis3dh_int2_cfg_t int2_cfg;
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lis3dh_int2_src_t int2_src;
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lis3dh_int2_ths_t int2_ths;
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lis3dh_int2_duration_t int2_duration;
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lis3dh_click_cfg_t click_cfg;
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lis3dh_click_src_t click_src;
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lis3dh_click_ths_t click_ths;
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lis3dh_time_limit_t time_limit;
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lis3dh_time_latency_t time_latency;
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lis3dh_time_window_t time_window;
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lis3dh_act_ths_t act_ths;
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lis3dh_act_dur_t act_dur;
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bitwise_t bitwise;
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uint8_t byte;
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} lis3dh_reg_t;
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/**
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* @}
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*
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*/
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int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
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uint16_t len);
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int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data,
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uint16_t len);
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extern float lis3dh_from_fs2_hr_to_mg(int16_t lsb);
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extern float lis3dh_from_fs4_hr_to_mg(int16_t lsb);
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extern float lis3dh_from_fs8_hr_to_mg(int16_t lsb);
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extern float lis3dh_from_fs16_hr_to_mg(int16_t lsb);
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extern float lis3dh_from_lsb_hr_to_celsius(int16_t lsb);
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extern float lis3dh_from_fs2_nm_to_mg(int16_t lsb);
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extern float lis3dh_from_fs4_nm_to_mg(int16_t lsb);
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extern float lis3dh_from_fs8_nm_to_mg(int16_t lsb);
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extern float lis3dh_from_fs16_nm_to_mg(int16_t lsb);
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extern float lis3dh_from_lsb_nm_to_celsius(int16_t lsb);
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extern float lis3dh_from_fs2_lp_to_mg(int16_t lsb);
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extern float lis3dh_from_fs4_lp_to_mg(int16_t lsb);
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extern float lis3dh_from_fs8_lp_to_mg(int16_t lsb);
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extern float lis3dh_from_fs16_lp_to_mg(int16_t lsb);
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extern float lis3dh_from_lsb_lp_to_celsius(int16_t lsb);
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int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff);
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int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
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int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
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int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, uint16_t *buff);
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int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
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typedef enum {
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LIS3DH_AUX_DISABLE = 0,
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LIS3DH_AUX_ON_TEMPERATURE = 3,
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LIS3DH_AUX_ON_PADS = 1,
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} lis3dh_temp_en_t;
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int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val);
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int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val);
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typedef enum {
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LIS3DH_HR_12bit = 0,
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LIS3DH_NM_10bit = 1,
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LIS3DH_LP_8bit = 2,
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} lis3dh_op_md_t;
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int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx,
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lis3dh_op_md_t val);
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int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx,
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lis3dh_op_md_t *val);
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typedef enum {
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LIS3DH_POWER_DOWN = 0x00,
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LIS3DH_ODR_1Hz = 0x01,
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LIS3DH_ODR_10Hz = 0x02,
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LIS3DH_ODR_25Hz = 0x03,
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LIS3DH_ODR_50Hz = 0x04,
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LIS3DH_ODR_100Hz = 0x05,
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LIS3DH_ODR_200Hz = 0x06,
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LIS3DH_ODR_400Hz = 0x07,
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LIS3DH_ODR_1kHz620_LP = 0x08,
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LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09,
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} lis3dh_odr_t;
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int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val);
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int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val);
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int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val);
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int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val);
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typedef enum {
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LIS3DH_AGGRESSIVE = 0,
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LIS3DH_STRONG = 1,
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LIS3DH_MEDIUM = 2,
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LIS3DH_LIGHT = 3,
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} lis3dh_hpcf_t;
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int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
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lis3dh_hpcf_t val);
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int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
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lis3dh_hpcf_t *val);
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typedef enum {
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LIS3DH_NORMAL_WITH_RST = 0,
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LIS3DH_REFERENCE_MODE = 1,
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LIS3DH_NORMAL = 2,
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LIS3DH_AUTORST_ON_INT = 3,
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} lis3dh_hpm_t;
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int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val);
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int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, lis3dh_hpm_t *val);
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typedef enum {
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LIS3DH_2g = 0,
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LIS3DH_4g = 1,
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LIS3DH_8g = 2,
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LIS3DH_16g = 3,
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} lis3dh_fs_t;
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int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val);
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int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val);
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int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
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int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val);
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int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff);
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int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff);
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int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val);
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int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val);
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int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
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int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
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typedef enum {
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LIS3DH_ST_DISABLE = 0,
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LIS3DH_ST_POSITIVE = 1,
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LIS3DH_ST_NEGATIVE = 2,
|
} lis3dh_st_t;
|
int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val);
|
int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val);
|
|
typedef enum {
|
LIS3DH_LSB_AT_LOW_ADD = 0,
|
LIS3DH_MSB_AT_LOW_ADD = 1,
|
} lis3dh_ble_t;
|
int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val);
|
int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val);
|
|
int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val);
|
|
int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
|
lis3dh_int1_cfg_t *val);
|
int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
|
lis3dh_int1_cfg_t *val);
|
|
int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx,
|
lis3dh_int1_src_t *val);
|
|
int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
|
lis3dh_int2_cfg_t *val);
|
int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
|
lis3dh_int2_cfg_t *val);
|
|
int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx,
|
lis3dh_int2_src_t *val);
|
|
int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
typedef enum {
|
LIS3DH_DISC_FROM_INT_GENERATOR = 0,
|
LIS3DH_ON_INT1_GEN = 1,
|
LIS3DH_ON_INT2_GEN = 2,
|
LIS3DH_ON_TAP_GEN = 4,
|
LIS3DH_ON_INT1_INT2_GEN = 3,
|
LIS3DH_ON_INT1_TAP_GEN = 5,
|
LIS3DH_ON_INT2_TAP_GEN = 6,
|
LIS3DH_ON_INT1_INT2_TAP_GEN = 7,
|
} lis3dh_hp_t;
|
int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
|
lis3dh_hp_t val);
|
int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
|
lis3dh_hp_t *val);
|
|
int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg3_t *val);
|
int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg3_t *val);
|
|
int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
typedef enum {
|
LIS3DH_INT2_PULSED = 0,
|
LIS3DH_INT2_LATCHED = 1,
|
} lis3dh_lir_int2_t;
|
int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_lir_int2_t val);
|
int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_lir_int2_t *val);
|
|
int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
typedef enum {
|
LIS3DH_INT1_PULSED = 0,
|
LIS3DH_INT1_LATCHED = 1,
|
} lis3dh_lir_int1_t;
|
int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_lir_int1_t val);
|
int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_lir_int1_t *val);
|
|
int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg6_t *val);
|
int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg6_t *val);
|
|
int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
typedef enum {
|
LIS3DH_INT1_GEN = 0,
|
LIS3DH_INT2_GEN = 1,
|
} lis3dh_tr_t;
|
int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
|
lis3dh_tr_t val);
|
int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
|
lis3dh_tr_t *val);
|
|
typedef enum {
|
LIS3DH_BYPASS_MODE = 0,
|
LIS3DH_FIFO_MODE = 1,
|
LIS3DH_DYNAMIC_STREAM_MODE = 2,
|
LIS3DH_STREAM_TO_FIFO_MODE = 3,
|
} lis3dh_fm_t;
|
int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val);
|
int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val);
|
|
int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx,
|
lis3dh_fifo_src_reg_t *val);
|
|
int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val);
|
int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val);
|
|
int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx,
|
lis3dh_click_src_t *val);
|
|
int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
typedef enum {
|
LIS3DH_TAP_PULSED = 0,
|
LIS3DH_TAP_LATCHED = 1,
|
} lis3dh_lir_click_t;
|
int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_lir_click_t val);
|
int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_lir_click_t *val);
|
|
int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val);
|
int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val);
|
|
typedef enum {
|
LIS3DH_PULL_UP_DISCONNECT = 0,
|
LIS3DH_PULL_UP_CONNECT = 1,
|
} lis3dh_sdo_pu_disc_t;
|
int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_sdo_pu_disc_t val);
|
int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_sdo_pu_disc_t *val);
|
|
typedef enum {
|
LIS3DH_SPI_4_WIRE = 0,
|
LIS3DH_SPI_3_WIRE = 1,
|
} lis3dh_sim_t;
|
int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val);
|
int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val);
|
|
/**
|
* @}
|
*
|
*/
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /* LIS3DH_REGS_H */
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
