XRange_Tag.git - Gitblit

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C:a9iC9aà:iC:a8iC8aà:iC:a8iC8a h(Ðÿ÷þÿ8i0Ôÿ÷þÿAHBÙ °ð½8iòÕ"àÿ÷þÿ8iÕÿ÷þÿA    HBÙ °ð½à@@@p@8iâÔ(Ñ°k!    C°c`j(dÐ-IÐ%-(Ð0h¨C0`ÿ÷þÿF0hUÕÿ÷þÿ(3Ù Éç0h¨C0`ÿ÷þÿF0h    Õÿ÷þÿÀ(Ù ¹ç0hõÔáj jòhC!ký#CCCð`0h(C0`ÿ÷þÿF0h'Ôÿ÷þÿ(Ù ç0hõÕà0hÃÔà(Ððh!    ¢j@BÑ!âj@BÑ!@!kBÐ |ç zç xç^ð´²&F²^C F7XC6!yAFnC76yA&FnCð¼pGø..\Drivers\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\git\XRange_Tag - À¼ÖÝ»ú³¡\MDK-ARM__asm___19_stm32l0xx_hal_rcc_c_b7071a4b____REV16X> ..\Drivers\CMSIS\Include\cmsis_armcc.hÐø..\Drivers\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\git\XRange_Tag - À¼ÖÝ»ú³¡\MDK-ARM__asm___19_stm32l0xx_hal_rcc_c_b7071a4b____REVSHX> ..\Drivers\CMSIS\Include\cmsis_armcc.hß0ÿÿÿÿarmcc+|     
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../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM@../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMÊ>ÂÝHAL_RCC_DeInitõÊ___resultõ5Ytmpreg¾hZtickstartYi\vl_maskYZstatusõ"l../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM>î»    
HAL_RCC_GetSysClockFreqY___resultY^ZtmpregYÆZpllmY5ZplldY"YpllvcoY\msiclkrangeYZsysclockfreqY³Ä../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMò>ÄÐHAL_RCC_OscConfigõòiRCC_OscInitStructÄe___resultõqZtickstartYÒZhsi_stateY=Zstatusõ´Zsysclk_sourceYGZpll_configYJüYtmpreg¾dÃüðZpwrclkchangedÔ X../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMâ>ØÙHAL_RCC_ClockConfigõâiRCC_ClkInitStructÊiFLatencyYô___resultõ4ZtickstartYÀZstatusõ!../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM?ÞHAL_RCC_MCOConfigiRCC_MCOxYiRCC_MCOSourceYeiRCC_MCODivYGYgpio\ÒvYtmpreg¾Xî&Ytmpreg¾X*PYtmpreg¾Xè../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM?é    HAL_RCC_EnableCSS../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM>
 
HAL_RCC_GetHCLKFreqY^__resultYP../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM>
 
HAL_RCC_GetPCLK1FreqY^__resultYP../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM>
 
HAL_RCC_GetPCLK2FreqY^__resultYP../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM¶?¥
HAL_RCC_GetOscConfig¶iRCC_OscInitStructÄ-../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM:?HAL_RCC_GetClockConfig:iRCC_ClkInitStructÊAipFLatencyÐ.ì../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM?ë¼ HAL_RCC_CSSCallbackì../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM?î«HAL_RCC_NMI_IRQHandlerXN ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cN ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cÝ;"
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zzs!~"(!!#    &&N ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c("((&hN ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cÀN ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c«~}Ê}pvP24PXZP¦¨PÈÊP ÈT}}PTJZPdnPx~P,.P68P:<P>@PbdPvxPP>@P8R<JR}}.} .0}0H} HJ}Jª} ª¬}¬Ð} ÐÒ}Ò"} "$}$l} ln}n¨} ¨ª}ªä} äæ}æ<} <>}>} }À} ÀÂ}Âî} îð}ðF} FH}H¾} ¾À}Àæ} æè}è}ò} dbhP28P$WnW°WÐæW>bWrW<PT\W¼TâP$JPhjPP,0PFJP¨¬PÎÒP $PjnP¦ªPâæP:>PP¾ÂPìðPDHP¼ÀPäP*W0üWÂàP*U0,UP<TPT¼æTêîT}â}ÞàP@BPDFPPPP PÔÖPîðPP:<PPàâP(BVFPV°PVnVQªUPÀT}}N}(NP}P}(RUQHTPT(PPTP}}}}}}}´}´¶}¶P}8}8:}:Q.P}}}__DATE__ "Sep  7 2023"__TIME__ "17:28:43"__STDC__ 1__STDC_VERSION__ 199901L__STDC_HOSTED__ 1__STDC_ISO_10646__ 200607__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060750__TARGET_CPU_CORTEX_M0_ 1__TARGET_FPU_SOFTVFP 1__TARGET_FPU_SOFTVFP 1__MICROLIB 1__UVISION_VERSION 530_RTE_ 1STM32L071xx 1_RTE_ 1USE_HAL_DRIVER 1STM32L071xx 1__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_6S_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 3__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_DMB 1__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0__APCS_INTERWORK 1__thumb 1__thumb__ 1__t32__ 1__OPTIMISE_TIME 1__OPTIMISE_LEVEL 1__SOFTFP__ 1!DÂHAL_RCC_DeInit*pÂHAL_RCC_GetSysClockFreq$ÈÂHAL_RCC_OscConfig&\ÂHAL_RCC_ClockConfig$ÂHAL_RCC_MCOConfig$ìÂHAL_RCC_EnableCSS&ÂHAL_RCC_GetHCLKFreq'ÂHAL_RCC_GetPCLK1Freq'ÂHAL_RCC_GetPCLK2Freq'ÂHAL_RCC_GetOscConfig) ÂHAL_RCC_GetClockConfig&ðÂHAL_RCC_CSSCallback)ðÂHAL_RCC_NMI_IRQHandler]%.(ÿÿÿÿarmcc+|  2A|WÄÅÆÇ`ab__stdint_h __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)INT_FAST8_MIN (~0x7fffffff)INT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)¡INT_FAST8_MAX 2147483647¢INT_FAST16_MAX 2147483647£INT_FAST32_MAX 2147483647¤INT_FAST64_MAX __INT64_C(9223372036854775807)§UINT_FAST8_MAX 4294967295u¨UINT_FAST16_MAX 4294967295u©UINT_FAST32_MAX 4294967295uªUINT_FAST64_MAX __UINT64_C(18446744073709551615)²INTPTR_MIN INT32_MIN¹INTPTR_MAX INT32_MAXÀUINTPTR_MAX UINT32_MAXÆINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)ÉINTMAX_MAX __ESCAPE__(9223372036854775807ll)ÌUINTMAX_MAX __ESCAPE__(18446744073709551615ull)ÕPTRDIFF_MIN INT32_MINÖPTRDIFF_MAX INT32_MAXÚSIG_ATOMIC_MIN (~0x7fffffff)ÛSIG_ATOMIC_MAX 2147483647áSIZE_MAX UINT32_MAXçWCHAR_MINèWCHAR_MAXîWCHAR_MIN 0ïWCHAR_MAX 65535óWINT_MIN (~0x7fffffff)ôWINT_MAX 2147483647ûINT8_C(x) (x)üINT16_C(x) (x)ýINT32_C(x) (x)þINT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)²__INT64³__LONGLONGPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t¢: Pint64_t©; Puint8_t¶> Puint16_tÇ? Puint32_tÙ@ Puint64_téA Pint_least8_tG Pint_least16_tH Pint_least32_t¢I Pint_least64_t©J Puint_least8_t¶M Puint_least16_tÇN Puint_least32_tÙO Puint_least64_téP Pint_fast8_t¢U Pint_fast16_t¢V Pint_fast32_t¢W Pint_fast64_t©X Puint_fast8_tÙ[ Puint_fast16_tÙ\ Puint_fast32_tÙ] Puint_fast64_té^ Pintptr_t¢e Puintptr_tÙf Pintmax_t©j!Puintmax_ték!def __CMSIS_VERSION_H #__CM_CMSIS_VERSION_MAIN ( 5U)$__CM_CMSIS_VERSION_SUB ( 1U)%__CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB )L@ ../Drivers/CMSIS/Include/cmsis_version.h°
../Drivers/CMSIS/Include/cmsis_version.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMhij__CMSIS_ARMCC_H $__ARM_ARCH_6M__ 15__ASM __asm8__INLINE __inline;__STATIC_INLINE static __inline>__STATIC_FORCEINLINE static __forceinlineA__NO_RETURN __declspec(noreturn)D__USED __attribute__((used))G__WEAK __attribute__((weak))J__PACKED __attribute__((packed))M__PACKED_STRUCT __packed structP__PACKED_UNION __packed unionS__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))V__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val))Y__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val))___UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))b__ALIGNED(x) __attribute__((aligned(x)))e__RESTRICT __restrict__NOP __nop__WFI __wfi__WFE __wfe__SEV __sev¢__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U)__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U)¸__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U)Å__REV __reví__ROR __ror÷__BKPT(value) __breakpoint(value)__CLZ __clzH> ../Drivers/CMSIS/Include/cmsis_armcc.h 
../Drivers/CMSIS/Include/cmsis_armcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM;î__get_CONTROLYa__resultYY__regControlYP<¨__set_CONTROL$YcontrolY__regControlYP;ã__get_IPSRYa__resultYY__regIPSRYP;¦__get_APSRYa__resultYY__regAPSRYP;Ù²__get_xPSRYa__resultYY__regXPSRYP;¢¾__get_PSPYa__resultYY__regProcessStackPointerYP<ëÊ__set_PSP$YtopOfProcStackY__regProcessStackPointerYP;±Ö__get_MSPYa__resultYY__regMainStackPointerYP<÷â__set_MSP$YtopOfMainStackY__regMainStackPointerYP;¸î__get_PRIMASKYa__resultYY__regPriMaskYP<òú__set_PRIMASK$YpriMaskY__regPriMaskYP;Ù__get_FPSCRYa__resultY<½ê__set_FPSCR$Yfpscr;9__RBITY$Yvaluea__resultY\resultY\sY;Ðà8__SSAT$val$Ysata__resultÏ\maxP\minP;    ù9__USATY$val$Ysata__resultY    \maxYlmn__CMSIS_COMPILER_H " ../Drivers/CMSIS/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.hstdint.hcmsis_armcc.h°
../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMpqr ARM_MPU_ARMV7_H "ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)#ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)$ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)%ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)&ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)'ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)(ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU))ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)*ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)+ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU),ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)-ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU).ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)/ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)0ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)1ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)2ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)3ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)4ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)5ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)6ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)7ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)8ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)9ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU):ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU);ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)<ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)=ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)?ARM_MPU_AP_NONE 0U@ARM_MPU_AP_PRIV 1UAARM_MPU_AP_URO 2UBARM_MPU_AP_FULL 3UCARM_MPU_AP_PRO 5UDARM_MPU_AP_RO 6UKARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk))XARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))gARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))xARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))ARM_MPU_CACHEP_NOCACHE 0U¤ARM_MPU_CACHEP_WB_WRA 1U©ARM_MPU_CACHEP_WT_NWA 2U®ARM_MPU_CACHEP_WB_NWA 3UH< ../Drivers/CMSIS/Include/mpu_armv7.hL
../Drivers/CMSIS/Include/mpu_armv7.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*ÌRBARY#RASRY#PARM_MPU_Region_t«·<¼ARM_MPU_Enable$YMPU_Control<¨ÈARM_MPU_Disable<ÍÕARM_MPU_ClrRegion$Yrnr<þßARM_MPU_SetRegion$Yrbar$Yrasr<»êARM_MPU_SetRegionEx$Yrnr$Yrbar$Yrasr<ñöorderedCpy$÷dst$src$Ylen\iYtY"ñY"û#<ÅARM_MPU_Load$Itable$YcntsrowWordSizeûÌ"Etuv __CORE_CM0PLUS_H_GENERIC "?B__CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)D__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )G__CORTEX_M (0U)L__FPU_USED 0Us__CORE_CM0PLUS_H_DEPENDANT ¬__I volatile const®__O volatile¯__IO volatile²__IM volatile const³__OM volatile´__IOM volatileàAPSR_N_Pos 31UáAPSR_N_Msk (1UL << APSR_N_Pos)ãAPSR_Z_Pos 30UäAPSR_Z_Msk (1UL << APSR_Z_Pos)æAPSR_C_Pos 29UçAPSR_C_Msk (1UL << APSR_C_Pos)éAPSR_V_Pos 28UêAPSR_V_Msk (1UL << APSR_V_Pos)ûIPSR_ISR_Pos 0UüIPSR_ISR_Msk (0x1FFUL )xPSR_N_Pos 31UxPSR_N_Msk (1UL << xPSR_N_Pos)xPSR_Z_Pos 30UxPSR_Z_Msk (1UL << xPSR_Z_Pos)xPSR_C_Pos 29UxPSR_C_Msk (1UL << xPSR_C_Pos)xPSR_V_Pos 28UxPSR_V_Msk (1UL << xPSR_V_Pos)xPSR_T_Pos 24U xPSR_T_Msk (1UL << xPSR_T_Pos)¢xPSR_ISR_Pos 0U£xPSR_ISR_Msk (0x1FFUL )µCONTROL_SPSEL_Pos 1U¶CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)¸CONTROL_nPRIV_Pos 0U¹CONTROL_nPRIV_Msk (1UL )õSCB_CPUID_IMPLEMENTER_Pos 24UöSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)øSCB_CPUID_VARIANT_Pos 20UùSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)ûSCB_CPUID_ARCHITECTURE_Pos 16UüSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)þSCB_CPUID_PARTNO_Pos 4UÿSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)SCB_CPUID_REVISION_Pos 0USCB_CPUID_REVISION_Msk (0xFUL )SCB_ICSR_NMIPENDSET_Pos 31USCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)SCB_ICSR_PENDSVSET_Pos 28USCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)SCB_ICSR_PENDSVCLR_Pos 27USCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)SCB_ICSR_PENDSTSET_Pos 26USCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)SCB_ICSR_PENDSTCLR_Pos 25USCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)SCB_ICSR_ISRPREEMPT_Pos 23USCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)SCB_ICSR_ISRPENDING_Pos 22USCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)SCB_ICSR_VECTPENDING_Pos 12USCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)SCB_ICSR_VECTACTIVE_Pos 0USCB_ICSR_VECTACTIVE_Msk (0x1FFUL )¢SCB_VTOR_TBLOFF_Pos 8U£SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)§SCB_AIRCR_VECTKEY_Pos 16U¨SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)ªSCB_AIRCR_VECTKEYSTAT_Pos 16U«SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)SCB_AIRCR_ENDIANESS_Pos 15U®SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)°SCB_AIRCR_SYSRESETREQ_Pos 2U±SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)³SCB_AIRCR_VECTCLRACTIVE_Pos 1U´SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)·SCB_SCR_SEVONPEND_Pos 4U¸SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)ºSCB_SCR_SLEEPDEEP_Pos 2U»SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)½SCB_SCR_SLEEPONEXIT_Pos 1U¾SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)ÁSCB_CCR_STKALIGN_Pos 9UÂSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)ÄSCB_CCR_UNALIGN_TRP_Pos 3UÅSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)ÈSCB_SHCSR_SVCALLPENDED_Pos 15UÉSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)áSysTick_CTRL_COUNTFLAG_Pos 16UâSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)äSysTick_CTRL_CLKSOURCE_Pos 2UåSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)çSysTick_CTRL_TICKINT_Pos 1UèSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)êSysTick_CTRL_ENABLE_Pos 0UëSysTick_CTRL_ENABLE_Msk (1UL )îSysTick_LOAD_RELOAD_Pos 0UïSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )òSysTick_VAL_CURRENT_Pos 0UóSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )öSysTick_CALIB_NOREF_Pos 31U÷SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)ùSysTick_CALIB_SKEW_Pos 30UúSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)üSysTick_CALIB_TENMS_Pos 0UýSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )MPU_TYPE_RALIASES 1UMPU_TYPE_IREGION_Pos 16UMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)MPU_TYPE_DREGION_Pos 8UMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)MPU_TYPE_SEPARATE_Pos 0UMPU_TYPE_SEPARATE_Msk (1UL )¢MPU_CTRL_PRIVDEFENA_Pos 2U£MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)¥MPU_CTRL_HFNMIENA_Pos 1U¦MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)¨MPU_CTRL_ENABLE_Pos 0U©MPU_CTRL_ENABLE_Msk (1UL )¬MPU_RNR_REGION_Pos 0UMPU_RNR_REGION_Msk (0xFFUL )°MPU_RBAR_ADDR_Pos 8U±MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)³MPU_RBAR_VALID_Pos 4U´MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)¶MPU_RBAR_REGION_Pos 0U·MPU_RBAR_REGION_Msk (0xFUL )ºMPU_RASR_ATTRS_Pos 16U»MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)½MPU_RASR_XN_Pos 28U¾MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)ÀMPU_RASR_AP_Pos 24UÁMPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)ÃMPU_RASR_TEX_Pos 19UÄMPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)ÆMPU_RASR_S_Pos 18UÇMPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)ÉMPU_RASR_C_Pos 17UÊMPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)ÌMPU_RASR_B_Pos 16UÍMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)ÏMPU_RASR_SRD_Pos 8UÐMPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)ÒMPU_RASR_SIZE_Pos 1UÓMPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)ÕMPU_RASR_ENABLE_Pos 0UÖMPU_RASR_ENABLE_Msk (1UL )ó_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)û_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)SCS_BASE (0xE000E000UL)SysTick_BASE (SCS_BASE + 0x0010UL)NVIC_BASE (SCS_BASE + 0x0100UL)SCB_BASE (SCS_BASE + 0x0D00UL)SCB ((SCB_Type *) SCB_BASE )SysTick ((SysTick_Type *) SysTick_BASE )NVIC ((NVIC_Type *) NVIC_BASE )MPU_BASE (SCS_BASE + 0x0D90UL)MPU ((MPU_Type *) MPU_BASE )µNVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping¶NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping·NVIC_EnableIRQ __NVIC_EnableIRQ¸NVIC_GetEnableIRQ __NVIC_GetEnableIRQ¹NVIC_DisableIRQ __NVIC_DisableIRQºNVIC_GetPendingIRQ __NVIC_GetPendingIRQ»NVIC_SetPendingIRQ __NVIC_SetPendingIRQ¼NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ¾NVIC_SetPriority __NVIC_SetPriority¿NVIC_GetPriority __NVIC_GetPriorityÀNVIC_SystemReset __NVIC_SystemResetÉNVIC_SetVector __NVIC_SetVectorÊNVIC_GetVector __NVIC_GetVectorÍNVIC_USER_IRQ_OFFSET 16ÑEXC_RETURN_HANDLER (0xFFFFFFF1UL)ÒEXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)ÓEXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)Ø_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)Ù_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )Ú_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )Ü__NVIC_SetPriorityGrouping(X) (void)(X)Ý__NVIC_GetPriorityGrouping() (0U)ë°¦ ../Drivers/CMSIS/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm0plus.hstdint.hcmsis_version.hcmsis_compiler.hmpu_armv7.hÜ
../Drivers/CMSIS/Include/core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*!_reserved0Y#!VY#!CY#!ZY#!NY#Sb®wYPAPSR_TypeÝ*Ó!ISRY#    !_reserved0Y#Sæb'wYPIPSR_TypeSø*!ISRY#    !_reserved0Y#!TY#!_reserved1Y#!VY#!CY#!ZY#!NY#SbxwYPxPSR_Type*æ!nPRIVY#!SPSELY#!_reserved1Y#Sùb&wYPCONTROL_Typef²* ISER#³YRESERVED0¨#ÍICERÄ#åYRSERVED1Ú#ÿISPRö#YRESERVED2#²ICPR)#ÊYRESERVED3?#çY?RESERVED4\#IPy#tYPNVIC_TypeÔ*§(CPUID-#ICSR#VTOR#AIRCR#SCR#CCR#RESERVED1Y#SHP#SHCSR#$Yt'PSCB_Type¦ò*÷CTRL#LOAD#VAL#CALIB-#PSysTick_TypeBÞ*Ì    TYPE-#CTRL#RNR#RBAR#RASR#PMPU_Type<
å__NVIC_EnableIRQ$§IRQn;¿
ö__NVIC_GetEnableIRQY$§IRQna__resultY<å
__NVIC_DisableIRQ$§IRQn;£__NVIC_GetPendingIRQY$§IRQna__resultY<Ì¯__NVIC_SetPendingIRQ$§IRQn<÷¾__NVIC_ClearPendingIRQ$§IRQn<Ð__NVIC_SetPriority$§IRQn$Ypriority;éè__NVIC_GetPriorityY$§IRQna__resultY;NVIC_EncodePriorityY$YPriorityGroup$YPreemptPriority$YSubPrioritya__resultY\PriorityGroupTmpY\PreemptPriorityBitsY\SubPriorityBitsY<ËNVIC_DecodePriority$YPriority$YPriorityGroup$ÑpPreemptPriority$ÑpSubPriority\PriorityGroupTmpY\PreemptPriorityBitsY\SubPriorityBitsY"YË<´__NVIC_SetVector$§IRQn$Yvector\vectorsË;ÙÇ__NVIC_GetVectorY$§IRQna__resultY\vectorsË<õ×"__NVIC_SystemReset;¢ÿSCB_GetFPUTypeYa__resultY;ÛSysTick_ConfigY$Yticksa__resultYxyz{__SYSTEM_STM32L0XX_H `W ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h8
../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMqSystemCoreClockY:íÞqAHBPrescTableäÞqAPBPrescTable§ÞqPLLMulTableV<ÆSystemCoreClockíAHBPrescTable
APBPrescTable'PLLMulTable}~$__STM32L071xx_H 1__CM0PLUS_REV 0U2__MPU_PRESENT 1U3__VTOR_PRESENT 1U4__NVIC_PRIO_BITS 2U5__Vendor_SysTickConfig 0UqrsýFLASH_BASE (0x08000000UL)ÿDATA_EEPROM_BASE (0x08080000UL)DATA_EEPROM_BANK2_BASE (0x08080C00UL)DATA_EEPROM_BANK1_END (0x08080BFFUL)DATA_EEPROM_BANK2_END (0x080817FFUL)SRAM_BASE (0x20000000UL)SRAM_SIZE_MAX (0x00005000UL)PERIPH_BASE (0x40000000UL)APBPERIPH_BASE PERIPH_BASEAHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)RTC_BASE (APBPERIPH_BASE + 0x00002800UL)WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)USART2_BASE (APBPERIPH_BASE + 0x00004400UL)LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)USART5_BASE (APBPERIPH_BASE + 0x00005000UL)I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)PWR_BASE (APBPERIPH_BASE + 0x00007000UL)LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)I2C3_BASE (APBPERIPH_BASE + 0x00007800UL)SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)¡COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)¢COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)£EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)¤TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)¥TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)¦FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)§ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)¨ADC_BASE (APBPERIPH_BASE + 0x00012708UL)©SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)ªUSART1_BASE (APBPERIPH_BASE + 0x00013800UL)«DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)®DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)¯DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)°DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)±DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)²DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)³DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)´DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)µDMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)¸RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)¹FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)ºOB_BASE (0x1FF80000UL)»FLASHSIZE_BASE (0x1FF8007CUL)¼UID_BASE (0x1FF80050UL)½CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)¿GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)ÀGPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)ÁGPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)ÂGPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)ÃGPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)ÄGPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)ÎTIM2 ((TIM_TypeDef *) TIM2_BASE)ÏTIM3 ((TIM_TypeDef *) TIM3_BASE)ÐTIM6 ((TIM_TypeDef *) TIM6_BASE)ÑTIM7 ((TIM_TypeDef *) TIM7_BASE)ÒRTC ((RTC_TypeDef *) RTC_BASE)ÓWWDG ((WWDG_TypeDef *) WWDG_BASE)ÔIWDG ((IWDG_TypeDef *) IWDG_BASE)ÕSPI2 ((SPI_TypeDef *) SPI2_BASE)ÖUSART2 ((USART_TypeDef *) USART2_BASE)×LPUART1 ((USART_TypeDef *) LPUART1_BASE)ØI2C1 ((I2C_TypeDef *) I2C1_BASE)ÙI2C2 ((I2C_TypeDef *) I2C2_BASE)ÚI2C3 ((I2C_TypeDef *) I2C3_BASE)ÛPWR ((PWR_TypeDef *) PWR_BASE)ÜLPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)ÝUSART4 ((USART_TypeDef *) USART4_BASE)ÞUSART5 ((USART_TypeDef *) USART5_BASE)àSYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)áCOMP1 ((COMP_TypeDef *) COMP1_BASE)âCOMP2 ((COMP_TypeDef *) COMP2_BASE)ãEXTI ((EXTI_TypeDef *) EXTI_BASE)äTIM21 ((TIM_TypeDef *) TIM21_BASE)åTIM22 ((TIM_TypeDef *) TIM22_BASE)æFIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)çADC1 ((ADC_TypeDef *) ADC1_BASE)èADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)êADC ADC1_COMMONëSPI1 ((SPI_TypeDef *) SPI1_BASE)ìUSART1 ((USART_TypeDef *) USART1_BASE)íDBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)ïDMA1 ((DMA_TypeDef *) DMA1_BASE)ðDMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)ñDMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)òDMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)óDMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)ôDMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)õDMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)öDMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)÷DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)úFLASH ((FLASH_TypeDef *) FLASH_R_BASE)ûOB ((OB_TypeDef *) OB_BASE)üRCC ((RCC_TypeDef *) RCC_BASE)ýCRC ((CRC_TypeDef *) CRC_BASE)ÿGPIOA ((GPIO_TypeDef *) GPIOA_BASE)GPIOB ((GPIO_TypeDef *) GPIOB_BASE)GPIOC ((GPIO_TypeDef *) GPIOC_BASE)GPIOD ((GPIO_TypeDef *) GPIOD_BASE)GPIOE ((GPIO_TypeDef *) GPIOE_BASE)GPIOH ((GPIO_TypeDef *) GPIOH_BASE)LSI_STARTUP_TIME 200U¤ADC_ISR_EOCAL_Pos (11U)¥ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos)¦ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk§ADC_ISR_AWD_Pos (7U)¨ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos)©ADC_ISR_AWD ADC_ISR_AWD_MskªADC_ISR_OVR_Pos (4U)«ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)¬ADC_ISR_OVR ADC_ISR_OVR_MskADC_ISR_EOSEQ_Pos (3U)®ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos)¯ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk°ADC_ISR_EOC_Pos (2U)±ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)²ADC_ISR_EOC ADC_ISR_EOC_Msk³ADC_ISR_EOSMP_Pos (1U)´ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)µADC_ISR_EOSMP ADC_ISR_EOSMP_Msk¶ADC_ISR_ADRDY_Pos (0U)·ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)¸ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk»ADC_ISR_EOS ADC_ISR_EOSEQ¾ADC_IER_EOCALIE_Pos (11U)¿ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos)ÀADC_IER_EOCALIE ADC_IER_EOCALIE_MskÁADC_IER_AWDIE_Pos (7U)ÂADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos)ÃADC_IER_AWDIE ADC_IER_AWDIE_MskÄADC_IER_OVRIE_Pos (4U)ÅADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)ÆADC_IER_OVRIE ADC_IER_OVRIE_MskÇADC_IER_EOSEQIE_Pos (3U)ÈADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos)ÉADC_IER_EOSEQIE ADC_IER_EOSEQIE_MskÊADC_IER_EOCIE_Pos (2U)ËADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)ÌADC_IER_EOCIE ADC_IER_EOCIE_MskÍADC_IER_EOSMPIE_Pos (1U)ÎADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)ÏADC_IER_EOSMPIE ADC_IER_EOSMPIE_MskÐADC_IER_ADRDYIE_Pos (0U)ÑADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)ÒADC_IER_ADRDYIE ADC_IER_ADRDYIE_MskÕADC_IER_EOSIE ADC_IER_EOSEQIEØADC_CR_ADCAL_Pos (31U)ÙADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)ÚADC_CR_ADCAL ADC_CR_ADCAL_MskÛADC_CR_ADVREGEN_Pos (28U)ÜADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)ÝADC_CR_ADVREGEN ADC_CR_ADVREGEN_MskÞADC_CR_ADSTP_Pos (4U)ßADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)àADC_CR_ADSTP ADC_CR_ADSTP_MskáADC_CR_ADSTART_Pos (2U)âADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)ãADC_CR_ADSTART ADC_CR_ADSTART_MskäADC_CR_ADDIS_Pos (1U)åADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)æADC_CR_ADDIS ADC_CR_ADDIS_MskçADC_CR_ADEN_Pos (0U)èADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)éADC_CR_ADEN ADC_CR_ADEN_MskìADC_CFGR1_AWDCH_Pos (26U)íADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos)îADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_MskïADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos)ðADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos)ñADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos)òADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos)óADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos)ôADC_CFGR1_AWDEN_Pos (23U)õADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos)öADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk÷ADC_CFGR1_AWDSGL_Pos (22U)øADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos)ùADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_MskúADC_CFGR1_DISCEN_Pos (16U)ûADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos)üADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_MskýADC_CFGR1_AUTOFF_Pos (15U)þADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos)ÿADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_MskADC_CFGR1_WAIT_Pos (14U)ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos)ADC_CFGR1_WAIT ADC_CFGR1_WAIT_MskADC_CFGR1_CONT_Pos (13U)ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos)ADC_CFGR1_CONT ADC_CFGR1_CONT_MskADC_CFGR1_OVRMOD_Pos (12U)ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos)ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_MskADC_CFGR1_EXTEN_Pos (10U)ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos)ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_MskADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos)ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos)ADC_CFGR1_EXTSEL_Pos (6U)ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos)ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_MskADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos)ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos)ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos)ADC_CFGR1_ALIGN_Pos (5U)ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos)ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_MskADC_CFGR1_RES_Pos (3U)ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)ADC_CFGR1_RES ADC_CFGR1_RES_MskADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos)ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos)ADC_CFGR1_SCANDIR_Pos (2U)ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos)ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_MskADC_CFGR1_DMACFG_Pos (1U) ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)¡ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk¢ADC_CFGR1_DMAEN_Pos (0U)£ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)¤ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk§ADC_CFGR1_AUTDLY ADC_CFGR1_WAITªADC_CFGR2_TOVS_Pos (9U)«ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos)¬ADC_CFGR2_TOVS ADC_CFGR2_TOVS_MskADC_CFGR2_OVSS_Pos (5U)®ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)¯ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk°ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)±ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)²ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)³ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)´ADC_CFGR2_OVSR_Pos (2U)µADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)¶ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk·ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)¸ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)¹ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)ºADC_CFGR2_OVSE_Pos (0U)»ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos)¼ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk½ADC_CFGR2_CKMODE_Pos (30U)¾ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos)¿ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_MskÀADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos)ÁADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos)ÅADC_SMPR_SMP_Pos (0U)ÆADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos)ÇADC_SMPR_SMP ADC_SMPR_SMP_MskÈADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos)ÉADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos)ÊADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos)ÍADC_SMPR_SMPR ADC_SMPR_SMPÎADC_SMPR_SMPR_0 ADC_SMPR_SMP_0ÏADC_SMPR_SMPR_1 ADC_SMPR_SMP_1ÐADC_SMPR_SMPR_2 ADC_SMPR_SMP_2ÓADC_TR_HT_Pos (16U)ÔADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos)ÕADC_TR_HT ADC_TR_HT_MskÖADC_TR_LT_Pos (0U)×ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos)ØADC_TR_LT ADC_TR_LT_MskÛADC_CHSELR_CHSEL_Pos (0U)ÜADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)ÝADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_MskÞADC_CHSELR_CHSEL18_Pos (18U)ßADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos)àADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_MskáADC_CHSELR_CHSEL17_Pos (17U)âADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos)ãADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_MskäADC_CHSELR_CHSEL15_Pos (15U)åADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos)æADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_MskçADC_CHSELR_CHSEL14_Pos (14U)èADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos)éADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_MskêADC_CHSELR_CHSEL13_Pos (13U)ëADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos)ìADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_MskíADC_CHSELR_CHSEL12_Pos (12U)îADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos)ïADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_MskðADC_CHSELR_CHSEL11_Pos (11U)ñADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos)òADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_MskóADC_CHSELR_CHSEL10_Pos (10U)ôADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos)õADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_MsköADC_CHSELR_CHSEL9_Pos (9U)÷ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos)øADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_MskùADC_CHSELR_CHSEL8_Pos (8U)úADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos)ûADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_MsküADC_CHSELR_CHSEL7_Pos (7U)ýADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos)þADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_MskÿADC_CHSELR_CHSEL6_Pos (6U)ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos)ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_MskADC_CHSELR_CHSEL5_Pos (5U)ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos)ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_MskADC_CHSELR_CHSEL4_Pos (4U)ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos)ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_MskADC_CHSELR_CHSEL3_Pos (3U)ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos)ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_MskADC_CHSELR_CHSEL2_Pos (2U)ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos)ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_MskADC_CHSELR_CHSEL1_Pos (1U)ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos)ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_MskADC_CHSELR_CHSEL0_Pos (0U)ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos)ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_MskADC_DR_DATA_Pos (0U)ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)ADC_DR_DATA ADC_DR_DATA_MskADC_CALFACT_CALFACT_Pos (0U)ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos)ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk ADC_CCR_LFMEN_Pos (25U)¡ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos)¢ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk£ADC_CCR_TSEN_Pos (23U)¤ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)¥ADC_CCR_TSEN ADC_CCR_TSEN_Msk¦ADC_CCR_VREFEN_Pos (22U)§ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)¨ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk©ADC_CCR_PRESC_Pos (18U)ªADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)«ADC_CCR_PRESC ADC_CCR_PRESC_Msk¬ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)®ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)¯ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)¸COMP_CSR_COMP1EN_Pos (0U)¹COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos)ºCOMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk»COMP_CSR_COMP1INNSEL_Pos (4U)¼COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos)½COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk¾COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos)¿COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos)ÀCOMP_CSR_COMP1WM_Pos (8U)ÁCOMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos)ÂCOMP_CSR_COMP1WM COMP_CSR_COMP1WM_MskÃCOMP_CSR_COMP1LPTIM1IN1_Pos (12U)ÄCOMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)ÅCOMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_MskÆCOMP_CSR_COMP1POLARITY_Pos (15U)ÇCOMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos)ÈCOMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_MskÉCOMP_CSR_COMP1VALUE_Pos (30U)ÊCOMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos)ËCOMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_MskÌCOMP_CSR_COMP1LOCK_Pos (31U)ÍCOMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos)ÎCOMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_MskÐCOMP_CSR_COMP2EN_Pos (0U)ÑCOMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos)ÒCOMP_CSR_COMP2EN COMP_CSR_COMP2EN_MskÓCOMP_CSR_COMP2SPEED_Pos (3U)ÔCOMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos)ÕCOMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_MskÖCOMP_CSR_COMP2INNSEL_Pos (4U)×COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos)ØCOMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_MskÙCOMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos)ÚCOMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos)ÛCOMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos)ÜCOMP_CSR_COMP2INPSEL_Pos (8U)ÝCOMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos)ÞCOMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_MskßCOMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos)àCOMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos)áCOMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos)âCOMP_CSR_COMP2LPTIM1IN2_Pos (12U)ãCOMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)äCOMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_MskåCOMP_CSR_COMP2LPTIM1IN1_Pos (13U)æCOMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)çCOMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_MskèCOMP_CSR_COMP2POLARITY_Pos (15U)éCOMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos)êCOMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_MskëCOMP_CSR_COMP2VALUE_Pos (30U)ìCOMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos)íCOMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_MskîCOMP_CSR_COMP2LOCK_Pos (31U)ïCOMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos)ðCOMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_MskóCOMP_CSR_COMPxEN_Pos (0U)ôCOMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos)õCOMP_CSR_COMPxEN COMP_CSR_COMPxEN_MsköCOMP_CSR_COMPxPOLARITY_Pos (15U)÷COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)øCOMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_MskùCOMP_CSR_COMPxOUTVALUE_Pos (30U)úCOMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)ûCOMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_MsküCOMP_CSR_COMPxLOCK_Pos (31U)ýCOMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos)þCOMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_MskCOMP_CSR_WINMODE COMP_CSR_COMP1WMCRC_DR_DR_Pos (0U)CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)CRC_DR_DR CRC_DR_DR_MskCRC_IDR_IDR (0xFFU)CRC_CR_RESET_Pos (0U)CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)CRC_CR_RESET CRC_CR_RESET_MskCRC_CR_POLYSIZE_Pos (3U)CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)CRC_CR_POLYSIZE CRC_CR_POLYSIZE_MskCRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)CRC_CR_REV_IN_Pos (5U)CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)CRC_CR_REV_IN CRC_CR_REV_IN_MskCRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)CRC_CR_REV_OUT_Pos (7U)CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk£CRC_INIT_INIT_Pos (0U)¤CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)¥CRC_INIT_INIT CRC_INIT_INIT_Msk¨CRC_POL_POL_Pos (0U)©CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)ªCRC_POL_POL CRC_POL_POL_Msk³DBGMCU_IDCODE_DEV_ID_Pos (0U)´DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)µDBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk·DBGMCU_IDCODE_REV_ID_Pos (16U)¸DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)¹DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_MskºDBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)»DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)¼DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)½DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)¾DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)¿DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)ÀDBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)ÁDBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)ÂDBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)ÃDBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)ÄDBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)ÅDBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)ÆDBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)ÇDBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)ÈDBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)ÉDBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)ÌDBGMCU_CR_DBG_Pos (0U)ÍDBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos)ÎDBGMCU_CR_DBG DBGMCU_CR_DBG_MskÏDBGMCU_CR_DBG_SLEEP_Pos (0U)ÐDBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)ÑDBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_MskÒDBGMCU_CR_DBG_STOP_Pos (1U)ÓDBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)ÔDBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_MskÕDBGMCU_CR_DBG_STANDBY_Pos (2U)ÖDBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)×DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_MskÚDBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)ÛDBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)ÜDBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_MskÝDBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)ÞDBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)ßDBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_MskàDBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)áDBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)âDBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_MskãDBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)äDBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)åDBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_MskæDBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)çDBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)èDBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_MskéDBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)êDBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)ëDBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_MskìDBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)íDBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)îDBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_MskïDBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)ðDBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos)ñDBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_MskòDBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)óDBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos)ôDBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_MskõDBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)öDBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos)÷DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_MskøDBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)ùDBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos)úDBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_MsküDBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)ýDBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos)þDBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_MskÿDBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)    DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos)    DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk    DMA_ISR_GIF1_Pos (0U)    DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)    DMA_ISR_GIF1 DMA_ISR_GIF1_Msk    DMA_ISR_TCIF1_Pos (1U)    DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)    DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk    DMA_ISR_HTIF1_Pos (2U)    DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)    DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk    DMA_ISR_TEIF1_Pos (3U)    DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)    DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk    DMA_ISR_GIF2_Pos (4U)    DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)    DMA_ISR_GIF2 DMA_ISR_GIF2_Msk    DMA_ISR_TCIF2_Pos (5U)    DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)    DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk    DMA_ISR_HTIF2_Pos (6U)    DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)    DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk    DMA_ISR_TEIF2_Pos (7U)     DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)¡    DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk¢    DMA_ISR_GIF3_Pos (8U)£    DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)¤    DMA_ISR_GIF3 DMA_ISR_GIF3_Msk¥    DMA_ISR_TCIF3_Pos (9U)¦    DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)§    DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk¨    DMA_ISR_HTIF3_Pos (10U)©    DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)ª    DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk«    DMA_ISR_TEIF3_Pos (11U)¬    DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)    DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk®    DMA_ISR_GIF4_Pos (12U)¯    DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)°    DMA_ISR_GIF4 DMA_ISR_GIF4_Msk±    DMA_ISR_TCIF4_Pos (13U)²    DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)³    DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk´    DMA_ISR_HTIF4_Pos (14U)µ    DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)¶    DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk·    DMA_ISR_TEIF4_Pos (15U)¸    DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)¹    DMA_ISR_TEIF4 DMA_ISR_TEIF4_Mskº    DMA_ISR_GIF5_Pos (16U)»    DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)¼    DMA_ISR_GIF5 DMA_ISR_GIF5_Msk½    DMA_ISR_TCIF5_Pos (17U)¾    DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)¿    DMA_ISR_TCIF5 DMA_ISR_TCIF5_MskÀ    DMA_ISR_HTIF5_Pos (18U)Á    DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)Â    DMA_ISR_HTIF5 DMA_ISR_HTIF5_MskÃ    DMA_ISR_TEIF5_Pos (19U)Ä    DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)Å    DMA_ISR_TEIF5 DMA_ISR_TEIF5_MskÆ    DMA_ISR_GIF6_Pos (20U)Ç    DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)È    DMA_ISR_GIF6 DMA_ISR_GIF6_MskÉ    DMA_ISR_TCIF6_Pos (21U)Ê    DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)Ë    DMA_ISR_TCIF6 DMA_ISR_TCIF6_MskÌ    DMA_ISR_HTIF6_Pos (22U)Í    DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)Î    DMA_ISR_HTIF6 DMA_ISR_HTIF6_MskÏ    DMA_ISR_TEIF6_Pos (23U)Ð    DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)Ñ    DMA_ISR_TEIF6 DMA_ISR_TEIF6_MskÒ    DMA_ISR_GIF7_Pos (24U)Ó    DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)Ô    DMA_ISR_GIF7 DMA_ISR_GIF7_MskÕ    DMA_ISR_TCIF7_Pos (25U)Ö    DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)×    DMA_ISR_TCIF7 DMA_ISR_TCIF7_MskØ    DMA_ISR_HTIF7_Pos (26U)Ù    DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)Ú    DMA_ISR_HTIF7 DMA_ISR_HTIF7_MskÛ    DMA_ISR_TEIF7_Pos (27U)Ü    DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)Ý    DMA_ISR_TEIF7 DMA_ISR_TEIF7_Mskà    DMA_IFCR_CGIF1_Pos (0U)á    DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)â    DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Mskã    DMA_IFCR_CTCIF1_Pos (1U)ä    DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)å    DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Mskæ    DMA_IFCR_CHTIF1_Pos (2U)ç    DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)è    DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Mské    DMA_IFCR_CTEIF1_Pos (3U)ê    DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)ë    DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Mskì    DMA_IFCR_CGIF2_Pos (4U)í    DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)î    DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Mskï    DMA_IFCR_CTCIF2_Pos (5U)ð    DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)ñ    DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Mskò    DMA_IFCR_CHTIF2_Pos (6U)ó    DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)ô    DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Mskõ    DMA_IFCR_CTEIF2_Pos (7U)ö    DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)÷    DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Mskø    DMA_IFCR_CGIF3_Pos (8U)ù    DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)ú    DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Mskû    DMA_IFCR_CTCIF3_Pos (9U)ü    DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)ý    DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Mskþ    DMA_IFCR_CHTIF3_Pos (10U)ÿ    DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
DMA_IFCR_CTEIF3_Pos (11U)
DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
DMA_IFCR_CGIF4_Pos (12U)
DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
DMA_IFCR_CTCIF4_Pos (13U)
DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
DMA_IFCR_CHTIF4_Pos (14U)
DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
DMA_IFCR_CTEIF4_Pos (15U)
DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
DMA_IFCR_CGIF5_Pos (16U)
DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
DMA_IFCR_CTCIF5_Pos (17U)
DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
DMA_IFCR_CHTIF5_Pos (18U)
DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
DMA_IFCR_CTEIF5_Pos (19U)
DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
DMA_IFCR_CGIF6_Pos (20U)
DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
DMA_IFCR_CTCIF6_Pos (21U) 
DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)¡
DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk¢
DMA_IFCR_CHTIF6_Pos (22U)£
DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)¤
DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk¥
DMA_IFCR_CTEIF6_Pos (23U)¦
DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)§
DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk¨
DMA_IFCR_CGIF7_Pos (24U)©
DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)ª
DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk«
DMA_IFCR_CTCIF7_Pos (25U)¬
DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk®
DMA_IFCR_CHTIF7_Pos (26U)¯
DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)°
DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk±
DMA_IFCR_CTEIF7_Pos (27U)²
DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)³
DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk¶
DMA_CCR_EN_Pos (0U)·
DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)¸
DMA_CCR_EN DMA_CCR_EN_Msk¹
DMA_CCR_TCIE_Pos (1U)º
DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)»
DMA_CCR_TCIE DMA_CCR_TCIE_Msk¼
DMA_CCR_HTIE_Pos (2U)½
DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)¾
DMA_CCR_HTIE DMA_CCR_HTIE_Msk¿
DMA_CCR_TEIE_Pos (3U)À
DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)Á
DMA_CCR_TEIE DMA_CCR_TEIE_MskÂ
DMA_CCR_DIR_Pos (4U)Ã
DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)Ä
DMA_CCR_DIR DMA_CCR_DIR_MskÅ
DMA_CCR_CIRC_Pos (5U)Æ
DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)Ç
DMA_CCR_CIRC DMA_CCR_CIRC_MskÈ
DMA_CCR_PINC_Pos (6U)É
DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)Ê
DMA_CCR_PINC DMA_CCR_PINC_MskË
DMA_CCR_MINC_Pos (7U)Ì
DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)Í
DMA_CCR_MINC DMA_CCR_MINC_MskÏ
DMA_CCR_PSIZE_Pos (8U)Ð
DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)Ñ
DMA_CCR_PSIZE DMA_CCR_PSIZE_MskÒ
DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)Ó
DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)Õ
DMA_CCR_MSIZE_Pos (10U)Ö
DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)×
DMA_CCR_MSIZE DMA_CCR_MSIZE_MskØ
DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)Ù
DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)Û
DMA_CCR_PL_Pos (12U)Ü
DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)Ý
DMA_CCR_PL DMA_CCR_PL_MskÞ
DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)ß
DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)á
DMA_CCR_MEM2MEM_Pos (14U)â
DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)ã
DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Mskæ
DMA_CNDTR_NDT_Pos (0U)ç
DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)è
DMA_CNDTR_NDT DMA_CNDTR_NDT_Mskë
DMA_CPAR_PA_Pos (0U)ì
DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)í
DMA_CPAR_PA DMA_CPAR_PA_Mskð
DMA_CMAR_MA_Pos (0U)ñ
DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)ò
DMA_CMAR_MA DMA_CMAR_MA_Mskö
DMA_CSELR_C1S_Pos (0U)÷
DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos)ø
DMA_CSELR_C1S DMA_CSELR_C1S_Mskù
DMA_CSELR_C2S_Pos (4U)ú
DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos)û
DMA_CSELR_C2S DMA_CSELR_C2S_Mskü
DMA_CSELR_C3S_Pos (8U)ý
DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos)þ
DMA_CSELR_C3S DMA_CSELR_C3S_Mskÿ
DMA_CSELR_C4S_Pos (12U)DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos)DMA_CSELR_C4S DMA_CSELR_C4S_MskDMA_CSELR_C5S_Pos (16U)DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos)DMA_CSELR_C5S DMA_CSELR_C5S_MskDMA_CSELR_C6S_Pos (20U)DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos)DMA_CSELR_C6S DMA_CSELR_C6S_MskDMA_CSELR_C7S_Pos (24U)DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos)DMA_CSELR_C7S DMA_CSELR_C7S_MskEXTI_IMR_IM0_Pos (0U)EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos)EXTI_IMR_IM0 EXTI_IMR_IM0_MskEXTI_IMR_IM1_Pos (1U)EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos)EXTI_IMR_IM1 EXTI_IMR_IM1_MskEXTI_IMR_IM2_Pos (2U)EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos)EXTI_IMR_IM2 EXTI_IMR_IM2_MskEXTI_IMR_IM3_Pos (3U)EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos)EXTI_IMR_IM3 EXTI_IMR_IM3_MskEXTI_IMR_IM4_Pos (4U) EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos)¡EXTI_IMR_IM4 EXTI_IMR_IM4_Msk¢EXTI_IMR_IM5_Pos (5U)£EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos)¤EXTI_IMR_IM5 EXTI_IMR_IM5_Msk¥EXTI_IMR_IM6_Pos (6U)¦EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos)§EXTI_IMR_IM6 EXTI_IMR_IM6_Msk¨EXTI_IMR_IM7_Pos (7U)©EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos)ªEXTI_IMR_IM7 EXTI_IMR_IM7_Msk«EXTI_IMR_IM8_Pos (8U)¬EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos)EXTI_IMR_IM8 EXTI_IMR_IM8_Msk®EXTI_IMR_IM9_Pos (9U)¯EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos)°EXTI_IMR_IM9 EXTI_IMR_IM9_Msk±EXTI_IMR_IM10_Pos (10U)²EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos)³EXTI_IMR_IM10 EXTI_IMR_IM10_Msk´EXTI_IMR_IM11_Pos (11U)µEXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos)¶EXTI_IMR_IM11 EXTI_IMR_IM11_Msk·EXTI_IMR_IM12_Pos (12U)¸EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos)¹EXTI_IMR_IM12 EXTI_IMR_IM12_MskºEXTI_IMR_IM13_Pos (13U)»EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos)¼EXTI_IMR_IM13 EXTI_IMR_IM13_Msk½EXTI_IMR_IM14_Pos (14U)¾EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos)¿EXTI_IMR_IM14 EXTI_IMR_IM14_MskÀEXTI_IMR_IM15_Pos (15U)ÁEXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos)ÂEXTI_IMR_IM15 EXTI_IMR_IM15_MskÃEXTI_IMR_IM16_Pos (16U)ÄEXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos)ÅEXTI_IMR_IM16 EXTI_IMR_IM16_MskÆEXTI_IMR_IM17_Pos (17U)ÇEXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos)ÈEXTI_IMR_IM17 EXTI_IMR_IM17_MskÉEXTI_IMR_IM18_Pos (18U)ÊEXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos)ËEXTI_IMR_IM18 EXTI_IMR_IM18_MskÌEXTI_IMR_IM19_Pos (19U)ÍEXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos)ÎEXTI_IMR_IM19 EXTI_IMR_IM19_MskÏEXTI_IMR_IM20_Pos (20U)ÐEXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos)ÑEXTI_IMR_IM20 EXTI_IMR_IM20_MskÒEXTI_IMR_IM21_Pos (21U)ÓEXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos)ÔEXTI_IMR_IM21 EXTI_IMR_IM21_MskÕEXTI_IMR_IM22_Pos (22U)ÖEXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos)×EXTI_IMR_IM22 EXTI_IMR_IM22_MskØEXTI_IMR_IM23_Pos (23U)ÙEXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos)ÚEXTI_IMR_IM23 EXTI_IMR_IM23_MskÛEXTI_IMR_IM24_Pos (24U)ÜEXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos)ÝEXTI_IMR_IM24 EXTI_IMR_IM24_MskÞEXTI_IMR_IM25_Pos (25U)ßEXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos)àEXTI_IMR_IM25 EXTI_IMR_IM25_MskáEXTI_IMR_IM26_Pos (26U)âEXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos)ãEXTI_IMR_IM26 EXTI_IMR_IM26_MskäEXTI_IMR_IM28_Pos (28U)åEXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos)æEXTI_IMR_IM28 EXTI_IMR_IM28_MskçEXTI_IMR_IM29_Pos (29U)èEXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos)éEXTI_IMR_IM29 EXTI_IMR_IM29_MskëEXTI_IMR_IM_Pos (0U)ìEXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos)íEXTI_IMR_IM EXTI_IMR_IM_MskðEXTI_EMR_EM0_Pos (0U)ñEXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos)òEXTI_EMR_EM0 EXTI_EMR_EM0_MskóEXTI_EMR_EM1_Pos (1U)ôEXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos)õEXTI_EMR_EM1 EXTI_EMR_EM1_MsköEXTI_EMR_EM2_Pos (2U)÷EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos)øEXTI_EMR_EM2 EXTI_EMR_EM2_MskùEXTI_EMR_EM3_Pos (3U)úEXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos)ûEXTI_EMR_EM3 EXTI_EMR_EM3_MsküEXTI_EMR_EM4_Pos (4U)ýEXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos)þEXTI_EMR_EM4 EXTI_EMR_EM4_MskÿEXTI_EMR_EM5_Pos (5U)EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos)EXTI_EMR_EM5 EXTI_EMR_EM5_MskEXTI_EMR_EM6_Pos (6U)EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos)EXTI_EMR_EM6 EXTI_EMR_EM6_MskEXTI_EMR_EM7_Pos (7U)EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos)EXTI_EMR_EM7 EXTI_EMR_EM7_MskEXTI_EMR_EM8_Pos (8U)EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos)EXTI_EMR_EM8 EXTI_EMR_EM8_MskEXTI_EMR_EM9_Pos (9U)EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos)EXTI_EMR_EM9 EXTI_EMR_EM9_MskEXTI_EMR_EM10_Pos (10U)EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos)EXTI_EMR_EM10 EXTI_EMR_EM10_MskEXTI_EMR_EM11_Pos (11U)EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos)EXTI_EMR_EM11 EXTI_EMR_EM11_MskEXTI_EMR_EM12_Pos (12U)EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos)EXTI_EMR_EM12 EXTI_EMR_EM12_MskEXTI_EMR_EM13_Pos (13U)EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos)EXTI_EMR_EM13 EXTI_EMR_EM13_MskEXTI_EMR_EM14_Pos (14U)EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos)EXTI_EMR_EM14 EXTI_EMR_EM14_MskEXTI_EMR_EM15_Pos (15U)EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos)EXTI_EMR_EM15 EXTI_EMR_EM15_Msk EXTI_EMR_EM16_Pos (16U)¡EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos)¢EXTI_EMR_EM16 EXTI_EMR_EM16_Msk£EXTI_EMR_EM17_Pos (17U)¤EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos)¥EXTI_EMR_EM17 EXTI_EMR_EM17_Msk¦EXTI_EMR_EM18_Pos (18U)§EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos)¨EXTI_EMR_EM18 EXTI_EMR_EM18_Msk©EXTI_EMR_EM19_Pos (19U)ªEXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos)«EXTI_EMR_EM19 EXTI_EMR_EM19_Msk¬EXTI_EMR_EM20_Pos (20U)EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos)®EXTI_EMR_EM20 EXTI_EMR_EM20_Msk¯EXTI_EMR_EM21_Pos (21U)°EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos)±EXTI_EMR_EM21 EXTI_EMR_EM21_Msk²EXTI_EMR_EM22_Pos (22U)³EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos)´EXTI_EMR_EM22 EXTI_EMR_EM22_MskµEXTI_EMR_EM23_Pos (23U)¶EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos)·EXTI_EMR_EM23 EXTI_EMR_EM23_Msk¸EXTI_EMR_EM24_Pos (24U)¹EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos)ºEXTI_EMR_EM24 EXTI_EMR_EM24_Msk»EXTI_EMR_EM25_Pos (25U)¼EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos)½EXTI_EMR_EM25 EXTI_EMR_EM25_Msk¾EXTI_EMR_EM26_Pos (26U)¿EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos)ÀEXTI_EMR_EM26 EXTI_EMR_EM26_MskÁEXTI_EMR_EM28_Pos (28U)ÂEXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos)ÃEXTI_EMR_EM28 EXTI_EMR_EM28_MskÄEXTI_EMR_EM29_Pos (29U)ÅEXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos)ÆEXTI_EMR_EM29 EXTI_EMR_EM29_MskÉEXTI_RTSR_RT0_Pos (0U)ÊEXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos)ËEXTI_RTSR_RT0 EXTI_RTSR_RT0_MskÌEXTI_RTSR_RT1_Pos (1U)ÍEXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos)ÎEXTI_RTSR_RT1 EXTI_RTSR_RT1_MskÏEXTI_RTSR_RT2_Pos (2U)ÐEXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos)ÑEXTI_RTSR_RT2 EXTI_RTSR_RT2_MskÒEXTI_RTSR_RT3_Pos (3U)ÓEXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos)ÔEXTI_RTSR_RT3 EXTI_RTSR_RT3_MskÕEXTI_RTSR_RT4_Pos (4U)ÖEXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos)×EXTI_RTSR_RT4 EXTI_RTSR_RT4_MskØEXTI_RTSR_RT5_Pos (5U)ÙEXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos)ÚEXTI_RTSR_RT5 EXTI_RTSR_RT5_MskÛEXTI_RTSR_RT6_Pos (6U)ÜEXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos)ÝEXTI_RTSR_RT6 EXTI_RTSR_RT6_MskÞEXTI_RTSR_RT7_Pos (7U)ßEXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos)àEXTI_RTSR_RT7 EXTI_RTSR_RT7_MskáEXTI_RTSR_RT8_Pos (8U)âEXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos)ãEXTI_RTSR_RT8 EXTI_RTSR_RT8_MskäEXTI_RTSR_RT9_Pos (9U)åEXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos)æEXTI_RTSR_RT9 EXTI_RTSR_RT9_MskçEXTI_RTSR_RT10_Pos (10U)èEXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos)éEXTI_RTSR_RT10 EXTI_RTSR_RT10_MskêEXTI_RTSR_RT11_Pos (11U)ëEXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos)ìEXTI_RTSR_RT11 EXTI_RTSR_RT11_MskíEXTI_RTSR_RT12_Pos (12U)îEXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos)ïEXTI_RTSR_RT12 EXTI_RTSR_RT12_MskðEXTI_RTSR_RT13_Pos (13U)ñEXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos)òEXTI_RTSR_RT13 EXTI_RTSR_RT13_MskóEXTI_RTSR_RT14_Pos (14U)ôEXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos)õEXTI_RTSR_RT14 EXTI_RTSR_RT14_MsköEXTI_RTSR_RT15_Pos (15U)÷EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos)øEXTI_RTSR_RT15 EXTI_RTSR_RT15_MskùEXTI_RTSR_RT16_Pos (16U)úEXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos)ûEXTI_RTSR_RT16 EXTI_RTSR_RT16_MsküEXTI_RTSR_RT17_Pos (17U)ýEXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos)þEXTI_RTSR_RT17 EXTI_RTSR_RT17_MskÿEXTI_RTSR_RT19_Pos (19U) EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk EXTI_RTSR_RT20_Pos (20U) EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk EXTI_RTSR_RT21_Pos (21U) EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk EXTI_RTSR_RT22_Pos (22U) EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk EXTI_RTSR_TR0 EXTI_RTSR_RT0 EXTI_RTSR_TR1 EXTI_RTSR_RT1 EXTI_RTSR_TR2 EXTI_RTSR_RT2 EXTI_RTSR_TR3 EXTI_RTSR_RT3 EXTI_RTSR_TR4 EXTI_RTSR_RT4 EXTI_RTSR_TR5 EXTI_RTSR_RT5 EXTI_RTSR_TR6 EXTI_RTSR_RT6 EXTI_RTSR_TR7 EXTI_RTSR_RT7 EXTI_RTSR_TR8 EXTI_RTSR_RT8 EXTI_RTSR_TR9 EXTI_RTSR_RT9 EXTI_RTSR_TR10 EXTI_RTSR_RT10 EXTI_RTSR_TR11 EXTI_RTSR_RT11 EXTI_RTSR_TR12 EXTI_RTSR_RT12 EXTI_RTSR_TR13 EXTI_RTSR_RT13 EXTI_RTSR_TR14 EXTI_RTSR_RT14 EXTI_RTSR_TR15 EXTI_RTSR_RT15 EXTI_RTSR_TR16 EXTI_RTSR_RT16 EXTI_RTSR_TR17 EXTI_RTSR_RT17 EXTI_RTSR_TR19 EXTI_RTSR_RT19  EXTI_RTSR_TR20 EXTI_RTSR_RT20¡ EXTI_RTSR_TR21 EXTI_RTSR_RT21¢ EXTI_RTSR_TR22 EXTI_RTSR_RT22¥ EXTI_FTSR_FT0_Pos (0U)¦ EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos)§ EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk¨ EXTI_FTSR_FT1_Pos (1U)© EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos)ª EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk« EXTI_FTSR_FT2_Pos (2U)¬ EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk® EXTI_FTSR_FT3_Pos (3U)¯ EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos)° EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk± EXTI_FTSR_FT4_Pos (4U)² EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos)³ EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk´ EXTI_FTSR_FT5_Pos (5U)µ EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos)¶ EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk· EXTI_FTSR_FT6_Pos (6U)¸ EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos)¹ EXTI_FTSR_FT6 EXTI_FTSR_FT6_Mskº EXTI_FTSR_FT7_Pos (7U)» EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos)¼ EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk½ EXTI_FTSR_FT8_Pos (8U)¾ EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos)¿ EXTI_FTSR_FT8 EXTI_FTSR_FT8_MskÀ EXTI_FTSR_FT9_Pos (9U)Á EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos)Â EXTI_FTSR_FT9 EXTI_FTSR_FT9_MskÃ EXTI_FTSR_FT10_Pos (10U)Ä EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos)Å EXTI_FTSR_FT10 EXTI_FTSR_FT10_MskÆ EXTI_FTSR_FT11_Pos (11U)Ç EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos)È EXTI_FTSR_FT11 EXTI_FTSR_FT11_MskÉ EXTI_FTSR_FT12_Pos (12U)Ê EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos)Ë EXTI_FTSR_FT12 EXTI_FTSR_FT12_MskÌ EXTI_FTSR_FT13_Pos (13U)Í EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos)Î EXTI_FTSR_FT13 EXTI_FTSR_FT13_MskÏ EXTI_FTSR_FT14_Pos (14U)Ð EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos)Ñ EXTI_FTSR_FT14 EXTI_FTSR_FT14_MskÒ EXTI_FTSR_FT15_Pos (15U)Ó EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos)Ô EXTI_FTSR_FT15 EXTI_FTSR_FT15_MskÕ EXTI_FTSR_FT16_Pos (16U)Ö EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos)× EXTI_FTSR_FT16 EXTI_FTSR_FT16_MskØ EXTI_FTSR_FT17_Pos (17U)Ù EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos)Ú EXTI_FTSR_FT17 EXTI_FTSR_FT17_MskÛ EXTI_FTSR_FT19_Pos (19U)Ü EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos)Ý EXTI_FTSR_FT19 EXTI_FTSR_FT19_MskÞ EXTI_FTSR_FT20_Pos (20U)ß EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos)à EXTI_FTSR_FT20 EXTI_FTSR_FT20_Mská EXTI_FTSR_FT21_Pos (21U)â EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos)ã EXTI_FTSR_FT21 EXTI_FTSR_FT21_Mskä EXTI_FTSR_FT22_Pos (22U)å EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos)æ EXTI_FTSR_FT22 EXTI_FTSR_FT22_Mské EXTI_FTSR_TR0 EXTI_FTSR_FT0ê EXTI_FTSR_TR1 EXTI_FTSR_FT1ë EXTI_FTSR_TR2 EXTI_FTSR_FT2ì EXTI_FTSR_TR3 EXTI_FTSR_FT3í EXTI_FTSR_TR4 EXTI_FTSR_FT4î EXTI_FTSR_TR5 EXTI_FTSR_FT5ï EXTI_FTSR_TR6 EXTI_FTSR_FT6ð EXTI_FTSR_TR7 EXTI_FTSR_FT7ñ EXTI_FTSR_TR8 EXTI_FTSR_FT8ò EXTI_FTSR_TR9 EXTI_FTSR_FT9ó EXTI_FTSR_TR10 EXTI_FTSR_FT10ô EXTI_FTSR_TR11 EXTI_FTSR_FT11õ EXTI_FTSR_TR12 EXTI_FTSR_FT12ö EXTI_FTSR_TR13 EXTI_FTSR_FT13÷ EXTI_FTSR_TR14 EXTI_FTSR_FT14ø EXTI_FTSR_TR15 EXTI_FTSR_FT15ù EXTI_FTSR_TR16 EXTI_FTSR_FT16ú EXTI_FTSR_TR17 EXTI_FTSR_FT17û EXTI_FTSR_TR19 EXTI_FTSR_FT19ü EXTI_FTSR_TR20 EXTI_FTSR_FT20ý EXTI_FTSR_TR21 EXTI_FTSR_FT21þ EXTI_FTSR_TR22 EXTI_FTSR_FT22EXTI_SWIER_SWI0_Pos (0U)EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos)EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_MskEXTI_SWIER_SWI1_Pos (1U)EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos)EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_MskEXTI_SWIER_SWI2_Pos (2U)EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos)EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_MskEXTI_SWIER_SWI3_Pos (3U)EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos)EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_MskEXTI_SWIER_SWI4_Pos (4U)EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos)EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_MskEXTI_SWIER_SWI5_Pos (5U)EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos)EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_MskEXTI_SWIER_SWI6_Pos (6U)EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos)EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_MskEXTI_SWIER_SWI7_Pos (7U)EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos)EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_MskEXTI_SWIER_SWI8_Pos (8U)EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos)EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_MskEXTI_SWIER_SWI9_Pos (9U)EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos)EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_MskEXTI_SWIER_SWI10_Pos (10U) EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos)¡EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk¢EXTI_SWIER_SWI11_Pos (11U)£EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos)¤EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk¥EXTI_SWIER_SWI12_Pos (12U)¦EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos)§EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk¨EXTI_SWIER_SWI13_Pos (13U)©EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos)ªEXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk«EXTI_SWIER_SWI14_Pos (14U)¬EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos)EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk®EXTI_SWIER_SWI15_Pos (15U)¯EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos)°EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk±EXTI_SWIER_SWI16_Pos (16U)²EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos)³EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk´EXTI_SWIER_SWI17_Pos (17U)µEXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos)¶EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk·EXTI_SWIER_SWI19_Pos (19U)¸EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos)¹EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_MskºEXTI_SWIER_SWI20_Pos (20U)»EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos)¼EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk½EXTI_SWIER_SWI21_Pos (21U)¾EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos)¿EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_MskÀEXTI_SWIER_SWI22_Pos (22U)ÁEXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos)ÂEXTI_SWIER_SWI22 EXTI_SWIER_SWI22_MskÅEXTI_SWIER_SWIER0 EXTI_SWIER_SWI0ÆEXTI_SWIER_SWIER1 EXTI_SWIER_SWI1ÇEXTI_SWIER_SWIER2 EXTI_SWIER_SWI2ÈEXTI_SWIER_SWIER3 EXTI_SWIER_SWI3ÉEXTI_SWIER_SWIER4 EXTI_SWIER_SWI4ÊEXTI_SWIER_SWIER5 EXTI_SWIER_SWI5ËEXTI_SWIER_SWIER6 EXTI_SWIER_SWI6ÌEXTI_SWIER_SWIER7 EXTI_SWIER_SWI7ÍEXTI_SWIER_SWIER8 EXTI_SWIER_SWI8ÎEXTI_SWIER_SWIER9 EXTI_SWIER_SWI9ÏEXTI_SWIER_SWIER10 EXTI_SWIER_SWI10ÐEXTI_SWIER_SWIER11 EXTI_SWIER_SWI11ÑEXTI_SWIER_SWIER12 EXTI_SWIER_SWI12ÒEXTI_SWIER_SWIER13 EXTI_SWIER_SWI13ÓEXTI_SWIER_SWIER14 EXTI_SWIER_SWI14ÔEXTI_SWIER_SWIER15 EXTI_SWIER_SWI15ÕEXTI_SWIER_SWIER16 EXTI_SWIER_SWI16ÖEXTI_SWIER_SWIER17 EXTI_SWIER_SWI17×EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19ØEXTI_SWIER_SWIER20 EXTI_SWIER_SWI20ÙEXTI_SWIER_SWIER21 EXTI_SWIER_SWI21ÚEXTI_SWIER_SWIER22 EXTI_SWIER_SWI22ÝEXTI_PR_PIF0_Pos (0U)ÞEXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos)ßEXTI_PR_PIF0 EXTI_PR_PIF0_MskàEXTI_PR_PIF1_Pos (1U)áEXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos)âEXTI_PR_PIF1 EXTI_PR_PIF1_MskãEXTI_PR_PIF2_Pos (2U)äEXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos)åEXTI_PR_PIF2 EXTI_PR_PIF2_MskæEXTI_PR_PIF3_Pos (3U)çEXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos)èEXTI_PR_PIF3 EXTI_PR_PIF3_MskéEXTI_PR_PIF4_Pos (4U)êEXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos)ëEXTI_PR_PIF4 EXTI_PR_PIF4_MskìEXTI_PR_PIF5_Pos (5U)íEXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos)îEXTI_PR_PIF5 EXTI_PR_PIF5_MskïEXTI_PR_PIF6_Pos (6U)ðEXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos)ñEXTI_PR_PIF6 EXTI_PR_PIF6_MskòEXTI_PR_PIF7_Pos (7U)óEXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos)ôEXTI_PR_PIF7 EXTI_PR_PIF7_MskõEXTI_PR_PIF8_Pos (8U)öEXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos)÷EXTI_PR_PIF8 EXTI_PR_PIF8_MskøEXTI_PR_PIF9_Pos (9U)ùEXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos)úEXTI_PR_PIF9 EXTI_PR_PIF9_MskûEXTI_PR_PIF10_Pos (10U)üEXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos)ýEXTI_PR_PIF10 EXTI_PR_PIF10_MskþEXTI_PR_PIF11_Pos (11U)ÿEXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos)EXTI_PR_PIF11 EXTI_PR_PIF11_MskEXTI_PR_PIF12_Pos (12U)EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos)EXTI_PR_PIF12 EXTI_PR_PIF12_MskEXTI_PR_PIF13_Pos (13U)EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos)EXTI_PR_PIF13 EXTI_PR_PIF13_MskEXTI_PR_PIF14_Pos (14U)EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos)EXTI_PR_PIF14 EXTI_PR_PIF14_MskEXTI_PR_PIF15_Pos (15U)EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos)EXTI_PR_PIF15 EXTI_PR_PIF15_MskEXTI_PR_PIF16_Pos (16U)EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos)EXTI_PR_PIF16 EXTI_PR_PIF16_MskEXTI_PR_PIF17_Pos (17U)EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos)EXTI_PR_PIF17 EXTI_PR_PIF17_MskEXTI_PR_PIF19_Pos (19U)EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos)EXTI_PR_PIF19 EXTI_PR_PIF19_MskEXTI_PR_PIF20_Pos (20U)EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos)EXTI_PR_PIF20 EXTI_PR_PIF20_MskEXTI_PR_PIF21_Pos (21U)EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos)EXTI_PR_PIF21 EXTI_PR_PIF21_MskEXTI_PR_PIF22_Pos (22U)EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos)EXTI_PR_PIF22 EXTI_PR_PIF22_Msk¡EXTI_PR_PR0 EXTI_PR_PIF0¢EXTI_PR_PR1 EXTI_PR_PIF1£EXTI_PR_PR2 EXTI_PR_PIF2¤EXTI_PR_PR3 EXTI_PR_PIF3¥EXTI_PR_PR4 EXTI_PR_PIF4¦EXTI_PR_PR5 EXTI_PR_PIF5§EXTI_PR_PR6 EXTI_PR_PIF6¨EXTI_PR_PR7 EXTI_PR_PIF7©EXTI_PR_PR8 EXTI_PR_PIF8ªEXTI_PR_PR9 EXTI_PR_PIF9«EXTI_PR_PR10 EXTI_PR_PIF10¬EXTI_PR_PR11 EXTI_PR_PIF11EXTI_PR_PR12 EXTI_PR_PIF12®EXTI_PR_PR13 EXTI_PR_PIF13¯EXTI_PR_PR14 EXTI_PR_PIF14°EXTI_PR_PR15 EXTI_PR_PIF15±EXTI_PR_PR16 EXTI_PR_PIF16²EXTI_PR_PR17 EXTI_PR_PIF17³EXTI_PR_PR19 EXTI_PR_PIF19´EXTI_PR_PR20 EXTI_PR_PIF20µEXTI_PR_PR21 EXTI_PR_PIF21¶EXTI_PR_PR22 EXTI_PR_PIF22¿FLASH_ACR_LATENCY_Pos (0U)ÀFLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos)ÁFLASH_ACR_LATENCY FLASH_ACR_LATENCY_MskÂFLASH_ACR_PRFTEN_Pos (1U)ÃFLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)ÄFLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_MskÅFLASH_ACR_SLEEP_PD_Pos (3U)ÆFLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)ÇFLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_MskÈFLASH_ACR_RUN_PD_Pos (4U)ÉFLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)ÊFLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_MskËFLASH_ACR_DISAB_BUF_Pos (5U)ÌFLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos)ÍFLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_MskÎFLASH_ACR_PRE_READ_Pos (6U)ÏFLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos)ÐFLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_MskÓFLASH_PECR_PELOCK_Pos (0U)ÔFLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos)ÕFLASH_PECR_PELOCK FLASH_PECR_PELOCK_MskÖFLASH_PECR_PRGLOCK_Pos (1U)×FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos)ØFLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_MskÙFLASH_PECR_OPTLOCK_Pos (2U)ÚFLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos)ÛFLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_MskÜFLASH_PECR_PROG_Pos (3U)ÝFLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos)ÞFLASH_PECR_PROG FLASH_PECR_PROG_MskßFLASH_PECR_DATA_Pos (4U)àFLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos)áFLASH_PECR_DATA FLASH_PECR_DATA_MskâFLASH_PECR_FIX_Pos (8U)ãFLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos)äFLASH_PECR_FIX FLASH_PECR_FIX_MskåFLASH_PECR_ERASE_Pos (9U)æFLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos)çFLASH_PECR_ERASE FLASH_PECR_ERASE_MskèFLASH_PECR_FPRG_Pos (10U)éFLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos)êFLASH_PECR_FPRG FLASH_PECR_FPRG_MskëFLASH_PECR_PARALLBANK_Pos (15U)ìFLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos)íFLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_MskîFLASH_PECR_EOPIE_Pos (16U)ïFLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos)ðFLASH_PECR_EOPIE FLASH_PECR_EOPIE_MskñFLASH_PECR_ERRIE_Pos (17U)òFLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos)óFLASH_PECR_ERRIE FLASH_PECR_ERRIE_MskôFLASH_PECR_OBL_LAUNCH_Pos (18U)õFLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)öFLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk÷FLASH_PECR_HALF_ARRAY_Pos (19U)øFLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)ùFLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_MskúFLASH_PECR_NZDISABLE_Pos (22U)ûFLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos)üFLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_MskÿFLASH_PDKEYR_PDKEYR_Pos (0U)FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_MskFLASH_PEKEYR_PEKEYR_Pos (0U)FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_MskFLASH_PRGKEYR_PRGKEYR_Pos (0U)FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos)FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_MskFLASH_OPTKEYR_OPTKEYR_Pos (0U)FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_MskFLASH_SR_BSY_Pos (0U)FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)FLASH_SR_BSY FLASH_SR_BSY_MskFLASH_SR_EOP_Pos (1U)FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)FLASH_SR_EOP FLASH_SR_EOP_MskFLASH_SR_HVOFF_Pos (2U)FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos)FLASH_SR_HVOFF FLASH_SR_HVOFF_MskFLASH_SR_READY_Pos (3U)FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos)FLASH_SR_READY FLASH_SR_READY_Msk FLASH_SR_WRPERR_Pos (8U)¡FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)¢FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk£FLASH_SR_PGAERR_Pos (9U)¤FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)¥FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk¦FLASH_SR_SIZERR_Pos (10U)§FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)¨FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk©FLASH_SR_OPTVERR_Pos (11U)ªFLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)«FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk¬FLASH_SR_RDERR_Pos (13U)FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)®FLASH_SR_RDERR FLASH_SR_RDERR_Msk¯FLASH_SR_NOTZEROERR_Pos (16U)°FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos)±FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk²FLASH_SR_FWWERR_Pos (17U)³FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos)´FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk·FLASH_SR_FWWER FLASH_SR_FWWERR¸FLASH_SR_ENHV FLASH_SR_HVOFF¹FLASH_SR_ENDHV FLASH_SR_HVOFF¼FLASH_OPTR_RDPROT_Pos (0U)½FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos)¾FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk¿FLASH_OPTR_WPRMOD_Pos (8U)ÀFLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos)ÁFLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_MskÂFLASH_OPTR_BOR_LEV_Pos (16U)ÃFLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos)ÄFLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_MskÅFLASH_OPTR_IWDG_SW_Pos (20U)ÆFLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)ÇFLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_MskÈFLASH_OPTR_nRST_STOP_Pos (21U)ÉFLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)ÊFLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_MskËFLASH_OPTR_nRST_STDBY_Pos (22U)ÌFLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)ÍFLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_MskÎFLASH_OPTR_BFB2_Pos (23U)ÏFLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos)ÐFLASH_OPTR_BFB2 FLASH_OPTR_BFB2_MskÑFLASH_OPTR_USER_Pos (20U)ÒFLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos)ÓFLASH_OPTR_USER FLASH_OPTR_USER_MskÔFLASH_OPTR_BOOT1_Pos (31U)ÕFLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos)ÖFLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_MskÙFLASH_WRPR_WRP_Pos (0U)ÚFLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos)ÛFLASH_WRPR_WRP FLASH_WRPR_WRP_MskãGPIO_MODER_MODE0_Pos (0U)äGPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)åGPIO_MODER_MODE0 GPIO_MODER_MODE0_MskæGPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)çGPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)èGPIO_MODER_MODE1_Pos (2U)éGPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)êGPIO_MODER_MODE1 GPIO_MODER_MODE1_MskëGPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)ìGPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)íGPIO_MODER_MODE2_Pos (4U)îGPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)ïGPIO_MODER_MODE2 GPIO_MODER_MODE2_MskðGPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)ñGPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)òGPIO_MODER_MODE3_Pos (6U)óGPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)ôGPIO_MODER_MODE3 GPIO_MODER_MODE3_MskõGPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)öGPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)÷GPIO_MODER_MODE4_Pos (8U)øGPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)ùGPIO_MODER_MODE4 GPIO_MODER_MODE4_MskúGPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)ûGPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)üGPIO_MODER_MODE5_Pos (10U)ýGPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)þGPIO_MODER_MODE5 GPIO_MODER_MODE5_MskÿGPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)GPIO_MODER_MODE6_Pos (12U)GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)GPIO_MODER_MODE6 GPIO_MODER_MODE6_MskGPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)GPIO_MODER_MODE7_Pos (14U)GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)GPIO_MODER_MODE7 GPIO_MODER_MODE7_MskGPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)GPIO_MODER_MODE8_Pos (16U)GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)GPIO_MODER_MODE8 GPIO_MODER_MODE8_MskGPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)GPIO_MODER_MODE9_Pos (18U)GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)GPIO_MODER_MODE9 GPIO_MODER_MODE9_MskGPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)GPIO_MODER_MODE10_Pos (20U)GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)GPIO_MODER_MODE10 GPIO_MODER_MODE10_MskGPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)GPIO_MODER_MODE11_Pos (22U)GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)GPIO_MODER_MODE11 GPIO_MODER_MODE11_MskGPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)GPIO_MODER_MODE12_Pos (24U) GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)¡GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk¢GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)£GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)¤GPIO_MODER_MODE13_Pos (26U)¥GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)¦GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk§GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)¨GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)©GPIO_MODER_MODE14_Pos (28U)ªGPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)«GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk¬GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)®GPIO_MODER_MODE15_Pos (30U)¯GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)°GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk±GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)²GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)µGPIO_OTYPER_OT_0 (0x00000001U)¶GPIO_OTYPER_OT_1 (0x00000002U)·GPIO_OTYPER_OT_2 (0x00000004U)¸GPIO_OTYPER_OT_3 (0x00000008U)¹GPIO_OTYPER_OT_4 (0x00000010U)ºGPIO_OTYPER_OT_5 (0x00000020U)»GPIO_OTYPER_OT_6 (0x00000040U)¼GPIO_OTYPER_OT_7 (0x00000080U)½GPIO_OTYPER_OT_8 (0x00000100U)¾GPIO_OTYPER_OT_9 (0x00000200U)¿GPIO_OTYPER_OT_10 (0x00000400U)ÀGPIO_OTYPER_OT_11 (0x00000800U)ÁGPIO_OTYPER_OT_12 (0x00001000U)ÂGPIO_OTYPER_OT_13 (0x00002000U)ÃGPIO_OTYPER_OT_14 (0x00004000U)ÄGPIO_OTYPER_OT_15 (0x00008000U)ÇGPIO_OSPEEDER_OSPEED0_Pos (0U)ÈGPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)ÉGPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_MskÊGPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)ËGPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)ÌGPIO_OSPEEDER_OSPEED1_Pos (2U)ÍGPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)ÎGPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_MskÏGPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)ÐGPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)ÑGPIO_OSPEEDER_OSPEED2_Pos (4U)ÒGPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)ÓGPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_MskÔGPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)ÕGPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)ÖGPIO_OSPEEDER_OSPEED3_Pos (6U)×GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)ØGPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_MskÙGPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)ÚGPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)ÛGPIO_OSPEEDER_OSPEED4_Pos (8U)ÜGPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)ÝGPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_MskÞGPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)ßGPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)àGPIO_OSPEEDER_OSPEED5_Pos (10U)áGPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)âGPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_MskãGPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)äGPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)åGPIO_OSPEEDER_OSPEED6_Pos (12U)æGPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)çGPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_MskèGPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)éGPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)êGPIO_OSPEEDER_OSPEED7_Pos (14U)ëGPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)ìGPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_MskíGPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)îGPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)ïGPIO_OSPEEDER_OSPEED8_Pos (16U)ðGPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)ñGPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_MskòGPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)óGPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)ôGPIO_OSPEEDER_OSPEED9_Pos (18U)õGPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)öGPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk÷GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)øGPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)ùGPIO_OSPEEDER_OSPEED10_Pos (20U)úGPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)ûGPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_MsküGPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)ýGPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)þGPIO_OSPEEDER_OSPEED11_Pos (22U)ÿGPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_MskGPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)GPIO_OSPEEDER_OSPEED12_Pos (24U)GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_MskGPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)GPIO_OSPEEDER_OSPEED13_Pos (26U)GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_MskGPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)GPIO_OSPEEDER_OSPEED14_Pos (28U)GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_MskGPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)GPIO_OSPEEDER_OSPEED15_Pos (30U)GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_MskGPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)GPIO_PUPDR_PUPD0_Pos (0U)GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_MskGPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)GPIO_PUPDR_PUPD1_Pos (2U)GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk¡GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)¢GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)£GPIO_PUPDR_PUPD2_Pos (4U)¤GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)¥GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk¦GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)§GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)¨GPIO_PUPDR_PUPD3_Pos (6U)©GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)ªGPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk«GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)¬GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)GPIO_PUPDR_PUPD4_Pos (8U)®GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)¯GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk°GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)±GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)²GPIO_PUPDR_PUPD5_Pos (10U)³GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)´GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_MskµGPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)¶GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)·GPIO_PUPDR_PUPD6_Pos (12U)¸GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)¹GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_MskºGPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)»GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)¼GPIO_PUPDR_PUPD7_Pos (14U)½GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)¾GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk¿GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)ÀGPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)ÁGPIO_PUPDR_PUPD8_Pos (16U)ÂGPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)ÃGPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_MskÄGPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)ÅGPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)ÆGPIO_PUPDR_PUPD9_Pos (18U)ÇGPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)ÈGPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_MskÉGPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)ÊGPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)ËGPIO_PUPDR_PUPD10_Pos (20U)ÌGPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)ÍGPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_MskÎGPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)ÏGPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)ÐGPIO_PUPDR_PUPD11_Pos (22U)ÑGPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)ÒGPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_MskÓGPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)ÔGPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)ÕGPIO_PUPDR_PUPD12_Pos (24U)ÖGPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)×GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_MskØGPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)ÙGPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)ÚGPIO_PUPDR_PUPD13_Pos (26U)ÛGPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)ÜGPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_MskÝGPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)ÞGPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)ßGPIO_PUPDR_PUPD14_Pos (28U)àGPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)áGPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_MskâGPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)ãGPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)äGPIO_PUPDR_PUPD15_Pos (30U)åGPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)æGPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_MskçGPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)èGPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)ëGPIO_IDR_ID0_Pos (0U)ìGPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)íGPIO_IDR_ID0 GPIO_IDR_ID0_MskîGPIO_IDR_ID1_Pos (1U)ïGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)ðGPIO_IDR_ID1 GPIO_IDR_ID1_MskñGPIO_IDR_ID2_Pos (2U)òGPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)óGPIO_IDR_ID2 GPIO_IDR_ID2_MskôGPIO_IDR_ID3_Pos (3U)õGPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)öGPIO_IDR_ID3 GPIO_IDR_ID3_Msk÷GPIO_IDR_ID4_Pos (4U)øGPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)ùGPIO_IDR_ID4 GPIO_IDR_ID4_MskúGPIO_IDR_ID5_Pos (5U)ûGPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)üGPIO_IDR_ID5 GPIO_IDR_ID5_MskýGPIO_IDR_ID6_Pos (6U)þGPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)ÿGPIO_IDR_ID6 GPIO_IDR_ID6_MskGPIO_IDR_ID7_Pos (7U)GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)GPIO_IDR_ID7 GPIO_IDR_ID7_MskGPIO_IDR_ID8_Pos (8U)GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)GPIO_IDR_ID8 GPIO_IDR_ID8_MskGPIO_IDR_ID9_Pos (9U)GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)GPIO_IDR_ID9 GPIO_IDR_ID9_MskGPIO_IDR_ID10_Pos (10U)GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)GPIO_IDR_ID10 GPIO_IDR_ID10_MskGPIO_IDR_ID11_Pos (11U)GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)GPIO_IDR_ID11 GPIO_IDR_ID11_MskGPIO_IDR_ID12_Pos (12U)GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)GPIO_IDR_ID12 GPIO_IDR_ID12_MskGPIO_IDR_ID13_Pos (13U)GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)GPIO_IDR_ID13 GPIO_IDR_ID13_MskGPIO_IDR_ID14_Pos (14U)GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)GPIO_IDR_ID14 GPIO_IDR_ID14_MskGPIO_IDR_ID15_Pos (15U)GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)GPIO_IDR_ID15 GPIO_IDR_ID15_MskGPIO_ODR_OD0_Pos (0U)GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)GPIO_ODR_OD0 GPIO_ODR_OD0_Msk GPIO_ODR_OD1_Pos (1U)¡GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)¢GPIO_ODR_OD1 GPIO_ODR_OD1_Msk£GPIO_ODR_OD2_Pos (2U)¤GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)¥GPIO_ODR_OD2 GPIO_ODR_OD2_Msk¦GPIO_ODR_OD3_Pos (3U)§GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)¨GPIO_ODR_OD3 GPIO_ODR_OD3_Msk©GPIO_ODR_OD4_Pos (4U)ªGPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)«GPIO_ODR_OD4 GPIO_ODR_OD4_Msk¬GPIO_ODR_OD5_Pos (5U)GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)®GPIO_ODR_OD5 GPIO_ODR_OD5_Msk¯GPIO_ODR_OD6_Pos (6U)°GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)±GPIO_ODR_OD6 GPIO_ODR_OD6_Msk²GPIO_ODR_OD7_Pos (7U)³GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)´GPIO_ODR_OD7 GPIO_ODR_OD7_MskµGPIO_ODR_OD8_Pos (8U)¶GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)·GPIO_ODR_OD8 GPIO_ODR_OD8_Msk¸GPIO_ODR_OD9_Pos (9U)¹GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)ºGPIO_ODR_OD9 GPIO_ODR_OD9_Msk»GPIO_ODR_OD10_Pos (10U)¼GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)½GPIO_ODR_OD10 GPIO_ODR_OD10_Msk¾GPIO_ODR_OD11_Pos (11U)¿GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)ÀGPIO_ODR_OD11 GPIO_ODR_OD11_MskÁGPIO_ODR_OD12_Pos (12U)ÂGPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)ÃGPIO_ODR_OD12 GPIO_ODR_OD12_MskÄGPIO_ODR_OD13_Pos (13U)ÅGPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)ÆGPIO_ODR_OD13 GPIO_ODR_OD13_MskÇGPIO_ODR_OD14_Pos (14U)ÈGPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)ÉGPIO_ODR_OD14 GPIO_ODR_OD14_MskÊGPIO_ODR_OD15_Pos (15U)ËGPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)ÌGPIO_ODR_OD15 GPIO_ODR_OD15_MskÏGPIO_BSRR_BS_0 (0x00000001U)ÐGPIO_BSRR_BS_1 (0x00000002U)ÑGPIO_BSRR_BS_2 (0x00000004U)ÒGPIO_BSRR_BS_3 (0x00000008U)ÓGPIO_BSRR_BS_4 (0x00000010U)ÔGPIO_BSRR_BS_5 (0x00000020U)ÕGPIO_BSRR_BS_6 (0x00000040U)ÖGPIO_BSRR_BS_7 (0x00000080U)×GPIO_BSRR_BS_8 (0x00000100U)ØGPIO_BSRR_BS_9 (0x00000200U)ÙGPIO_BSRR_BS_10 (0x00000400U)ÚGPIO_BSRR_BS_11 (0x00000800U)ÛGPIO_BSRR_BS_12 (0x00001000U)ÜGPIO_BSRR_BS_13 (0x00002000U)ÝGPIO_BSRR_BS_14 (0x00004000U)ÞGPIO_BSRR_BS_15 (0x00008000U)ßGPIO_BSRR_BR_0 (0x00010000U)àGPIO_BSRR_BR_1 (0x00020000U)áGPIO_BSRR_BR_2 (0x00040000U)âGPIO_BSRR_BR_3 (0x00080000U)ãGPIO_BSRR_BR_4 (0x00100000U)äGPIO_BSRR_BR_5 (0x00200000U)åGPIO_BSRR_BR_6 (0x00400000U)æGPIO_BSRR_BR_7 (0x00800000U)çGPIO_BSRR_BR_8 (0x01000000U)èGPIO_BSRR_BR_9 (0x02000000U)éGPIO_BSRR_BR_10 (0x04000000U)êGPIO_BSRR_BR_11 (0x08000000U)ëGPIO_BSRR_BR_12 (0x10000000U)ìGPIO_BSRR_BR_13 (0x20000000U)íGPIO_BSRR_BR_14 (0x40000000U)îGPIO_BSRR_BR_15 (0x80000000U)ñGPIO_LCKR_LCK0_Pos (0U)òGPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)óGPIO_LCKR_LCK0 GPIO_LCKR_LCK0_MskôGPIO_LCKR_LCK1_Pos (1U)õGPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)öGPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk÷GPIO_LCKR_LCK2_Pos (2U)øGPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)ùGPIO_LCKR_LCK2 GPIO_LCKR_LCK2_MskúGPIO_LCKR_LCK3_Pos (3U)ûGPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)üGPIO_LCKR_LCK3 GPIO_LCKR_LCK3_MskýGPIO_LCKR_LCK4_Pos (4U)þGPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)ÿGPIO_LCKR_LCK4 GPIO_LCKR_LCK4_MskGPIO_LCKR_LCK5_Pos (5U)GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_MskGPIO_LCKR_LCK6_Pos (6U)GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_MskGPIO_LCKR_LCK7_Pos (7U)GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_MskGPIO_LCKR_LCK8_Pos (8U)GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_MskGPIO_LCKR_LCK9_Pos (9U)GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_MskGPIO_LCKR_LCK10_Pos (10U)GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_MskGPIO_LCKR_LCK11_Pos (11U)GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_MskGPIO_LCKR_LCK12_Pos (12U)GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_MskGPIO_LCKR_LCK13_Pos (13U)GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_MskGPIO_LCKR_LCK14_Pos (14U)GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_MskGPIO_LCKR_LCK15_Pos (15U)GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk¡GPIO_LCKR_LCKK_Pos (16U)¢GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)£GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk¦GPIO_AFRL_AFSEL0_Pos (0U)§GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)¨GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk©GPIO_AFRL_AFSEL1_Pos (4U)ªGPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)«GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk¬GPIO_AFRL_AFSEL2_Pos (8U)GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)®GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk¯GPIO_AFRL_AFSEL3_Pos (12U)°GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)±GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk²GPIO_AFRL_AFSEL4_Pos (16U)³GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)´GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_MskµGPIO_AFRL_AFSEL5_Pos (20U)¶GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)·GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk¸GPIO_AFRL_AFSEL6_Pos (24U)¹GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)ºGPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk»GPIO_AFRL_AFSEL7_Pos (28U)¼GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)½GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_MskÀGPIO_AFRH_AFSEL8_Pos (0U)ÁGPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)ÂGPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_MskÃGPIO_AFRH_AFSEL9_Pos (4U)ÄGPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)ÅGPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_MskÆGPIO_AFRH_AFSEL10_Pos (8U)ÇGPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)ÈGPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_MskÉGPIO_AFRH_AFSEL11_Pos (12U)ÊGPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)ËGPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_MskÌGPIO_AFRH_AFSEL12_Pos (16U)ÍGPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)ÎGPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_MskÏGPIO_AFRH_AFSEL13_Pos (20U)ÐGPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)ÑGPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_MskÒGPIO_AFRH_AFSEL14_Pos (24U)ÓGPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)ÔGPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_MskÕGPIO_AFRH_AFSEL15_Pos (28U)ÖGPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)×GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_MskÚGPIO_BRR_BR_0 (0x00000001U)ÛGPIO_BRR_BR_1 (0x00000002U)ÜGPIO_BRR_BR_2 (0x00000004U)ÝGPIO_BRR_BR_3 (0x00000008U)ÞGPIO_BRR_BR_4 (0x00000010U)ßGPIO_BRR_BR_5 (0x00000020U)àGPIO_BRR_BR_6 (0x00000040U)áGPIO_BRR_BR_7 (0x00000080U)âGPIO_BRR_BR_8 (0x00000100U)ãGPIO_BRR_BR_9 (0x00000200U)äGPIO_BRR_BR_10 (0x00000400U)åGPIO_BRR_BR_11 (0x00000800U)æGPIO_BRR_BR_12 (0x00001000U)çGPIO_BRR_BR_13 (0x00002000U)èGPIO_BRR_BR_14 (0x00004000U)éGPIO_BRR_BR_15 (0x00008000U)òI2C_CR1_PE_Pos (0U)óI2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)ôI2C_CR1_PE I2C_CR1_PE_MskõI2C_CR1_TXIE_Pos (1U)öI2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)÷I2C_CR1_TXIE I2C_CR1_TXIE_MskøI2C_CR1_RXIE_Pos (2U)ùI2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)úI2C_CR1_RXIE I2C_CR1_RXIE_MskûI2C_CR1_ADDRIE_Pos (3U)üI2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)ýI2C_CR1_ADDRIE I2C_CR1_ADDRIE_MskþI2C_CR1_NACKIE_Pos (4U)ÿI2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)I2C_CR1_NACKIE I2C_CR1_NACKIE_MskI2C_CR1_STOPIE_Pos (5U)I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)I2C_CR1_STOPIE I2C_CR1_STOPIE_MskI2C_CR1_TCIE_Pos (6U)I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)I2C_CR1_TCIE I2C_CR1_TCIE_MskI2C_CR1_ERRIE_Pos (7U)I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)I2C_CR1_ERRIE I2C_CR1_ERRIE_MskI2C_CR1_DNF_Pos (8U)I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)I2C_CR1_DNF I2C_CR1_DNF_MskI2C_CR1_ANFOFF_Pos (12U)I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)I2C_CR1_ANFOFF I2C_CR1_ANFOFF_MskI2C_CR1_TXDMAEN_Pos (14U)I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_MskI2C_CR1_RXDMAEN_Pos (15U)I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_MskI2C_CR1_SBC_Pos (16U)I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)I2C_CR1_SBC I2C_CR1_SBC_MskI2C_CR1_NOSTRETCH_Pos (17U)I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_MskI2C_CR1_WUPEN_Pos (18U)I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)I2C_CR1_WUPEN I2C_CR1_WUPEN_MskI2C_CR1_GCEN_Pos (19U) I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)¡I2C_CR1_GCEN I2C_CR1_GCEN_Msk¢I2C_CR1_SMBHEN_Pos (20U)£I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)¤I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk¥I2C_CR1_SMBDEN_Pos (21U)¦I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)§I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk¨I2C_CR1_ALERTEN_Pos (22U)©I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)ªI2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk«I2C_CR1_PECEN_Pos (23U)¬I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)I2C_CR1_PECEN I2C_CR1_PECEN_Msk°I2C_CR2_SADD_Pos (0U)±I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)²I2C_CR2_SADD I2C_CR2_SADD_Msk³I2C_CR2_RD_WRN_Pos (10U)´I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)µI2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk¶I2C_CR2_ADD10_Pos (11U)·I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)¸I2C_CR2_ADD10 I2C_CR2_ADD10_Msk¹I2C_CR2_HEAD10R_Pos (12U)ºI2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)»I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk¼I2C_CR2_START_Pos (13U)½I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)¾I2C_CR2_START I2C_CR2_START_Msk¿I2C_CR2_STOP_Pos (14U)ÀI2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)ÁI2C_CR2_STOP I2C_CR2_STOP_MskÂI2C_CR2_NACK_Pos (15U)ÃI2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)ÄI2C_CR2_NACK I2C_CR2_NACK_MskÅI2C_CR2_NBYTES_Pos (16U)ÆI2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)ÇI2C_CR2_NBYTES I2C_CR2_NBYTES_MskÈI2C_CR2_RELOAD_Pos (24U)ÉI2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)ÊI2C_CR2_RELOAD I2C_CR2_RELOAD_MskËI2C_CR2_AUTOEND_Pos (25U)ÌI2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)ÍI2C_CR2_AUTOEND I2C_CR2_AUTOEND_MskÎI2C_CR2_PECBYTE_Pos (26U)ÏI2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)ÐI2C_CR2_PECBYTE I2C_CR2_PECBYTE_MskÓI2C_OAR1_OA1_Pos (0U)ÔI2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)ÕI2C_OAR1_OA1 I2C_OAR1_OA1_MskÖI2C_OAR1_OA1MODE_Pos (10U)×I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)ØI2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_MskÙI2C_OAR1_OA1EN_Pos (15U)ÚI2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)ÛI2C_OAR1_OA1EN I2C_OAR1_OA1EN_MskÞI2C_OAR2_OA2_Pos (1U)ßI2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)àI2C_OAR2_OA2 I2C_OAR2_OA2_MskáI2C_OAR2_OA2MSK_Pos (8U)âI2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)ãI2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_MskäI2C_OAR2_OA2NOMASK (0x00000000U)åI2C_OAR2_OA2MASK01_Pos (8U)æI2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)çI2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_MskèI2C_OAR2_OA2MASK02_Pos (9U)éI2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)êI2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_MskëI2C_OAR2_OA2MASK03_Pos (8U)ìI2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)íI2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_MskîI2C_OAR2_OA2MASK04_Pos (10U)ïI2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)ðI2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_MskñI2C_OAR2_OA2MASK05_Pos (8U)òI2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)óI2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_MskôI2C_OAR2_OA2MASK06_Pos (9U)õI2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)öI2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk÷I2C_OAR2_OA2MASK07_Pos (8U)øI2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)ùI2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_MskúI2C_OAR2_OA2EN_Pos (15U)ûI2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)üI2C_OAR2_OA2EN I2C_OAR2_OA2EN_MskÿI2C_TIMINGR_SCLL_Pos (0U)I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_MskI2C_TIMINGR_SCLH_Pos (8U)I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_MskI2C_TIMINGR_SDADEL_Pos (16U)I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_MskI2C_TIMINGR_SCLDEL_Pos (20U)I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_MskI2C_TIMINGR_PRESC_Pos (28U)I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_MskI2C_TIMEOUTR_TIMEOUTA_Pos (0U)I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_MskI2C_TIMEOUTR_TIDLE_Pos (12U)I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_MskI2C_TIMEOUTR_TIMOUTEN_Pos (15U)I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_MskI2C_TIMEOUTR_TIMEOUTB_Pos (16U)I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_MskI2C_TIMEOUTR_TEXTEN_Pos (31U)I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk¡I2C_ISR_TXE_Pos (0U)¢I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)£I2C_ISR_TXE I2C_ISR_TXE_Msk¤I2C_ISR_TXIS_Pos (1U)¥I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)¦I2C_ISR_TXIS I2C_ISR_TXIS_Msk§I2C_ISR_RXNE_Pos (2U)¨I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)©I2C_ISR_RXNE I2C_ISR_RXNE_MskªI2C_ISR_ADDR_Pos (3U)«I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)¬I2C_ISR_ADDR I2C_ISR_ADDR_MskI2C_ISR_NACKF_Pos (4U)®I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)¯I2C_ISR_NACKF I2C_ISR_NACKF_Msk°I2C_ISR_STOPF_Pos (5U)±I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)²I2C_ISR_STOPF I2C_ISR_STOPF_Msk³I2C_ISR_TC_Pos (6U)´I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)µI2C_ISR_TC I2C_ISR_TC_Msk¶I2C_ISR_TCR_Pos (7U)·I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)¸I2C_ISR_TCR I2C_ISR_TCR_Msk¹I2C_ISR_BERR_Pos (8U)ºI2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)»I2C_ISR_BERR I2C_ISR_BERR_Msk¼I2C_ISR_ARLO_Pos (9U)½I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)¾I2C_ISR_ARLO I2C_ISR_ARLO_Msk¿I2C_ISR_OVR_Pos (10U)ÀI2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)ÁI2C_ISR_OVR I2C_ISR_OVR_MskÂI2C_ISR_PECERR_Pos (11U)ÃI2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)ÄI2C_ISR_PECERR I2C_ISR_PECERR_MskÅI2C_ISR_TIMEOUT_Pos (12U)ÆI2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)ÇI2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_MskÈI2C_ISR_ALERT_Pos (13U)ÉI2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)ÊI2C_ISR_ALERT I2C_ISR_ALERT_MskËI2C_ISR_BUSY_Pos (15U)ÌI2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)ÍI2C_ISR_BUSY I2C_ISR_BUSY_MskÎI2C_ISR_DIR_Pos (16U)ÏI2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)ÐI2C_ISR_DIR I2C_ISR_DIR_MskÑI2C_ISR_ADDCODE_Pos (17U)ÒI2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)ÓI2C_ISR_ADDCODE I2C_ISR_ADDCODE_MskÖI2C_ICR_ADDRCF_Pos (3U)×I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)ØI2C_ICR_ADDRCF I2C_ICR_ADDRCF_MskÙI2C_ICR_NACKCF_Pos (4U)ÚI2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)ÛI2C_ICR_NACKCF I2C_ICR_NACKCF_MskÜI2C_ICR_STOPCF_Pos (5U)ÝI2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)ÞI2C_ICR_STOPCF I2C_ICR_STOPCF_MskßI2C_ICR_BERRCF_Pos (8U)àI2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)áI2C_ICR_BERRCF I2C_ICR_BERRCF_MskâI2C_ICR_ARLOCF_Pos (9U)ãI2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)äI2C_ICR_ARLOCF I2C_ICR_ARLOCF_MskåI2C_ICR_OVRCF_Pos (10U)æI2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)çI2C_ICR_OVRCF I2C_ICR_OVRCF_MskèI2C_ICR_PECCF_Pos (11U)éI2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)êI2C_ICR_PECCF I2C_ICR_PECCF_MskëI2C_ICR_TIMOUTCF_Pos (12U)ìI2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)íI2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_MskîI2C_ICR_ALERTCF_Pos (13U)ïI2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)ðI2C_ICR_ALERTCF I2C_ICR_ALERTCF_MskóI2C_PECR_PEC_Pos (0U)ôI2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)õI2C_PECR_PEC I2C_PECR_PEC_MskøI2C_RXDR_RXDATA_Pos (0U)ùI2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)úI2C_RXDR_RXDATA I2C_RXDR_RXDATA_MskýI2C_TXDR_TXDATA_Pos (0U)þI2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)ÿI2C_TXDR_TXDATA I2C_TXDR_TXDATA_MskIWDG_KR_KEY_Pos (0U)IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)IWDG_KR_KEY IWDG_KR_KEY_MskIWDG_PR_PR_Pos (0U)IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)IWDG_PR_PR IWDG_PR_PR_MskIWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)IWDG_RLR_RL_Pos (0U)IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)IWDG_RLR_RL IWDG_RLR_RL_MskIWDG_SR_PVU_Pos (0U)IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)IWDG_SR_PVU IWDG_SR_PVU_MskIWDG_SR_RVU_Pos (1U)IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)IWDG_SR_RVU IWDG_SR_RVU_MskIWDG_SR_WVU_Pos (2U) IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)¡IWDG_SR_WVU IWDG_SR_WVU_Msk¤IWDG_WINR_WIN_Pos (0U)¥IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)¦IWDG_WINR_WIN IWDG_WINR_WIN_Msk®LPTIM_ISR_CMPM_Pos (0U)¯LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)°LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk±LPTIM_ISR_ARRM_Pos (1U)²LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)³LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk´LPTIM_ISR_EXTTRIG_Pos (2U)µLPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)¶LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk·LPTIM_ISR_CMPOK_Pos (3U)¸LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)¹LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_MskºLPTIM_ISR_ARROK_Pos (4U)»LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)¼LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk½LPTIM_ISR_UP_Pos (5U)¾LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)¿LPTIM_ISR_UP LPTIM_ISR_UP_MskÀLPTIM_ISR_DOWN_Pos (6U)ÁLPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)ÂLPTIM_ISR_DOWN LPTIM_ISR_DOWN_MskÅLPTIM_ICR_CMPMCF_Pos (0U)ÆLPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)ÇLPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_MskÈLPTIM_ICR_ARRMCF_Pos (1U)ÉLPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)ÊLPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_MskËLPTIM_ICR_EXTTRIGCF_Pos (2U)ÌLPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)ÍLPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_MskÎLPTIM_ICR_CMPOKCF_Pos (3U)ÏLPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)ÐLPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_MskÑLPTIM_ICR_ARROKCF_Pos (4U)ÒLPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)ÓLPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_MskÔLPTIM_ICR_UPCF_Pos (5U)ÕLPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)ÖLPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk×LPTIM_ICR_DOWNCF_Pos (6U)ØLPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)ÙLPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_MskÜLPTIM_IER_CMPMIE_Pos (0U)ÝLPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)ÞLPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_MskßLPTIM_IER_ARRMIE_Pos (1U)àLPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)áLPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_MskâLPTIM_IER_EXTTRIGIE_Pos (2U)ãLPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)äLPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_MskåLPTIM_IER_CMPOKIE_Pos (3U)æLPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)çLPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_MskèLPTIM_IER_ARROKIE_Pos (4U)éLPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)êLPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_MskëLPTIM_IER_UPIE_Pos (5U)ìLPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)íLPTIM_IER_UPIE LPTIM_IER_UPIE_MskîLPTIM_IER_DOWNIE_Pos (6U)ïLPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)ðLPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_MskóLPTIM_CFGR_CKSEL_Pos (0U)ôLPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)õLPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk÷LPTIM_CFGR_CKPOL_Pos (1U)øLPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)ùLPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_MskúLPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)ûLPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)ýLPTIM_CFGR_CKFLT_Pos (3U)þLPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)ÿLPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_MskLPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)LPTIM_CFGR_TRGFLT_Pos (6U)LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_MskLPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)LPTIM_CFGR_PRESC_Pos (9U)LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_MskLPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)LPTIM_CFGR_TRIGSEL_Pos (13U)LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_MskLPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)LPTIM_CFGR_TRIGEN_Pos (17U)LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_MskLPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)LPTIM_CFGR_TIMOUT_Pos (19U)LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk LPTIM_CFGR_WAVE_Pos (20U)¡LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)¢LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk£LPTIM_CFGR_WAVPOL_Pos (21U)¤LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)¥LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk¦LPTIM_CFGR_PRELOAD_Pos (22U)§LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)¨LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk©LPTIM_CFGR_COUNTMODE_Pos (23U)ªLPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)«LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk¬LPTIM_CFGR_ENC_Pos (24U)LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)®LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk±LPTIM_CR_ENABLE_Pos (0U)²LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)³LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk´LPTIM_CR_SNGSTRT_Pos (1U)µLPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)¶LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk·LPTIM_CR_CNTSTRT_Pos (2U)¸LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)¹LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk¼LPTIM_CMP_CMP_Pos (0U)½LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)¾LPTIM_CMP_CMP LPTIM_CMP_CMP_MskÁLPTIM_ARR_ARR_Pos (0U)ÂLPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)ÃLPTIM_ARR_ARR LPTIM_ARR_ARR_MskÆLPTIM_CNT_CNT_Pos (0U)ÇLPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)ÈLPTIM_CNT_CNT LPTIM_CNT_CNT_MskÑFW_CSSA_ADD_Pos (8U)ÒFW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos)ÓFW_CSSA_ADD FW_CSSA_ADD_MskÔFW_CSL_LENG_Pos (8U)ÕFW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos)ÖFW_CSL_LENG FW_CSL_LENG_Msk×FW_NVDSSA_ADD_Pos (8U)ØFW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos)ÙFW_NVDSSA_ADD FW_NVDSSA_ADD_MskÚFW_NVDSL_LENG_Pos (8U)ÛFW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos)ÜFW_NVDSL_LENG FW_NVDSL_LENG_MskÝFW_VDSSA_ADD_Pos (6U)ÞFW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos)ßFW_VDSSA_ADD FW_VDSSA_ADD_MskàFW_VDSL_LENG_Pos (6U)áFW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos)âFW_VDSL_LENG FW_VDSL_LENG_MskåFW_CR_FPA_Pos (0U)æFW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos)çFW_CR_FPA FW_CR_FPA_MskèFW_CR_VDS_Pos (1U)éFW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos)êFW_CR_VDS FW_CR_VDS_MskëFW_CR_VDE_Pos (2U)ìFW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos)íFW_CR_VDE FW_CR_VDE_MskõPWR_PVD_SUPPORT øPWR_CR_LPSDSR_Pos (0U)ùPWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos)úPWR_CR_LPSDSR PWR_CR_LPSDSR_MskûPWR_CR_PDDS_Pos (1U)üPWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)ýPWR_CR_PDDS PWR_CR_PDDS_MskþPWR_CR_CWUF_Pos (2U)ÿPWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)PWR_CR_CWUF PWR_CR_CWUF_MskPWR_CR_CSBF_Pos (3U)PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)PWR_CR_CSBF PWR_CR_CSBF_MskPWR_CR_PVDE_Pos (4U)PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)PWR_CR_PVDE PWR_CR_PVDE_MskPWR_CR_PLS_Pos (5U)PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)PWR_CR_PLS PWR_CR_PLS_MskPWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)PWR_CR_PLS_LEV0 (0x00000000U)PWR_CR_PLS_LEV1 (0x00000020U)PWR_CR_PLS_LEV2 (0x00000040U)PWR_CR_PLS_LEV3 (0x00000060U)PWR_CR_PLS_LEV4 (0x00000080U)PWR_CR_PLS_LEV5 (0x000000A0U)PWR_CR_PLS_LEV6 (0x000000C0U)PWR_CR_PLS_LEV7 (0x000000E0U)PWR_CR_DBP_Pos (8U)PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)PWR_CR_DBP PWR_CR_DBP_MskPWR_CR_ULP_Pos (9U)PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos)PWR_CR_ULP PWR_CR_ULP_MskPWR_CR_FWU_Pos (10U) PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos)¡PWR_CR_FWU PWR_CR_FWU_Msk£PWR_CR_VOS_Pos (11U)¤PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)¥PWR_CR_VOS PWR_CR_VOS_Msk¦PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos)§PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos)¨PWR_CR_DSEEKOFF_Pos (13U)©PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos)ªPWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk«PWR_CR_LPRUN_Pos (14U)¬PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos)PWR_CR_LPRUN PWR_CR_LPRUN_Msk°PWR_CSR_WUF_Pos (0U)±PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)²PWR_CSR_WUF PWR_CSR_WUF_Msk³PWR_CSR_SBF_Pos (1U)´PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)µPWR_CSR_SBF PWR_CSR_SBF_Msk¶PWR_CSR_PVDO_Pos (2U)·PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)¸PWR_CSR_PVDO PWR_CSR_PVDO_Msk¹PWR_CSR_VREFINTRDYF_Pos (3U)ºPWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos)»PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk¼PWR_CSR_VOSF_Pos (4U)½PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos)¾PWR_CSR_VOSF PWR_CSR_VOSF_Msk¿PWR_CSR_REGLPF_Pos (5U)ÀPWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos)ÁPWR_CSR_REGLPF PWR_CSR_REGLPF_MskÃPWR_CSR_EWUP1_Pos (8U)ÄPWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)ÅPWR_CSR_EWUP1 PWR_CSR_EWUP1_MskÆPWR_CSR_EWUP2_Pos (9U)ÇPWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)ÈPWR_CSR_EWUP2 PWR_CSR_EWUP2_MskÉPWR_CSR_EWUP3_Pos (10U)ÊPWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)ËPWR_CSR_EWUP3 PWR_CSR_EWUP3_MskÕRCC_HSECSS_SUPPORT ÖRCC_MCO3_SUPPORT ×RCC_MCO3_AF2_SUPPORT ÚRCC_CR_HSION_Pos (0U)ÛRCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)ÜRCC_CR_HSION RCC_CR_HSION_MskÝRCC_CR_HSIKERON_Pos (1U)ÞRCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)ßRCC_CR_HSIKERON RCC_CR_HSIKERON_MskàRCC_CR_HSIRDY_Pos (2U)áRCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)âRCC_CR_HSIRDY RCC_CR_HSIRDY_MskãRCC_CR_HSIDIVEN_Pos (3U)äRCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos)åRCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_MskæRCC_CR_HSIDIVF_Pos (4U)çRCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)èRCC_CR_HSIDIVF RCC_CR_HSIDIVF_MskéRCC_CR_HSIOUTEN_Pos (5U)êRCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos)ëRCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_MskìRCC_CR_MSION_Pos (8U)íRCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)îRCC_CR_MSION RCC_CR_MSION_MskïRCC_CR_MSIRDY_Pos (9U)ðRCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)ñRCC_CR_MSIRDY RCC_CR_MSIRDY_MskòRCC_CR_HSEON_Pos (16U)óRCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)ôRCC_CR_HSEON RCC_CR_HSEON_MskõRCC_CR_HSERDY_Pos (17U)öRCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)÷RCC_CR_HSERDY RCC_CR_HSERDY_MskøRCC_CR_HSEBYP_Pos (18U)ùRCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)úRCC_CR_HSEBYP RCC_CR_HSEBYP_MskûRCC_CR_CSSHSEON_Pos (19U)üRCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)ýRCC_CR_CSSHSEON RCC_CR_CSSHSEON_MskþRCC_CR_RTCPRE_Pos (20U)ÿRCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos)RCC_CR_RTCPRE RCC_CR_RTCPRE_MskRCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos)RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos)RCC_CR_PLLON_Pos (24U)RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)RCC_CR_PLLON RCC_CR_PLLON_MskRCC_CR_PLLRDY_Pos (25U)RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)RCC_CR_PLLRDY RCC_CR_PLLRDY_MskRCC_CR_CSSON RCC_CR_CSSHSEONRCC_ICSCR_HSICAL_Pos (0U)RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MskRCC_ICSCR_HSITRIM_Pos (8U)RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos)RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MskRCC_ICSCR_MSIRANGE_Pos (13U)RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_MskRCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos)RCC_ICSCR_MSICAL_Pos (16U) RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)¡RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk¢RCC_ICSCR_MSITRIM_Pos (24U)£RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)¤RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk©RCC_CFGR_SW_Pos (0U)ªRCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)«RCC_CFGR_SW RCC_CFGR_SW_Msk¬RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)¯RCC_CFGR_SW_MSI (0x00000000U)°RCC_CFGR_SW_HSI (0x00000001U)±RCC_CFGR_SW_HSE (0x00000002U)²RCC_CFGR_SW_PLL (0x00000003U)µRCC_CFGR_SWS_Pos (2U)¶RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)·RCC_CFGR_SWS RCC_CFGR_SWS_Msk¸RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)¹RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)»RCC_CFGR_SWS_MSI (0x00000000U)¼RCC_CFGR_SWS_HSI (0x00000004U)½RCC_CFGR_SWS_HSE (0x00000008U)¾RCC_CFGR_SWS_PLL (0x0000000CU)ÁRCC_CFGR_HPRE_Pos (4U)ÂRCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)ÃRCC_CFGR_HPRE RCC_CFGR_HPRE_MskÄRCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)ÅRCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)ÆRCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)ÇRCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)ÉRCC_CFGR_HPRE_DIV1 (0x00000000U)ÊRCC_CFGR_HPRE_DIV2 (0x00000080U)ËRCC_CFGR_HPRE_DIV4 (0x00000090U)ÌRCC_CFGR_HPRE_DIV8 (0x000000A0U)ÍRCC_CFGR_HPRE_DIV16 (0x000000B0U)ÎRCC_CFGR_HPRE_DIV64 (0x000000C0U)ÏRCC_CFGR_HPRE_DIV128 (0x000000D0U)ÐRCC_CFGR_HPRE_DIV256 (0x000000E0U)ÑRCC_CFGR_HPRE_DIV512 (0x000000F0U)ÔRCC_CFGR_PPRE1_Pos (8U)ÕRCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)ÖRCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk×RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)ØRCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)ÙRCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)ÛRCC_CFGR_PPRE1_DIV1 (0x00000000U)ÜRCC_CFGR_PPRE1_DIV2 (0x00000400U)ÝRCC_CFGR_PPRE1_DIV4 (0x00000500U)ÞRCC_CFGR_PPRE1_DIV8 (0x00000600U)ßRCC_CFGR_PPRE1_DIV16 (0x00000700U)âRCC_CFGR_PPRE2_Pos (11U)ãRCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)äRCC_CFGR_PPRE2 RCC_CFGR_PPRE2_MskåRCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)æRCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)çRCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)éRCC_CFGR_PPRE2_DIV1 (0x00000000U)êRCC_CFGR_PPRE2_DIV2 (0x00002000U)ëRCC_CFGR_PPRE2_DIV4 (0x00002800U)ìRCC_CFGR_PPRE2_DIV8 (0x00003000U)íRCC_CFGR_PPRE2_DIV16 (0x00003800U)ïRCC_CFGR_STOPWUCK_Pos (15U)ðRCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)ñRCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_MskôRCC_CFGR_PLLSRC_Pos (16U)õRCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)öRCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_MskøRCC_CFGR_PLLSRC_HSI (0x00000000U)ùRCC_CFGR_PLLSRC_HSE (0x00010000U)ýRCC_CFGR_PLLMUL_Pos (18U)þRCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)ÿRCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_MskRCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)RCC_CFGR_PLLMUL3 (0x00000000U)RCC_CFGR_PLLMUL4 (0x00040000U)RCC_CFGR_PLLMUL6 (0x00080000U)RCC_CFGR_PLLMUL8 (0x000C0000U)RCC_CFGR_PLLMUL12 (0x00100000U)RCC_CFGR_PLLMUL16 (0x00140000U)RCC_CFGR_PLLMUL24 (0x00180000U)RCC_CFGR_PLLMUL32 (0x001C0000U)RCC_CFGR_PLLMUL48 (0x00200000U)RCC_CFGR_PLLDIV_Pos (22U)RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos)RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_MskRCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos)RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos)RCC_CFGR_PLLDIV2_Pos (22U)RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos)RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_MskRCC_CFGR_PLLDIV3_Pos (23U)RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos)RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_MskRCC_CFGR_PLLDIV4_Pos (22U)RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos)RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk¡RCC_CFGR_MCOSEL_Pos (24U)¢RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)£RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk¤RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)¥RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)¦RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)§RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)©RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U)ªRCC_CFGR_MCOSEL_SYSCLK_Pos (24U)«RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos)¬RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_MskRCC_CFGR_MCOSEL_HSI_Pos (25U)®RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)¯RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk°RCC_CFGR_MCOSEL_MSI_Pos (24U)±RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)²RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk³RCC_CFGR_MCOSEL_HSE_Pos (26U)´RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)µRCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk¶RCC_CFGR_MCOSEL_PLL_Pos (24U)·RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)¸RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk¹RCC_CFGR_MCOSEL_LSI_Pos (25U)ºRCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)»RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk¼RCC_CFGR_MCOSEL_LSE_Pos (24U)½RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)¾RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_MskÀRCC_CFGR_MCOPRE_Pos (28U)ÁRCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)ÂRCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_MskÃRCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)ÄRCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)ÅRCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)ÇRCC_CFGR_MCOPRE_DIV1 (0x00000000U)ÈRCC_CFGR_MCOPRE_DIV2 (0x10000000U)ÉRCC_CFGR_MCOPRE_DIV4 (0x20000000U)ÊRCC_CFGR_MCOPRE_DIV8 (0x30000000U)ËRCC_CFGR_MCOPRE_DIV16 (0x40000000U)ÎRCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCKÏRCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLKÐRCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSIÑRCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSIÒRCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSEÓRCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLLÔRCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSIÕRCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSEÚRCC_CFGR_MCO_PRE RCC_CFGR_MCOPREÛRCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1ÜRCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2ÝRCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4ÞRCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8ßRCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16âRCC_CIER_LSIRDYIE_Pos (0U)ãRCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)äRCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_MskåRCC_CIER_LSERDYIE_Pos (1U)æRCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)çRCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_MskèRCC_CIER_HSIRDYIE_Pos (2U)éRCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)êRCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_MskëRCC_CIER_HSERDYIE_Pos (3U)ìRCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)íRCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_MskîRCC_CIER_PLLRDYIE_Pos (4U)ïRCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)ðRCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_MskñRCC_CIER_MSIRDYIE_Pos (5U)òRCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)óRCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_MskôRCC_CIER_CSSLSE_Pos (7U)õRCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos)öRCC_CIER_CSSLSE RCC_CIER_CSSLSE_MskùRCC_CIER_LSECSSIE RCC_CIER_CSSLSEüRCC_CIFR_LSIRDYF_Pos (0U)ýRCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)þRCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_MskÿRCC_CIFR_LSERDYF_Pos (1U)RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_MskRCC_CIFR_HSIRDYF_Pos (2U)RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_MskRCC_CIFR_HSERDYF_Pos (3U)RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_MskRCC_CIFR_PLLRDYF_Pos (4U)RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_MskRCC_CIFR_MSIRDYF_Pos (5U)RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_MskRCC_CIFR_CSSLSEF_Pos (7U)RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos)RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_MskRCC_CIFR_CSSHSEF_Pos (8U)RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos)RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_MskRCC_CIFR_LSECSSF RCC_CIFR_CSSLSEFRCC_CIFR_CSSF RCC_CIFR_CSSHSEFRCC_CICR_LSIRDYC_Pos (0U)RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_MskRCC_CICR_LSERDYC_Pos (1U)RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk RCC_CICR_HSIRDYC_Pos (2U)¡RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)¢RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk£RCC_CICR_HSERDYC_Pos (3U)¤RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)¥RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk¦RCC_CICR_PLLRDYC_Pos (4U)§RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)¨RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk©RCC_CICR_MSIRDYC_Pos (5U)ªRCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)«RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk¬RCC_CICR_CSSLSEC_Pos (7U)RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos)®RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk¯RCC_CICR_CSSHSEC_Pos (8U)°RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos)±RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk´RCC_CICR_LSECSSC RCC_CICR_CSSLSECµRCC_CICR_CSSC RCC_CICR_CSSHSEC·RCC_IOPRSTR_IOPARST_Pos (0U)¸RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos)¹RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_MskºRCC_IOPRSTR_IOPBRST_Pos (1U)»RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)¼RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk½RCC_IOPRSTR_IOPCRST_Pos (2U)¾RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)¿RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_MskÀRCC_IOPRSTR_IOPDRST_Pos (3U)ÁRCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)ÂRCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_MskÃRCC_IOPRSTR_IOPERST_Pos (4U)ÄRCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos)ÅRCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_MskÆRCC_IOPRSTR_IOPHRST_Pos (7U)ÇRCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)ÈRCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_MskËRCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARSTÌRCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRSTÍRCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRSTÎRCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRSTÏRCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERSTÐRCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRSTÔRCC_AHBRSTR_DMARST_Pos (0U)ÕRCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos)ÖRCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk×RCC_AHBRSTR_MIFRST_Pos (8U)ØRCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos)ÙRCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_MskÚRCC_AHBRSTR_CRCRST_Pos (12U)ÛRCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos)ÜRCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_MskßRCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARSTâRCC_APB2RSTR_SYSCFGRST_Pos (0U)ãRCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)äRCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_MskåRCC_APB2RSTR_TIM21RST_Pos (2U)æRCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)çRCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_MskèRCC_APB2RSTR_TIM22RST_Pos (5U)éRCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)êRCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_MskëRCC_APB2RSTR_ADCRST_Pos (9U)ìRCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)íRCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_MskîRCC_APB2RSTR_SPI1RST_Pos (12U)ïRCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)ðRCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_MskñRCC_APB2RSTR_USART1RST_Pos (14U)òRCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)óRCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_MskôRCC_APB2RSTR_DBGRST_Pos (22U)õRCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos)öRCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_MskùRCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRSTúRCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRSTýRCC_APB1RSTR_TIM2RST_Pos (0U)þRCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)ÿRCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_MskRCC_APB1RSTR_TIM3RST_Pos (1U)RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_MskRCC_APB1RSTR_TIM6RST_Pos (4U)RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_MskRCC_APB1RSTR_TIM7RST_Pos (5U)RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_MskRCC_APB1RSTR_WWDGRST_Pos (11U)RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_MskRCC_APB1RSTR_SPI2RST_Pos (14U)RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_MskRCC_APB1RSTR_USART2RST_Pos (17U)RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_MskRCC_APB1RSTR_LPUART1RST_Pos (18U)RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos)RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_MskRCC_APB1RSTR_USART4RST_Pos (19U)RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos)RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_MskRCC_APB1RSTR_USART5RST_Pos (20U)RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos)RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_MskRCC_APB1RSTR_I2C1RST_Pos (21U)RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_MskRCC_APB1RSTR_I2C2RST_Pos (22U)RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk¡RCC_APB1RSTR_PWRRST_Pos (28U)¢RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)£RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk¤RCC_APB1RSTR_I2C3RST_Pos (30U)¥RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)¦RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk§RCC_APB1RSTR_LPTIM1RST_Pos (31U)¨RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)©RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk¬RCC_IOPENR_IOPAEN_Pos (0U)RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos)®RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk¯RCC_IOPENR_IOPBEN_Pos (1U)°RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos)±RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk²RCC_IOPENR_IOPCEN_Pos (2U)³RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos)´RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_MskµRCC_IOPENR_IOPDEN_Pos (3U)¶RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos)·RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk¸RCC_IOPENR_IOPEEN_Pos (4U)¹RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos)ºRCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk»RCC_IOPENR_IOPHEN_Pos (7U)¼RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos)½RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_MskÀRCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAENÁRCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBENÂRCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCENÃRCC_IOPENR_GPIODEN RCC_IOPENR_IOPDENÄRCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEENÅRCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHENÈRCC_AHBENR_DMAEN_Pos (0U)ÉRCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos)ÊRCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_MskËRCC_AHBENR_MIFEN_Pos (8U)ÌRCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos)ÍRCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_MskÎRCC_AHBENR_CRCEN_Pos (12U)ÏRCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)ÐRCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_MskÓRCC_AHBENR_DMA1EN RCC_AHBENR_DMAENÖRCC_APB2ENR_SYSCFGEN_Pos (0U)×RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)ØRCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_MskÙRCC_APB2ENR_TIM21EN_Pos (2U)ÚRCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos)ÛRCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_MskÜRCC_APB2ENR_TIM22EN_Pos (5U)ÝRCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos)ÞRCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_MskßRCC_APB2ENR_FWEN_Pos (7U)àRCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos)áRCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_MskâRCC_APB2ENR_ADCEN_Pos (9U)ãRCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos)äRCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_MskåRCC_APB2ENR_SPI1EN_Pos (12U)æRCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)çRCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_MskèRCC_APB2ENR_USART1EN_Pos (14U)éRCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)êRCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_MskëRCC_APB2ENR_DBGEN_Pos (22U)ìRCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos)íRCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_MskñRCC_APB2ENR_MIFIEN RCC_APB2ENR_FWENòRCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCENóRCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGENöRCC_APB1ENR_TIM2EN_Pos (0U)÷RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)øRCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_MskùRCC_APB1ENR_TIM3EN_Pos (1U)úRCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)ûRCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_MsküRCC_APB1ENR_TIM6EN_Pos (4U)ýRCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)þRCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_MskÿRCC_APB1ENR_TIM7EN_Pos (5U)RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_MskRCC_APB1ENR_WWDGEN_Pos (11U)RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_MskRCC_APB1ENR_SPI2EN_Pos (14U)RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_MskRCC_APB1ENR_USART2EN_Pos (17U)RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_MskRCC_APB1ENR_LPUART1EN_Pos (18U)RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_MskRCC_APB1ENR_USART4EN_Pos (19U)RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos)RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_MskRCC_APB1ENR_USART5EN_Pos (20U)RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos)RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_MskRCC_APB1ENR_I2C1EN_Pos (21U)RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_MskRCC_APB1ENR_I2C2EN_Pos (22U)RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_MskRCC_APB1ENR_PWREN_Pos (28U)RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_MskRCC_APB1ENR_I2C3EN_Pos (30U)RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk RCC_APB1ENR_LPTIM1EN_Pos (31U)¡RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)¢RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk¥RCC_IOPSMENR_IOPASMEN_Pos (0U)¦RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)§RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk¨RCC_IOPSMENR_IOPBSMEN_Pos (1U)©RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)ªRCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk«RCC_IOPSMENR_IOPCSMEN_Pos (2U)¬RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk®RCC_IOPSMENR_IOPDSMEN_Pos (3U)¯RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)°RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk±RCC_IOPSMENR_IOPESMEN_Pos (4U)²RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)³RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk´RCC_IOPSMENR_IOPHSMEN_Pos (7U)µRCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)¶RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk¹RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMENºRCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN»RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN¼RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN½RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN¾RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMENÁRCC_AHBSMENR_DMASMEN_Pos (0U)ÂRCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)ÃRCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_MskÄRCC_AHBSMENR_MIFSMEN_Pos (8U)ÅRCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)ÆRCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_MskÇRCC_AHBSMENR_SRAMSMEN_Pos (9U)ÈRCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)ÉRCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_MskÊRCC_AHBSMENR_CRCSMEN_Pos (12U)ËRCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)ÌRCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_MskÏRCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMENÒRCC_APB2SMENR_SYSCFGSMEN_Pos (0U)ÓRCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)ÔRCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_MskÕRCC_APB2SMENR_TIM21SMEN_Pos (2U)ÖRCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos)×RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_MskØRCC_APB2SMENR_TIM22SMEN_Pos (5U)ÙRCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos)ÚRCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_MskÛRCC_APB2SMENR_ADCSMEN_Pos (9U)ÜRCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)ÝRCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_MskÞRCC_APB2SMENR_SPI1SMEN_Pos (12U)ßRCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)àRCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_MskáRCC_APB2SMENR_USART1SMEN_Pos (14U)âRCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)ãRCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_MskäRCC_APB2SMENR_DBGSMEN_Pos (22U)åRCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)æRCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_MskéRCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMENêRCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMENíRCC_APB1SMENR_TIM2SMEN_Pos (0U)îRCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)ïRCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_MskðRCC_APB1SMENR_TIM3SMEN_Pos (1U)ñRCC_APB1SMENR_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)òRCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_MskóRCC_APB1SMENR_TIM6SMEN_Pos (4U)ôRCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)õRCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_MsköRCC_APB1SMENR_TIM7SMEN_Pos (5U)÷RCC_APB1SMENR_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)øRCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_MskùRCC_APB1SMENR_WWDGSMEN_Pos (11U)úRCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)ûRCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_MsküRCC_APB1SMENR_SPI2SMEN_Pos (14U)ýRCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)þRCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_MskÿRCC_APB1SMENR_USART2SMEN_Pos (17U)RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos)RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_MskRCC_APB1SMENR_LPUART1SMEN_Pos (18U)RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos)RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_MskRCC_APB1SMENR_USART4SMEN_Pos (19U)RCC_APB1SMENR_USART4SMEN_Msk (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos)RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_MskRCC_APB1SMENR_USART5SMEN_Pos (20U)RCC_APB1SMENR_USART5SMEN_Msk (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos)RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_MskRCC_APB1SMENR_I2C1SMEN_Pos (21U)RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_MskRCC_APB1SMENR_I2C2SMEN_Pos (22U)RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_MskRCC_APB1SMENR_PWRSMEN_Pos (28U)RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_MskRCC_APB1SMENR_I2C3SMEN_Pos (30U)RCC_APB1SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_MskRCC_APB1SMENR_LPTIM1SMEN_Pos (31U)RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos)RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_MskRCC_CCIPR_USART1SEL_Pos (0U)RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)¡RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)¤RCC_CCIPR_USART2SEL_Pos (2U)¥RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)¦RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk§RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)¨RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)«RCC_CCIPR_LPUART1SEL_Pos (10U)¬RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk®RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)¯RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)²RCC_CCIPR_I2C1SEL_Pos (12U)³RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)´RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_MskµRCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)¶RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)¹RCC_CCIPR_I2C3SEL_Pos (16U)ºRCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)»RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk¼RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)½RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)ÀRCC_CCIPR_LPTIM1SEL_Pos (18U)ÁRCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)ÂRCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_MskÃRCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)ÄRCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)ÇRCC_CSR_LSION_Pos (0U)ÈRCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)ÉRCC_CSR_LSION RCC_CSR_LSION_MskÊRCC_CSR_LSIRDY_Pos (1U)ËRCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)ÌRCC_CSR_LSIRDY RCC_CSR_LSIRDY_MskÎRCC_CSR_LSEON_Pos (8U)ÏRCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos)ÐRCC_CSR_LSEON RCC_CSR_LSEON_MskÑRCC_CSR_LSERDY_Pos (9U)ÒRCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos)ÓRCC_CSR_LSERDY RCC_CSR_LSERDY_MskÔRCC_CSR_LSEBYP_Pos (10U)ÕRCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos)ÖRCC_CSR_LSEBYP RCC_CSR_LSEBYP_MskØRCC_CSR_LSEDRV_Pos (11U)ÙRCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos)ÚRCC_CSR_LSEDRV RCC_CSR_LSEDRV_MskÛRCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos)ÜRCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos)ÞRCC_CSR_LSECSSON_Pos (13U)ßRCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos)àRCC_CSR_LSECSSON RCC_CSR_LSECSSON_MskáRCC_CSR_LSECSSD_Pos (14U)âRCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos)ãRCC_CSR_LSECSSD RCC_CSR_LSECSSD_MskæRCC_CSR_RTCSEL_Pos (16U)çRCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos)èRCC_CSR_RTCSEL RCC_CSR_RTCSEL_MskéRCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos)êRCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos)ìRCC_CSR_RTCSEL_NOCLOCK (0x00000000U)íRCC_CSR_RTCSEL_LSE_Pos (16U)îRCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)ïRCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_MskðRCC_CSR_RTCSEL_LSI_Pos (17U)ñRCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)òRCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_MskóRCC_CSR_RTCSEL_HSE_Pos (16U)ôRCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)õRCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk÷RCC_CSR_RTCEN_Pos (18U)øRCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos)ùRCC_CSR_RTCEN RCC_CSR_RTCEN_MskúRCC_CSR_RTCRST_Pos (19U)ûRCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos)üRCC_CSR_RTCRST RCC_CSR_RTCRST_MskþRCC_CSR_RMVF_Pos (23U)ÿRCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) RCC_CSR_RMVF RCC_CSR_RMVF_Msk RCC_CSR_FWRSTF_Pos (24U) RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk RCC_CSR_OBLRSTF_Pos (25U) RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk RCC_CSR_PINRSTF_Pos (26U) RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk RCC_CSR_PORRSTF_Pos (27U) RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk RCC_CSR_SFTRSTF_Pos (28U) RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk RCC_CSR_IWDGRSTF_Pos (29U) RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk RCC_CSR_WWDGRSTF_Pos (30U) RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk RCC_CSR_LPWRRSTF_Pos (31U) RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk RCC_CSR_OBL RCC_CSR_OBLRSTF¦ RTC_TAMPER1_SUPPORT § RTC_TAMPER2_SUPPORT ¨ RTC_TAMPER3_SUPPORT © RTC_WAKEUP_SUPPORT ª RTC_BACKUP_SUPPORT  RTC_TR_PM_Pos (22U)® RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)¯ RTC_TR_PM RTC_TR_PM_Msk° RTC_TR_HT_Pos (20U)± RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)² RTC_TR_HT RTC_TR_HT_Msk³ RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)´ RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)µ RTC_TR_HU_Pos (16U)¶ RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)· RTC_TR_HU RTC_TR_HU_Msk¸ RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)¹ RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)º RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)» RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)¼ RTC_TR_MNT_Pos (12U)½ RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)¾ RTC_TR_MNT RTC_TR_MNT_Msk¿ RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)À RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)Á RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)Â RTC_TR_MNU_Pos (8U)Ã RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)Ä RTC_TR_MNU RTC_TR_MNU_MskÅ RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)Æ RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)Ç RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)È RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)É RTC_TR_ST_Pos (4U)Ê RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)Ë RTC_TR_ST RTC_TR_ST_MskÌ RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)Í RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)Î RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)Ï RTC_TR_SU_Pos (0U)Ð RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)Ñ RTC_TR_SU RTC_TR_SU_MskÒ RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)Ó RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)Ô RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)Õ RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)Ø RTC_DR_YT_Pos (20U)Ù RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)Ú RTC_DR_YT RTC_DR_YT_MskÛ RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)Ü RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)Ý RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)Þ RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)ß RTC_DR_YU_Pos (16U)à RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)á RTC_DR_YU RTC_DR_YU_Mskâ RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)ã RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)ä RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)å RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)æ RTC_DR_WDU_Pos (13U)ç RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)è RTC_DR_WDU RTC_DR_WDU_Mské RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)ê RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)ë RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)ì RTC_DR_MT_Pos (12U)í RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)î RTC_DR_MT RTC_DR_MT_Mskï RTC_DR_MU_Pos (8U)ð RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)ñ RTC_DR_MU RTC_DR_MU_Mskò RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)ó RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)ô RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)õ RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)ö RTC_DR_DT_Pos (4U)÷ RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)ø RTC_DR_DT RTC_DR_DT_Mskù RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)ú RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)û RTC_DR_DU_Pos (0U)ü RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)ý RTC_DR_DU RTC_DR_DU_Mskþ RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)ÿ RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)!RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)!RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)!RTC_CR_COE_Pos (23U)!RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)!RTC_CR_COE RTC_CR_COE_Msk!RTC_CR_OSEL_Pos (21U)!RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)!RTC_CR_OSEL RTC_CR_OSEL_Msk!RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)!RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)!RTC_CR_POL_Pos (20U)!RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)!RTC_CR_POL RTC_CR_POL_Msk!RTC_CR_COSEL_Pos (19U)!RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)!RTC_CR_COSEL RTC_CR_COSEL_Msk!RTC_CR_BKP_Pos (18U)!RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)!RTC_CR_BKP RTC_CR_BKP_Msk!RTC_CR_SUB1H_Pos (17U)!RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)!RTC_CR_SUB1H RTC_CR_SUB1H_Msk!RTC_CR_ADD1H_Pos (16U)!RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)!RTC_CR_ADD1H RTC_CR_ADD1H_Msk!RTC_CR_TSIE_Pos (15U)!RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)!RTC_CR_TSIE RTC_CR_TSIE_Msk!RTC_CR_WUTIE_Pos (14U)!RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) !RTC_CR_WUTIE RTC_CR_WUTIE_Msk¡!RTC_CR_ALRBIE_Pos (13U)¢!RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)£!RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk¤!RTC_CR_ALRAIE_Pos (12U)¥!RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)¦!RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk§!RTC_CR_TSE_Pos (11U)¨!RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)©!RTC_CR_TSE RTC_CR_TSE_Mskª!RTC_CR_WUTE_Pos (10U)«!RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)¬!RTC_CR_WUTE RTC_CR_WUTE_Msk!RTC_CR_ALRBE_Pos (9U)®!RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)¯!RTC_CR_ALRBE RTC_CR_ALRBE_Msk°!RTC_CR_ALRAE_Pos (8U)±!RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)²!RTC_CR_ALRAE RTC_CR_ALRAE_Msk³!RTC_CR_FMT_Pos (6U)´!RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)µ!RTC_CR_FMT RTC_CR_FMT_Msk¶!RTC_CR_BYPSHAD_Pos (5U)·!RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)¸!RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk¹!RTC_CR_REFCKON_Pos (4U)º!RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)»!RTC_CR_REFCKON RTC_CR_REFCKON_Msk¼!RTC_CR_TSEDGE_Pos (3U)½!RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)¾!RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk¿!RTC_CR_WUCKSEL_Pos (0U)À!RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)Á!RTC_CR_WUCKSEL RTC_CR_WUCKSEL_MskÂ!RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)Ã!RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)Ä!RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)Ç!RTC_ISR_RECALPF_Pos (16U)È!RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)É!RTC_ISR_RECALPF RTC_ISR_RECALPF_MskÊ!RTC_ISR_TAMP3F_Pos (15U)Ë!RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)Ì!RTC_ISR_TAMP3F RTC_ISR_TAMP3F_MskÍ!RTC_ISR_TAMP2F_Pos (14U)Î!RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)Ï!RTC_ISR_TAMP2F RTC_ISR_TAMP2F_MskÐ!RTC_ISR_TAMP1F_Pos (13U)Ñ!RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)Ò!RTC_ISR_TAMP1F RTC_ISR_TAMP1F_MskÓ!RTC_ISR_TSOVF_Pos (12U)Ô!RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)Õ!RTC_ISR_TSOVF RTC_ISR_TSOVF_MskÖ!RTC_ISR_TSF_Pos (11U)×!RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)Ø!RTC_ISR_TSF RTC_ISR_TSF_MskÙ!RTC_ISR_WUTF_Pos (10U)Ú!RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)Û!RTC_ISR_WUTF RTC_ISR_WUTF_MskÜ!RTC_ISR_ALRBF_Pos (9U)Ý!RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)Þ!RTC_ISR_ALRBF RTC_ISR_ALRBF_Mskß!RTC_ISR_ALRAF_Pos (8U)à!RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)á!RTC_ISR_ALRAF RTC_ISR_ALRAF_Mskâ!RTC_ISR_INIT_Pos (7U)ã!RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)ä!RTC_ISR_INIT RTC_ISR_INIT_Mskå!RTC_ISR_INITF_Pos (6U)æ!RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)ç!RTC_ISR_INITF RTC_ISR_INITF_Mskè!RTC_ISR_RSF_Pos (5U)é!RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)ê!RTC_ISR_RSF RTC_ISR_RSF_Mskë!RTC_ISR_INITS_Pos (4U)ì!RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)í!RTC_ISR_INITS RTC_ISR_INITS_Mskî!RTC_ISR_SHPF_Pos (3U)ï!RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)ð!RTC_ISR_SHPF RTC_ISR_SHPF_Mskñ!RTC_ISR_WUTWF_Pos (2U)ò!RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)ó!RTC_ISR_WUTWF RTC_ISR_WUTWF_Mskô!RTC_ISR_ALRBWF_Pos (1U)õ!RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)ö!RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk÷!RTC_ISR_ALRAWF_Pos (0U)ø!RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)ù!RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Mskü!RTC_PRER_PREDIV_A_Pos (16U)ý!RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)þ!RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Mskÿ!RTC_PRER_PREDIV_S_Pos (0U)"RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)"RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk"RTC_WUTR_WUT_Pos (0U)"RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)"RTC_WUTR_WUT RTC_WUTR_WUT_Msk"RTC_ALRMAR_MSK4_Pos (31U)"RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)"RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk"RTC_ALRMAR_WDSEL_Pos (30U)"RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)"RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk"RTC_ALRMAR_DT_Pos (28U)"RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)"RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk"RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)"RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)"RTC_ALRMAR_DU_Pos (24U)"RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)"RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk"RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)"RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)"RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)"RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)"RTC_ALRMAR_MSK3_Pos (23U)"RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)"RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk"RTC_ALRMAR_PM_Pos (22U)"RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) "RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk¡"RTC_ALRMAR_HT_Pos (20U)¢"RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)£"RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk¤"RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)¥"RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)¦"RTC_ALRMAR_HU_Pos (16U)§"RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)¨"RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk©"RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)ª"RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)«"RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)¬"RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)"RTC_ALRMAR_MSK2_Pos (15U)®"RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)¯"RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk°"RTC_ALRMAR_MNT_Pos (12U)±"RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)²"RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk³"RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)´"RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)µ"RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)¶"RTC_ALRMAR_MNU_Pos (8U)·"RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)¸"RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk¹"RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)º"RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)»"RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)¼"RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)½"RTC_ALRMAR_MSK1_Pos (7U)¾"RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)¿"RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_MskÀ"RTC_ALRMAR_ST_Pos (4U)Á"RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)Â"RTC_ALRMAR_ST RTC_ALRMAR_ST_MskÃ"RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)Ä"RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)Å"RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)Æ"RTC_ALRMAR_SU_Pos (0U)Ç"RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)È"RTC_ALRMAR_SU RTC_ALRMAR_SU_MskÉ"RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)Ê"RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)Ë"RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)Ì"RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)Ï"RTC_ALRMBR_MSK4_Pos (31U)Ð"RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)Ñ"RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_MskÒ"RTC_ALRMBR_WDSEL_Pos (30U)Ó"RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)Ô"RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_MskÕ"RTC_ALRMBR_DT_Pos (28U)Ö"RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)×"RTC_ALRMBR_DT RTC_ALRMBR_DT_MskØ"RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)Ù"RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)Ú"RTC_ALRMBR_DU_Pos (24U)Û"RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)Ü"RTC_ALRMBR_DU RTC_ALRMBR_DU_MskÝ"RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)Þ"RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)ß"RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)à"RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)á"RTC_ALRMBR_MSK3_Pos (23U)â"RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)ã"RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Mskä"RTC_ALRMBR_PM_Pos (22U)å"RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)æ"RTC_ALRMBR_PM RTC_ALRMBR_PM_Mskç"RTC_ALRMBR_HT_Pos (20U)è"RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)é"RTC_ALRMBR_HT RTC_ALRMBR_HT_Mskê"RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)ë"RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)ì"RTC_ALRMBR_HU_Pos (16U)í"RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)î"RTC_ALRMBR_HU RTC_ALRMBR_HU_Mskï"RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)ð"RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)ñ"RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)ò"RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)ó"RTC_ALRMBR_MSK2_Pos (15U)ô"RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)õ"RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Mskö"RTC_ALRMBR_MNT_Pos (12U)÷"RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)ø"RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Mskù"RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)ú"RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)û"RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)ü"RTC_ALRMBR_MNU_Pos (8U)ý"RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)þ"RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Mskÿ"RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)#RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)#RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)#RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)#RTC_ALRMBR_MSK1_Pos (7U)#RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)#RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk#RTC_ALRMBR_ST_Pos (4U)#RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)#RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk#RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)#RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)#RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)#RTC_ALRMBR_SU_Pos (0U)#RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)#RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk#RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)#RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)#RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)#RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)#RTC_WPR_KEY_Pos (0U)#RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)#RTC_WPR_KEY RTC_WPR_KEY_Msk#RTC_SSR_SS_Pos (0U)#RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)#RTC_SSR_SS RTC_SSR_SS_Msk#RTC_SHIFTR_SUBFS_Pos (0U) #RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)¡#RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk¢#RTC_SHIFTR_ADD1S_Pos (31U)£#RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)¤#RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk§#RTC_TSTR_PM_Pos (22U)¨#RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)©#RTC_TSTR_PM RTC_TSTR_PM_Mskª#RTC_TSTR_HT_Pos (20U)«#RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)¬#RTC_TSTR_HT RTC_TSTR_HT_Msk#RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)®#RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)¯#RTC_TSTR_HU_Pos (16U)°#RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)±#RTC_TSTR_HU RTC_TSTR_HU_Msk²#RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)³#RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)´#RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)µ#RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)¶#RTC_TSTR_MNT_Pos (12U)·#RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)¸#RTC_TSTR_MNT RTC_TSTR_MNT_Msk¹#RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)º#RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)»#RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)¼#RTC_TSTR_MNU_Pos (8U)½#RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)¾#RTC_TSTR_MNU RTC_TSTR_MNU_Msk¿#RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)À#RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)Á#RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)Â#RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)Ã#RTC_TSTR_ST_Pos (4U)Ä#RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)Å#RTC_TSTR_ST RTC_TSTR_ST_MskÆ#RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)Ç#RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)È#RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)É#RTC_TSTR_SU_Pos (0U)Ê#RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)Ë#RTC_TSTR_SU RTC_TSTR_SU_MskÌ#RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)Í#RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)Î#RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)Ï#RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)Ò#RTC_TSDR_WDU_Pos (13U)Ó#RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)Ô#RTC_TSDR_WDU RTC_TSDR_WDU_MskÕ#RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)Ö#RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)×#RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)Ø#RTC_TSDR_MT_Pos (12U)Ù#RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)Ú#RTC_TSDR_MT RTC_TSDR_MT_MskÛ#RTC_TSDR_MU_Pos (8U)Ü#RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)Ý#RTC_TSDR_MU RTC_TSDR_MU_MskÞ#RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)ß#RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)à#RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)á#RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)â#RTC_TSDR_DT_Pos (4U)ã#RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)ä#RTC_TSDR_DT RTC_TSDR_DT_Mskå#RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)æ#RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)ç#RTC_TSDR_DU_Pos (0U)è#RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)é#RTC_TSDR_DU RTC_TSDR_DU_Mskê#RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)ë#RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)ì#RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)í#RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)ð#RTC_TSSSR_SS_Pos (0U)ñ#RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)ò#RTC_TSSSR_SS RTC_TSSSR_SS_Mskõ#RTC_CALR_CALP_Pos (15U)ö#RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)÷#RTC_CALR_CALP RTC_CALR_CALP_Mskø#RTC_CALR_CALW8_Pos (14U)ù#RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)ú#RTC_CALR_CALW8 RTC_CALR_CALW8_Mskû#RTC_CALR_CALW16_Pos (13U)ü#RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)ý#RTC_CALR_CALW16 RTC_CALR_CALW16_Mskþ#RTC_CALR_CALM_Pos (0U)ÿ#RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM RTC_CALR_CALM_Msk$RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)$RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)$RTC_CAL_CALP RTC_CALR_CALP$RTC_CAL_CALW8 RTC_CALR_CALW8$RTC_CAL_CALW16 RTC_CALR_CALW16$RTC_CAL_CALM RTC_CALR_CALM$RTC_CAL_CALM_0 RTC_CALR_CALM_0$RTC_CAL_CALM_1 RTC_CALR_CALM_1$RTC_CAL_CALM_2 RTC_CALR_CALM_2$RTC_CAL_CALM_3 RTC_CALR_CALM_3$RTC_CAL_CALM_4 RTC_CALR_CALM_4$RTC_CAL_CALM_5 RTC_CALR_CALM_5$RTC_CAL_CALM_6 RTC_CALR_CALM_6$RTC_CAL_CALM_7 RTC_CALR_CALM_7$RTC_CAL_CALM_8 RTC_CALR_CALM_8$RTC_TAMPCR_TAMP3MF_Pos (24U)$RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)$RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk$RTC_TAMPCR_TAMP3NOERASE_Pos (23U)$RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) $RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk¡$RTC_TAMPCR_TAMP3IE_Pos (22U)¢$RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)£$RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk¤$RTC_TAMPCR_TAMP2MF_Pos (21U)¥$RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)¦$RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk§$RTC_TAMPCR_TAMP2NOERASE_Pos (20U)¨$RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)©$RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Mskª$RTC_TAMPCR_TAMP2IE_Pos (19U)«$RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)¬$RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk$RTC_TAMPCR_TAMP1MF_Pos (18U)®$RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)¯$RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk°$RTC_TAMPCR_TAMP1NOERASE_Pos (17U)±$RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)²$RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk³$RTC_TAMPCR_TAMP1IE_Pos (16U)´$RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)µ$RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk¶$RTC_TAMPCR_TAMPPUDIS_Pos (15U)·$RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)¸$RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk¹$RTC_TAMPCR_TAMPPRCH_Pos (13U)º$RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)»$RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk¼$RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)½$RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)¾$RTC_TAMPCR_TAMPFLT_Pos (11U)¿$RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)À$RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_MskÁ$RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)Â$RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)Ã$RTC_TAMPCR_TAMPFREQ_Pos (8U)Ä$RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)Å$RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_MskÆ$RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)Ç$RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)È$RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)É$RTC_TAMPCR_TAMPTS_Pos (7U)Ê$RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)Ë$RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_MskÌ$RTC_TAMPCR_TAMP3TRG_Pos (6U)Í$RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)Î$RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_MskÏ$RTC_TAMPCR_TAMP3E_Pos (5U)Ð$RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)Ñ$RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_MskÒ$RTC_TAMPCR_TAMP2TRG_Pos (4U)Ó$RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)Ô$RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_MskÕ$RTC_TAMPCR_TAMP2E_Pos (3U)Ö$RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)×$RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_MskØ$RTC_TAMPCR_TAMPIE_Pos (2U)Ù$RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)Ú$RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_MskÛ$RTC_TAMPCR_TAMP1TRG_Pos (1U)Ü$RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)Ý$RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_MskÞ$RTC_TAMPCR_TAMP1E_Pos (0U)ß$RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)à$RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Mskã$RTC_ALRMASSR_MASKSS_Pos (24U)ä$RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)å$RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Mskæ$RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)ç$RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)è$RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)é$RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)ê$RTC_ALRMASSR_SS_Pos (0U)ë$RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)ì$RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Mskï$RTC_ALRMBSSR_MASKSS_Pos (24U)ð$RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)ñ$RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Mskò$RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)ó$RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)ô$RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)õ$RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)ö$RTC_ALRMBSSR_SS_Pos (0U)÷$RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)ø$RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Mskû$RTC_OR_OUT_RMP_Pos (1U)ü$RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)ý$RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Mskþ$RTC_OR_ALARMOUTTYPE_Pos (0U)ÿ$RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)%RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk%RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP%RTC_BKP0R_Pos (0U)%RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)%RTC_BKP0R RTC_BKP0R_Msk%RTC_BKP1R_Pos (0U)%RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)%RTC_BKP1R RTC_BKP1R_Msk%RTC_BKP2R_Pos (0U)%RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)%RTC_BKP2R RTC_BKP2R_Msk%RTC_BKP3R_Pos (0U)%RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)%RTC_BKP3R RTC_BKP3R_Msk%RTC_BKP4R_Pos (0U)%RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)%RTC_BKP4R RTC_BKP4R_Msk%RTC_BKP_NUMBER (0x00000005U)ª%SPI_I2S_SUPPORT %SPI_CR1_CPHA_Pos (0U)®%SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)¯%SPI_CR1_CPHA SPI_CR1_CPHA_Msk°%SPI_CR1_CPOL_Pos (1U)±%SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)²%SPI_CR1_CPOL SPI_CR1_CPOL_Msk³%SPI_CR1_MSTR_Pos (2U)´%SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)µ%SPI_CR1_MSTR SPI_CR1_MSTR_Msk¶%SPI_CR1_BR_Pos (3U)·%SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)¸%SPI_CR1_BR SPI_CR1_BR_Msk¹%SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)º%SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)»%SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)¼%SPI_CR1_SPE_Pos (6U)½%SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)¾%SPI_CR1_SPE SPI_CR1_SPE_Msk¿%SPI_CR1_LSBFIRST_Pos (7U)À%SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)Á%SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_MskÂ%SPI_CR1_SSI_Pos (8U)Ã%SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)Ä%SPI_CR1_SSI SPI_CR1_SSI_MskÅ%SPI_CR1_SSM_Pos (9U)Æ%SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)Ç%SPI_CR1_SSM SPI_CR1_SSM_MskÈ%SPI_CR1_RXONLY_Pos (10U)É%SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)Ê%SPI_CR1_RXONLY SPI_CR1_RXONLY_MskË%SPI_CR1_DFF_Pos (11U)Ì%SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)Í%SPI_CR1_DFF SPI_CR1_DFF_MskÎ%SPI_CR1_CRCNEXT_Pos (12U)Ï%SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)Ð%SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_MskÑ%SPI_CR1_CRCEN_Pos (13U)Ò%SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)Ó%SPI_CR1_CRCEN SPI_CR1_CRCEN_MskÔ%SPI_CR1_BIDIOE_Pos (14U)Õ%SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)Ö%SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk×%SPI_CR1_BIDIMODE_Pos (15U)Ø%SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)Ù%SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_MskÜ%SPI_CR2_RXDMAEN_Pos (0U)Ý%SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)Þ%SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Mskß%SPI_CR2_TXDMAEN_Pos (1U)à%SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)á%SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Mskâ%SPI_CR2_SSOE_Pos (2U)ã%SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)ä%SPI_CR2_SSOE SPI_CR2_SSOE_Mskå%SPI_CR2_FRF_Pos (4U)æ%SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)ç%SPI_CR2_FRF SPI_CR2_FRF_Mskè%SPI_CR2_ERRIE_Pos (5U)é%SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)ê%SPI_CR2_ERRIE SPI_CR2_ERRIE_Mskë%SPI_CR2_RXNEIE_Pos (6U)ì%SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)í%SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Mskî%SPI_CR2_TXEIE_Pos (7U)ï%SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)ð%SPI_CR2_TXEIE SPI_CR2_TXEIE_Mskó%SPI_SR_RXNE_Pos (0U)ô%SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)õ%SPI_SR_RXNE SPI_SR_RXNE_Mskö%SPI_SR_TXE_Pos (1U)÷%SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)ø%SPI_SR_TXE SPI_SR_TXE_Mskù%SPI_SR_CHSIDE_Pos (2U)ú%SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)û%SPI_SR_CHSIDE SPI_SR_CHSIDE_Mskü%SPI_SR_UDR_Pos (3U)ý%SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)þ%SPI_SR_UDR SPI_SR_UDR_Mskÿ%SPI_SR_CRCERR_Pos (4U)&SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)&SPI_SR_CRCERR SPI_SR_CRCERR_Msk&SPI_SR_MODF_Pos (5U)&SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)&SPI_SR_MODF SPI_SR_MODF_Msk&SPI_SR_OVR_Pos (6U)&SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)&SPI_SR_OVR SPI_SR_OVR_Msk&SPI_SR_BSY_Pos (7U)&SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)&SPI_SR_BSY SPI_SR_BSY_Msk&SPI_SR_FRE_Pos (8U)&SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)&SPI_SR_FRE SPI_SR_FRE_Msk&SPI_DR_DR_Pos (0U)&SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)&SPI_DR_DR SPI_DR_DR_Msk&SPI_CRCPR_CRCPOLY_Pos (0U)&SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)&SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk&SPI_RXCRCR_RXCRC_Pos (0U)&SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)&SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk&SPI_TXCRCR_TXCRC_Pos (0U) &SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)¡&SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk¤&SPI_I2SCFGR_CHLEN_Pos (0U)¥&SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)¦&SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk§&SPI_I2SCFGR_DATLEN_Pos (1U)¨&SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)©&SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Mskª&SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)«&SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)¬&SPI_I2SCFGR_CKPOL_Pos (3U)&SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)®&SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk¯&SPI_I2SCFGR_I2SSTD_Pos (4U)°&SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)±&SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk²&SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)³&SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)´&SPI_I2SCFGR_PCMSYNC_Pos (7U)µ&SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)¶&SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk·&SPI_I2SCFGR_I2SCFG_Pos (8U)¸&SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)¹&SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Mskº&SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)»&SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)¼&SPI_I2SCFGR_I2SE_Pos (10U)½&SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)¾&SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk¿&SPI_I2SCFGR_I2SMOD_Pos (11U)À&SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)Á&SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_MskÂ&SPI_I2SCFGR_ASTRTEN_Pos (12U)Ã&SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)Ä&SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_MskÆ&SPI_I2SPR_I2SDIV_Pos (0U)Ç&SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)È&SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_MskÉ&SPI_I2SPR_ODD_Pos (8U)Ê&SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)Ë&SPI_I2SPR_ODD SPI_I2SPR_ODD_MskÌ&SPI_I2SPR_MCKOE_Pos (9U)Í&SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)Î&SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_MskÖ&SYSCFG_CFGR1_MEM_MODE_Pos (0U)×&SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)Ø&SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_MskÙ&SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)Ú&SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)Û&SYSCFG_CFGR1_UFB_Pos (3U)Ü&SYSCFG_CFGR1_UFB_Msk (0x1UL << SYSCFG_CFGR1_UFB_Pos)Ý&SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_MskÞ&SYSCFG_CFGR1_BOOT_MODE_Pos (8U)ß&SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos)à&SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Mská&SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos)â&SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos)å&SYSCFG_CFGR2_FWDISEN_Pos (0U)æ&SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos)ç&SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Mskè&SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)é&SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos)ê&SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Mskë&SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)ì&SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos)í&SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Mskî&SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)ï&SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos)ð&SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Mskñ&SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)ò&SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos)ó&SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Mskô&SYSCFG_CFGR2_I2C1_FMP_Pos (12U)õ&SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos)ö&SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk÷&SYSCFG_CFGR2_I2C2_FMP_Pos (13U)ø&SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos)ù&SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Mskú&SYSCFG_CFGR2_I2C3_FMP_Pos (14U)û&SYSCFG_CFGR2_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos)ü&SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Mskÿ&SYSCFG_EXTICR1_EXTI0_Pos (0U)'SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)'SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk'SYSCFG_EXTICR1_EXTI1_Pos (4U)'SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)'SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk'SYSCFG_EXTICR1_EXTI2_Pos (8U)'SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)'SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk'SYSCFG_EXTICR1_EXTI3_Pos (12U)'SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)'SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk'SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)'SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)'SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)'SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)'SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)'SYSCFG_EXTICR1_EXTI0_PH (0x00000005U)'SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)'SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)'SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)'SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)'SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)'SYSCFG_EXTICR1_EXTI1_PH (0x00000050U)£'SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)¤'SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)¥'SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)¦'SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)§'SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)¬'SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)'SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)®'SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)¯'SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)°'SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)³'SYSCFG_EXTICR2_EXTI4_Pos (0U)´'SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)µ'SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk¶'SYSCFG_EXTICR2_EXTI5_Pos (4U)·'SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)¸'SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk¹'SYSCFG_EXTICR2_EXTI6_Pos (8U)º'SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)»'SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk¼'SYSCFG_EXTICR2_EXTI7_Pos (12U)½'SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)¾'SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_MskÃ'SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)Ä'SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)Å'SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)Æ'SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)Ç'SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)Ì'SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)Í'SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)Î'SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)Ï'SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)Ð'SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)Õ'SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)Ö'SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)×'SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)Ø'SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)Ù'SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)Þ'SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)ß'SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)à'SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)á'SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)â'SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)å'SYSCFG_EXTICR3_EXTI8_Pos (0U)æ'SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)ç'SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Mskè'SYSCFG_EXTICR3_EXTI9_Pos (4U)é'SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)ê'SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Mskë'SYSCFG_EXTICR3_EXTI10_Pos (8U)ì'SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)í'SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Mskî'SYSCFG_EXTICR3_EXTI11_Pos (12U)ï'SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)ð'SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Mskõ'SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)ö'SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)÷'SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)ø'SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)ù'SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)þ'SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)ÿ'SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)(SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)(SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)(SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)(SYSCFG_EXTICR3_EXTI9_PH (0x00000050U)(SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)(SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)(SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)(SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)(SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)(SYSCFG_EXTICR3_EXTI10_PH (0x00000500U)(SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)(SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)(SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)(SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)(SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)(SYSCFG_EXTICR4_EXTI12_Pos (0U)(SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)(SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk(SYSCFG_EXTICR4_EXTI13_Pos (4U)(SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)(SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk(SYSCFG_EXTICR4_EXTI14_Pos (8U) (SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)¡(SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk¢(SYSCFG_EXTICR4_EXTI15_Pos (12U)£(SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)¤(SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk©(SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)ª(SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)«(SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)¬(SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)(SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)²(SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)³(SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)´(SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)µ(SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)¶(SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)»(SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)¼(SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)½(SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)¾(SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)¿(SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)Ä(SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)Å(SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)Æ(SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)Ç(SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)È(SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)Ì(SYSCFG_CFGR3_EN_VREFINT_Pos (0U)Í(SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos)Î(SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_MskÏ(SYSCFG_CFGR3_VREF_OUT_Pos (4U)Ð(SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos)Ñ(SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_MskÒ(SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos)Ó(SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos)Ô(SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)Õ(SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos)Ö(SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk×(SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)Ø(SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos)Ù(SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_MskÚ(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)Û(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos)Ü(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_MskÝ(SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)Þ(SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos)ß(SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Mskà(SYSCFG_CFGR3_REF_LOCK_Pos (31U)á(SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos)â(SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Mskæ(SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINTç(SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADCè(SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMPé(SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYFê(SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYFë(SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYFì(SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYFö(TIM_TIM2_REMAP_HSI_SUPPORT ÷(TIM_TIM2_REMAP_HSI48_SUPPORT ú(TIM_CR1_CEN_Pos (0U)û(TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)ü(TIM_CR1_CEN TIM_CR1_CEN_Mský(TIM_CR1_UDIS_Pos (1U)þ(TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)ÿ(TIM_CR1_UDIS TIM_CR1_UDIS_Msk)TIM_CR1_URS_Pos (2U))TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos))TIM_CR1_URS TIM_CR1_URS_Msk)TIM_CR1_OPM_Pos (3U))TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos))TIM_CR1_OPM TIM_CR1_OPM_Msk)TIM_CR1_DIR_Pos (4U))TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos))TIM_CR1_DIR TIM_CR1_DIR_Msk)TIM_CR1_CMS_Pos (5U))TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos))TIM_CR1_CMS TIM_CR1_CMS_Msk)TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos))TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos))TIM_CR1_ARPE_Pos (7U))TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos))TIM_CR1_ARPE TIM_CR1_ARPE_Msk)TIM_CR1_CKD_Pos (8U))TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos))TIM_CR1_CKD TIM_CR1_CKD_Msk)TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos))TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos))TIM_CR2_CCDS_Pos (3U))TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos))TIM_CR2_CCDS TIM_CR2_CCDS_Msk)TIM_CR2_MMS_Pos (4U) )TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)¡)TIM_CR2_MMS TIM_CR2_MMS_Msk¢)TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)£)TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)¤)TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)¦)TIM_CR2_TI1S_Pos (7U)§)TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)¨)TIM_CR2_TI1S TIM_CR2_TI1S_Msk«)TIM_SMCR_SMS_Pos (0U)¬)TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos))TIM_SMCR_SMS TIM_SMCR_SMS_Msk®)TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)¯)TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)°)TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)²)TIM_SMCR_TS_Pos (4U)³)TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)´)TIM_SMCR_TS TIM_SMCR_TS_Mskµ)TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)¶)TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)·)TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)¹)TIM_SMCR_MSM_Pos (7U)º)TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)»)TIM_SMCR_MSM TIM_SMCR_MSM_Msk½)TIM_SMCR_ETF_Pos (8U)¾)TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)¿)TIM_SMCR_ETF TIM_SMCR_ETF_MskÀ)TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)Á)TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)Â)TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)Ã)TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)Å)TIM_SMCR_ETPS_Pos (12U)Æ)TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)Ç)TIM_SMCR_ETPS TIM_SMCR_ETPS_MskÈ)TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)É)TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)Ë)TIM_SMCR_ECE_Pos (14U)Ì)TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)Í)TIM_SMCR_ECE TIM_SMCR_ECE_MskÎ)TIM_SMCR_ETP_Pos (15U)Ï)TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)Ð)TIM_SMCR_ETP TIM_SMCR_ETP_MskÓ)TIM_DIER_UIE_Pos (0U)Ô)TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)Õ)TIM_DIER_UIE TIM_DIER_UIE_MskÖ)TIM_DIER_CC1IE_Pos (1U)×)TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)Ø)TIM_DIER_CC1IE TIM_DIER_CC1IE_MskÙ)TIM_DIER_CC2IE_Pos (2U)Ú)TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)Û)TIM_DIER_CC2IE TIM_DIER_CC2IE_MskÜ)TIM_DIER_CC3IE_Pos (3U)Ý)TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)Þ)TIM_DIER_CC3IE TIM_DIER_CC3IE_Mskß)TIM_DIER_CC4IE_Pos (4U)à)TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)á)TIM_DIER_CC4IE TIM_DIER_CC4IE_Mskâ)TIM_DIER_TIE_Pos (6U)ã)TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)ä)TIM_DIER_TIE TIM_DIER_TIE_Mskå)TIM_DIER_UDE_Pos (8U)æ)TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)ç)TIM_DIER_UDE TIM_DIER_UDE_Mskè)TIM_DIER_CC1DE_Pos (9U)é)TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)ê)TIM_DIER_CC1DE TIM_DIER_CC1DE_Mskë)TIM_DIER_CC2DE_Pos (10U)ì)TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)í)TIM_DIER_CC2DE TIM_DIER_CC2DE_Mskî)TIM_DIER_CC3DE_Pos (11U)ï)TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)ð)TIM_DIER_CC3DE TIM_DIER_CC3DE_Mskñ)TIM_DIER_CC4DE_Pos (12U)ò)TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)ó)TIM_DIER_CC4DE TIM_DIER_CC4DE_Mskô)TIM_DIER_TDE_Pos (14U)õ)TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)ö)TIM_DIER_TDE TIM_DIER_TDE_Mskù)TIM_SR_UIF_Pos (0U)ú)TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)û)TIM_SR_UIF TIM_SR_UIF_Mskü)TIM_SR_CC1IF_Pos (1U)ý)TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)þ)TIM_SR_CC1IF TIM_SR_CC1IF_Mskÿ)TIM_SR_CC2IF_Pos (2U)*TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)*TIM_SR_CC2IF TIM_SR_CC2IF_Msk*TIM_SR_CC3IF_Pos (3U)*TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)*TIM_SR_CC3IF TIM_SR_CC3IF_Msk*TIM_SR_CC4IF_Pos (4U)*TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)*TIM_SR_CC4IF TIM_SR_CC4IF_Msk*TIM_SR_TIF_Pos (6U)*TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)*TIM_SR_TIF TIM_SR_TIF_Msk*TIM_SR_CC1OF_Pos (9U)*TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)*TIM_SR_CC1OF TIM_SR_CC1OF_Msk*TIM_SR_CC2OF_Pos (10U)*TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)*TIM_SR_CC2OF TIM_SR_CC2OF_Msk*TIM_SR_CC3OF_Pos (11U)*TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)*TIM_SR_CC3OF TIM_SR_CC3OF_Msk*TIM_SR_CC4OF_Pos (12U)*TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)*TIM_SR_CC4OF TIM_SR_CC4OF_Msk*TIM_EGR_UG_Pos (0U)*TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)*TIM_EGR_UG TIM_EGR_UG_Msk*TIM_EGR_CC1G_Pos (1U)*TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)*TIM_EGR_CC1G TIM_EGR_CC1G_Msk*TIM_EGR_CC2G_Pos (2U) *TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)¡*TIM_EGR_CC2G TIM_EGR_CC2G_Msk¢*TIM_EGR_CC3G_Pos (3U)£*TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)¤*TIM_EGR_CC3G TIM_EGR_CC3G_Msk¥*TIM_EGR_CC4G_Pos (4U)¦*TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)§*TIM_EGR_CC4G TIM_EGR_CC4G_Msk¨*TIM_EGR_TG_Pos (6U)©*TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)ª*TIM_EGR_TG TIM_EGR_TG_Msk*TIM_CCMR1_CC1S_Pos (0U)®*TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)¯*TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk°*TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)±*TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)³*TIM_CCMR1_OC1FE_Pos (2U)´*TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)µ*TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk¶*TIM_CCMR1_OC1PE_Pos (3U)·*TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)¸*TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Mskº*TIM_CCMR1_OC1M_Pos (4U)»*TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)¼*TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk½*TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)¾*TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)¿*TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)Á*TIM_CCMR1_OC1CE_Pos (7U)Â*TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)Ã*TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_MskÅ*TIM_CCMR1_CC2S_Pos (8U)Æ*TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)Ç*TIM_CCMR1_CC2S TIM_CCMR1_CC2S_MskÈ*TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)É*TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)Ë*TIM_CCMR1_OC2FE_Pos (10U)Ì*TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)Í*TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_MskÎ*TIM_CCMR1_OC2PE_Pos (11U)Ï*TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)Ð*TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_MskÒ*TIM_CCMR1_OC2M_Pos (12U)Ó*TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)Ô*TIM_CCMR1_OC2M TIM_CCMR1_OC2M_MskÕ*TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)Ö*TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)×*TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)Ù*TIM_CCMR1_OC2CE_Pos (15U)Ú*TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)Û*TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Mskß*TIM_CCMR1_IC1PSC_Pos (2U)à*TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)á*TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Mskâ*TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)ã*TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)å*TIM_CCMR1_IC1F_Pos (4U)æ*TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)ç*TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Mskè*TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)é*TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)ê*TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)ë*TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)í*TIM_CCMR1_IC2PSC_Pos (10U)î*TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)ï*TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Mskð*TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)ñ*TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)ó*TIM_CCMR1_IC2F_Pos (12U)ô*TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)õ*TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Mskö*TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)÷*TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)ø*TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)ù*TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)ü*TIM_CCMR2_CC3S_Pos (0U)ý*TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)þ*TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Mskÿ*TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)+TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)+TIM_CCMR2_OC3FE_Pos (2U)+TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)+TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk+TIM_CCMR2_OC3PE_Pos (3U)+TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)+TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk+TIM_CCMR2_OC3M_Pos (4U)+TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)+TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk+TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)+TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)+TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)+TIM_CCMR2_OC3CE_Pos (7U)+TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)+TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk+TIM_CCMR2_CC4S_Pos (8U)+TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)+TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk+TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)+TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)+TIM_CCMR2_OC4FE_Pos (10U)+TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)+TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk+TIM_CCMR2_OC4PE_Pos (11U)+TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)+TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk¡+TIM_CCMR2_OC4M_Pos (12U)¢+TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)£+TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk¤+TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)¥+TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)¦+TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)¨+TIM_CCMR2_OC4CE_Pos (15U)©+TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)ª+TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk®+TIM_CCMR2_IC3PSC_Pos (2U)¯+TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)°+TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk±+TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)²+TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)´+TIM_CCMR2_IC3F_Pos (4U)µ+TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)¶+TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk·+TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)¸+TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)¹+TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)º+TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)¼+TIM_CCMR2_IC4PSC_Pos (10U)½+TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)¾+TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk¿+TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)À+TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)Â+TIM_CCMR2_IC4F_Pos (12U)Ã+TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)Ä+TIM_CCMR2_IC4F TIM_CCMR2_IC4F_MskÅ+TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)Æ+TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)Ç+TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)È+TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)Ë+TIM_CCER_CC1E_Pos (0U)Ì+TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)Í+TIM_CCER_CC1E TIM_CCER_CC1E_MskÎ+TIM_CCER_CC1P_Pos (1U)Ï+TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)Ð+TIM_CCER_CC1P TIM_CCER_CC1P_MskÑ+TIM_CCER_CC1NP_Pos (3U)Ò+TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)Ó+TIM_CCER_CC1NP TIM_CCER_CC1NP_MskÔ+TIM_CCER_CC2E_Pos (4U)Õ+TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)Ö+TIM_CCER_CC2E TIM_CCER_CC2E_Msk×+TIM_CCER_CC2P_Pos (5U)Ø+TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)Ù+TIM_CCER_CC2P TIM_CCER_CC2P_MskÚ+TIM_CCER_CC2NP_Pos (7U)Û+TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)Ü+TIM_CCER_CC2NP TIM_CCER_CC2NP_MskÝ+TIM_CCER_CC3E_Pos (8U)Þ+TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)ß+TIM_CCER_CC3E TIM_CCER_CC3E_Mskà+TIM_CCER_CC3P_Pos (9U)á+TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)â+TIM_CCER_CC3P TIM_CCER_CC3P_Mskã+TIM_CCER_CC3NP_Pos (11U)ä+TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)å+TIM_CCER_CC3NP TIM_CCER_CC3NP_Mskæ+TIM_CCER_CC4E_Pos (12U)ç+TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)è+TIM_CCER_CC4E TIM_CCER_CC4E_Mské+TIM_CCER_CC4P_Pos (13U)ê+TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)ë+TIM_CCER_CC4P TIM_CCER_CC4P_Mskì+TIM_CCER_CC4NP_Pos (15U)í+TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)î+TIM_CCER_CC4NP TIM_CCER_CC4NP_Mskñ+TIM_CNT_CNT_Pos (0U)ò+TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos)ó+TIM_CNT_CNT TIM_CNT_CNT_Mskö+TIM_PSC_PSC_Pos (0U)÷+TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)ø+TIM_PSC_PSC TIM_PSC_PSC_Mskû+TIM_ARR_ARR_Pos (0U)ü+TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos)ý+TIM_ARR_ARR TIM_ARR_ARR_Msk,TIM_CCR1_CCR1_Pos (0U),TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos),TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk,TIM_CCR2_CCR2_Pos (0U),TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos),TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk,TIM_CCR3_CCR3_Pos (0U),TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos),TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk,TIM_CCR4_CCR4_Pos (0U),TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos),TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk,TIM_DCR_DBA_Pos (0U),TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos),TIM_DCR_DBA TIM_DCR_DBA_Msk,TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos),TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos),TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos),TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos),TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos),TIM_DCR_DBL_Pos (8U),TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos),TIM_DCR_DBL TIM_DCR_DBL_Msk ,TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)¡,TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)¢,TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)£,TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)¤,TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)§,TIM_DMAR_DMAB_Pos (0U)¨,TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)©,TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk¬,TIM2_OR_ETR_RMP_Pos (0U),TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos)®,TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk¯,TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos)°,TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos)±,TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos)²,TIM2_OR_TI4_RMP_Pos (3U)³,TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos)´,TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Mskµ,TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos)¶,TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos)¸,TIM21_OR_ETR_RMP_Pos (0U)¹,TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos)º,TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk»,TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos)¼,TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos)½,TIM21_OR_TI1_RMP_Pos (2U)¾,TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos)¿,TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_MskÀ,TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos)Á,TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos)Â,TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos)Ã,TIM21_OR_TI2_RMP_Pos (5U)Ä,TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos)Å,TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_MskÇ,TIM22_OR_ETR_RMP_Pos (0U)È,TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos)É,TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_MskÊ,TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos)Ë,TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos)Ì,TIM22_OR_TI1_RMP_Pos (2U)Í,TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos)Î,TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_MskÏ,TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos)Ð,TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos)Ò,TIM3_OR_ETR_RMP_Pos (0U)Ó,TIM3_OR_ETR_RMP_Msk (0x3UL << TIM3_OR_ETR_RMP_Pos)Ô,TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_MskÕ,TIM3_OR_ETR_RMP_0 (0x1UL << TIM3_OR_ETR_RMP_Pos)Ö,TIM3_OR_ETR_RMP_1 (0x2UL << TIM3_OR_ETR_RMP_Pos)×,TIM3_OR_TI1_RMP_Pos (2U)Ø,TIM3_OR_TI1_RMP_Msk (0x1UL << TIM3_OR_TI1_RMP_Pos)Ù,TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_MskÚ,TIM3_OR_TI2_RMP_Pos (3U)Û,TIM3_OR_TI2_RMP_Msk (0x1UL << TIM3_OR_TI2_RMP_Pos)Ü,TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_MskÝ,TIM3_OR_TI4_RMP_Pos (4U)Þ,TIM3_OR_TI4_RMP_Msk (0x1UL << TIM3_OR_TI4_RMP_Pos)ß,TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Mskî,USART_CR1_UE_Pos (0U)ï,USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)ð,USART_CR1_UE USART_CR1_UE_Mskñ,USART_CR1_UESM_Pos (1U)ò,USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)ó,USART_CR1_UESM USART_CR1_UESM_Mskô,USART_CR1_RE_Pos (2U)õ,USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)ö,USART_CR1_RE USART_CR1_RE_Msk÷,USART_CR1_TE_Pos (3U)ø,USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)ù,USART_CR1_TE USART_CR1_TE_Mskú,USART_CR1_IDLEIE_Pos (4U)û,USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)ü,USART_CR1_IDLEIE USART_CR1_IDLEIE_Mský,USART_CR1_RXNEIE_Pos (5U)þ,USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)ÿ,USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk-USART_CR1_TCIE_Pos (6U)-USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)-USART_CR1_TCIE USART_CR1_TCIE_Msk-USART_CR1_TXEIE_Pos (7U)-USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)-USART_CR1_TXEIE USART_CR1_TXEIE_Msk-USART_CR1_PEIE_Pos (8U)-USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)-USART_CR1_PEIE USART_CR1_PEIE_Msk-USART_CR1_PS_Pos (9U)-USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)-USART_CR1_PS USART_CR1_PS_Msk-USART_CR1_PCE_Pos (10U)-USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)-USART_CR1_PCE USART_CR1_PCE_Msk-USART_CR1_WAKE_Pos (11U)-USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)-USART_CR1_WAKE USART_CR1_WAKE_Msk-USART_CR1_M_Pos (12U)-USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)-USART_CR1_M USART_CR1_M_Msk-USART_CR1_M0_Pos (12U)-USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)-USART_CR1_M0 USART_CR1_M0_Msk-USART_CR1_MME_Pos (13U)-USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)-USART_CR1_MME USART_CR1_MME_Msk-USART_CR1_CMIE_Pos (14U)-USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)-USART_CR1_CMIE USART_CR1_CMIE_Msk-USART_CR1_OVER8_Pos (15U)-USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) -USART_CR1_OVER8 USART_CR1_OVER8_Msk¡-USART_CR1_DEDT_Pos (16U)¢-USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)£-USART_CR1_DEDT USART_CR1_DEDT_Msk¤-USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)¥-USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)¦-USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)§-USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)¨-USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)©-USART_CR1_DEAT_Pos (21U)ª-USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)«-USART_CR1_DEAT USART_CR1_DEAT_Msk¬-USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)-USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)®-USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)¯-USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)°-USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)±-USART_CR1_RTOIE_Pos (26U)²-USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)³-USART_CR1_RTOIE USART_CR1_RTOIE_Msk´-USART_CR1_EOBIE_Pos (27U)µ-USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)¶-USART_CR1_EOBIE USART_CR1_EOBIE_Msk·-USART_CR1_M1_Pos (28U)¸-USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)¹-USART_CR1_M1 USART_CR1_M1_Msk»-USART_CR2_ADDM7_Pos (4U)¼-USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)½-USART_CR2_ADDM7 USART_CR2_ADDM7_Msk¾-USART_CR2_LBDL_Pos (5U)¿-USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)À-USART_CR2_LBDL USART_CR2_LBDL_MskÁ-USART_CR2_LBDIE_Pos (6U)Â-USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)Ã-USART_CR2_LBDIE USART_CR2_LBDIE_MskÄ-USART_CR2_LBCL_Pos (8U)Å-USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)Æ-USART_CR2_LBCL USART_CR2_LBCL_MskÇ-USART_CR2_CPHA_Pos (9U)È-USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)É-USART_CR2_CPHA USART_CR2_CPHA_MskÊ-USART_CR2_CPOL_Pos (10U)Ë-USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)Ì-USART_CR2_CPOL USART_CR2_CPOL_MskÍ-USART_CR2_CLKEN_Pos (11U)Î-USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)Ï-USART_CR2_CLKEN USART_CR2_CLKEN_MskÐ-USART_CR2_STOP_Pos (12U)Ñ-USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)Ò-USART_CR2_STOP USART_CR2_STOP_MskÓ-USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)Ô-USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)Õ-USART_CR2_LINEN_Pos (14U)Ö-USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)×-USART_CR2_LINEN USART_CR2_LINEN_MskØ-USART_CR2_SWAP_Pos (15U)Ù-USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)Ú-USART_CR2_SWAP USART_CR2_SWAP_MskÛ-USART_CR2_RXINV_Pos (16U)Ü-USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)Ý-USART_CR2_RXINV USART_CR2_RXINV_MskÞ-USART_CR2_TXINV_Pos (17U)ß-USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)à-USART_CR2_TXINV USART_CR2_TXINV_Mská-USART_CR2_DATAINV_Pos (18U)â-USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)ã-USART_CR2_DATAINV USART_CR2_DATAINV_Mskä-USART_CR2_MSBFIRST_Pos (19U)å-USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)æ-USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Mskç-USART_CR2_ABREN_Pos (20U)è-USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)é-USART_CR2_ABREN USART_CR2_ABREN_Mskê-USART_CR2_ABRMODE_Pos (21U)ë-USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)ì-USART_CR2_ABRMODE USART_CR2_ABRMODE_Mskí-USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)î-USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)ï-USART_CR2_RTOEN_Pos (23U)ð-USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)ñ-USART_CR2_RTOEN USART_CR2_RTOEN_Mskò-USART_CR2_ADD_Pos (24U)ó-USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)ô-USART_CR2_ADD USART_CR2_ADD_Msk÷-USART_CR3_EIE_Pos (0U)ø-USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)ù-USART_CR3_EIE USART_CR3_EIE_Mskú-USART_CR3_IREN_Pos (1U)û-USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)ü-USART_CR3_IREN USART_CR3_IREN_Mský-USART_CR3_IRLP_Pos (2U)þ-USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)ÿ-USART_CR3_IRLP USART_CR3_IRLP_Msk.USART_CR3_HDSEL_Pos (3U).USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos).USART_CR3_HDSEL USART_CR3_HDSEL_Msk.USART_CR3_NACK_Pos (4U).USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos).USART_CR3_NACK USART_CR3_NACK_Msk.USART_CR3_SCEN_Pos (5U).USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos).USART_CR3_SCEN USART_CR3_SCEN_Msk.USART_CR3_DMAR_Pos (6U).USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos).USART_CR3_DMAR USART_CR3_DMAR_Msk.USART_CR3_DMAT_Pos (7U).USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos).USART_CR3_DMAT USART_CR3_DMAT_Msk.USART_CR3_RTSE_Pos (8U).USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos).USART_CR3_RTSE USART_CR3_RTSE_Msk.USART_CR3_CTSE_Pos (9U).USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos).USART_CR3_CTSE USART_CR3_CTSE_Msk.USART_CR3_CTSIE_Pos (10U).USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos).USART_CR3_CTSIE USART_CR3_CTSIE_Msk.USART_CR3_ONEBIT_Pos (11U).USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos).USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk.USART_CR3_OVRDIS_Pos (12U).USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos).USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk.USART_CR3_DDRE_Pos (13U).USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) .USART_CR3_DDRE USART_CR3_DDRE_Msk¡.USART_CR3_DEM_Pos (14U)¢.USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)£.USART_CR3_DEM USART_CR3_DEM_Msk¤.USART_CR3_DEP_Pos (15U)¥.USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)¦.USART_CR3_DEP USART_CR3_DEP_Msk§.USART_CR3_SCARCNT_Pos (17U)¨.USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)©.USART_CR3_SCARCNT USART_CR3_SCARCNT_Mskª.USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)«.USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)¬.USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos).USART_CR3_WUS_Pos (20U)®.USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)¯.USART_CR3_WUS USART_CR3_WUS_Msk°.USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)±.USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)².USART_CR3_WUFIE_Pos (22U)³.USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)´.USART_CR3_WUFIE USART_CR3_WUFIE_Mskµ.USART_CR3_UCESM_Pos (23U)¶.USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)·.USART_CR3_UCESM USART_CR3_UCESM_Mskº.USART_BRR_DIV_FRACTION_Pos (0U)».USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)¼.USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk½.USART_BRR_DIV_MANTISSA_Pos (4U)¾.USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)¿.USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_MskÂ.USART_GTPR_PSC_Pos (0U)Ã.USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)Ä.USART_GTPR_PSC USART_GTPR_PSC_MskÅ.USART_GTPR_GT_Pos (8U)Æ.USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)Ç.USART_GTPR_GT USART_GTPR_GT_MskË.USART_RTOR_RTO_Pos (0U)Ì.USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)Í.USART_RTOR_RTO USART_RTOR_RTO_MskÎ.USART_RTOR_BLEN_Pos (24U)Ï.USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)Ð.USART_RTOR_BLEN USART_RTOR_BLEN_MskÓ.USART_RQR_ABRRQ_Pos (0U)Ô.USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)Õ.USART_RQR_ABRRQ USART_RQR_ABRRQ_MskÖ.USART_RQR_SBKRQ_Pos (1U)×.USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)Ø.USART_RQR_SBKRQ USART_RQR_SBKRQ_MskÙ.USART_RQR_MMRQ_Pos (2U)Ú.USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)Û.USART_RQR_MMRQ USART_RQR_MMRQ_MskÜ.USART_RQR_RXFRQ_Pos (3U)Ý.USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)Þ.USART_RQR_RXFRQ USART_RQR_RXFRQ_Mskß.USART_RQR_TXFRQ_Pos (4U)à.USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)á.USART_RQR_TXFRQ USART_RQR_TXFRQ_Mskä.USART_ISR_PE_Pos (0U)å.USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)æ.USART_ISR_PE USART_ISR_PE_Mskç.USART_ISR_FE_Pos (1U)è.USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)é.USART_ISR_FE USART_ISR_FE_Mskê.USART_ISR_NE_Pos (2U)ë.USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)ì.USART_ISR_NE USART_ISR_NE_Mskí.USART_ISR_ORE_Pos (3U)î.USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)ï.USART_ISR_ORE USART_ISR_ORE_Mskð.USART_ISR_IDLE_Pos (4U)ñ.USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)ò.USART_ISR_IDLE USART_ISR_IDLE_Mskó.USART_ISR_RXNE_Pos (5U)ô.USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)õ.USART_ISR_RXNE USART_ISR_RXNE_Mskö.USART_ISR_TC_Pos (6U)÷.USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)ø.USART_ISR_TC USART_ISR_TC_Mskù.USART_ISR_TXE_Pos (7U)ú.USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)û.USART_ISR_TXE USART_ISR_TXE_Mskü.USART_ISR_LBDF_Pos (8U)ý.USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)þ.USART_ISR_LBDF USART_ISR_LBDF_Mskÿ.USART_ISR_CTSIF_Pos (9U)/USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)/USART_ISR_CTSIF USART_ISR_CTSIF_Msk/USART_ISR_CTS_Pos (10U)/USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)/USART_ISR_CTS USART_ISR_CTS_Msk/USART_ISR_RTOF_Pos (11U)/USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)/USART_ISR_RTOF USART_ISR_RTOF_Msk/USART_ISR_EOBF_Pos (12U)/USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)/USART_ISR_EOBF USART_ISR_EOBF_Msk/USART_ISR_ABRE_Pos (14U)/USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)/USART_ISR_ABRE USART_ISR_ABRE_Msk/USART_ISR_ABRF_Pos (15U)/USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)/USART_ISR_ABRF USART_ISR_ABRF_Msk/USART_ISR_BUSY_Pos (16U)/USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)/USART_ISR_BUSY USART_ISR_BUSY_Msk/USART_ISR_CMF_Pos (17U)/USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)/USART_ISR_CMF USART_ISR_CMF_Msk/USART_ISR_SBKF_Pos (18U)/USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)/USART_ISR_SBKF USART_ISR_SBKF_Msk/USART_ISR_RWU_Pos (19U)/USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)/USART_ISR_RWU USART_ISR_RWU_Msk/USART_ISR_WUF_Pos (20U)/USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)/USART_ISR_WUF USART_ISR_WUF_Msk /USART_ISR_TEACK_Pos (21U)¡/USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)¢/USART_ISR_TEACK USART_ISR_TEACK_Msk£/USART_ISR_REACK_Pos (22U)¤/USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)¥/USART_ISR_REACK USART_ISR_REACK_Msk¨/USART_ICR_PECF_Pos (0U)©/USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)ª/USART_ICR_PECF USART_ICR_PECF_Msk«/USART_ICR_FECF_Pos (1U)¬/USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)/USART_ICR_FECF USART_ICR_FECF_Msk®/USART_ICR_NCF_Pos (2U)¯/USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)°/USART_ICR_NCF USART_ICR_NCF_Msk±/USART_ICR_ORECF_Pos (3U)²/USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)³/USART_ICR_ORECF USART_ICR_ORECF_Msk´/USART_ICR_IDLECF_Pos (4U)µ/USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)¶/USART_ICR_IDLECF USART_ICR_IDLECF_Msk·/USART_ICR_TCCF_Pos (6U)¸/USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)¹/USART_ICR_TCCF USART_ICR_TCCF_Mskº/USART_ICR_LBDCF_Pos (8U)»/USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)¼/USART_ICR_LBDCF USART_ICR_LBDCF_Msk½/USART_ICR_CTSCF_Pos (9U)¾/USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)¿/USART_ICR_CTSCF USART_ICR_CTSCF_MskÀ/USART_ICR_RTOCF_Pos (11U)Á/USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)Â/USART_ICR_RTOCF USART_ICR_RTOCF_MskÃ/USART_ICR_EOBCF_Pos (12U)Ä/USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)Å/USART_ICR_EOBCF USART_ICR_EOBCF_MskÆ/USART_ICR_CMCF_Pos (17U)Ç/USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)È/USART_ICR_CMCF USART_ICR_CMCF_MskÉ/USART_ICR_WUCF_Pos (20U)Ê/USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)Ë/USART_ICR_WUCF USART_ICR_WUCF_MskÎ/USART_ICR_NECF USART_ICR_NCFÑ/USART_RDR_RDR_Pos (0U)Ò/USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)Ó/USART_RDR_RDR USART_RDR_RDR_MskÖ/USART_TDR_TDR_Pos (0U)×/USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)Ø/USART_TDR_TDR USART_TDR_TDR_Mská/WWDG_CR_T_Pos (0U)â/WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)ã/WWDG_CR_T WWDG_CR_T_Mskä/WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)å/WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)æ/WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)ç/WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)è/WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)é/WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)ê/WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)í/WWDG_CR_T0 WWDG_CR_T_0î/WWDG_CR_T1 WWDG_CR_T_1ï/WWDG_CR_T2 WWDG_CR_T_2ð/WWDG_CR_T3 WWDG_CR_T_3ñ/WWDG_CR_T4 WWDG_CR_T_4ò/WWDG_CR_T5 WWDG_CR_T_5ó/WWDG_CR_T6 WWDG_CR_T_6õ/WWDG_CR_WDGA_Pos (7U)ö/WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)÷/WWDG_CR_WDGA WWDG_CR_WDGA_Mskú/WWDG_CFR_W_Pos (0U)û/WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)ü/WWDG_CFR_W WWDG_CFR_W_Mský/WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)þ/WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)ÿ/WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)0WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)0WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)0WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)0WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)0WWDG_CFR_W0 WWDG_CFR_W_00WWDG_CFR_W1 WWDG_CFR_W_10WWDG_CFR_W2 WWDG_CFR_W_20WWDG_CFR_W3 WWDG_CFR_W_30WWDG_CFR_W4 WWDG_CFR_W_40WWDG_CFR_W5 WWDG_CFR_W_50WWDG_CFR_W6 WWDG_CFR_W_60WWDG_CFR_WDGTB_Pos (7U)0WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)0WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk0WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)0WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)0WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_00WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_10WWDG_CFR_EWI_Pos (9U)0WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)0WWDG_CFR_EWI WWDG_CFR_EWI_Msk0WWDG_SR_EWIF_Pos (0U)0WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)0WWDG_SR_EWIF WWDG_SR_EWIF_Msk®0IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)¯0IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)²0IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))µ0IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)¸0IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)»0IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5) || ((INSTANCE) == DMA1_Channel6) || ((INSTANCE) == DMA1_Channel7))Ä0IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE) || ((INSTANCE) == GPIOH))Ë0IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE))Ò0IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2) || ((INSTANCE) == I2C3))×0IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C3))Ü0IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)à0IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)ã0IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C3))ç0IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2))ë0IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)î0IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)ñ0IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))ù0IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))ÿ0IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))1IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))1IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))1IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7))1IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))1IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))1IS_TIM_CCX_INSTANCE(INSTANCE,CHANNEL) (((((INSTANCE) == TIM2) || ((INSTANCE) == TIM3)) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM21) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM22) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))))1IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))³1IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21))¸1IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))¾1IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21))Ã1IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))É1IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))Ï1IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))Õ1IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))Û1IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))ã1IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))é1IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))ï1IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))ó1IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))÷1IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5))ý1IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5))2IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))2IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == LPUART1))2IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == LPUART1))2IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))2IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == LPUART1))2IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == LPUART1))¦2IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))ª2IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))®2IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)±2IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)´2IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)Ä2RNG_LPUART1_IRQn LPUART1_IRQnÅ2AES_LPUART1_IRQn LPUART1_IRQnÆ2AES_RNG_LPUART1_IRQn LPUART1_IRQnÇ2TIM6_DAC_IRQn TIM6_IRQnÈ2RCC_CRS_IRQn RCC_IRQnÉ2DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQnÊ2ADC1_IRQn ADC1_COMP_IRQnË2SVC_IRQn SVCall_IRQnÎ2RNG_LPUART1_IRQHandler LPUART1_IRQHandlerÏ2AES_LPUART1_IRQHandler LPUART1_IRQHandlerÐ2AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandlerÑ2TIM6_DAC_IRQHandler TIM6_IRQHandlerÒ2RCC_CRS_IRQHandler RCC_IRQHandlerÓ2DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandlerÔ2ADC1_IRQHandler ADC1_COMP_IRQHandlerÐÅ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/../Drivers/CMSIS/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\stm32l071xx.hcore_cm0plus.hsystem_stm32l0xx.hstdint.hl
../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM§NonMaskableInt_IRQnrHardFault_IRQnsSVCall_IRQn{PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQnRTC_IRQnFLASH_IRQnRCC_IRQnEXTI0_1_IRQnEXTI2_3_IRQnEXTI4_15_IRQnDMA1_Channel1_IRQn    DMA1_Channel2_3_IRQn
DMA1_Channel4_5_6_7_IRQnADC1_COMP_IRQnLPTIM1_IRQn USART4_5_IRQnTIM2_IRQnTIM3_IRQnTIM6_IRQnTIM7_IRQnTIM21_IRQnI2C3_IRQnTIM22_IRQnI2C1_IRQnI2C2_IRQnSPI1_IRQnSPI2_IRQnUSART1_IRQnUSART2_IRQnLPUART1_IRQnPIRQn_TypeÁk*§¸ISR§#IER§#CR§#CFGR1§#CFGR2§#SMPR§#RESERVED1Y#RESERVED2Y#TR§# RESERVED3Y#$CHSELR§#(ßYRESERVED4T#,DR§#@YRESERVED5z#DCALFACT§#´tYPADC_TypeDef¸*ÑCCR§#PADC_Common_TypeDefÁ*üCSR§#PCOMP_TypeDefì*¡CSR§#PCOMP_Common_TypeDef¢*±    DR§#IDR±#RESERVED0:#RESERVED1I#CR§#RESERVED2Y#INIT§#POL§#t:PCRC_TypeDef=³*
IDCODE§#CR§#APB1FZ§#APB2FZ§#PDBGMCU_TypeDefË¿*Ð
CCR§#CNDTR§#CPAR§#CMAR§#PDMA_Channel_TypeDefË*ISR§#IFCR§#PDMA_TypeDeflÑ*®CSELR§#PDMA_Request_TypeDefÖ*IMR§#EMR§#RTSR§#FTSR§#SWIER§#PR§#PEXTI_TypeDefÊä*Ê ACR§#PECR§#PDKEYR§#PEKEYR§#PRGKEYR§#OPTKEYR§#SR§#OPTR§#WRPR§# ª §RESERVED1¡#$WRPR2§#PFLASH_TypeDef)ö*£RDP§#USER§#WRP01§#WRP23§#WRP45§#POB_TypeDefà*¿,MODER§#OTYPER§#OSPEEDR§#PUPDR§#IDR§#ODR§#BSRR§#LCKR§#¨§AFR# BRR§#(PGPIO_TypeDef6*± ISR§#ICR§#IER§#CFGR§#CR§#CMP§#ARR§#CNT§#PLPTIM_TypeDefÔ¥*¥$CFGR1§#CFGR2§#î§EXTICRe#YRESERVED|#CFGR3§# PSYSCFG_TypeDefG²*È,CR1§#CR2§#OAR1§#OAR2§#TIMINGR§#TIMEOUTR§#ISR§#ICR§#PECR§# RXDR§#$TXDR§#(PI2C_TypeDef¼Ç*KR§#PR§#RLR§#SR§#WINR§#PIWDG_TypeDef\    Ô*$CSSA§#CSL§#NVDSSA§#NVDSL§#VDSSA§#VDSL§#LSSA§#LSL§#CR§# PFIREWALL_TypeDef«    å*ÏCR§#CSR§#PPWR_TypeDef5
î*TCR§#ICSCR§#CRRCR§#CFGR§#CIER§#CIFR§#CICR§#IOPRSTR§#AHBRSTR§# APB2RSTR§#$APB1RSTR§#(IOPENR§#,AHBENR§#0APB2ENR§#4APB1ENR§#8IOPSMENR§#<AHBSMENR§#@APB2SMENR§#DAPB1SMENR§#HCCIPR§#LCSR§#PPRCC_TypeDefc
*ädTR§#DR§#CR§#ISR§#PRER§#WUTR§#RESERVEDY#ALRMAR§#ALRMBR§# WPR§#$SSR§#(SHIFTR§#,TSTR§#0TSDR§#4TSSSR§#8CALR§#<TAMPCR§#@ALRMASSR§#DALRMBSSR§#HOR§#LBKP0R§#PBKP1R§#TBKP2R§#XBKP3R§#\BKP4R§#`PRTC_TypeDef¢ª*ì$CR1§#CR2§#SR§#DR§#CRCPR§#RXCRCR§#TXCRCR§#I2SCFGR§#I2SPR§# PSPI_TypeDefø»*TCR1§#CR2§#SMCR§#DIER§#SR§#EGR§#CCMR1§#CCMR2§#CCER§# CNT§#$PSC§#(ARR§#,RESERVED12Y#0CCR1§#4CCR2§#8CCR3§#<CCR4§#@RESERVED17Y#DDCR§#HDMAR§#LOR§#PPTIM_TypeDef ×*,CR1§#CR2§#CR3§#BRR§#GTPR§#RTOR§#RQR§#ISR§#ICR§# RDR§#$TDR§#(PUSART_TypeDefé*ÖCR§#CFR§#SR§#PWWDG_TypeDef2ó__STM32L0xx_HAL_H ?SYSCFG_BOOT_MAINFLASH (0x00000000U)@SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_BOOT_MODE_0ASYSCFG_BOOT_SRAM SYSCFG_CFGR1_BOOT_MODEJDBGMCU_SLEEP DBGMCU_CR_DBG_SLEEPKDBGMCU_STOP DBGMCU_CR_DBG_STOPLDBGMCU_STANDBY DBGMCU_CR_DBG_STANDBYMIS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U))kSYSCFG_VREFINT_OUT_NONE (0x00000000U)lSYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0mSYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1nSYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUTpIS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)){SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF}IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY))SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMPSYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMPSYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMPSYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMPIS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) )«__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)¬__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)³__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)´__HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)»__HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)¼__HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)Ã__HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)Ä__HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)Ë__HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)Ì__HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)Ó__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)Ô__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)Û__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)Ü__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)ã__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)ä__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)ë__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)ì__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)ó__HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)ô__HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)û__HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)ü__HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)__HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)__HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)__HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)__HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)__HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)__HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1)£__HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); } while (0)Ë__HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)Ó__HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))Ü__HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); }while(0)æ__HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); }while(0)òIS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p ../Drivers/STM32L0xx_HAL_Driver/Inc/../Core/Inc/stm32l0xx_hal.hstm32l0xx_hal_conf.hl
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMHAL_TICK_FREQ_10HZdHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZHAL_TICK_FREQ_DEFAULTPHAL_TickFreqTypeDefº7tYquwTick6quwTickPrioYquwTickFreq7p<uwTickIuwTickPrio\uwTickFreq(__STM32L0xx_H 6STM32L0 h__STM32L0xx_CMSIS_VERSION_MAIN (0x01)i__STM32L0xx_CMSIS_VERSION_SUB1 (0x09)j__STM32L0xx_CMSIS_VERSION_SUB2 (0x03)k__STM32L0xx_CMSIS_VERSION_RC (0x00)l__STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24) |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16) |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 ) |(__STM32L0xx_CMSIS_VERSION_RC))´IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))ÄSET_BIT(REG,BIT) ((REG) |= (BIT))ÆCLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))ÈREAD_BIT(REG,BIT) ((REG) & (BIT))ÊCLEAR_REG(REG) ((REG) = (0x0))ÌWRITE_REG(REG,VAL) ((REG) = (VAL))ÎREAD_REG(REG) ((REG))ÐMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))ÔATOMIC_SET_BIT(REG,BIT) do { uint32_t primask; primask = __get_PRIMASK(); __set_PRIMASK(1); SET_BIT((REG), (BIT)); __set_PRIMASK(primask); } while(0)ÞATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t primask; primask = __get_PRIMASK(); __set_PRIMASK(1); CLEAR_BIT((REG), (BIT)); __set_PRIMASK(primask); } while(0)èATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t primask; primask = __get_PRIMASK(); __set_PRIMASK(1); MODIFY_REG((REG), (CLEARMSK), (SETMASK)); __set_PRIMASK(primask); } while(0)òATOMIC_SETH_BIT(REG,BIT) ATOMIC_SET_BIT(REG, BIT)õATOMIC_CLEARH_BIT(REG,BIT) ATOMIC_CLEAR_BIT(REG, BIT)øATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)ÿ¤ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx.hstm32l071xx.hstm32l0xx_hal.hX
../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMÔRESETSETPFlagStatus¿PITStatus¿DISABLEENABLEPFunctionalStateø³ÃSUCCESSERRORPErrorStatus*ºSTM32_HAL_LEGACY #AES_FLAG_RDERR CRYP_FLAG_RDERR$AES_FLAG_WRERR CRYP_FLAG_WRERR%AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF&AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR'AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR9ADC_RESOLUTION12b ADC_RESOLUTION_12B:ADC_RESOLUTION10b ADC_RESOLUTION_10B;ADC_RESOLUTION8b ADC_RESOLUTION_8B<ADC_RESOLUTION6b ADC_RESOLUTION_6B=OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN>OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED?EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV@EOC_SEQ_CONV ADC_EOC_SEQ_CONVAEOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONVBREGULAR_GROUP ADC_REGULAR_GROUPCINJECTED_GROUP ADC_INJECTED_GROUPDREGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUPEAWD_EVENT ADC_AWD_EVENTFAWD1_EVENT ADC_AWD1_EVENTGAWD2_EVENT ADC_AWD2_EVENTHAWD3_EVENT ADC_AWD3_EVENTIOVR_EVENT ADC_OVR_EVENTJJQOVF_EVENT ADC_JQOVF_EVENTKALL_CHANNELS ADC_ALL_CHANNELSLREGULAR_CHANNELS ADC_REGULAR_CHANNELSMINJECTED_CHANNELS ADC_INJECTED_CHANNELSNSYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOROSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINTPADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1QADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2RADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4SADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6TADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8UADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGOVADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2WADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGOXADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4YADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGOZADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11[ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE]ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING^ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING_ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING`ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5bHAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSYcHAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSYdHAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOCeHAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOCfHAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNALgHAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNALhHAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1__HAL_CEC_GET_IT __HAL_CEC_GET_FLAGCOMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLECOMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLECOMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U)COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLRCOMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMONCOMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3¡COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4¢COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5£COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6¥COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT¦COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT§COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT¨COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT©COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1ªCOMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2«COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1¬COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1²COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2³COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2¸COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4¹COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5»COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW¼COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGHÃCOMP_FLAG_LOCK COMP_CSR_COMP1LOCKÓCOMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEEDÔCOMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWERé__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfigøHAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_ReverseúHAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_ReverseCRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLECRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLEDAC1_CHANNEL_1 DAC_CHANNEL_1DAC1_CHANNEL_2 DAC_CHANNEL_2DAC2_CHANNEL_1 DAC_CHANNEL_1DAC_WAVE_NONE 0x00000000UDAC_WAVE_NOISE DAC_CR_WAVE1_0DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1DAC_WAVEGENERATION_NONE DAC_WAVE_NONEDAC_WAVEGENERATION_NOISE DAC_WAVE_NOISEDAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE¸HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2¹HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4ºHAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5»HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4¼HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2½HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32¾HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6¿HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7ÀHAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67ÁHAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67ÂHAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76ÃHAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6ÄHAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7ÅHAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6ÇIS_HAL_REMAPDMA IS_DMA_REMAPÈ__HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLEÉ__HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLEÇTYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTEÈTYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORDÉTYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORDÊTYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORDËTYPEERASE_SECTORS FLASH_TYPEERASE_SECTORSÌTYPEERASE_PAGES FLASH_TYPEERASE_PAGESÍTYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGESÎTYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASEÏWRPSTATE_DISABLE OB_WRPSTATE_DISABLEÐWRPSTATE_ENABLE OB_WRPSTATE_ENABLEÑHAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUEÒOBEX_PCROP OPTIONBYTE_PCROPÓOBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIGÔPCROPSTATE_DISABLE OB_PCROP_STATE_DISABLEÕPCROPSTATE_ENABLE OB_PCROP_STATE_ENABLEÖTYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE×TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORDØTYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORDÙTYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTEÚTYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORDÛTYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORDÜTYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTEÝTYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORDÞTYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORDßPAGESIZE FLASH_PAGE_SIZEàTYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTEáTYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORDâTYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORDãVOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1äVOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2åVOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3æVOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4çTYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FASTèTYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LASTéWRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAAêWRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREABëWRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAAìWRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREABíIWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZEîIWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUNïIWDG_STOP_FREEZE OB_IWDG_STOP_FREEZEðIWDG_STOP_ACTIVE OB_IWDG_STOP_RUNñFLASH_ERROR_NONE HAL_FLASH_ERROR_NONEòFLASH_ERROR_RD HAL_FLASH_ERROR_RDóFLASH_ERROR_PG HAL_FLASH_ERROR_PROGôFLASH_ERROR_PGP HAL_FLASH_ERROR_PGSõFLASH_ERROR_WRP HAL_FLASH_ERROR_WRPöFLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV÷FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSRøFLASH_ERROR_PROG HAL_FLASH_ERROR_PROGùFLASH_ERROR_OP HAL_FLASH_ERROR_OPERATIONúFLASH_ERROR_PGA HAL_FLASH_ERROR_PGAûFLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZEüFLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZEýFLASH_ERROR_PGS HAL_FLASH_ERROR_PGSþFLASH_ERROR_MIS HAL_FLASH_ERROR_MISÿFLASH_ERROR_FAST HAL_FLASH_ERROR_FASTFLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERRFLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZEROFLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATIONFLASH_ERROR_ERS HAL_FLASH_ERROR_ERSOB_WDG_SW OB_IWDG_SWOB_WDG_HW OB_IWDG_HWOB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SETOB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESETOB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SETOB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESETIS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOROB_RDP_LEVEL0 OB_RDP_LEVEL_0OB_RDP_LEVEL1 OB_RDP_LEVEL_1OB_RDP_LEVEL2 OB_RDP_LEVEL_2OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLEOB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLEÅHAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9ÆHAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10ÇHAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6ÈHAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7ÉHAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8ÊHAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9ËHAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1ÌHAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2ÍHAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3ÕFSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDefÖFSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDefÞGET_GPIO_SOURCE GPIO_GET_INDEXßGET_GPIO_INDEX GPIO_GET_INDEXGPIO_AF0_LPTIM GPIO_AF0_LPTIM1GPIO_AF1_LPTIM GPIO_AF1_LPTIM1GPIO_AF2_LPTIM GPIO_AF2_LPTIM1GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOWGPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUMGPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGHGPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGHGPIO_AF6_DFSDM GPIO_AF6_DFSDM1ÆHRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLEDÇHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6ÈHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6ÉHRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6ÊHRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6ËHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7ÌHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7ÍHRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7ÎHRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7Ð__HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTERÑ__HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTERÒ__HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIODÓ__HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIODÔ__HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALERÕ__HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALERÖ__HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE×__HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPAREëI2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLEìI2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLEíI2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLEîI2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLEïI2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLEðI2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLEñI2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLEòI2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLEIRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLEIRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLEKR_KEY_RELOAD IWDG_KEY_RELOADKR_KEY_ENABLE IWDG_KEY_ENABLEKR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLEKR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLELPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITIONLPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONSLPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONSLPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONSLPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISINGLPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING¢LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION£LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS¤LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS¥LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS©LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONSªLPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS«LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS±HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValueÂHAL_NAND_Read_Page HAL_NAND_Read_Page_8bÃHAL_NAND_Write_Page HAL_NAND_Write_Page_8bÄHAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8bÅHAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8bÇNAND_AddressTypedef NAND_AddressTypeDefÉ__ARRAY_ADDRESS ARRAY_ADDRESSÊ__ADDR_1st_CYCLE ADDR_1ST_CYCLEË__ADDR_2nd_CYCLE ADDR_2ND_CYCLEÌ__ADDR_3rd_CYCLE ADDR_3RD_CYCLEÍ__ADDR_4th_CYCLE ADDR_4TH_CYCLEÕNOR_StatusTypedef HAL_NOR_StatusTypeDefÖNOR_SUCCESS HAL_NOR_STATUS_SUCCESS×NOR_ONGOING HAL_NOR_STATUS_ONGOINGØNOR_ERROR HAL_NOR_STATUS_ERRORÙNOR_TIMEOUT HAL_NOR_STATUS_TIMEOUTÛ__NOR_WRITE NOR_WRITEÜ__NOR_ADDR_SHIFT NOR_ADDR_SHIFTåOPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0æOPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1çOPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2èOPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3êOPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0ëOPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1ìOPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2íOPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3ïOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0ðOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1òIOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0óIOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1õOPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0öOPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1øOPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1úOPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NOûOPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0üOPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1    I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS¦    CF_DATA ATA_DATA§    CF_SECTOR_COUNT ATA_SECTOR_COUNT¨    CF_SECTOR_NUMBER ATA_SECTOR_NUMBER©    CF_CYLINDER_LOW ATA_CYLINDER_LOWª    CF_CYLINDER_HIGH ATA_CYLINDER_HIGH«    CF_CARD_HEAD ATA_CARD_HEAD¬    CF_STATUS_CMD ATA_STATUS_CMD    CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE®    CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA±    CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD²    CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD³    CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD´    CF_IDENTIFY_CMD ATA_IDENTIFY_CMD¶    PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef·    PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS¸    PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING¹    PCCARD_ERROR HAL_PCCARD_STATUS_ERRORº    PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUTÃ    FORMAT_BIN RTC_FORMAT_BINÄ    FORMAT_BCD RTC_FORMAT_BCDÆ    RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONEÇ    RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLEÈ    RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLEÉ    RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLEË    RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLEÌ    RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLEÍ    RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLEÎ    RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPTÏ    RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPTÑ    RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULTÒ    RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1Ó    RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1Ô    RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2Ö    RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE×    RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1Ø    RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1Ú    RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULTÛ    RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1Ü    RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1ý    RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1þ    RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2ÿ    RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 
SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE¡
SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE¢
SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE£
SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE¤
SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE¥
SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE¦
SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE§
SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE¨
SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE©
SMBUS_PEC_ENABLED SMBUS_PEC_ENABLEª
HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN²
SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE³
SPI_TIMODE_ENABLED SPI_TIMODE_ENABLEµ
SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE¶
SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE¸
SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE¹
SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLEÑ
CCER_CCxE_MASK TIM_CCER_CCxE_MASKÒ
CCER_CCxNE_MASK TIM_CCER_CCxNE_MASKÔ
TIM_DMABase_CR1 TIM_DMABASE_CR1Õ
TIM_DMABase_CR2 TIM_DMABASE_CR2Ö
TIM_DMABase_SMCR TIM_DMABASE_SMCR×
TIM_DMABase_DIER TIM_DMABASE_DIERØ
TIM_DMABase_SR TIM_DMABASE_SRÙ
TIM_DMABase_EGR TIM_DMABASE_EGRÚ
TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1Û
TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2Ü
TIM_DMABase_CCER TIM_DMABASE_CCERÝ
TIM_DMABase_CNT TIM_DMABASE_CNTÞ
TIM_DMABase_PSC TIM_DMABASE_PSCß
TIM_DMABase_ARR TIM_DMABASE_ARRà
TIM_DMABase_RCR TIM_DMABASE_RCRá
TIM_DMABase_CCR1 TIM_DMABASE_CCR1â
TIM_DMABase_CCR2 TIM_DMABASE_CCR2ã
TIM_DMABase_CCR3 TIM_DMABASE_CCR3ä
TIM_DMABase_CCR4 TIM_DMABASE_CCR4å
TIM_DMABase_BDTR TIM_DMABASE_BDTRæ
TIM_DMABase_DCR TIM_DMABASE_DCRç
TIM_DMABase_DMAR TIM_DMABASE_DMARè
TIM_DMABase_OR1 TIM_DMABASE_OR1é
TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3ê
TIM_DMABase_CCR5 TIM_DMABASE_CCR5ë
TIM_DMABase_CCR6 TIM_DMABASE_CCR6ì
TIM_DMABase_OR2 TIM_DMABASE_OR2í
TIM_DMABase_OR3 TIM_DMABASE_OR3î
TIM_DMABase_OR TIM_DMABASE_ORð
TIM_EventSource_Update TIM_EVENTSOURCE_UPDATEñ
TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1ò
TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2ó
TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3ô
TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4õ
TIM_EventSource_COM TIM_EVENTSOURCE_COMö
TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER÷
TIM_EventSource_Break TIM_EVENTSOURCE_BREAKø
TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2ú
TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFERû
TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERSü
TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERSý
TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERSþ
TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERSÿ
TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERSTIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERSTIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERSTIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERSTIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERSTIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERSTIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERSTIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERSTIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERSTIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERSTIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERSTIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERSTIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERSTIM22_TI1_GPIO1 TIM22_TI1_GPIOTIM22_TI1_GPIO2 TIM22_TI1_GPIO³TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING´TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING¼UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE½UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE¾UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE¿UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLEÁ__HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLEÂ__HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLEÄ__DIV_SAMPLING16 UART_DIV_SAMPLING16Å__DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16Æ__DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16Ç__UART_BRR_SAMPLING16 UART_BRR_SAMPLING16É__DIV_SAMPLING8 UART_DIV_SAMPLING8Ê__DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8Ë__DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8Ì__UART_BRR_SAMPLING8 UART_BRR_SAMPLING8Î__DIV_LPUART UART_DIV_LPUARTÐUART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINEÑUART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARKÜUSART_CLOCK_DISABLED USART_CLOCK_DISABLEÝUSART_CLOCK_ENABLED USART_CLOCK_ENABLEßUSARTNACK_ENABLED USART_NACK_ENABLEàUSARTNACK_DISABLED USART_NACK_DISABLEèCFR_BASE WWDG_CFR_BASEñCAN_FilterFIFO0 CAN_FILTER_FIFO0òCAN_FilterFIFO1 CAN_FILTER_FIFO1óCAN_IT_RQCP0 CAN_IT_TMEôCAN_IT_RQCP1 CAN_IT_TMEõCAN_IT_RQCP2 CAN_IT_TMEöINAK_TIMEOUT CAN_TIMEOUT_VALUE÷SLAK_TIMEOUT CAN_TIMEOUT_VALUEøCAN_TXSTATUS_FAILED ((uint8_t)0x00U)ùCAN_TXSTATUS_OK ((uint8_t)0x01U)úCAN_TXSTATUS_PENDING ((uint8_t)0x02U)VLAN_TAG ETH_VLAN_TAGMIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOADMAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOADJUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOADMACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASKMACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASKMACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASKDMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASKETH_MMCCR 0x00000100UETH_MMCRIR 0x00000104UETH_MMCTIR 0x00000108UETH_MMCRIMR 0x0000010CUETH_MMCTIMR 0x00000110UETH_MMCTGFSCCR 0x0000014CUETH_MMCTGFMSCCR 0x00000150UETH_MMCTGFCR 0x00000168UETH_MMCRFCECR 0x00000194UETH_MMCRFAECR 0x00000198UETH_MMCRGUFCR 0x000001C4UETH_MAC_TXFIFO_FULL 0x02000000UETH_MAC_TXFIFONOT_EMPTY 0x01000000UETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000UETH_MAC_TXFIFO_IDLE 0x00000000UETH_MAC_TXFIFO_READ 0x00100000UETH_MAC_TXFIFO_WAITING 0x00200000U¡ETH_MAC_TXFIFO_WRITING 0x00300000U£ETH_MAC_TRANSMISSION_PAUSE 0x00080000U¤ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U¥ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U§ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U©ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U«ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U¬ETH_MAC_RXFIFO_EMPTY 0x00000000UETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U¯ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U±ETH_MAC_RXFIFO_FULL 0x00000300U´ETH_MAC_READCONTROLLER_IDLE 0x00000000UµETH_MAC_READCONTROLLER_READING_DATA 0x00000020U¶ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U¹ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U»ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U¼ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U½ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U¾ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U¿ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006UÀETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001UÉHAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVRÊDCMI_IT_OVF DCMI_IT_OVRËDCMI_FLAG_OVFRI DCMI_FLAG_OVRRIÌDCMI_FLAG_OVFMI DCMI_FLAG_OVRMIÎHAL_DCMI_ConfigCROP HAL_DCMI_ConfigCropÏHAL_DCMI_EnableCROP HAL_DCMI_EnableCropÐHAL_DCMI_DisableCROP HAL_DCMI_DisableCrop HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback£ HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler¬ HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef® HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish¯ HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish° HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish± HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finishµ HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1¶ HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224· HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256¸ HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5º HASH_AlgoMode_HASH HASH_ALGOMODE_HASH» HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC½ HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY¾ HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEYÞ HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepModeß HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepModeà HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopModeá HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopModeâ HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyModeã HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyModeä HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))ç HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelectè HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())í HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())î HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgramFLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDownFLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDownHAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_UnlockHAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_LockHAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_EraseHAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_ProgramHAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilterHAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilterHAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilterHAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilterHAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) ((cmd == ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_ITHAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_ITHAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_ITHAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT£HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA¤HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA¥HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA¦HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMAÁHAL_PWR_PVDConfig HAL_PWR_ConfigPVDÂHAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpRegÃHAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDownÄHAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2MonitorÅHAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpRegÆHAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDownÇHAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2MonitorÈHAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandlerÉHAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVDÊHAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandlerËHAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallbackÌHAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDriveÍHAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDriveÎHAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADCÏHAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADCÐHAL_PWREx_PVMConfig HAL_PWREx_ConfigPVMÒPWR_MODE_NORMAL PWR_PVD_MODE_NORMALÓPWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISINGÔPWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLINGÕPWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLINGÖPWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING×PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLINGØPWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLINGÚCR_OFFSET_BB PWR_CR_OFFSET_BBÛCSR_OFFSET_BB PWR_CSR_OFFSET_BBÜPMODE_BIT_NUMBER VOS_BIT_NUMBERÝCR_PMODE_BB CR_VOS_BBßDBP_BitNumber DBP_BIT_NUMBERàPVDE_BitNumber PVDE_BIT_NUMBERáPMODE_BitNumber PMODE_BIT_NUMBERâEWUP_BitNumber EWUP_BIT_NUMBERãFPDS_BitNumber FPDS_BIT_NUMBERäODEN_BitNumber ODEN_BIT_NUMBERåODSWEN_BitNumber ODSWEN_BIT_NUMBERæMRLVDS_BitNumber MRLVDS_BIT_NUMBERçLPLVDS_BitNumber LPLVDS_BIT_NUMBERèBRE_BitNumber BRE_BIT_NUMBERêPWR_MODE_EVT PWR_PVD_MODE_NORMALØHAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_ITÙHAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallbackÚHAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallbackâHAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifoêHAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCpltëHAL_TIM_DMAError TIM_DMAErrorìHAL_TIM_DMACaptureCplt TIM_DMACaptureCpltíHAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCpltðHAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchroñHAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_ITòHAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallbackóHAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEventôHAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_ITõHAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMAþHAL_UART_WakeupCallback HAL_UARTEx_WakeupCallbackHAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallbackHAL_LTDC_Relaod HAL_LTDC_ReloadHAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfigHAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfigAES_IT_CC CRYP_IT_CCAES_IT_ERR CRYP_IT_ERRAES_FLAG_CCF CRYP_FLAG_CCF¦__HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE§__HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH¨__HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH©__HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAMª__HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC«__HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM¬__HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC__HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI®__HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK¯__HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG°__HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG±__HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE²__HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE³__HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLEµSYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY¶SYSCFG_FLAG_RC48 RCC_FLAG_HSI48·IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS¸UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER¹CMP_PD_BitNumber CMP_PD_BIT_NUMBERÃ__ADC_ENABLE __HAL_ADC_ENABLEÄ__ADC_DISABLE __HAL_ADC_DISABLEÅ__HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONSÆ__HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONSÇ__HAL_ADC_IS_ENABLED ADC_IS_ENABLEÈ__ADC_IS_ENABLED ADC_IS_ENABLEÉ__HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULARÊ__HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTEDË__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTEDÌ__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULARÍ__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTEDÎ__HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOINGÏ__HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODEÑ__HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTIONÒ__HAL_ADC_JSQR_RK ADC_JSQR_RKÓ__HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFTÔ__HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CRÕ__HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSIONÖ__HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE×__HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUSØ__HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUSÙ__HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUMÚ__HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAITÛ__HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUSÜ__HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUNÝ__HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQÞ__HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SETß__HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SETà__HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNELá__HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNELâ__HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SETã__HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GETä__HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLDæ__HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTIONç__HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTIONè__HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTIONé__HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTERê__HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTIë__HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLEì__ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLEí__HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTERî__HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHERï__HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVEñ__HAL_ADC_SQR1_L ADC_SQR1_L_SHIFTò__HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFTó__HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JLô__HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUMõ__HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SETö__HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE÷__HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGEø__HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALERú__HAL_ADC_SQR1 ADC_SQR1û__HAL_ADC_SMPR1 ADC_SMPR1ü__HAL_ADC_SMPR2 ADC_SMPR2ý__HAL_ADC_SQR3_RK ADC_SQR3_RKþ__HAL_ADC_SQR2_RK ADC_SQR2_RKÿ__HAL_ADC_SQR1_RK ADC_SQR1_RK__HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS__HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS__HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV__HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection__HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq__HAL_ADC_JSQR ADC_JSQR__HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL__HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS__HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF__HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT__HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS__HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN__HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR__HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ__HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT__HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT__HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENTIS_DAC_GENERATE_WAVE IS_DAC_WAVE£__HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1¤__HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1¥__HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2¦__HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2§__HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3¨__HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3©__HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4ª__HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4«__HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5¬__HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5__HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6®__HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6¯__HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7°__HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7±__HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8²__HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8´__HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9µ__HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9¶__HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10·__HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10¸__HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11¹__HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11º__HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12»__HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12¼__HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13½__HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13¾__HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14¿__HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14À__HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2Á__HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2Ä__HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15Å__HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15Æ__HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16Ç__HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16È__HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17É__HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17Ê__HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTCË__HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTCÒ__HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDGÓ__HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDGÔ__HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDGÕ__HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG×__HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUTØ__HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUTÙ__HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUTÚ__HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUTÛ__HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUTÜ__HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUTÝ__HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1Þ__HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1ß__HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1à__HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1á__HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2â__HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2ú__HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())ü__HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())þ__HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())__HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())__HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())__HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())__HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())__HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())__HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE__HAL_COMP_GET_FLAG(__HANDLE__,__FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))HAL_COMP_Start_IT HAL_COMP_StartHAL_COMP_Stop_IT HAL_COMP_StopªIS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE)|| ((WAVE) == DAC_WAVE_TRIANGLE))¶IS_WRPAREA IS_OB_WRPAREA·IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM¸IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM¹IS_TYPEERASE IS_FLASH_TYPEERASEºIS_NBSECTORS IS_FLASH_NBSECTORS»IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCEÅ__HAL_I2C_RESET_CR2 I2C_RESET_CR2Æ__HAL_I2C_GENERATE_START I2C_GENERATE_STARTÊ__HAL_I2C_FREQ_RANGE I2C_FREQ_RANGEÌ__HAL_I2C_RISE_TIME I2C_RISE_TIMEÍ__HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARDÎ__HAL_I2C_SPEED_FAST I2C_SPEED_FASTÏ__HAL_I2C_SPEED I2C_SPEEDÐ__HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITEÑ__HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READÒ__HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESSÓ__HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITEÔ__HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READÕ__HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSBÖ__HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB×__HAL_I2C_FREQRANGE I2C_FREQRANGEàIS_I2S_INSTANCE IS_I2S_ALL_INSTANCEáIS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXTï__IRDA_DISABLE __HAL_IRDA_DISABLEð__IRDA_ENABLE __HAL_IRDA_ENABLEò__HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCEó__HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATIONô__IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCEõ__IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION÷IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE__HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS__HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS__HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT__HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT__HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE__OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD__OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX__OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX__OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX__OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX__OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L__OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM¡__OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES¢__OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX£__OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT¤__OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION¥__OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET¯__HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT°__HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT±__HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE²__HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE³__HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE´__HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGEµ__HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE¶__HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE·__HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE¸__HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE¹__HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLEº__HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE»__HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine¼__HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine½__HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig¾__HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig¿__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)Â__HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENTÃ__HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENTÄ__HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGEÅ__HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGEÆ__HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGEÇ__HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGEÈ__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGEÉ__HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGEÊ__HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)Í__HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)Ð__HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetentionÑ__HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetentionÒ__HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2Ó__HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2Ô__HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGEÕ__HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGEÖ__HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB×__HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSBà__HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAGá__HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_ITâ__HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_ITã__HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWITä__HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAGïRCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSIðRCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSIòHAL_RCC_CCSCallback HAL_RCC_CSSCallbackóHAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())ö__ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE÷__ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLEø__ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLEù__ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLEú__ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESETû__ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESETü__ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLEý__ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLEþ__ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESETÿ__ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET__ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE__ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE__ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE__ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE__ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET__ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET__ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE__ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE__ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET__ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET__AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE__AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE__AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE__AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE__AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET__AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET__CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE__CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE__CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE__CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE__CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET__CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET__AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE__AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE__AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET__AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET__AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET__AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET__AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET__AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET__AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET__AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET¡__AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET¢__APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET£__APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET¤__APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET¥__APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET¦__BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE§__BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE¨__BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET©__BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESETª__CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE«__CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE¬__CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE__CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE®__CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET¯__CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET°__CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE±__CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE²__CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET³__CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET´__CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLEµ__CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE¶__CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET·__CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET¸__CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE¹__CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLEº__COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE»__COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE¼__COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET½__COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET¾__COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE¿__COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLEÀ__CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESETÁ__CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESETÂ__CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLEÃ__CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLEÄ__CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLEÅ__CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLEÆ__CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESETÇ__CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESETÈ__DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLEÉ__DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLEÊ__DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESETË__DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESETÌ__DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLEÍ__DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLEÎ__DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLEÏ__DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLEÐ__DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESETÑ__DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESETÒ__DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLEÓ__DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLEÔ__DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESETÕ__DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESETÖ__DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE×__DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLEØ__DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLEÙ__DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLEÚ__DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESETÛ__DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESETÜ__DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLEÝ__DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLEÞ__DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLEß__DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLEà__DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESETá__DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESETâ__DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLEã__DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLEä__DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLEå__DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLEæ__DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESETç__DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESETè__ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLEé__ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLEê__ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESETë__ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESETì__ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLEí__ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLEî__ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLEï__ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLEð__FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLEñ__FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLEò__FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLEó__FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLEô__FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLEõ__FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLEö__FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET÷__FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESETø__FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLEù__FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLEú__FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESETû__FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESETü__FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLEý__FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLEþ__FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLEÿ__FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE__FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE__FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE__FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET__FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET__FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE__FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE__GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE__GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE__GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE__GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE__GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET__GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET__GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE__GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE__GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE__GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE__GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET__GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET__GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE__GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE__GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE__GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE__GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET__GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET__GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE__GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE__GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE__GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE__GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET__GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET__GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE__GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE¡__GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE¢__GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET£__GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET¤__GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE¥__GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE¦__GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE§__GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE¨__GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET©__GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESETª__GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE«__GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE¬__GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE__GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE®__GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET¯__GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET°__GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE±__GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE²__GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE³__GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE´__GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESETµ__GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET¶__I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE·__I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE¸__I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE¹__I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLEº__I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET»__I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET¼__I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE½__I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE¾__I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE¿__I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLEÀ__I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESETÁ__I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESETÂ__I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLEÃ__I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLEÄ__I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLEÅ__I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLEÆ__I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESETÇ__I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESETÈ__LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLEÉ__LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLEÊ__LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLEË__LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLEÌ__LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESETÍ__LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESETÎ__LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLEÏ__LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLEÐ__LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLEÑ__LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLEÒ__LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESETÓ__LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESETÔ__LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLEÕ__LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLEÖ__LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE×__LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLEØ__LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESETÙ__LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESETÚ__LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLEÛ__LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLEÜ__LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLEÝ__LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLEÞ__LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESETß__LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESETà__OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLEá__OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLEâ__OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLEã__OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLEä__OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESETå__OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESETæ__OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLEç__OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLEè__OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLEé__OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLEê__OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESETë__OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESETì__PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLEí__PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLEî__PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLEï__PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLEð__PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESETñ__PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESETò__QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLEó__QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLEô__QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLEõ__QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLEö__QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET÷__QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET__RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE__RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE__RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE__RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE__RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET__RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET__SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE__SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE__SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE__SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE__SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET__SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET__SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE__SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE__SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE__SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE__SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET__SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET__SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE__SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE__SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE__SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE__SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE__SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE__SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET¡__SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE¢__SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE£__SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE¤__SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE¥__SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET¦__SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET§__SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE¨__SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE©__SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLEª__SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE«__SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET¬__SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET__SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE®__SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE¯__SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE°__SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE±__SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET²__SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET³__SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE´__SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLEµ__SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE¶__SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE·__SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE¸__SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE¹__SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLEº__SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE»__SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE¼__SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE½__SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET¾__SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET¿__SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLEÀ__SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLEÁ__SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLEÂ__SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLEÃ__SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESETÄ__SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESETÅ__TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLEÆ__TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLEÇ__TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLEÈ__TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLEÉ__TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESETÊ__TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESETË__TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLEÌ__TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLEÍ__TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESETÎ__TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESETÏ__TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLEÐ__TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLEÑ__TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESETÒ__TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESETÓ__TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLEÔ__TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLEÕ__TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESETÖ__TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET×__TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLEØ__TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLEÙ__TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESETÚ__TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESETÛ__TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLEÜ__TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLEÝ__TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESETÞ__TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESETß__TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLEà__TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLEá__TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLEâ__TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLEã__TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESETä__TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESETå__TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLEæ__TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLEç__TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLEè__TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLEé__TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESETê__TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESETë__TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLEì__TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLEí__TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLEî__TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLEï__TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESETð__TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESETñ__TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLEò__TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLEó__TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLEô__TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLEõ__TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESETö__TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET÷__TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLEø__TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLEù__TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLEú__TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLEû__TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESETü__TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESETý__TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLEþ__TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLEÿ__TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE__TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE__TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET__TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET__TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE__TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE__TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE__TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE__TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET__TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET__TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE__TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE__TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE__TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE__TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET__TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET__TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE__TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE__TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE__TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE__TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET__TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET__TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE__TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE__TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE__TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE__TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET__TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET__TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE__TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE__TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET__TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET__TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE¡__TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE¢__TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE£__TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET¤__TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET¥__UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE¦__UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE§__UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE¨__UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE©__UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESETª__UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET«__UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE¬__UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE__UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE®__UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE¯__UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET°__UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET±__USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE²__USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE³__USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE´__USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLEµ__USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET¶__USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET·__USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE¸__USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE¹__USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLEº__USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE»__USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET¼__USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET½__USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE¾__USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE¿__USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLEÀ__USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLEÁ__USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESETÂ__USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESETÃ__USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLEÄ__USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLEÅ__USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLEÆ__USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLEÇ__USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESETÈ__USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESETÉ__USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLEÊ__USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLEË__USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLEÌ__USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLEÍ__USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESETÎ__USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESETÏ__USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLEÐ__USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLEÑ__USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESETÒ__USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESETÓ__USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLEÔ__USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLEÕ__USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESETÖ__USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET×__USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLEØ__USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLEÙ__USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESETÚ__USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLEÛ__USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLEÜ__USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLEÝ__USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLEÞ__USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESETó__WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLEô__WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLEõ__WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLEö__WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE÷__WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESETø__WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESETú__TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLEû__TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLEü__TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESETý__TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESETþ__TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLEÿ__TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE__TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE__TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE__TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET__TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET__TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE__TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE__CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE__CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE__CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE__CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE__CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET__CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET__RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE__RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE__USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET__USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET__USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE__USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE__USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE__USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE__USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE__USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE__TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE__TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE__TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE__TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE__TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE__TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE__ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE__ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE__ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE¡__HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE¢__HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET£__HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET¤__HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE¥__HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE¦__HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE§__SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE¨__SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE©__SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESETª__SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET«__SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE¬__SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE__SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE®__SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE¯__SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET°__SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET±__SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE²__SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE³__LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE´__LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLEµ__LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET¶__LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET·__LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE¸__ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE¹__ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLEº__ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE»__ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE¼__ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE½__ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE¾__TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE¿__TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLEÀ__TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLEÁ__TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLEÂ__TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLEÃ__TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLEÄ__BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLEÅ__BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLEÆ__BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLEÇ__BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLEÈ__CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLEÉ__CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLEÊ__USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLEË__USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLEÌ__USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESETÍ__USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESETÎ__USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLEÏ__USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLEÐ__SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLEÑ__SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLEÒ__SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESETÓ__SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESETÔ__SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLEÕ__SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLEÖ__GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE×__GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLEØ__GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESETÙ__GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESETÚ__GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLEÛ__GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLEÜ__GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLEÝ__GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLEÞ__GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESETß__GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESETà__GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLEá__GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLEâ__GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLEã__GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLEä__GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESETå__GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLEæ__GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLEç__ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLEè__ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLEé__DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLEê__DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLEë__DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESETì__DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESETí__DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLEî__DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLEï__UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLEð__UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLEñ__UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESETò__UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESETó__UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLEô__UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLEõ__UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLEö__UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE÷__UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESETø__UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESETù__UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLEú__UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLEû__OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLEü__OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLEý__OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESETþ__OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESETÿ__OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE__OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE__HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE__HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE__HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED__HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED__HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET__HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET__HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE__HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED__SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE__CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE__CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE__DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE__DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE__ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE__ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE__ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE__ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE__FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET__FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET__FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE__FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE__SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET__SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET__SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE__SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE__DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE__DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE__DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET__DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE¡__DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE¤__HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET¥__HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET§__ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE¨__ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE©__ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLEª__ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE«__DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE¬__DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE__TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE®__TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE¯__TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE°__TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE±__TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE²__TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE³__HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE´__HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLEµ__SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE¶__SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE·__SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE¸__SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE¹__SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLEº__SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE¼__ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET½__ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET¾__ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET¿__ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESETÀ__DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESETÁ__DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESETÂ__TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESETÃ__TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESETÄ__TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESETÅ__TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESETÆ__TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESETÇ__TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESETÈ__HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESETÉ__HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESETÊ__SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESETË__SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESETÌ__SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESETÍ__SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESETÎ__SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESETÏ__SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESETÑ__ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLEDÒ__ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLEDÓ__ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLEDÔ__ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLEDÕ__ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLEDÖ__ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED×__CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLEDØ__CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLEDÙ__CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLEDÚ__CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLEDÛ__DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLEDÜ__DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLEDÝ__DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLEDÞ__DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLEDß__DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLEDà__DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLEDá__DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLEDâ__DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLEDã__FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLEDä__FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLEDå__FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLEDæ__FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLEDç__GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLEDè__GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLEDé__GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLEDê__GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLEDë__GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLEDì__GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLEDí__GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLEDî__GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLEDï__GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLEDð__GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLEDñ__GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLEDò__GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLEDó__GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLEDô__GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLEDõ__GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLEDö__GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED÷__HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLEDø__HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLEDù__I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLEDú__I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLEDû__I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLEDü__I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLEDý__I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLEDþ__I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLEDÿ__PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED__PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED__SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED__SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED__SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED__SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED__SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED__SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED__SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED__SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED__SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED__SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED__SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED__SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED__SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED__SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED__SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED__SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED__SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED__SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED__TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED__TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED__TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED__TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED__TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED__TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED__TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED__TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED__TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED__TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED__TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED__TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED__TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED¡__TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED¢__TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED£__TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED¤__TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED¥__TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED¦__TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED§__TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED¨__TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED©__TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLEDª__TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED«__TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED¬__TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED__TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED®__TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED¯__TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED°__TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED±__TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED²__TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED³__TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED´__TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLEDµ__TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED¶__TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED·__UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED¸__UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED¹__UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLEDº__UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED»__USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED¼__USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED½__USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED¾__USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED¿__USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLEDÀ__USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLEDÁ__USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLEDÂ__USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLEDÃ__WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLEDÄ__WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED__HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG__HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG__RCC_PLLSRC RCC_GET_PLL_OSCSOURCEIS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGEIS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCEIS_RCC_SYSCLK_DIV IS_RCC_HCLKIS_RCC_HCLK_DIV IS_RCC_PCLKIS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCKRCC_IT_HSI14 RCC_IT_HSI14RDYRCC_IT_CSSLSE RCC_IT_LSECSSRCC_IT_CSSHSE RCC_IT_CSSRCC_PLLMUL_3 RCC_PLL_MUL3RCC_PLLMUL_4 RCC_PLL_MUL4RCC_PLLMUL_6 RCC_PLL_MUL6RCC_PLLMUL_8 RCC_PLL_MUL8 RCC_PLLMUL_12 RCC_PLL_MUL12¡RCC_PLLMUL_16 RCC_PLL_MUL16¢RCC_PLLMUL_24 RCC_PLL_MUL24£RCC_PLLMUL_32 RCC_PLL_MUL32¤RCC_PLLMUL_48 RCC_PLL_MUL48¦RCC_PLLDIV_2 RCC_PLL_DIV2§RCC_PLLDIV_3 RCC_PLL_DIV3¨RCC_PLLDIV_4 RCC_PLL_DIV4ªIS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE«__HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG¬RCC_MCO_NODIV RCC_MCODIV_1RCC_MCO_DIV1 RCC_MCODIV_1®RCC_MCO_DIV2 RCC_MCODIV_2¯RCC_MCO_DIV4 RCC_MCODIV_4°RCC_MCO_DIV8 RCC_MCODIV_8±RCC_MCO_DIV16 RCC_MCODIV_16²RCC_MCO_DIV32 RCC_MCODIV_32³RCC_MCO_DIV64 RCC_MCODIV_64´RCC_MCO_DIV128 RCC_MCODIV_128µRCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK¶RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI·RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE¸RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK¹RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSIºRCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14»RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48¼RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE½RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK¾RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK¿RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2ÅRCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLKÈRCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1ÉRCC_USBCLK_PLL RCC_USBCLKSOURCE_PLLÊRCC_USBCLK_MSI RCC_USBCLKSOURCE_MSIËRCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLLÌRCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLLÍRCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5ÎRCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2ÏRCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3ÑHSION_BitNumber RCC_HSION_BIT_NUMBERÒHSION_BITNUMBER RCC_HSION_BIT_NUMBERÓHSEON_BitNumber RCC_HSEON_BIT_NUMBERÔHSEON_BITNUMBER RCC_HSEON_BIT_NUMBERÕMSION_BITNUMBER RCC_MSION_BIT_NUMBERÖCSSON_BitNumber RCC_CSSON_BIT_NUMBER×CSSON_BITNUMBER RCC_CSSON_BIT_NUMBERØPLLON_BitNumber RCC_PLLON_BIT_NUMBERÙPLLON_BITNUMBER RCC_PLLON_BIT_NUMBERÚPLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBERÛI2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBERÜRTCEN_BitNumber RCC_RTCEN_BIT_NUMBERÝRTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBERÞBDRST_BitNumber RCC_BDRST_BIT_NUMBERßBDRST_BITNUMBER RCC_BDRST_BIT_NUMBERàRTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBERáLSION_BitNumber RCC_LSION_BIT_NUMBERâLSION_BITNUMBER RCC_LSION_BIT_NUMBERãLSEON_BitNumber RCC_LSEON_BIT_NUMBERäLSEON_BITNUMBER RCC_LSEON_BIT_NUMBERåLSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBERæPLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBERçTIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBERèRMVF_BitNumber RCC_RMVF_BIT_NUMBERéRMVF_BITNUMBER RCC_RMVF_BIT_NUMBERêRCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBERëCR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESSìCIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESSíCIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESSîBDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESSïDBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUEðLSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUEòCR_HSION_BB RCC_CR_HSION_BBóCR_CSSON_BB RCC_CR_CSSON_BBôCR_PLLON_BB RCC_CR_PLLON_BBõCR_PLLI2SON_BB RCC_CR_PLLI2SON_BBöCR_MSION_BB RCC_CR_MSION_BB÷CSR_LSION_BB RCC_CSR_LSION_BBøCSR_LSEON_BB RCC_CSR_LSEON_BBùCSR_LSEBYP_BB RCC_CSR_LSEBYP_BBúCSR_RTCEN_BB RCC_CSR_RTCEN_BBûCSR_RTCRST_BB RCC_CSR_RTCRST_BBüCFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BBýBDCR_RTCEN_BB RCC_BDCR_RTCEN_BBþBDCR_BDRST_BB RCC_BDCR_BDRST_BBÿCR_HSEON_BB RCC_CR_HSEON_BBCSR_RMVF_BB RCC_CSR_RMVF_BBCR_PLLSAION_BB RCC_CR_PLLSAION_BBDCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB__HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE__HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE__HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE__HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE__HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE__HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_ITRCC_CRS_SYNCWARM RCC_CRS_SYNCWARNRCC_CRS_TRIMOV RCC_CRS_TRIMOVFRCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQRCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIPRCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQIS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCERCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48__HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE__HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE__HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED__HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED__HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET__HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET__HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE__HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE__HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED__HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED DfsdmClockSelection Dfsdm1ClockSelection¡RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1¢RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2£RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK¤__HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG¥__HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE¦RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2§RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1¨RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1©RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1«RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1¬RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1®RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2¯RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2°RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2±RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1°HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)½__HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG¿__HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_ITÀ__HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_ITÍ__HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))Ð__HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))Ó__HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))Ö__HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))Ù__HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))ÞIS_ALARM IS_RTC_ALARMßIS_ALARM_MASK IS_RTC_ALARM_MASKàIS_TAMPER IS_RTC_TAMPERáIS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODEâIS_TAMPER_FILTER IS_RTC_TAMPER_FILTERãIS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPTäIS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATEåIS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATIONæIS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATEçIS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQèIS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTIONéIS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGERêIS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCKëIS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTERí__RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLEî__RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLEýSD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITEþSD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUSeMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGEeMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGEeMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGESDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIVSDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV×__SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_ITØ__SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_ITÙ__SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLEÚ__SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLEÛ__SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLEÜ__SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLEÞ__HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCEß__SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCEáIS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLEê__HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1ë__HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2ì__HAL_SMBUS_GENERATE_START SMBUS_GENERATE_STARTí__HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCHî__HAL_SMBUS_GET_DIR SMBUS_GET_DIRï__HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODEð__HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODEñ__HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLEDú__HAL_SPI_1LINE_TX SPI_1LINE_TXû__HAL_SPI_1LINE_RX SPI_1LINE_RXü__HAL_SPI_RESET_CRC SPI_RESET_CRC __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE __UART_MASK_COMPUTATION UART_MASK_COMPUTATION IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE __USART_ENABLE_IT __HAL_USART_ENABLE_IT __USART_DISABLE_IT __HAL_USART_DISABLE_IT __USART_ENABLE __HAL_USART_ENABLE __USART_DISABLE __HAL_USART_DISABLE __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE¯ USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE± USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE² USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE³ USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE´ USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE¶ USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE· USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE¸ USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE¹ USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE» __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT¼ __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT½ __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG¾ __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG¿ __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGEÀ __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGEÁ __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGEÃ __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_ITÄ __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_ITÅ __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAGÆ __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAGÇ __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGEÈ __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGEÉ __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGEÊ __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWITÌ __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_ITÍ __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_ITÎ __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAGÏ __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAGÐ __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGEÑ __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGEÒ __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGEÓ __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWITÕ HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeupÖ HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeupØ HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFoÙ HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFoá __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUEâ __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUEä TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCEå TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_ITç __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCEé __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWNê __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALERë __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTERì __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTERí __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOADî __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOADï __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISIONð __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISIONñ __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALERò __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALERó __HAL_TIM_SetCompare __HAL_TIM_SET_COMPAREô __HAL_TIM_GetCompare __HAL_TIM_GET_COMPAREö TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1ÿ __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT!__HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT!__HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG!__HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG!__HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER!__HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER!__HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER!ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE!ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE!IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE!__HAL_LTDC_LAYER LTDC_LAYER!__HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG!SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE!SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE!SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE!SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE!SAI_STREOMODE SAI_STEREOMODE!SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY !SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL¡!SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL¢!SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL£!SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL¤!SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL¥!IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE¦!SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1§!SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE`U ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hÄ
../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM__stddef_h __ARMCLIB_VERSION 5060037__STDDEF_DECLS __CLIBNS __CLIBNS SNULLTNULL 0[offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb)))PD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hC:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]intunsigned intunsigned shortlong doublePptrdiff_t&Psize_t.Pwchar_t¡@Pmax_align_t³___STM32L0xx_HAL_DEF :UNUSED(X) (void)X=HAL_MAX_DELAY 0xFFFFFFFFU?HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) == (BIT))@HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == 0U)B__HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0)W__HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)___HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0)k__HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0)__ALIGN_END __ALIGN_BEGIN __align(4)®__RAM_FUNC °__NOINLINE __attribute__ ( (noinline) )äÚ ../Drivers/STM32L0xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32L0xx/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\stm32l0xx_hal_def.hstm32l0xx.hLegacy/stm32_hal_legacy.hstddef.hH
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMõHAL_OKHAL_ERRORHAL_BUSYHAL_TIMEOUTPHAL_StatusTypeDef¾,±HAL_UNLOCKEDHAL_LOCKEDPHAL_LockTypeDef5__STM32L0xx_HAL_RCC_EX_H VIS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))\IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))bIS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))gIS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))lIS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))qIS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK1) || ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19)RCC_PERIPHCLK_USART1 (0x00000001U) RCC_PERIPHCLK_USART2 (0x00000002U)¡RCC_PERIPHCLK_LPUART1 (0x00000004U)¢RCC_PERIPHCLK_I2C1 (0x00000008U)£RCC_PERIPHCLK_I2C2 (0x00000010U)¤RCC_PERIPHCLK_RTC (0x00000020U)¨RCC_PERIPHCLK_LPTIM1 (0x00000080U)RCC_PERIPHCLK_I2C3 (0x00000100U)¸RCC_USART1CLKSOURCE_PCLK2 (0x00000000U)¹RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0ºRCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1»RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)ÄRCC_USART2CLKSOURCE_PCLK1 (0x00000000U)ÅRCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0ÆRCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1ÇRCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)ÏRCC_LPUART1CLKSOURCE_PCLK1 (0x00000000U)ÐRCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0ÑRCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1ÒRCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)ÚRCC_I2C1CLKSOURCE_PCLK1 (0x00000000U)ÛRCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0ÜRCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1æRCC_I2C3CLKSOURCE_PCLK1 (0x00000000U)çRCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0èRCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1ñRCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)òRCC_TIMPRES_ACTIVATED ((uint8_t)0x01)RCC_LPTIM1CLKSOURCE_PCLK1 (0x00000000U)RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1¡RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SELªRCC_STOP_WAKEUPCLOCK_MSI (0x00000000U)«RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK´RCC_LSEDRIVE_LOW (0x00000000U)µRCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0¶RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1·RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRVù__HAL_RCC_GPIOE_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); UNUSED(tmpreg); } while(0)__HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))__HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != 0U)__HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == 0U)__HAL_RCC_GPIOD_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); UNUSED(tmpreg); } while(0)__HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))__HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U)__HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U)__HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))__HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))__HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))__HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))__HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))__HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))__HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))__HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))__HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))__HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))__HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))__HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))__HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))__HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))__HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))__HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))__HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))__HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))__HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))__HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))__HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))__HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))__HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))¡__HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))¢__HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))£__HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))¤__HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))¦__HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U)§__HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != 0U)¨__HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U)©__HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != 0U)ª__HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U)«__HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)¬__HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != 0U)__HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != 0U)®__HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U)¯__HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U)°__HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U)±__HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != 0U)²__HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U)³__HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U)´__HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U)µ__HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == 0U)¶__HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U)·__HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == 0U)¸__HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U)¹__HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)º__HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == 0U)»__HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == 0U)¼__HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U)½__HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U)¾__HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U)¿__HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == 0U)À__HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U)Á__HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U)×__HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))Ù__HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))Û__HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))Ü__HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))Ý__HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))ß__HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))á__HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))ã__HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))ä__HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))å__HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))ç__HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))è__HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))ë__HAL_RCC_TIM21_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != 0U)í__HAL_RCC_TIM22_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != 0U)ï__HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != 0U)ð__HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)ñ__HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)ó__HAL_RCC_TIM21_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN) == 0U)õ__HAL_RCC_TIM22_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN) == 0U)÷__HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == 0U)ø__HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN) == 0U)ù__HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN) == 0U)û__HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != 0U)ü__HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN) == 0U)¤__HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))¦__HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))__HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))®__HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))å__HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))æ__HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))ç__HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))è__HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))é__HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))ê__HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))ë__HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))ì__HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))í__HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))î__HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))ï__HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))ð__HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))ñ__HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))ò__HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))ô__HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))õ__HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))ö__HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))÷__HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))ø__HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))ù__HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))ú__HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))û__HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))ü__HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))ý__HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))þ__HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))ÿ__HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))__HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))__HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))¢__HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))£__HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))¤__HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))¥__HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))¦__HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))¨__HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))©__HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))ª__HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))«__HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))¬__HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))ø__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))ù__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))û__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != 0U)ü__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == 0U)    __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))    __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))    __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != 0U)    __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == 0U)Æ    __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))Ç    __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))È    __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))É    __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))Ê    __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))Ë    __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))Ì    __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))Í    __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))Î    __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))Ï    __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))Ð    __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))Ñ    __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))Ò    __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))Ó    __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))Õ    __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))Ö    __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))×    __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))Ø    __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))Ù    __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))Ú    __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))Û    __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))Ü    __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))Ý    __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))Þ    __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))ß    __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))à    __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))á    __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))â    __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))ä    __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U)å    __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != 0U)æ    __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U)ç    __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != 0U)è    __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U)é    __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U)ê    __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != 0U)ë    __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != 0U)ì    __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U)í    __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U)î    __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U)ï    __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != 0U)ð    __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U)ñ    __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U)ò    __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U)ó    __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == 0U)ô    __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U)õ    __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == 0U)ö    __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U)÷    __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U)ø    __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == 0U)ù    __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == 0U)ú    __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U)û    __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U)ü    __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U)ý    __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == 0U)þ    __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U)ÿ    __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U)Ê
__HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))Ì
__HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))Î
__HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))Ï
__HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))Ð
__HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))Ò
__HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))Ô
__HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))Ö
__HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))×
__HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))Ø
__HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))Ú
__HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != 0U)Ü
__HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != 0U)Þ
__HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != 0U)ß
__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)à
__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)â
__HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN) == 0U)ä
__HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN) == 0U)æ
__HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN) == 0U)ç
__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN) == 0U)è
__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN) == 0U)ù
__HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)ÿ
__HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)¦__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)¬__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); } while(0)¶__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); } while(0)À__HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))Æ__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))Ì__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)ü__HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))__HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))__HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))__HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))§__HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))±__HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))½__HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))Ç__HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))Ò__HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))Ü__HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))ç__HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))ñ__HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))´ __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)» __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)Ç __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))Ò __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))å__HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)ë__HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)ti ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.hstm32l0xx_hal_def.hÐ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*¯ PeriphClockSelectionY#RTCClockSelectionY#Usart1ClockSelectionY#Usart2ClockSelectionY#Lpuart1ClockSelectionY#I2c1ClockSelectionY#I2c3ClockSelectionY#LptimClockSelectionY#PRCC_PeriphCLKInitTypeDefÁÒ__STM32L0xx_HAL_RCC_H .RCC_DBP_TIMEOUT_VALUE (100U)0RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT1CLOCKSWITCH_TIMEOUT_VALUE (5000U)2HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT3MSI_TIMEOUT_VALUE (2U)4HSI_TIMEOUT_VALUE (2U)5LSI_TIMEOUT_VALUE (2U)6PLL_TIMEOUT_VALUE (2U)CRCC_OFFSET (RCC_BASE - PERIPH_BASE)FRCC_CR_OFFSET (RCC_OFFSET + 0x00U)IRCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)KRCC_CSR_OFFSET (RCC_OFFSET + 0x74U)NRCC_CR_BYTE2_ADDRESS (0x40023802U)QCIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))XCR_REG_INDEX ((uint8_t)1)YCSR_REG_INDEX ((uint8_t)2)ZCRRCR_REG_INDEX ((uint8_t)3)\RCC_FLAG_MASK ((uint8_t)0x1F)pIS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))wIS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))yIS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS)){IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))~IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_ON)) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_DIV4)))IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || ((__RANGE__) == RCC_MSIRANGE_1) || ((__RANGE__) == RCC_MSIRANGE_2) || ((__RANGE__) == RCC_MSIRANGE_3) || ((__RANGE__) == RCC_MSIRANGE_4) || ((__RANGE__) == RCC_MSIRANGE_5) || ((__RANGE__) == RCC_MSIRANGE_6))IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || ((__MUL__) == RCC_PLL_MUL48))IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))£IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))§IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))¬IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))°IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2) || ((__MCO__) == RCC_MCO3))µIS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || ((__DIV__) == RCC_MCODIV_16))¿IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))ÄIS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))³RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI´RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE½RCC_OSCILLATORTYPE_NONE (0x00000000U)¾RCC_OSCILLATORTYPE_HSE (0x00000001U)¿RCC_OSCILLATORTYPE_HSI (0x00000002U)ÀRCC_OSCILLATORTYPE_LSE (0x00000004U)ÁRCC_OSCILLATORTYPE_LSI (0x00000008U)ÂRCC_OSCILLATORTYPE_MSI (0x00000010U)ÍRCC_HSE_OFF (0x00000000U)ÎRCC_HSE_ON RCC_CR_HSEONÏRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))×RCC_LSE_OFF (0x00000000U)ØRCC_LSE_ON RCC_CSR_LSEONÙRCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))âRCC_HSI_OFF (0x00000000U)ãRCC_HSI_ON RCC_CR_HSIONäRCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)æRCC_HSI_OUTEN RCC_CR_HSIOUTENêRCC_HSICALIBRATION_DEFAULT (0x10U)ôRCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0õRCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1öRCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2÷RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3øRCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4ùRCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5úRCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6RCC_LSI_OFF (0x00000000U)RCC_LSI_ON RCC_CSR_LSIONRCC_MSI_OFF (0x00000000U)RCC_MSI_ON (0x00000001U)RCC_MSICALIBRATION_DEFAULT (0x00000000U)¥RCC_PLL_NONE (0x00000000U)¦RCC_PLL_OFF (0x00000001U)§RCC_PLL_ON (0x00000002U)°RCC_CLOCKTYPE_SYSCLK (0x00000001U)±RCC_CLOCKTYPE_HCLK (0x00000002U)²RCC_CLOCKTYPE_PCLK1 (0x00000004U)³RCC_CLOCKTYPE_PCLK2 (0x00000008U)¼RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI½RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI¾RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE¿RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLLÈRCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSIÉRCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSIÊRCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSEËRCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLLÔRCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1ÕRCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2ÖRCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4×RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8ØRCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16ÙRCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64ÚRCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128ÛRCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256ÜRCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512åRCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1æRCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2çRCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4èRCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8éRCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16òRCC_RTC_HSE_DIV_2 (0x00000000U)óRCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0ôRCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1õRCC_RTC_HSE_DIV_16 RCC_CR_RTCPREýRCC_RTCCLKSOURCE_NO_CLK (0x00000000U)þRCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSEÿRCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSIRCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSERCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE)RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE)RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE)RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)RCC_PLL_DIV2 RCC_CFGR_PLLDIV2RCC_PLL_DIV3 RCC_CFGR_PLLDIV3RCC_PLL_DIV4 RCC_CFGR_PLLDIV4RCC_PLL_MUL3 RCC_CFGR_PLLMUL3RCC_PLL_MUL4 RCC_CFGR_PLLMUL4RCC_PLL_MUL6 RCC_CFGR_PLLMUL6RCC_PLL_MUL8 RCC_CFGR_PLLMUL8RCC_PLL_MUL12 RCC_CFGR_PLLMUL12RCC_PLL_MUL16 RCC_CFGR_PLLMUL16RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 RCC_PLL_MUL32 RCC_CFGR_PLLMUL32¡RCC_PLL_MUL48 RCC_CFGR_PLLMUL48ªRCC_MCO1 (0x00000000U)«RCC_MCO2 (0x00000001U)RCC_MCO3 (0x00000002U)±MCO3_GPIO_AF GPIO_AF2_MCO¼RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1½RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2¾RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4¿RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8ÀRCC_MCODIV_16 RCC_CFGR_MCO_PRE_16ÉRCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCKÊRCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLKËRCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSIÌRCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSIÍRCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSEÎRCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSIÏRCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSEÐRCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLLÛRCC_IT_LSIRDY RCC_CIFR_LSIRDYFÜRCC_IT_LSERDY RCC_CIFR_LSERDYFÝRCC_IT_HSIRDY RCC_CIFR_HSIRDYFÞRCC_IT_HSERDY RCC_CIFR_HSERDYFßRCC_IT_PLLRDY RCC_CIFR_PLLRDYFàRCC_IT_MSIRDY RCC_CIFR_MSIRDYFáRCC_IT_LSECSS RCC_CIFR_CSSLSEFãRCC_IT_CSS RCC_CIFR_CSSHSEF÷RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_Pos))øRCC_FLAG_HSIDIV ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIDIVF_Pos))ùRCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_MSIRDY_Pos))úRCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_Pos))ûRCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_Pos))ýRCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_Pos))þRCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSERDY_Pos))ÿRCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSECSSD_Pos))RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_Pos))RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_Pos))RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_Pos))RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_Pos))RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_Pos))RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_Pos))RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_Pos))RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_FWRSTF_Pos))¤__HAL_RCC_DMA1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); UNUSED(tmpreg); } while(0)¬__HAL_RCC_MIF_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN); UNUSED(tmpreg); } while(0)´__HAL_RCC_CRC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); UNUSED(tmpreg); } while(0)½__HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)¾__HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)¿__HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)Ì__HAL_RCC_GPIOA_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); UNUSED(tmpreg); } while(0)Ô__HAL_RCC_GPIOB_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); UNUSED(tmpreg); } while(0)Ü__HAL_RCC_GPIOC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); UNUSED(tmpreg); } while(0)ä__HAL_RCC_GPIOH_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN); UNUSED(tmpreg); } while(0)í__HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)î__HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)ï__HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)ð__HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)ý__HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))þ__HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))__HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))__HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))__HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))__HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))__HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))__HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))__HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)__HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != 0U) __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)¡__HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)¢__HAL_RCC_MIF_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == 0U)£__HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)±__HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U)²__HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U)³__HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U)´__HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != 0U)µ__HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U)¶__HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U)·__HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U)¸__HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == 0U)Å__HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != 0U)Æ__HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U)Ç__HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == 0U)È__HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U)Õ__HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)Ö__HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != 0U)×__HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)Ø__HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == 0U)â__HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)ã__HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))ä__HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))å__HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))ç__HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)è__HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))é__HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))ê__HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))ó__HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU)ô__HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))õ__HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))ö__HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))÷__HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))ù__HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00000000U)ú__HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))û__HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))ü__HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))ý__HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))__HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)__HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))__HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))__HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)__HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))__HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))__HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)__HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))__HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))__HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)__HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))__HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))«__HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))¬__HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))__HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))®__HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))°__HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))±__HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))²__HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))³__HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))Á__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))Â__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))Ã__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))Ä__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))Æ__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))Ç__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))È__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))É__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))Ö__HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))×__HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))Ù__HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))Ú__HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))è__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))é__HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))ë__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))ì__HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))ú__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != 0U)û__HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != 0U)ü__HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != 0U)ý__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != 0U)þ__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == 0U)ÿ__HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == 0U)__HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == 0U)__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == 0U)__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != 0U)__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != 0U)__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != 0U)__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != 0U)__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == 0U)__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == 0U)__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == 0U)__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == 0U)¤__HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != 0U)¥__HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != 0U)¦__HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == 0U)§__HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == 0U)µ__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)¶__HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != 0U)·__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)¸__HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == 0U)Ñ__HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))â__HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)ã__HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)ì__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))ü__HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)    __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)£    __HAL_RCC_HSE_CONFIG(__STATE__) do{ __IO uint32_t tmpreg; if ((__STATE__) == RCC_HSE_ON) { SET_BIT(RCC->CR, RCC_CR_HSEON); } else if ((__STATE__) == RCC_HSE_BYPASS) { SET_BIT(RCC->CR, RCC_CR_HSEBYP); SET_BIT(RCC->CR, RCC_CR_HSEON); } else { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); UNUSED(tmpreg); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } }while(0)Ò    __HAL_RCC_LSE_CONFIG(__STATE__) do{ if ((__STATE__) == RCC_LSE_ON) { SET_BIT(RCC->CSR, RCC_CSR_LSEON); } else if ((__STATE__) == RCC_LSE_OFF) { CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); } else if ((__STATE__) == RCC_LSE_BYPASS) { SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); SET_BIT(RCC->CSR, RCC_CSR_LSEON); } else { CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); } }while(0)ö    __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
__HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos)) 
__HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))®
__HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))¾
__HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)Ã
__HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)á
__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__,__PLLMUL__,__PLLDIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))ê
__HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))ý
__HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))__HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))¶__HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__,__MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))Û__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) { MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); } } while (0)â__HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); } while (0)î__HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))ú__HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))ÿ__HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)__HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)__HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)__HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)¬__HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))À__HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))Ï__HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))Þ__HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))å__HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )  ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.hstm32l0xx_hal_def.hstm32l0xx_hal_rcc_ex.h 
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*PLLStateY#PLLSourceY#PLLMULY#PLLDIVY#PRCC_PLLInitTypeDef¾æ*ö4OscillatorTypeY#HSEStateY#LSEStateY#HSIStateY#HSICalibrationValueY#LSIStateY#MSIStateY#MSICalibrationValueY#MSIClockRangeY# PLL#$PRCC_OscInitTypeDef#*ClockTypeY#SYSCLKSourceY#AHBCLKDividerY#APB1CLKDividerY#APB2CLKDividerY#PRCC_ClkInitTypeDef¤ __STM32L0xx_HAL_EXTI_H ZEXTI_LINE_0 (EXTI_GPIO | 0x00u)[EXTI_LINE_1 (EXTI_GPIO | 0x01u)\EXTI_LINE_2 (EXTI_GPIO | 0x02u)]EXTI_LINE_3 (EXTI_GPIO | 0x03u)^EXTI_LINE_4 (EXTI_GPIO | 0x04u)_EXTI_LINE_5 (EXTI_GPIO | 0x05u)`EXTI_LINE_6 (EXTI_GPIO | 0x06u)aEXTI_LINE_7 (EXTI_GPIO | 0x07u)bEXTI_LINE_8 (EXTI_GPIO | 0x08u)cEXTI_LINE_9 (EXTI_GPIO | 0x09u)dEXTI_LINE_10 (EXTI_GPIO | 0x0Au)eEXTI_LINE_11 (EXTI_GPIO | 0x0Bu)fEXTI_LINE_12 (EXTI_GPIO | 0x0Cu)gEXTI_LINE_13 (EXTI_GPIO | 0x0Du)hEXTI_LINE_14 (EXTI_GPIO | 0x0Eu)iEXTI_LINE_15 (EXTI_GPIO | 0x0Fu)kEXTI_LINE_16 (EXTI_CONFIG | 0x10u)oEXTI_LINE_17 (EXTI_CONFIG | 0x11u)qEXTI_LINE_18 (EXTI_DIRECT | 0x12u)uEXTI_LINE_19 (EXTI_CONFIG | 0x13u)vEXTI_LINE_20 (EXTI_CONFIG | 0x14u)xEXTI_LINE_21 (EXTI_CONFIG | 0x15u)}EXTI_LINE_22 (EXTI_CONFIG | 0x16u)EXTI_LINE_23 (EXTI_DIRECT | 0x17u)EXTI_LINE_24 (EXTI_DIRECT | 0x18u)EXTI_LINE_25 (EXTI_DIRECT | 0x19u)EXTI_LINE_26 (EXTI_DIRECT | 0x1Au)EXTI_LINE_27 (EXTI_RESERVED | 0x1Bu)EXTI_LINE_28 (EXTI_DIRECT | 0x1Cu)EXTI_LINE_29 (EXTI_DIRECT | 0x1Du)EXTI_MODE_NONE 0x00000000uEXTI_MODE_INTERRUPT 0x00000001uEXTI_MODE_EVENT 0x00000002u¢EXTI_TRIGGER_NONE 0x00000000u£EXTI_TRIGGER_RISING 0x00000001u¤EXTI_TRIGGER_FALLING 0x00000002u¥EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)®EXTI_GPIOA 0x00000000u¯EXTI_GPIOB 0x00000001u°EXTI_GPIOC 0x00000002u²EXTI_GPIOD 0x00000003uµEXTI_GPIOE 0x00000004u¸EXTI_GPIOH 0x00000007uÒEXTI_PROPERTY_SHIFT 24uÓEXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)ÔEXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)ÕEXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)ÖEXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)×EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)ÜEXTI_PIN_MASK 0x0000001FuáEXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)æEXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)ëEXTI_LINE_NB 30uõIS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))úIS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))ýIS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)ÿIS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOH))IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) ../Drivers/STM32L0xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx_hal_exti.hstm32l0xx.hØ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMHAL_EXTI_COMMON_CB_IDHAL_EXTI_RISING_CB_IDHAL_EXTI_FALLING_CB_IDPEXTI_CallbackIDTypeDef¿0*àLineY#OÄ"@PendingCallbackD#PEXTI_HandleTypeDef.:*½LineY#ModeY#TriggerY#GPIOSelY#PEXTI_ConfigTypeDefzJ¢£¤__STM32L0xx_HAL_GPIO_EX_H GPIO_AF0_EVENTOUT ((uint8_t)0x00U)GPIO_AF0_TIM21 ((uint8_t)0x00U)GPIO_AF0_SPI1 ((uint8_t)0x00U)GPIO_AF0_MCO ((uint8_t)0x00U)GPIO_AF0_SWDIO ((uint8_t)0x00U)GPIO_AF0_SWCLK ((uint8_t)0x00U)GPIO_AF0_USART1 ((uint8_t)0x00U)GPIO_AF0_SPI2 ((uint8_t)0x00U)GPIO_AF0_LPTIM1 ((uint8_t)0x00U)GPIO_AF0_TIM22 ((uint8_t)0x00U)GPIO_AF0_LPUART1 ((uint8_t)0x00U)GPIO_AF0_USART2 ((uint8_t)0x00U)GPIO_AF0_TIM2 ((uint8_t)0x00U)GPIO_AF1_I2C1 ((uint8_t)0x01U) GPIO_AF1_SPI2 ((uint8_t)0x01U)¡GPIO_AF1_TIM21 ((uint8_t)0x01U)ªGPIO_AF2_TIM2 ((uint8_t)0x02U)«GPIO_AF2_TIM3 ((uint8_t)0x02U)¬GPIO_AF2_EVENTOUT ((uint8_t)0x02U)GPIO_AF2_LPTIM1 ((uint8_t)0x02U)®GPIO_AF2_LPUART1 ((uint8_t)0x02U)¯GPIO_AF2_MCO ((uint8_t)0x02U)°GPIO_AF2_RTC ((uint8_t)0x02U)±GPIO_AF2_SPI2 ((uint8_t)0x02U)²GPIO_AF2_USART5 ((uint8_t)0x02U)³GPIO_AF2_SPI1 ((uint8_t)0x02U)¼GPIO_AF3_EVENTOUT ((uint8_t)0x03U)½GPIO_AF3_I2C1 ((uint8_t)0x03U)ÆGPIO_AF4_USART2 ((uint8_t)0x04U)ÇGPIO_AF4_LPUART1 ((uint8_t)0x04U)ÈGPIO_AF4_USART1 ((uint8_t)0x04U)ÉGPIO_AF4_EVENTOUT ((uint8_t)0x04U)ÊGPIO_AF4_TIM22 ((uint8_t)0x04U)ËGPIO_AF4_TIM3 ((uint8_t)0x04U)ÌGPIO_AF4_I2C1 ((uint8_t)0x04U)ÕGPIO_AF5_TIM2 ((uint8_t)0x05U)ÖGPIO_AF5_TIM21 ((uint8_t)0x05U)×GPIO_AF5_TIM22 ((uint8_t)0x05U)ØGPIO_AF5_USART1 ((uint8_t)0x05U)ÙGPIO_AF5_SPI2 ((uint8_t)0x05U)ÚGPIO_AF5_I2C2 ((uint8_t)0x05U)ãGPIO_AF6_USART4 ((uint8_t)0x06U)äGPIO_AF6_LPUART1 ((uint8_t)0x06U)åGPIO_AF6_EVENTOUT ((uint8_t)0x06U)æGPIO_AF6_I2C1 ((uint8_t)0x06U)çGPIO_AF6_I2C2 ((uint8_t)0x06U)èGPIO_AF6_USART5 ((uint8_t)0x06U)éGPIO_AF6_TIM21 ((uint8_t)0x06U)òGPIO_AF7_COMP1 ((uint8_t)0x07U)óGPIO_AF7_COMP2 ((uint8_t)0x07U)ôGPIO_AF7_I2C3 ((uint8_t)0x07U)õGPIO_AF7_LPUART1 ((uint8_t)0x07U)IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)¢GPIOA_PIN_AVAILABLE GPIO_PIN_All£GPIOB_PIN_AVAILABLE GPIO_PIN_All¤GPIOC_PIN_AVAILABLE GPIO_PIN_All¥GPIOD_PIN_AVAILABLE GPIO_PIN_All¦GPIOE_PIN_AVAILABLE GPIO_PIN_All§GPIOH_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_9 | GPIO_PIN_10)²GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U : ((__GPIOx__) == (GPIOB))? 1U : ((__GPIOx__) == (GPIOC))? 2U : ((__GPIOx__) == (GPIOD))? 3U : ((__GPIOx__) == (GPIOE))? 4U : ((__GPIOx__) == (GPIOH))? 5U : 6U)¹IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))tj ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.hstm32l0xx_hal_def.hÀ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM¦§¨__STM32L0xx_HAL_GPIO_H XIS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET))hGPIO_PIN_0 (0x0001U)iGPIO_PIN_1 (0x0002U)jGPIO_PIN_2 (0x0004U)kGPIO_PIN_3 (0x0008U)lGPIO_PIN_4 (0x0010U)mGPIO_PIN_5 (0x0020U)nGPIO_PIN_6 (0x0040U)oGPIO_PIN_7 (0x0080U)pGPIO_PIN_8 (0x0100U)qGPIO_PIN_9 (0x0200U)rGPIO_PIN_10 (0x0400U)sGPIO_PIN_11 (0x0800U)tGPIO_PIN_12 (0x1000U)uGPIO_PIN_13 (0x2000U)vGPIO_PIN_14 (0x4000U)wGPIO_PIN_15 (0x8000U)xGPIO_PIN_All (0xFFFFU)}GPIO_PIN_MASK (0x0000FFFFU)~IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) && (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))GPIO_MODE_INPUT MODE_INPUTGPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)GPIO_MODE_ANALOG MODE_ANALOGGPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) || ((__MODE__) == GPIO_MODE_OUTPUT_PP) || ((__MODE__) == GPIO_MODE_OUTPUT_OD) || ((__MODE__) == GPIO_MODE_AF_PP) || ((__MODE__) == GPIO_MODE_AF_OD) || ((__MODE__) == GPIO_MODE_IT_RISING) || ((__MODE__) == GPIO_MODE_IT_FALLING) || ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) || ((__MODE__) == GPIO_MODE_EVT_RISING) || ((__MODE__) == GPIO_MODE_EVT_FALLING) || ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) || ((__MODE__) == GPIO_MODE_ANALOG))°GPIO_SPEED_FREQ_LOW (0x00000000U)±GPIO_SPEED_FREQ_MEDIUM (0x00000001U)²GPIO_SPEED_FREQ_HIGH (0x00000002U)³GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)¹IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW ) || ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM ) || ((__SPEED__) == GPIO_SPEED_FREQ_HIGH ) || ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))ÁGPIO_NOPULL (0x00000000U)ÂGPIO_PULLUP (0x00000001U)ÃGPIO_PULLDOWN (0x00000002U)ÉIS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || ((__PULL__) == GPIO_PULLDOWN))Ý__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))å__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))í__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))õ__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))ý__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))¯GPIO_MODE_Pos 0U°GPIO_MODE (0x3UL << GPIO_MODE_Pos)±MODE_INPUT (0x0UL << GPIO_MODE_Pos)²MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)³MODE_AF (0x2UL << GPIO_MODE_Pos)´MODE_ANALOG (0x3UL << GPIO_MODE_Pos)µOUTPUT_TYPE_Pos 4U¶OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)·OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)¸OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)¹EXTI_MODE_Pos 16UºEXTI_MODE (0x3UL << EXTI_MODE_Pos)»EXTI_IT (0x1UL << EXTI_MODE_Pos)¼EXTI_EVT (0x2UL << EXTI_MODE_Pos)½TRIGGER_MODE_Pos 20U¾TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)¿TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)ÀTRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.hstm32l0xx_hal_def.hstm32l0xx_hal_gpio_ex.hd
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*PinY#ModeY#PullY#SpeedY#AlternateY#PGPIO_InitTypeDef¿CÎGPIO_PIN_RESETGPIO_PIN_SETPGPIO_PinState'Rª«¬STM32L0xx_HAL_DMA_H HAL_DMA_ERROR_NONE 0x00000000UHAL_DMA_ERROR_TE 0x00000001UHAL_DMA_ERROR_NO_XFER 0x00000004UHAL_DMA_ERROR_TIMEOUT 0x00000020UHAL_DMA_ERROR_NOT_SUPPORTED 0x00000100UáDMA_REQUEST_0 0UâDMA_REQUEST_1 1UãDMA_REQUEST_2 2UäDMA_REQUEST_3 3UåDMA_REQUEST_4 4UæDMA_REQUEST_5 5UçDMA_REQUEST_6 6UèDMA_REQUEST_7 7UéDMA_REQUEST_8 8UêDMA_REQUEST_9 9UëDMA_REQUEST_10 10UìDMA_REQUEST_12 12UíDMA_REQUEST_13 13UîDMA_REQUEST_14 14UïDMA_REQUEST_15 15UñIS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || ((REQUEST) == DMA_REQUEST_1) || ((REQUEST) == DMA_REQUEST_2) || ((REQUEST) == DMA_REQUEST_3) || ((REQUEST) == DMA_REQUEST_4) || ((REQUEST) == DMA_REQUEST_5) || ((REQUEST) == DMA_REQUEST_6) || ((REQUEST) == DMA_REQUEST_7) || ((REQUEST) == DMA_REQUEST_8) || ((REQUEST) == DMA_REQUEST_9) || ((REQUEST) == DMA_REQUEST_10) || ((REQUEST) == DMA_REQUEST_12) || ((REQUEST) == DMA_REQUEST_13) || ((REQUEST) == DMA_REQUEST_14) || ((REQUEST) == DMA_REQUEST_15))DMA_PERIPH_TO_MEMORY 0x00000000UDMA_MEMORY_TO_PERIPH DMA_CCR_DIRDMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEMDMA_PINC_ENABLE DMA_CCR_PINCDMA_PINC_DISABLE 0x00000000UDMA_MINC_ENABLE DMA_CCR_MINC DMA_MINC_DISABLE 0x00000000U¨DMA_PDATAALIGN_BYTE 0x00000000U©DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0ªDMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1²DMA_MDATAALIGN_BYTE 0x00000000U³DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0´DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1¼DMA_NORMAL 0x00000000U½DMA_CIRCULAR DMA_CCR_CIRCÅDMA_PRIORITY_LOW 0x00000000UÆDMA_PRIORITY_MEDIUM DMA_CCR_PL_0ÇDMA_PRIORITY_HIGH DMA_CCR_PL_1ÈDMA_PRIORITY_VERY_HIGH DMA_CCR_PLÑDMA_IT_TC DMA_CCR_TCIEÒDMA_IT_HT DMA_CCR_HTIEÓDMA_IT_TE DMA_CCR_TEIEÛDMA_FLAG_GL1 DMA_ISR_GIF1ÜDMA_FLAG_TC1 DMA_ISR_TCIF1ÝDMA_FLAG_HT1 DMA_ISR_HTIF1ÞDMA_FLAG_TE1 DMA_ISR_TEIF1ßDMA_FLAG_GL2 DMA_ISR_GIF2àDMA_FLAG_TC2 DMA_ISR_TCIF2áDMA_FLAG_HT2 DMA_ISR_HTIF2âDMA_FLAG_TE2 DMA_ISR_TEIF2ãDMA_FLAG_GL3 DMA_ISR_GIF3äDMA_FLAG_TC3 DMA_ISR_TCIF3åDMA_FLAG_HT3 DMA_ISR_HTIF3æDMA_FLAG_TE3 DMA_ISR_TEIF3çDMA_FLAG_GL4 DMA_ISR_GIF4èDMA_FLAG_TC4 DMA_ISR_TCIF4éDMA_FLAG_HT4 DMA_ISR_HTIF4êDMA_FLAG_TE4 DMA_ISR_TEIF4ëDMA_FLAG_GL5 DMA_ISR_GIF5ìDMA_FLAG_TC5 DMA_ISR_TCIF5íDMA_FLAG_HT5 DMA_ISR_HTIF5îDMA_FLAG_TE5 DMA_ISR_TEIF5ïDMA_FLAG_GL6 DMA_ISR_GIF6ðDMA_FLAG_TC6 DMA_ISR_TCIF6ñDMA_FLAG_HT6 DMA_ISR_HTIF6òDMA_FLAG_TE6 DMA_ISR_TEIF6óDMA_FLAG_GL7 DMA_ISR_GIF7ôDMA_FLAG_TC7 DMA_ISR_TCIF7õDMA_FLAG_HT7 DMA_ISR_HTIF7öDMA_FLAG_TE7 DMA_ISR_TEIF7__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)__HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)__HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)©__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 : DMA_FLAG_TC7)¿__HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 : DMA_FLAG_HT7)Õ__HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 : DMA_FLAG_TE7)ë__HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 : DMA_ISR_GIF7)__HAL_DMA_GET_FLAG(__HANDLE__,__FLAG__) (DMA1->ISR & (__FLAG__))__HAL_DMA_CLEAR_FLAG(__HANDLE__,__FLAG__) (DMA1->IFCR = (__FLAG__))__HAL_DMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))¦__HAL_DMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))²__HAL_DMA_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))¹__HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)óIS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))÷IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))ùIS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))üIS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))ÿIS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD ))IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || ((MODE) == DMA_CIRCULAR))IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))pf ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.hstm32l0xx_hal_def.hp
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMuvoid"¾"7tY"PDMA_InitTypeDefjJPHAL_DMA_StateTypeDef UPHAL_DMA_LevelCompleteTypeDefo^PHAL_DMA_CallbackIDTypeDef¦kPDMA_HandleTypeDef7* RequestY#DirectionY#PeriphIncY#MemIncY#PeriphDataAlignmentY#MemDataAlignmentY#ModeY#PriorityY#ïHAL_DMA_STATE_RESETHAL_DMA_STATE_READYHAL_DMA_STATE_BUSYHAL_DMA_STATE_TIMEOUT¦HAL_DMA_FULL_TRANSFERHAL_DMA_HALF_TRANSFER·HAL_DMA_XFER_CPLT_CB_IDHAL_DMA_XFER_HALFCPLT_CB_IDHAL_DMA_XFER_ERROR_CB_IDHAL_DMA_XFER_ABORT_CB_IDHAL_DMA_XFER_ALL_CB_ID)è__DMA_HandleTypeDefHInstanceh#InitØ#Lock1#$Staten#%ParentÄ#(O%È"XferCpltCallback#,OÀ%È"¸XferHalfCpltCallbackÀ#0Oè%È"àXferErrorCallbackè#4O%È"XferAbortCallback #8ErrorCodeÌ#<DmaBaseAddressÒ#@ChannelIndexY#D"Ptï®¯°__STM32L0xx_HAL_CORTEX_H ZIS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x10U)\IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0)aSYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)bSYSTICK_CLKSOURCE_HCLK (0x00000004U)cIS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))mMPU_HFNMI_PRIVDEF_NONE (0x00000000U)nMPU_HARDFAULT_NMI (0x00000002U)oMPU_PRIVILEGED_DEFAULT (0x00000004U)pMPU_HFNMI_PRIVDEF (0x00000006U)xMPU_REGION_ENABLE ((uint8_t)0x01)yMPU_REGION_DISABLE ((uint8_t)0x00)MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)MPU_ACCESS_SHAREABLE ((uint8_t)0x01)MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)MPU_ACCESS_CACHEABLE ((uint8_t)0x01)MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)¥MPU_REGION_SIZE_32B ((uint8_t)0x04)¦MPU_REGION_SIZE_64B ((uint8_t)0x05)§MPU_REGION_SIZE_128B ((uint8_t)0x06)¨MPU_REGION_SIZE_256B ((uint8_t)0x07)©MPU_REGION_SIZE_512B ((uint8_t)0x08)ªMPU_REGION_SIZE_1KB ((uint8_t)0x09)«MPU_REGION_SIZE_2KB ((uint8_t)0x0A)¬MPU_REGION_SIZE_4KB ((uint8_t)0x0B)MPU_REGION_SIZE_8KB ((uint8_t)0x0C)®MPU_REGION_SIZE_16KB ((uint8_t)0x0D)¯MPU_REGION_SIZE_32KB ((uint8_t)0x0E)°MPU_REGION_SIZE_64KB ((uint8_t)0x0F)±MPU_REGION_SIZE_128KB ((uint8_t)0x10)²MPU_REGION_SIZE_256KB ((uint8_t)0x11)³MPU_REGION_SIZE_512KB ((uint8_t)0x12)´MPU_REGION_SIZE_1MB ((uint8_t)0x13)µMPU_REGION_SIZE_2MB ((uint8_t)0x14)¶MPU_REGION_SIZE_4MB ((uint8_t)0x15)·MPU_REGION_SIZE_8MB ((uint8_t)0x16)¸MPU_REGION_SIZE_16MB ((uint8_t)0x17)¹MPU_REGION_SIZE_32MB ((uint8_t)0x18)ºMPU_REGION_SIZE_64MB ((uint8_t)0x19)»MPU_REGION_SIZE_128MB ((uint8_t)0x1A)¼MPU_REGION_SIZE_256MB ((uint8_t)0x1B)½MPU_REGION_SIZE_512MB ((uint8_t)0x1C)¾MPU_REGION_SIZE_1GB ((uint8_t)0x1D)¿MPU_REGION_SIZE_2GB ((uint8_t)0x1E)ÀMPU_REGION_SIZE_4GB ((uint8_t)0x1F)ÈMPU_REGION_NO_ACCESS ((uint8_t)0x00)ÉMPU_REGION_PRIV_RW ((uint8_t)0x01)ÊMPU_REGION_PRIV_RW_URO ((uint8_t)0x02)ËMPU_REGION_FULL_ACCESS ((uint8_t)0x03)ÌMPU_REGION_PRIV_RO ((uint8_t)0x05)ÍMPU_REGION_PRIV_RO_URO ((uint8_t)0x06)ÕMPU_REGION_NUMBER0 ((uint8_t)0x00)ÖMPU_REGION_NUMBER1 ((uint8_t)0x01)×MPU_REGION_NUMBER2 ((uint8_t)0x02)ØMPU_REGION_NUMBER3 ((uint8_t)0x03)ÙMPU_REGION_NUMBER4 ((uint8_t)0x04)ÚMPU_REGION_NUMBER5 ((uint8_t)0x05)ÛMPU_REGION_NUMBER6 ((uint8_t)0x06)ÜMPU_REGION_NUMBER7 ((uint8_t)0x07)IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))¡IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))¤IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))§IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))ªIS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) || ((TYPE) == MPU_REGION_PRIV_RO_URO))±IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))ºIS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))ÔIS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)ti ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.hstm32l0xx_hal_def.hÄ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*¨BaseAddressY#Enable:#Number:#Size:#SubRegionDisable:#TypeExtField:#AccessPermission:#    DisableExec:#
IsShareable:#IsCacheable:#IsBufferable:# PMPU_Region_InitTypeDefÁH²³´__STM32L0xx_HAL_ADC_EX_H 0ADC_SINGLE_ENDED 0x00000000U8ADC_EXTERNALTRIGCONV_T6_TRGO (0x00000000U)9ADC_EXTERNALTRIGCONV_T21_CC2 (ADC_CFGR1_EXTSEL_0):ADC_EXTERNALTRIGCONV_T2_TRGO (ADC_CFGR1_EXTSEL_1);ADC_EXTERNALTRIGCONV_T2_CC4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)<ADC_EXTERNALTRIGCONV_T22_TRGO (ADC_CFGR1_EXTSEL_2)=ADC_EXTERNALTRIGCONV_T3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1)>ADC_EXTERNALTRIGCONV_EXT_IT11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)?ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + 1U)IADC_EXTERNALTRIGCONV_T21_TRGO (ADC_EXTERNALTRIGCONV_T22_TRGO)SADC_EXTERNALTRIGCONV_T2_CC3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0)]ADC_FLAG_SENSOR SYSCFG_CFGR3_VREFINT_RDYF^ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYFmIS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) ((SING_DIFF) == ADC_SINGLE_ENDED)wIS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3 ) || ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || ((CONV) == ADC_SOFTWARE_START))ti ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.hstm32l0xx_hal_def.hÀ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM¶·¸__STM32L0xx_HAL_ADC_H åHAL_ADC_STATE_RESET (0x00000000U)æHAL_ADC_STATE_READY (0x00000001U)çHAL_ADC_STATE_BUSY_INTERNAL (0x00000002U)èHAL_ADC_STATE_TIMEOUT (0x00000004U)ëHAL_ADC_STATE_ERROR_INTERNAL (0x00000010U)ìHAL_ADC_STATE_ERROR_CONFIG (0x00000020U)íHAL_ADC_STATE_ERROR_DMA (0x00000040U)ðHAL_ADC_STATE_REG_BUSY (0x00000100U)òHAL_ADC_STATE_REG_EOC (0x00000200U)óHAL_ADC_STATE_REG_OVR (0x00000400U)ôHAL_ADC_STATE_REG_EOSMP (0x00000800U)÷HAL_ADC_STATE_INJ_BUSY (0x00001000U)ùHAL_ADC_STATE_INJ_EOC (0x00002000U)úHAL_ADC_STATE_INJ_JQOVF (0x00004000U)ýHAL_ADC_STATE_AWD1 (0x00010000U)þHAL_ADC_STATE_AWD2 (0x00020000U)ÿHAL_ADC_STATE_AWD3 (0x00040000U)HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U)ÆHAL_ADC_ERROR_NONE (0x00U)ÇHAL_ADC_ERROR_INTERNAL (0x01U)ÉHAL_ADC_ERROR_OVR (0x02U)ÊHAL_ADC_ERROR_DMA (0x04U)ÜADC_ENABLE_TIMEOUT 10UÝADC_DISABLE_TIMEOUT 10UÞADC_STOP_CONVERSION_TIMEOUT 10UâADC_DELAY_10US_MIN_CPU_CYCLES 1800UêADC_CLOCK_ASYNC_DIV1 (0x00000000U)ëADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)ìADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1)íADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)îADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2)ïADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)ðADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)ñADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)òADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)óADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)ôADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)õADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)÷ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE)ûADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0)üADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1)ADC_RESOLUTION_12B (0x00000000U)ADC_RESOLUTION_10B (ADC_CFGR1_RES_0)ADC_RESOLUTION_8B (ADC_CFGR1_RES_1)ADC_RESOLUTION_6B (ADC_CFGR1_RES)ADC_DATAALIGN_RIGHT (0x00000000U)ADC_DATAALIGN_LEFT (ADC_CFGR1_ALIGN)ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR1_EXTEN_0)ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR1_EXTEN_1)ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR1_EXTEN)¤ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)¥ADC_EOC_SEQ_CONV (ADC_ISR_EOS)ADC_OVR_DATA_PRESERVED (0x00000000U)®ADC_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD)·ADC_RANK_CHANNEL_NUMBER (0x00001000U)¸ADC_RANK_NONE (0x00001001U)ÁADC_CHANNEL_0 (ADC_CHSELR_CHSEL0)ÂADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)ÃADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)ÄADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)ÅADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)ÆADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)ÇADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)ÈADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)ÉADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)ÊADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)ËADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)ÌADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)ÍADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)ÎADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)ÏADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)ÐADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)ÔADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)ÕADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)ÛADC_CHANNEL_VREFINT ADC_CHANNEL_17ÝADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18æADC_CHANNEL_MASK (0x0007FFFFU)çADC_CHANNEL_AWD_MASK (0x7C000000U)ïADC_SAMPLETIME_1CYCLE_5 (0x00000000U)ðADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR_SMPR_0)ñADC_SAMPLETIME_7CYCLES_5 (ADC_SMPR_SMPR_1)òADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0))óADC_SAMPLETIME_19CYCLES_5 (ADC_SMPR_SMPR_2)ôADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0))õADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1))öADC_SAMPLETIME_160CYCLES_5 (ADC_SMPR_SMPR)ADC_SCAN_DIRECTION_FORWARD (0x00000001U)ADC_SCAN_DIRECTION_BACKWARD (0x00000002U)ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARDADC_OVERSAMPLING_RATIO_2 (0x00000000U)ADC_OVERSAMPLING_RATIO_4 (0x00000004U)ADC_OVERSAMPLING_RATIO_8 (0x00000008U)ADC_OVERSAMPLING_RATIO_16 (0x0000000CU)ADC_OVERSAMPLING_RATIO_32 (0x00000010U)ADC_OVERSAMPLING_RATIO_64 (0x00000014U)ADC_OVERSAMPLING_RATIO_128 (0x00000018U)ADC_OVERSAMPLING_RATIO_256 (0x0000001CU)¤ADC_RIGHTBITSHIFT_NONE (0x00000000U)¥ADC_RIGHTBITSHIFT_1 (0x00000020U)¦ADC_RIGHTBITSHIFT_2 (0x00000040U)§ADC_RIGHTBITSHIFT_3 (0x00000060U)¨ADC_RIGHTBITSHIFT_4 (0x00000080U)©ADC_RIGHTBITSHIFT_5 (0x000000A0U)ªADC_RIGHTBITSHIFT_6 (0x000000C0U)«ADC_RIGHTBITSHIFT_7 (0x000000E0U)¬ADC_RIGHTBITSHIFT_8 (0x00000100U)´ADC_TRIGGEREDMODE_SINGLE_TRIGGER (0x00000000U)µADC_TRIGGEREDMODE_MULTI_TRIGGER (0x00000200U)½ADC_ANALOGWATCHDOG_NONE (0x00000000U)¾ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))¿ADC_ANALOGWATCHDOG_ALL_REG ( ADC_CFGR1_AWDEN)ÇADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))ÏADC_AWD_EVENT (ADC_FLAG_AWD)ÐADC_OVR_EVENT (ADC_FLAG_OVR)ØADC_IT_RDY ADC_IER_ADRDYIEÙADC_IT_EOSMP ADC_IER_EOSMPIEÚADC_IT_EOC ADC_IER_EOCIEÛADC_IT_EOS ADC_IER_EOSEQIEÜADC_IT_OVR ADC_IER_OVRIEÝADC_IT_AWD ADC_IER_AWDIEÞADC_IT_EOCAL ADC_IER_EOCALIEæADC_FLAG_RDY ADC_ISR_ADRDYçADC_FLAG_EOSMP ADC_ISR_EOSMPèADC_FLAG_EOC ADC_ISR_EOCéADC_FLAG_EOS ADC_ISR_EOSEQêADC_FLAG_OVR ADC_ISR_OVRëADC_FLAG_AWD ADC_ISR_AWDìADC_FLAG_EOCAL ADC_ISR_EOCALïADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)__HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)__HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)ADC_ENABLING_CONDITIONS(__HANDLE__) (( ( ((__HANDLE__)->Instance->CR) & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) ) == RESET ) ? SET : RESET)¦__HAL_ADC_DISABLE(__HANDLE__) do{ (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); } while(0)±ADC_DISABLING_CONDITIONS(__HANDLE__) (( ( ((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN ) ? SET : RESET)»ADC_IS_ENABLE(__HANDLE__) (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) ) ? SET : RESET)ÅADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)ÌADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)ÖADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET ) ? RESET : SET)ßADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)æADC_SCANDIR(_SCAN_MODE_) ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) )? (ADC_CFGR1_SCANDIR) : (0x00000000U) )ð__HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)÷ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)þ__HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)__HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)__HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)¡ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__,_Offset_) ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))°ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__,_Threshold_) ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))¹__HAL_ADC_Value_Shift_left(_Value_,_Shift_) ((_Value_) << (_Shift_))Â__HAL_ADC_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))Ë__HAL_ADC_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))Õ__HAL_ADC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))ß__HAL_ADC_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))è__HAL_ADC_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))óADC_STATE_CLR_SET MODIFY_REGúADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)__HAL_ADC_CLOCK_PRESCALER(__HANDLE__) do{ if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) { (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; } else { (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); ADC->CCR &= ~(ADC_CCR_PRESC); ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; } } while(0)IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))¨IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || ((RESOLUTION) == ADC_RESOLUTION_10B) || ((RESOLUTION) == ADC_RESOLUTION_8B) || ((RESOLUTION) == ADC_RESOLUTION_6B))IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || ((RESOLUTION) == ADC_RESOLUTION_6B))°IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))³IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))¸IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))»IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || ((OVR) == ADC_OVR_DATA_OVERWRITTEN))¾IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || ((WATCHDOG) == ADC_RANK_NONE))ÖIS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5) || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || ((CHANNEL) == ADC_CHANNEL_VREFINT))üIS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || ((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_160CYCLES_5))IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))¢IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)¤IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || ((EVENT) == ADC_OVR_EVENT))¬IS_ADC_RANGE(RESOLUTION,ADC_VALUE) ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))))¸IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))Â ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.hstm32l0xx_hal_def.hstm32l0xx_hal_adc_ex.hP
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*RatioY#RightBitShiftY#TriggeredModeY#PADC_OversamplingTypeDef¾8*ËHClockPrescalerY#ResolutionY#DataAlignY#ScanConvModeY#EOCSelectionY#LowPowerAutoWaitY#LowPowerAutoPowerOffY#ContinuousConvMode#DiscontinuousConvMode#ExternalTrigConvY# ExternalTrigConvEdgeY#$DMAContinuousRequests#(OverrunY#,LowPowerFrequencyModeY#0SamplingTimeY#4OversamplingModeY#8Oversample#<PADC_InitTypeDefª*ChannelY#RankY#PADC_ChannelConfTypeDefã¿*WatchdogModeY#ChannelY#ITMode#HighThresholdY#LowThresholdY#PADC_AnalogWDGConfTypeDef&Ú)£__ADC_HandleTypeDef\Instance##InitË#DMA_Handle)#LLock1#PState/#TErrorCode/#X""PtYPADC_HandleTypeDef° º»¼__STM32L0xx_HAL_FLASH_EX_H )FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE)+WRP_MASK_LOW (0x0000FFFFU),WRP_MASK_HIGH (0xFFFF0000U)6IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))8IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1)));IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || ((__VALUE__) == OB_WRPSTATE_ENABLE))>IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))@IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) || ((__LEVEL__) == OB_RDP_LEVEL_1) || ((__LEVEL__) == OB_RDP_LEVEL_2))DIS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || ((__LEVEL__) == OB_BOR_LEVEL1) || ((__LEVEL__) == OB_BOR_LEVEL2) || ((__LEVEL__) == OB_BOR_LEVEL3) || ((__LEVEL__) == OB_BOR_LEVEL4) || ((__LEVEL__) == OB_BOR_LEVEL5))KIS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))MIS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))OIS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))SIS_OBEX(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_PCROP | OPTIONBYTE_BOOTCONFIG)) && ((__VALUE__) != 0U))aIS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || ((__VALUE__) == OB_PCROP_STATE_ENABLE))dIS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))iIS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))mIS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))nIS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD))tIS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))uIS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END))vIS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))wIS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))xIS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1))))yIS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))ñFLASH_TYPEERASE_PAGES (0x00U)úOPTIONBYTE_WRP (0x01U)ûOPTIONBYTE_RDP (0x02U)üOPTIONBYTE_USER (0x04U)ýOPTIONBYTE_BOR (0x08U)þOPTIONBYTE_BOOT_BIT1 (0x10U)OB_WRPSTATE_DISABLE (0x00U)OB_WRPSTATE_ENABLE (0x01U)»OB_WRP_Pages0to31 (0x00000001U)¼OB_WRP_Pages32to63 (0x00000002U)½OB_WRP_Pages64to95 (0x00000004U)¾OB_WRP_Pages96to127 (0x00000008U)¿OB_WRP_Pages128to159 (0x00000010U)ÀOB_WRP_Pages160to191 (0x00000020U)ÁOB_WRP_Pages192to223 (0x00000040U)ÂOB_WRP_Pages224to255 (0x00000080U)ÃOB_WRP_Pages256to287 (0x00000100U)ÄOB_WRP_Pages288to319 (0x00000200U)ÅOB_WRP_Pages320to351 (0x00000400U)ÆOB_WRP_Pages352to383 (0x00000800U)ÇOB_WRP_Pages384to415 (0x00001000U)ÈOB_WRP_Pages416to447 (0x00002000U)ÉOB_WRP_Pages448to479 (0x00004000U)ÊOB_WRP_Pages480to511 (0x00008000U)ËOB_WRP_Pages512to543 (0x00010000U)ÌOB_WRP_Pages544to575 (0x00020000U)ÍOB_WRP_Pages576to607 (0x00040000U)ÎOB_WRP_Pages608to639 (0x00080000U)ÏOB_WRP_Pages640to671 (0x00100000U)ÐOB_WRP_Pages672to703 (0x00200000U)ÑOB_WRP_Pages704to735 (0x00400000U)ÒOB_WRP_Pages736to767 (0x00800000U)ÓOB_WRP_Pages768to799 (0x01000000U)ÔOB_WRP_Pages800to831 (0x02000000U)ÕOB_WRP_Pages832to863 (0x04000000U)ÖOB_WRP_Pages864to895 (0x08000000U)×OB_WRP_Pages896to927 (0x10000000U)ØOB_WRP_Pages928to959 (0x20000000U)ÙOB_WRP_Pages960to991 (0x40000000U)ÚOB_WRP_Pages992to1023 (0x80000000U)ÛOB_WRP_AllPages (0xFFFFFFFFU)ãOB_WRP2_Pages1024to1055 (0x00000001U)äOB_WRP2_Pages1056to1087 (0x00000002U)åOB_WRP2_Pages1088to1119 (0x00000004U)æOB_WRP2_Pages1120to1151 (0x00000008U)çOB_WRP2_Pages1152to1183 (0x00000010U)èOB_WRP2_Pages1184to1215 (0x00000020U)éOB_WRP2_Pages1216to1247 (0x00000040U)êOB_WRP2_Pages1248to1279 (0x00000080U)ëOB_WRP2_Pages1280to1311 (0x00000100U)ìOB_WRP2_Pages1312to1343 (0x00000200U)íOB_WRP2_Pages1344to1375 (0x00000400U)îOB_WRP2_Pages1376to1407 (0x00000800U)ïOB_WRP2_Pages1408to1439 (0x00001000U)ðOB_WRP2_Pages1440to1471 (0x00002000U)ñOB_WRP2_Pages1472to1503 (0x00004000U)òOB_WRP2_Pages1504to1535 (0x00008000U)óOB_WRP2_AllPages (0x0000FFFFU)üOB_RDP_LEVEL_0 ((uint8_t)0xAA)ýOB_RDP_LEVEL_1 ((uint8_t)0xBB)þOB_RDP_LEVEL_2 ((uint8_t)0xCC)OB_BOR_OFF ((uint8_t)0x00)OB_BOR_LEVEL1 ((uint8_t)0x08)OB_BOR_LEVEL2 ((uint8_t)0x09)OB_BOR_LEVEL3 ((uint8_t)0x0A)OB_BOR_LEVEL4 ((uint8_t)0x0B)OB_BOR_LEVEL5 ((uint8_t)0x0C)OB_IWDG_SW ((uint8_t)0x10)OB_IWDG_HW ((uint8_t)0x00)¤OB_STOP_NORST ((uint8_t)0x20)¥OB_STOP_RST ((uint8_t)0x00)®OB_STDBY_NORST ((uint8_t)0x40)¯OB_STDBY_RST ((uint8_t)0x00)»OPTIONBYTE_PCROP (0x01U)ÉOPTIONBYTE_BOOTCONFIG (0x02U)ÖOB_PCROP_STATE_DISABLE (0x00U)×OB_PCROP_STATE_ENABLE (0x01U)àOB_PCROP_DESELECTED ((uint16_t)0x0000)áOB_PCROP_SELECTED ((uint16_t)FLASH_OPTR_WPRMOD)OB_PCROP_Pages0to31 (0x00000001U)OB_PCROP_Pages32to63 (0x00000002U)OB_PCROP_Pages64to95 (0x00000004U)OB_PCROP_Pages96to127 (0x00000008U)OB_PCROP_Pages128to159 (0x00000010U)OB_PCROP_Pages160to191 (0x00000020U)OB_PCROP_Pages192to223 (0x00000040U)OB_PCROP_Pages224to255 (0x00000080U)OB_PCROP_Pages256to287 (0x00000100U)OB_PCROP_Pages288to319 (0x00000200U) OB_PCROP_Pages320to351 (0x00000400U)¡OB_PCROP_Pages352to383 (0x00000800U)¢OB_PCROP_Pages384to415 (0x00001000U)£OB_PCROP_Pages416to447 (0x00002000U)¤OB_PCROP_Pages448to479 (0x00004000U)¥OB_PCROP_Pages480to511 (0x00008000U)¦OB_PCROP_Pages512to543 (0x00010000U)§OB_PCROP_Pages544to575 (0x00020000U)¨OB_PCROP_Pages576to607 (0x00040000U)©OB_PCROP_Pages608to639 (0x00080000U)ªOB_PCROP_Pages640to671 (0x00100000U)«OB_PCROP_Pages672to703 (0x00200000U)¬OB_PCROP_Pages704to735 (0x00400000U)OB_PCROP_Pages736to767 (0x00800000U)®OB_PCROP_Pages768to799 (0x01000000U)¯OB_PCROP_Pages800to831 (0x02000000U)°OB_PCROP_Pages832to863 (0x04000000U)±OB_PCROP_Pages864to895 (0x08000000U)²OB_PCROP_Pages896to927 (0x10000000U)³OB_PCROP_Pages928to959 (0x20000000U)´OB_PCROP_Pages960to991 (0x40000000U)µOB_PCROP_Pages992to1023 (0x80000000U)¶OB_PCROP_AllPages (0xFFFFFFFFU)¾OB_PCROP2_Pages1024to1055 (0x00000001U)¿OB_PCROP2_Pages1056to1087 (0x00000002U)ÀOB_PCROP2_Pages1088to1119 (0x00000004U)ÁOB_PCROP2_Pages1120to1151 (0x00000008U)ÂOB_PCROP2_Pages1152to1183 (0x00000010U)ÃOB_PCROP2_Pages1184to1215 (0x00000020U)ÄOB_PCROP2_Pages1216to1247 (0x00000040U)ÅOB_PCROP2_Pages1248to1279 (0x00000080U)ÆOB_PCROP2_Pages1280to1311 (0x00000100U)ÇOB_PCROP2_Pages1312to1343 (0x00000200U)ÈOB_PCROP2_Pages1344to1375 (0x00000400U)ÉOB_PCROP2_Pages1376to1407 (0x00000800U)ÊOB_PCROP2_Pages1408to1439 (0x00001000U)ËOB_PCROP2_Pages1440to1471 (0x00002000U)ÌOB_PCROP2_Pages1472to1503 (0x00004000U)ÍOB_PCROP2_Pages1504to1535 (0x00008000U)ÎOB_PCROP2_AllPages (0x0000FFFFU)×OB_BOOT_BIT1_RESET (uint8_t)(0x00)ØOB_BOOT_BIT1_SET (uint8_t)(0x01)àFLASH_TYPEPROGRAMDATA_BYTE (0x00U)áFLASH_TYPEPROGRAMDATA_HALFWORD (0x01U)âFLASH_TYPEPROGRAMDATA_WORD (0x02U)îOB_BOOT_BANK1 ((uint8_t)0x00)ðOB_BOOT_BANK2 ((uint8_t)(FLASH_OPTR_BFB2 >> 16))__HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))__HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))__HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)¦__HAL_FLASH_BUFFER_CACHE_ENABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)¬__HAL_FLASH_BUFFER_CACHE_DISABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)²__HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)¸__HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)¾__HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)Ä__HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)Ë__HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; FLASH->PDKEYR = FLASH_PDKEY2; SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); } while (0)Õ__HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; FLASH->PDKEYR = FLASH_PDKEY2; CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); } while (0)tk ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.hstm32l0xx_hal_def.hx
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*TypeEraseY#PageAddressY#NbPagesY#PFLASH_EraseInitTypeDefÃ£*ÂOptionTypeY#WRPStateY#WRPSectorY#WRPSector2Y#RDPLevel:#BORLevel:#USERConfig:#BOOTBit1Config:#PFLASH_OBProgramInitTypeDef Ä*ÑOptionTypeY#PCROPStateY#PCROPSectorY#PCROPSector2Y#BootConfigI#PFLASH_AdvOBProgramInitTypeDefåà¾¿À__STM32L0xx_FLASH_RAMFUNC_H |p ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.hstm32l0xx_hal_def.hÈ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMÂÃÄÅ__STM32L0xx_HAL_FLASH_H (FLASH_TIMEOUT_VALUE (50000U))FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE2IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)4IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1))jHAL_FLASH_ERROR_NONE 0x00UkHAL_FLASH_ERROR_PGA 0x01UlHAL_FLASH_ERROR_WRP 0x02UmHAL_FLASH_ERROR_OPTV 0x04UnHAL_FLASH_ERROR_SIZE 0x08UoHAL_FLASH_ERROR_RD 0x10UpHAL_FLASH_ERROR_FWWERR 0x20UqHAL_FLASH_ERROR_NOTZERO 0x40U{FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U)|FLASH_PAGE_SIZE (128U)~FLASH_END (FLASH_BASE + FLASH_SIZE - 1)FLASH_BANK2_BASE (FLASH_BASE + (FLASH_SIZE >> 1))FLASH_BANK1_END (FLASH_BANK2_BASE - 1)FLASH_BANK2_END (FLASH_END)FLASH_TYPEPROGRAM_WORD (0x02U)FLASH_LATENCY_0 (0x00000000U)FLASH_LATENCY_1 FLASH_ACR_LATENCY¡FLASH_IT_EOP FLASH_PECR_EOPIE¢FLASH_IT_ERR FLASH_PECR_ERRIE«FLASH_FLAG_BSY FLASH_SR_BSY¬FLASH_FLAG_EOP FLASH_SR_EOPFLASH_FLAG_ENDHV FLASH_SR_HVOFF®FLASH_FLAG_READY FLASH_SR_READY¯FLASH_FLAG_WRPERR FLASH_SR_WRPERR°FLASH_FLAG_PGAERR FLASH_SR_PGAERR±FLASH_FLAG_SIZERR FLASH_SR_SIZERR²FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR³FLASH_FLAG_RDERR FLASH_SR_RDERR´FLASH_FLAG_FWWERR FLASH_SR_FWWERRµFLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR¿FLASH_PDKEY1 (0x04152637U)ÀFLASH_PDKEY2 (0xFAFBFCFDU)ÃFLASH_PEKEY1 (0x89ABCDEFU)ÄFLASH_PEKEY2 (0x02030405U)ÈFLASH_PRGKEY1 (0x8C9DAEBFU)ÉFLASH_PRGKEY2 (0x13141516U)ÌFLASH_OPTKEY1 (0xFBEAD9C8U)ÍFLASH_OPTKEY2 (0x24252627U)ò__HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__))ü__HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))__HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))__HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))ª«°¥ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.hstm32l0xx_hal_def.hstm32l0xx_hal_flash_ex.hstm32l0xx_hal_flash_ramfunc.hÄ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMFLASH_PROC_NONEFLASH_PROC_PAGEERASEFLASH_PROC_PROGRAMPFLASH_ProcedureTypeDefÀH*ProcedureOnGoing#NbPagesToErase#Address#Page#Lock1#ErrorCode#ttYPFLASH_ProcessTypeDef$[qpFlashÈ·pFlashÇÈÉSTM32L0xx_HAL_I2C_EX_H /I2C_ANALOGFILTER_ENABLE 0x00000000U0I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF8I2C_FMP_NOT_SUPPORTED 0xAAAA0000U:I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP;I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMPAI2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMPBI2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMPHI2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMPMI2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMPRI2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMPIS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || ((FILTER) == I2C_ANALOGFILTER_DISABLE))IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))ti ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.hstm32l0xx_hal_def.hÀ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMËÌÍSTM32L0xx_HAL_I2C_H ¥HAL_I2C_ERROR_NONE (0x00000000U)¦HAL_I2C_ERROR_BERR (0x00000001U)§HAL_I2C_ERROR_ARLO (0x00000002U)¨HAL_I2C_ERROR_AF (0x00000004U)©HAL_I2C_ERROR_OVR (0x00000008U)ªHAL_I2C_ERROR_DMA (0x00000010U)«HAL_I2C_ERROR_TIMEOUT (0x00000020U)¬HAL_I2C_ERROR_SIZE (0x00000040U)HAL_I2C_ERROR_DMA_PARAM (0x00000080U)±HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)¯I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)°I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))±I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))²I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)³I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)´I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)¹I2C_OTHER_FRAME (0x000000AAU)ºI2C_OTHER_AND_LAST_FRAME (0x0000AA00U)ÂI2C_ADDRESSINGMODE_7BIT (0x00000001U)ÃI2C_ADDRESSINGMODE_10BIT (0x00000002U)ËI2C_DUALADDRESS_DISABLE (0x00000000U)ÌI2C_DUALADDRESS_ENABLE I2C_OAR2_OA2ENÔI2C_OA2_NOMASK ((uint8_t)0x00U)ÕI2C_OA2_MASK01 ((uint8_t)0x01U)ÖI2C_OA2_MASK02 ((uint8_t)0x02U)×I2C_OA2_MASK03 ((uint8_t)0x03U)ØI2C_OA2_MASK04 ((uint8_t)0x04U)ÙI2C_OA2_MASK05 ((uint8_t)0x05U)ÚI2C_OA2_MASK06 ((uint8_t)0x06U)ÛI2C_OA2_MASK07 ((uint8_t)0x07U)ãI2C_GENERALCALL_DISABLE (0x00000000U)äI2C_GENERALCALL_ENABLE I2C_CR1_GCENìI2C_NOSTRETCH_DISABLE (0x00000000U)íI2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCHõI2C_MEMADD_SIZE_8BIT (0x00000001U)öI2C_MEMADD_SIZE_16BIT (0x00000002U)þI2C_DIRECTION_TRANSMIT (0x00000000U)ÿI2C_DIRECTION_RECEIVE (0x00000001U)I2C_RELOAD_MODE I2C_CR2_RELOADI2C_AUTOEND_MODE I2C_CR2_AUTOENDI2C_SOFTEND_MODE (0x00000000U)I2C_NO_STARTSTOP (0x00000000U)I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)I2C_IT_ERRI I2C_CR1_ERRIE I2C_IT_TCI I2C_CR1_TCIE¡I2C_IT_STOPI I2C_CR1_STOPIE¢I2C_IT_NACKI I2C_CR1_NACKIE£I2C_IT_ADDRI I2C_CR1_ADDRIE¤I2C_IT_RXI I2C_CR1_RXIE¥I2C_IT_TXI I2C_CR1_TXIEI2C_FLAG_TXE I2C_ISR_TXE®I2C_FLAG_TXIS I2C_ISR_TXIS¯I2C_FLAG_RXNE I2C_ISR_RXNE°I2C_FLAG_ADDR I2C_ISR_ADDR±I2C_FLAG_AF I2C_ISR_NACKF²I2C_FLAG_STOPF I2C_ISR_STOPF³I2C_FLAG_TC I2C_ISR_TC´I2C_FLAG_TCR I2C_ISR_TCRµI2C_FLAG_BERR I2C_ISR_BERR¶I2C_FLAG_ARLO I2C_ISR_ARLO·I2C_FLAG_OVR I2C_ISR_OVR¸I2C_FLAG_PECERR I2C_ISR_PECERR¹I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUTºI2C_FLAG_ALERT I2C_ISR_ALERT»I2C_FLAG_BUSY I2C_ISR_BUSY¼I2C_FLAG_DIR I2C_ISR_DIRÖ__HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)ç__HAL_I2C_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))÷__HAL_I2C_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))__HAL_I2C_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)¡I2C_FLAG_MASK (0x0001FFFFU)¢__HAL_I2C_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)¶__HAL_I2C_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : ((__HANDLE__)->Instance->ICR = (__FLAG__)))¾__HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))Ä__HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))Ê__HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))ÐãIS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || ((MODE) == I2C_ADDRESSINGMODE_10BIT))æIS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))éIS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || ((MASK) == I2C_OA2_MASK01) || ((MASK) == I2C_OA2_MASK02) || ((MASK) == I2C_OA2_MASK03) || ((MASK) == I2C_OA2_MASK04) || ((MASK) == I2C_OA2_MASK05) || ((MASK) == I2C_OA2_MASK06) || ((MASK) == I2C_OA2_MASK07))òIS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))õIS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))øIS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))ûIS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || ((MODE) == I2C_AUTOEND_MODE) || ((MODE) == I2C_SOFTEND_MODE))ÿIS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || ((REQUEST) == I2C_GENERATE_START_READ) || ((REQUEST) == I2C_GENERATE_START_WRITE) || ((REQUEST) == I2C_NO_STARTSTOP))IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))¡I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))£I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))«I2C_CHECK_FLAG(__ISR__,__FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)I2C_CHECK_IT_SOURCE(__CR1__,__IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.hstm32l0xx_hal_def.hstm32l0xx_hal_i2c_ex.hÈ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*ø TimingY#OwnAddress1Y#AddressingModeY#DualAddressModeY#OwnAddress2Y#OwnAddress2MasksY#GeneralCallModeY#NoStretchModeY#PI2C_InitTypeDef¾K©HAL_I2C_STATE_RESETHAL_I2C_STATE_READY HAL_I2C_STATE_BUSY$HAL_I2C_STATE_BUSY_TX!HAL_I2C_STATE_BUSY_RX"HAL_I2C_STATE_LISTEN(HAL_I2C_STATE_BUSY_TX_LISTEN)HAL_I2C_STATE_BUSY_RX_LISTEN*HAL_I2C_STATE_ABORT`HAL_I2C_STATE_TIMEOUT HAL_I2C_STATE_ERRORàPHAL_I2C_StateTypeDef| HAL_I2C_MODE_NONEHAL_I2C_MODE_MASTERHAL_I2C_MODE_SLAVE HAL_I2C_MODE_MEM@PHAL_I2C_ModeTypeDefÅ)    __I2C_HandleTypeDefTInstance#Initx#pBuffPtr#$XferSizeI#(XferCount#*XferOptions#,PreviousState#0Näõ%%Y%Y"ËXferISRä#4hdmatx¢#8hdmarx¢#<Lock1#@State¨#AMode¬#BErrorCode#DAddrEventCount#HDevaddress#LMemaddress#P"H    ":tItY"<"Pt©t PI2C_HandleTypeDef<þÏÐÑSTM32L0xx_HAL_IWDG_H RIWDG_PRESCALER_4 0x00000000uSIWDG_PRESCALER_8 IWDG_PR_PR_0TIWDG_PRESCALER_16 IWDG_PR_PR_1UIWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)VIWDG_PRESCALER_64 IWDG_PR_PR_2WIWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)XIWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)`IWDG_WINDOW_DISABLE IWDG_WINR_WINs__HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE){__HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)¤IWDG_KEY_RELOAD 0x0000AAAAu¥IWDG_KEY_ENABLE 0x0000CCCCu¦IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u§IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u·IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)¾IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)ÅIS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128)|| ((__PRESCALER__) == IWDG_PRESCALER_256))ÒIS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)ÙIS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)pg ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.hstm32l0xx_hal_def.hP
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*÷PrescalerY#ReloadY#WindowY#PIWDG_InitTypeDef¿9*°Instance0#Init÷#"    PIWDG_HandleTypeDefCÓÔÕSTM32L0xx_HAL_LPTIM_H ,LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_IM29ÄLPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000UÅLPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSELÍLPTIM_PRESCALER_DIV1 0x00000000UÎLPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0ÏLPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1ÐLPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)ÑLPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2ÒLPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)ÓLPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)ÔLPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESCÝLPTIM_OUTPUTPOLARITY_HIGH 0x00000000UÞLPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOLæLPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000UçLPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0èLPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1éLPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLTñLPTIM_CLOCKPOLARITY_RISING 0x00000000UòLPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0óLPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1ûLPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFUüLPTIM_TRIGSOURCE_0 0x00000000UýLPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0þLPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1ÿLPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSELLPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGENLPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000ULPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT¡LPTIM_UPDATE_IMMEDIATE 0x00000000U¢LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD«LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U¬LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODEµLPTIM_FLAG_DOWN LPTIM_ISR_DOWN¶LPTIM_FLAG_UP LPTIM_ISR_UP·LPTIM_FLAG_ARROK LPTIM_ISR_ARROK¸LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK¹LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIGºLPTIM_FLAG_ARRM LPTIM_ISR_ARRM»LPTIM_FLAG_CMPM LPTIM_ISR_CMPMÃLPTIM_IT_DOWN LPTIM_IER_DOWNIEÄLPTIM_IT_UP LPTIM_IER_UPIEÅLPTIM_IT_ARROK LPTIM_IER_ARROKIEÆLPTIM_IT_CMPOK LPTIM_IER_CMPOKIEÇLPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIEÈLPTIM_IT_ARRM LPTIM_IER_ARRMIEÉLPTIM_IT_CMPM LPTIM_IER_CMPMIEâ__HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)ê__HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))ö__HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)ý__HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)__HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)__HAL_LPTIM_AUTORELOAD_SET(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))__HAL_LPTIM_COMPARE_SET(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))¥__HAL_LPTIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))µ__HAL_LPTIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))Æ__HAL_LPTIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))×__HAL_LPTIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))è__HAL_LPTIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)ï__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)ö__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))ý__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))«IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))¯IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))¸IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)ºIS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))½IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))ÂIS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))ÆIS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || ((__TRIG__) == LPTIM_TRIGSOURCE_0) || ((__TRIG__) == LPTIM_TRIGSOURCE_1) || ((__TRIG__) == LPTIM_TRIGSOURCE_2) || ((__TRIG__) == LPTIM_TRIGSOURCE_3) || ((__TRIG__) == LPTIM_TRIGSOURCE_4) || ((__TRIG__) == LPTIM_TRIGSOURCE_5) || ((__TRIG__) == LPTIM_TRIGSOURCE_6) || ((__TRIG__) == LPTIM_TRIGSOURCE_7))ÐIS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))ÔIS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))ÙIS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))ÜIS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))ßIS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) && ((__AUTORELOAD__) <= 0x0000FFFFUL))âIS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)äIS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) && ((__PERIOD__) <= 0x0000FFFFUL))çIS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)th ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.hstm32l0xx_hal_def.h`
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*èSourceY#PrescalerY#PLPTIM_ClockConfigTypeDefÀ9*³PolarityY#SampleTimeY#PLPTIM_ULPClockConfigTypeDefK*SourceY#ActiveEdgeY#SampleTimeY#PLPTIM_TriggerConfigTypeDefV\*³(Clockè#UltraLowPowerClock3#Trigger#OutputPolarityY#UpdateModeY# CounterSourceY#$PLPTIM_InitTypeDefµsÏHAL_LPTIM_STATE_RESETHAL_LPTIM_STATE_READYHAL_LPTIM_STATE_BUSYHAL_LPTIM_STATE_TIMEOUTHAL_LPTIM_STATE_ERRORPHAL_LPTIM_StateTypeDefL*¹0Instance9#Init3#Statusõ#,Lock1#-State?#."1tÏPLPTIM_HandleTypeDefí×ØÙ__STM32L0xx_HAL_PWR_EX_H /__HAL_PWR_FLASHWAKEUP_ENABLE() CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF)6__HAL_PWR_FLASHWAKEUP_DISABLE() SET_BIT(PWR->CR, PWR_CR_DSEEKOFF)ti ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.hstm32l0xx_hal_def.hÀ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMÛÜÝ__STM32L0xx_HAL_PWR_H APWR_EXTI_LINE_PVD EXTI_FTSR_TR16OPWR_WAKEUP_PIN1 PWR_CSR_EWUP1RPWR_WAKEUP_PIN2 PWR_CSR_EWUP2WPWR_WAKEUP_PIN3 PWR_CSR_EWUP3aPWR_PVDLEVEL_0 PWR_CR_PLS_LEV0bPWR_PVDLEVEL_1 PWR_CR_PLS_LEV1cPWR_PVDLEVEL_2 PWR_CR_PLS_LEV2dPWR_PVDLEVEL_3 PWR_CR_PLS_LEV3ePWR_PVDLEVEL_4 PWR_CR_PLS_LEV4fPWR_PVDLEVEL_5 PWR_CR_PLS_LEV5gPWR_PVDLEVEL_6 PWR_CR_PLS_LEV6hPWR_PVDLEVEL_7 PWR_CR_PLS_LEV7qPWR_PVD_MODE_NORMAL (0x00000000U)rPWR_PVD_MODE_IT_RISING (0x00010001U)sPWR_PVD_MODE_IT_FALLING (0x00010002U)tPWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)uPWR_PVD_MODE_EVENT_RISING (0x00020001U)vPWR_PVD_MODE_EVENT_FALLING (0x00020002U)wPWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)PWR_MAINREGULATOR_ON (0x00000000U)PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSRPWR_SLEEPENTRY_WFI (0x01U)PWR_SLEEPENTRY_WFE (0x02U)PWR_STOPENTRY_WFI (0x01U)PWR_STOPENTRY_WFE (0x02U)PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS¡IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))«PWR_FLAG_WU PWR_CSR_WUF¬PWR_FLAG_SB PWR_CSR_SBF®PWR_FLAG_PVDO PWR_CSR_PVDO°PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF±PWR_FLAG_VOS PWR_CSR_VOSF²PWR_FLAG_REGLP PWR_CSR_REGLPFÒ__HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))î__HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))ö__HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U)ý__HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)__HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)__HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)__HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)¡__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)¨__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)®__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0);µ__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0);»__HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))Á__HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))Ç__HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)ÓIS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))ØIS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))ßIS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || ((PIN) == PWR_WAKEUP_PIN3))íIS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))ïIS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))ñIS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))ø ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.hstm32l0xx_hal_def.hstm32l0xx_hal_pwr_ex.hø
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*ãPVDLevelY#ModeY#PPWR_PVDTypeDef¾5ßàáSTM32L0xx_HAL_SPI_H ¼HAL_SPI_ERROR_NONE (0x00000000U)½HAL_SPI_ERROR_MODF (0x00000001U)¾HAL_SPI_ERROR_CRC (0x00000002U)¿HAL_SPI_ERROR_OVR (0x00000004U)ÀHAL_SPI_ERROR_FRE (0x00000008U)ÁHAL_SPI_ERROR_DMA (0x00000010U)ÂHAL_SPI_ERROR_FLAG (0x00000020U)ÃHAL_SPI_ERROR_ABORT (0x00000040U)ÎSPI_MODE_SLAVE (0x00000000U)ÏSPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)×SPI_DIRECTION_2LINES (0x00000000U)ØSPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLYÙSPI_DIRECTION_1LINE SPI_CR1_BIDIMODEáSPI_DATASIZE_8BIT (0x00000000U)âSPI_DATASIZE_16BIT SPI_CR1_DFFêSPI_POLARITY_LOW (0x00000000U)ëSPI_POLARITY_HIGH SPI_CR1_CPOLóSPI_PHASE_1EDGE (0x00000000U)ôSPI_PHASE_2EDGE SPI_CR1_CPHAüSPI_NSS_SOFT SPI_CR1_SSMýSPI_NSS_HARD_INPUT (0x00000000U)þSPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)SPI_BAUDRATEPRESCALER_2 (0x00000000U)SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)SPI_FIRSTBIT_MSB (0x00000000U)SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRSTSPI_TIMODE_DISABLE (0x00000000U)SPI_TIMODE_ENABLE SPI_CR2_FRF§SPI_CRCCALCULATION_DISABLE (0x00000000U)¨SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN°SPI_IT_TXE SPI_CR2_TXEIE±SPI_IT_RXNE SPI_CR2_RXNEIE²SPI_IT_ERR SPI_CR2_ERRIEºSPI_FLAG_RXNE SPI_SR_RXNE»SPI_FLAG_TXE SPI_SR_TXE¼SPI_FLAG_BSY SPI_SR_BSY½SPI_FLAG_CRCERR SPI_SR_CRCERR¾SPI_FLAG_MODF SPI_SR_MODF¿SPI_FLAG_OVR SPI_SR_OVRÀSPI_FLAG_FRE SPI_SR_FREÁSPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)Ü__HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)é__HAL_SPI_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))õ__HAL_SPI_DISABLE_IT(__HANDLE__,__INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))__HAL_SPI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)__HAL_SPI_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))__HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_modf = 0x00U; tmpreg_modf = (__HANDLE__)->Instance->SR; CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); UNUSED(tmpreg_modf); } while(0U)__HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_ovr = 0x00U; tmpreg_ovr = (__HANDLE__)->Instance->DR; tmpreg_ovr = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_ovr); } while(0U)º__HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_fre = 0x00U; tmpreg_fre = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_fre); }while(0U)Æ__HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)Í__HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)ÝSPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)äSPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)ëSPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)ûSPI_CHECK_FLAG(__SR__,__FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)SPI_CHECK_IT_SOURCE(__CR2__,__INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || ((__MODE__) == SPI_DIRECTION_1LINE))IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)¥IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || ((__MODE__) == SPI_DIRECTION_1LINE))IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || ((__DATASIZE__) == SPI_DATASIZE_8BIT))µIS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || ((__CPOL__) == SPI_POLARITY_HIGH))½IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || ((__CPHA__) == SPI_PHASE_2EDGE))ÅIS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || ((__NSS__) == SPI_NSS_HARD_INPUT) || ((__NSS__) == SPI_NSS_HARD_OUTPUT))ÎIS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))ÜIS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || ((__BIT__) == SPI_FIRSTBIT_LSB))äIS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || ((__MODE__) == SPI_TIMODE_ENABLE))ìIS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))ôIS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))üIS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U)pf ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.hstm32l0xx_hal_def.hð
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*,ModeY#DirectionY#DataSizeY#CLKPolarityY#CLKPhaseY#NSSY#BaudRatePrescalerY#FirstBitY#TIModeY# CRCCalculationY#$CRCPolynomialY#(PSPI_InitTypeDef¾TòHAL_SPI_STATE_RESETHAL_SPI_STATE_READYHAL_SPI_STATE_BUSYHAL_SPI_STATE_BUSY_TXHAL_SPI_STATE_BUSY_RXHAL_SPI_STATE_BUSY_TX_RXHAL_SPI_STATE_ERRORHAL_SPI_STATE_ABORTPHAL_SPI_StateTypeDefc)¯__SPI_HandleTypeDefXInstance¯#Init#pTxBuffPtrµ#0TxXferSizeI#4TxXferCount»#6pRxBuffPtrµ#8RxXferSizeI#<RxXferCount»#>O¼%Á"4RxISR<#@OÕ%Á"MTxISRU#DhdmatxÅ#HhdmarxÅ#LLock1#PStateË#QErrorCodeÏ#T"l ":tI""PtrtYPSPI_HandleTypeDefãäåSTM32L0xx_HAL_TIM_EX_H 8TIM2_ETR_GPIO 0x00000000U<TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)=TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)?TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)@TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMPCTIM2_TI4_GPIO 0x00000000UETIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0FTIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1NTIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMPOTIM3_TI2_GPIO_DEF 0x00000000UPTIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMPVTIM3_TI1_GPIO TIM3_OR_TI1_RMPWTIM3_ETR_GPIO 0x00000000UXTIM3_ETR_HSI TIM3_OR_ETR_RMP_1[TIM21_ETR_GPIO 0x00000000U]TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0^TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1`TIM21_ETR_LSE TIM21_OR_ETR_RMPbTIM21_TI1_GPIO 0x00000000UcTIM21_TI1_MCO TIM21_OR_TI1_RMPdTIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0eTIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1fTIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1)gTIM21_TI1_LSE TIM21_OR_TI1_RMP_2hTIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0)jTIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1)mTIM21_TI2_GPIO 0x00000000UoTIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMPsTIM22_ETR_GPIO 0x00000000UuTIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0vTIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1xTIM22_ETR_LSE TIM22_OR_ETR_RMPzTIM22_TI1_GPIO 0x00000000U|TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0}TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1IS_TIM_REMAP(__INSTANCE__,__TIM_REMAP__) ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || (((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP))))IS_CHANNEL_AVAILABLE(__INSTANCE__,__CHANNEL__) ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))) || (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))))ti ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.hstm32l0xx_hal_def.hÀ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMçèéSTM32L0xx_HAL_TIM_H îTIM_CLEARINPUTSOURCE_NONE 0x00000000UïTIM_CLEARINPUTSOURCE_ETR 0x00000001U÷TIM_DMABASE_CR1 0x00000000UøTIM_DMABASE_CR2 0x00000001UùTIM_DMABASE_SMCR 0x00000002UúTIM_DMABASE_DIER 0x00000003UûTIM_DMABASE_SR 0x00000004UüTIM_DMABASE_EGR 0x00000005UýTIM_DMABASE_CCMR1 0x00000006UþTIM_DMABASE_CCMR2 0x00000007UÿTIM_DMABASE_CCER 0x00000008UTIM_DMABASE_CNT 0x00000009UTIM_DMABASE_PSC 0x0000000AUTIM_DMABASE_ARR 0x0000000BUTIM_DMABASE_CCR1 0x0000000DUTIM_DMABASE_CCR2 0x0000000EUTIM_DMABASE_CCR3 0x0000000FUTIM_DMABASE_CCR4 0x00000010UTIM_DMABASE_DCR 0x00000012UTIM_DMABASE_DMAR 0x00000013UTIM_DMABASE_OR 0x00000014UTIM_EVENTSOURCE_UPDATE TIM_EGR_UGTIM_EVENTSOURCE_CC1 TIM_EGR_CC1GTIM_EVENTSOURCE_CC2 TIM_EGR_CC2GTIM_EVENTSOURCE_CC3 TIM_EGR_CC3GTIM_EVENTSOURCE_CC4 TIM_EGR_CC4GTIM_EVENTSOURCE_TRIGGER TIM_EGR_TGTIM_INPUTCHANNELPOLARITY_RISING 0x00000000UTIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)¨TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP©TIM_ETRPOLARITY_NONINVERTED 0x00000000U±TIM_ETRPRESCALER_DIV1 0x00000000U²TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0³TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1´TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS¼TIM_COUNTERMODE_UP 0x00000000U½TIM_COUNTERMODE_DOWN TIM_CR1_DIR¾TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0¿TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1ÀTIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMSÈTIM_CLOCKDIVISION_DIV1 0x00000000UÉTIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0ÊTIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1ÒTIM_OUTPUTSTATE_DISABLE 0x00000000UÓTIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1EÛTIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000UÜTIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPEåTIM_OCFAST_DISABLE 0x00000000UæTIM_OCFAST_ENABLE TIM_CCMR1_OC1FEîTIM_OUTPUTNSTATE_DISABLE 0x00000000UïTIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE÷TIM_OCPOLARITY_HIGH 0x00000000UøTIM_OCPOLARITY_LOW TIM_CCER_CC1PTIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISINGTIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLINGTIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGETIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISINGTIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLINGTIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1TIM_ICSELECTION_TRC TIM_CCMR1_CC1STIM_ICPSC_DIV1 0x00000000UTIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC¨TIM_OPMODE_SINGLE TIM_CR1_OPM©TIM_OPMODE_REPETITIVE 0x00000000U±TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0²TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1³TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)»TIM_IT_UPDATE TIM_DIER_UIE¼TIM_IT_CC1 TIM_DIER_CC1IE½TIM_IT_CC2 TIM_DIER_CC2IE¾TIM_IT_CC3 TIM_DIER_CC3IE¿TIM_IT_CC4 TIM_DIER_CC4IEÀTIM_IT_TRIGGER TIM_DIER_TIEÈTIM_DMA_UPDATE TIM_DIER_UDEÉTIM_DMA_CC1 TIM_DIER_CC1DEÊTIM_DMA_CC2 TIM_DIER_CC2DEËTIM_DMA_CC3 TIM_DIER_CC3DEÌTIM_DMA_CC4 TIM_DIER_CC4DEÍTIM_DMA_TRIGGER TIM_DIER_TDEÕTIM_CCDMAREQUEST_CC 0x00000000UÖTIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDSÞTIM_FLAG_UPDATE TIM_SR_UIFßTIM_FLAG_CC1 TIM_SR_CC1IFàTIM_FLAG_CC2 TIM_SR_CC2IFáTIM_FLAG_CC3 TIM_SR_CC3IFâTIM_FLAG_CC4 TIM_SR_CC4IFãTIM_FLAG_TRIGGER TIM_SR_TIFäTIM_FLAG_CC1OF TIM_SR_CC1OFåTIM_FLAG_CC2OF TIM_SR_CC2OFæTIM_FLAG_CC3OF TIM_SR_CC3OFçTIM_FLAG_CC4OF TIM_SR_CC4OFïTIM_CHANNEL_1 0x00000000UðTIM_CHANNEL_2 0x00000004UñTIM_CHANNEL_3 0x00000008UòTIM_CHANNEL_4 0x0000000CUóTIM_CHANNEL_ALL 0x0000003CUûTIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0üTIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRFýTIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1þTIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_EDÿTIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTEDTIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTEDTIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISINGTIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLINGTIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGETIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8£TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED¤TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED¬TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2®TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4¯TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8·TIM_TRGO_RESET 0x00000000U¸TIM_TRGO_ENABLE TIM_CR2_MMS_0¹TIM_TRGO_UPDATE TIM_CR2_MMS_1ºTIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)»TIM_TRGO_OC1REF TIM_CR2_MMS_2¼TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)½TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)¾TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)ÆTIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSMÇTIM_MASTERSLAVEMODE_DISABLE 0x00000000UÏTIM_SLAVEMODE_DISABLE 0x00000000UÐTIM_SLAVEMODE_RESET TIM_SMCR_SMS_2ÑTIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)ÒTIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)ÓTIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)ÛTIM_OCMODE_TIMING 0x00000000UÜTIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0ÝTIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1ÞTIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)ßTIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)àTIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)áTIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)âTIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2êTIM_TS_ITR0 0x00000000UëTIM_TS_ITR1 TIM_SMCR_TS_0ìTIM_TS_ITR2 TIM_SMCR_TS_1íTIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)îTIM_TS_TI1F_ED TIM_SMCR_TS_2ïTIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)ðTIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)ñTIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)òTIM_TS_NONE 0x0000FFFFUúTIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTEDûTIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTEDüTIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISINGýTIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLINGþTIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGETIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8TIM_TI1SELECTION_CH1 0x00000000UTIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1STIM_DMABURSTLENGTH_1TRANSFER 0x00000000UTIM_DMABURSTLENGTH_2TRANSFERS 0x00000100UTIM_DMABURSTLENGTH_3TRANSFERS 0x00000200UTIM_DMABURSTLENGTH_4TRANSFERS 0x00000300UTIM_DMABURSTLENGTH_5TRANSFERS 0x00000400UTIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U¡TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U¢TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U£TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U¤TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U¥TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U¦TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U§TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U¨TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U©TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00UªTIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U«TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U³TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)´TIM_DMA_ID_CC1 ((uint16_t) 0x0001)µTIM_DMA_ID_CC2 ((uint16_t) 0x0002)¶TIM_DMA_ID_CC3 ((uint16_t) 0x0003)·TIM_DMA_ID_CC4 ((uint16_t) 0x0004)¸TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)ÀTIM_CCx_ENABLE 0x00000001UÁTIM_CCx_DISABLE 0x00000000Uê__HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { (__HANDLE__)->State = HAL_TIM_STATE_RESET; (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; } while(0)ù__HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))__HAL_TIM_DISABLE(__HANDLE__) do { if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); } } while(0)__HAL_TIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))¢__HAL_TIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))°__HAL_TIM_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))¾__HAL_TIM_DISABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))Ð__HAL_TIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))â__HAL_TIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))ñ__HAL_TIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)__HAL_TIM_CLEAR_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))__HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))__HAL_TIM_SET_PRESCALER(__HANDLE__,__PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))__HAL_TIM_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)¨__HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0)³__HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)¿__HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0)Î__HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)â__HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0)÷__HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)    __HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))    __HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))«    __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))¼    __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))Ñ    __HAL_TIM_ENABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))æ    __HAL_TIM_DISABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))ô    __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
__HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
__HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0) 
__HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__,__CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))®
TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))¸
IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))»
IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_OR))Í
IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))Ï
IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))Õ
IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4))Ù
IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))Ü
IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))ß
IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW))â
IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))å
IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))é
IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC))í
IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8))ò
IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE))õ
IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12))ù
IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))û
IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || ((__CHANNEL__) == TIM_CHANNEL_ALL))IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU))IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU)IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))£IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))¨IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)ªIS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF))³IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))¶IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || ((__MODE__) == TIM_SLAVEMODE_RESET) || ((__MODE__) == TIM_SLAVEMODE_GATED) || ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))¼IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2))¿IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))ÆIS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_TI1F_ED) || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF))ÏIS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_NONE))ÕIS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))ÛIS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))àIS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)âIS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))åIS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))øIS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))úIS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)üIS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)þTIM_SET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__,__ICPSC__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))TIM_RESET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))TIM_RESET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))TIM_CHANNEL_STATE_GET(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] : (__HANDLE__)->ChannelState[3])TIM_CHANNEL_STATE_SET(__HANDLE__,__CHANNEL__,__CHANNEL_STATE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))¢TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__) do { (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); } while(0)¯ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.hstm32l0xx_hal_def.hstm32l0xx_hal_tim_ex.hÄ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*PrescalerY#CounterModeY#PeriodY#ClockDivisionY#AutoReloadPreloadY#PTIM_Base_InitTypeDef¾?*OCModeY#PulseY#OCPolarityY#OCFastModeY#PTIM_OC_InitTypeDefIR*¢OCModeY#PulseY#OCPolarityY#ICPolarityY#ICSelectionY#ICFilterY#PTIM_OnePulse_InitTypeDef¯j*ICPolarityY#ICSelectionY#ICPrescalerY#ICFilterY#PTIM_IC_InitTypeDefB|*ó$EncoderModeY#IC1PolarityY#IC1SelectionY#IC1PrescalerY#IC1FilterY#IC2PolarityY#IC2SelectionY#IC2PrescalerY#IC2FilterY# PTIM_Encoder_InitTypeDef±*ñClockSourceY#ClockPolarityY#ClockPrescalerY#ClockFilterY#PTIM_ClockConfigTypeDef¬*    ClearInputStateY#ClearInputSourceY#ClearInputPolarityY#ClearInputPrescalerY#ClearInputFilterY#PTIM_ClearInputConfigTypeDef¾*ú    MasterOutputTriggerY#MasterSlaveModeY#PTIM_MasterConfigTypeDef¿Î*SlaveModeY#InputTriggerY#TriggerPolarityY#TriggerPrescalerY#TriggerFilterY#PTIM_SlaveConfigTypeDefàªHAL_TIM_STATE_RESETHAL_TIM_STATE_READYHAL_TIM_STATE_BUSYHAL_TIM_STATE_TIMEOUTHAL_TIM_STATE_ERRORPHAL_TIM_StateTypeDef±ì¨ HAL_TIM_CHANNEL_STATE_RESETHAL_TIM_CHANNEL_STATE_READYHAL_TIM_CHANNEL_STATE_BUSYPHAL_TIM_ChannelStateTypeDefGö§HAL_DMA_BURST_STATE_RESETHAL_DMA_BURST_STATE_READYHAL_DMA_BURST_STATE_BUSYPHAL_TIM_DMABurstStateTypeDefÌãHAL_TIM_ACTIVE_CHANNEL_1HAL_TIM_ACTIVE_CHANNEL_2HAL_TIM_ACTIVE_CHANNEL_3HAL_TIM_ACTIVE_CHANNEL_4HAL_TIM_ACTIVE_CHANNEL_CLEAREDPHAL_TIM_ActiveChannelL*@Instance#Init-#Channelã#¹hdma0#Lock1#8State#9é£ChannelState`#:DMABurstState§#>""Pt*t¨t'PTIM_HandleTypeDef¹ëìíSTM32L0xx_HAL_UART_EX_H GUART_WORDLENGTH_7B USART_CR1_M1HUART_WORDLENGTH_8B 0x00000000UIUART_WORDLENGTH_9B USART_CR1_M0QUART_ADDRESS_DETECT_4B 0x00000000URUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART4) { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; } else if((__HANDLE__)->Instance == USART5) { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; } else if((__HANDLE__)->Instance == LPUART1) { switch(__HAL_RCC_GET_LPUART1_SOURCE()) { case RCC_LPUART1CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_LPUART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_LPUART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_LPUART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; } } while(0)ûUART_MASK_COMPUTATION(__HANDLE__) do { if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x01FFU ; } else { (__HANDLE__)->Mask = 0x00FFU ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x00FFU ; } else { (__HANDLE__)->Mask = 0x007FU ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x007FU ; } else { (__HANDLE__)->Mask = 0x003FU ; } } else { (__HANDLE__)->Mask = 0x0000U; } } while(0U)©IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || ((__LENGTH__) == UART_WORDLENGTH_8B) || ((__LENGTH__) == UART_WORDLENGTH_9B))²IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))tj ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.hstm32l0xx_hal_def.h
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*WakeUpEventY#AddressLengthI#Address:#PUART_WakeUpTypeDefÂ9ïðñSTM32L0xx_HAL_UART_H ÂHAL_UART_STATE_RESET 0x00000000UÄHAL_UART_STATE_READY 0x00000020UÆHAL_UART_STATE_BUSY 0x00000024UÈHAL_UART_STATE_BUSY_TX 0x00000021UÊHAL_UART_STATE_BUSY_RX 0x00000022UÌHAL_UART_STATE_BUSY_TX_RX 0x00000023UÏHAL_UART_STATE_TIMEOUT 0x000000A0UÑHAL_UART_STATE_ERROR 0x000000E0UÚHAL_UART_ERROR_NONE (0x00000000U)ÛHAL_UART_ERROR_PE (0x00000001U)ÜHAL_UART_ERROR_NE (0x00000002U)ÝHAL_UART_ERROR_FE (0x00000004U)ÞHAL_UART_ERROR_ORE (0x00000008U)ßHAL_UART_ERROR_DMA (0x00000010U)àHAL_UART_ERROR_RTO (0x00000020U)ìUART_STOPBITS_0_5 USART_CR2_STOP_0íUART_STOPBITS_1 0x00000000UîUART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)ïUART_STOPBITS_2 USART_CR2_STOP_1÷UART_PARITY_NONE 0x00000000UøUART_PARITY_EVEN USART_CR1_PCEùUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)UART_HWCONTROL_NONE 0x00000000UUART_HWCONTROL_RTS USART_CR3_RTSEUART_HWCONTROL_CTS USART_CR3_CTSEUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)UART_MODE_RX USART_CR1_REUART_MODE_TX USART_CR1_TEUART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)UART_STATE_DISABLE 0x00000000UUART_STATE_ENABLE USART_CR1_UEUART_OVERSAMPLING_16 0x00000000U UART_OVERSAMPLING_8 USART_CR1_OVER8¨UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U©UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT±UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U³UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0µUART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1·UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODEÀUART_RECEIVER_TIMEOUT_DISABLE 0x00000000UÁUART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOENÉUART_LIN_DISABLE 0x00000000UÊUART_LIN_ENABLE USART_CR2_LINENÒUART_LINBREAKDETECTLENGTH_10B 0x00000000UÓUART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDLÛUART_DMA_TX_DISABLE 0x00000000UÜUART_DMA_TX_ENABLE USART_CR3_DMATäUART_DMA_RX_DISABLE 0x00000000UåUART_DMA_RX_ENABLE USART_CR3_DMARíUART_HALF_DUPLEX_DISABLE 0x00000000UîUART_HALF_DUPLEX_ENABLE USART_CR3_HDSELöUART_WAKEUPMETHOD_IDLELINE 0x00000000U÷UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKEÿUART_AUTOBAUD_REQUEST USART_RQR_ABRRQUART_SENDBREAK_REQUEST USART_RQR_SBKRQUART_MUTE_MODE_REQUEST USART_RQR_MMRQUART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQUART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQUART_ADVFEATURE_NO_INIT 0x00000000UUART_ADVFEATURE_TXINVERT_INIT 0x00000001UUART_ADVFEATURE_RXINVERT_INIT 0x00000002UUART_ADVFEATURE_DATAINVERT_INIT 0x00000004UUART_ADVFEATURE_SWAP_INIT 0x00000008UUART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010UUART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020UUART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040UUART_ADVFEATURE_MSBFIRST_INIT 0x00000080UUART_ADVFEATURE_TXINV_DISABLE 0x00000000UUART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV¤UART_ADVFEATURE_RXINV_DISABLE 0x00000000U¥UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINVUART_ADVFEATURE_DATAINV_DISABLE 0x00000000U®UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV¶UART_ADVFEATURE_SWAP_DISABLE 0x00000000U·UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP¿UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000UÀUART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDISÈUART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000UÉUART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABRENÑUART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000UÒUART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDREÚUART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000UÜUART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRSTåUART_ADVFEATURE_STOPMODE_DISABLE 0x00000000UæUART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESMîUART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000UïUART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME÷UART_CR2_ADDRESS_LSB_POS 24UÿUART_WAKEUP_ON_ADDRESS 0x00000000UUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUSUART_DE_POLARITY_HIGH 0x00000000UUART_DE_POLARITY_LOW USART_CR3_DEPUART_CR1_DEAT_ADDRESS_LSB_POS 21UUART_CR1_DEDT_ADDRESS_LSB_POS 16U¥UART_IT_MASK 0x001FUHAL_UART_TIMEOUT_VALUE 0x1FFFFFFU·UART_FLAG_REACK USART_ISR_REACK¸UART_FLAG_TEACK USART_ISR_TEACK¹UART_FLAG_WUF USART_ISR_WUFºUART_FLAG_RWU USART_ISR_RWU»UART_FLAG_SBKF USART_ISR_SBKF¼UART_FLAG_CMF USART_ISR_CMF½UART_FLAG_BUSY USART_ISR_BUSY¾UART_FLAG_ABRF USART_ISR_ABRF¿UART_FLAG_ABRE USART_ISR_ABREÀUART_FLAG_RTOF USART_ISR_RTOFÁUART_FLAG_CTS USART_ISR_CTSÂUART_FLAG_CTSIF USART_ISR_CTSIFÃUART_FLAG_LBDF USART_ISR_LBDFÄUART_FLAG_TXE USART_ISR_TXEÅUART_FLAG_TC USART_ISR_TCÆUART_FLAG_RXNE USART_ISR_RXNEÇUART_FLAG_IDLE USART_ISR_IDLEÈUART_FLAG_ORE USART_ISR_OREÉUART_FLAG_NE USART_ISR_NEÊUART_FLAG_FE USART_ISR_FEËUART_FLAG_PE USART_ISR_PEâUART_IT_PE 0x0028UãUART_IT_TXE 0x0727UäUART_IT_TC 0x0626UåUART_IT_RXNE 0x0525UæUART_IT_IDLE 0x0424UçUART_IT_LBD 0x0846UèUART_IT_CTS 0x096AUéUART_IT_CM 0x112EUêUART_IT_WUF 0x1476UëUART_IT_RTO 0x0B3AUíUART_IT_ERR 0x0060UïUART_IT_ORE 0x0300UðUART_IT_NE 0x0200UñUART_IT_FE 0x0100UùUART_CLEAR_PEF USART_ICR_PECFúUART_CLEAR_FEF USART_ICR_FECFûUART_CLEAR_NEF USART_ICR_NCFüUART_CLEAR_OREF USART_ICR_ORECFýUART_CLEAR_IDLEF USART_ICR_IDLECFþUART_CLEAR_TCF USART_ICR_TCCFÿUART_CLEAR_LBDF USART_ICR_LBDCFUART_CLEAR_CTSF USART_ICR_CTSCFUART_CLEAR_CMF USART_ICR_CMCFUART_CLEAR_WUF USART_ICR_WUCFUART_CLEAR_RTOF USART_ICR_RTOCFHAL_UART_RECEPTION_STANDARD (0x00000000U)HAL_UART_RECEPTION_TOIDLE (0x00000001U)HAL_UART_RECEPTION_TORTO (0x00000002U)HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)HAL_UART_RXEVENT_TC (0x00000000U)HAL_UART_RXEVENT_HT (0x00000001U)HAL_UART_RXEVENT_IDLE (0x00000002U)²__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U)¼__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); } while(0U)Ó__HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))Ù__HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)ß__HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)å__HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)ë__HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)ñ__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))¡__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ( ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))¼__HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ( ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))×__HAL_UART_GET_IT(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)ë__HAL_UART_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)__HAL_UART_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))__HAL_UART_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))__HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)__HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)¤__HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)ª__HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)¹__HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) do{ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; } while(0U)Ì__HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) do{ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); } while(0U)ß__HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) do{ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; } while(0U)ò__HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) do{ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); } while(0U)    UART_DIV_LPUART(__PCLK__,__BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__))    UART_DIV_SAMPLING8(__PCLK__,__BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))    UART_DIV_SAMPLING16(__PCLK__,__BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))    UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))¡    IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)§    IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)    IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)´    IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || ((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_1_5) || ((__STOPBITS__) == UART_STOPBITS_2))¾    IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_2))Æ    IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || ((__PARITY__) == UART_PARITY_EVEN) || ((__PARITY__) == UART_PARITY_ODD))Ï    IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__) (((__CONTROL__) == UART_HWCONTROL_NONE) || ((__CONTROL__) == UART_HWCONTROL_RTS) || ((__CONTROL__) == UART_HWCONTROL_CTS) || ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))Ú    IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))á    IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || ((__STATE__) == UART_STATE_ENABLE))é    IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || ((__SAMPLING__) == UART_OVERSAMPLING_8))ñ    IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))ù    IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || ((__LIN__) == UART_LIN_ENABLE))
IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))¢
IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || ((__DMATX__) == UART_DMA_TX_ENABLE))ª
IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || ((__DMARX__) == UART_DMA_RX_ENABLE))²
IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))º
IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))Â
IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || ((__PARAM__) == UART_SENDBREAK_REQUEST) || ((__PARAM__) == UART_MUTE_MODE_REQUEST) || ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))Í
IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | UART_ADVFEATURE_TXINVERT_INIT | UART_ADVFEATURE_RXINVERT_INIT | UART_ADVFEATURE_DATAINVERT_INIT | UART_ADVFEATURE_SWAP_INIT | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | UART_ADVFEATURE_DMADISABLEONERROR_INIT | UART_ADVFEATURE_AUTOBAUDRATE_INIT | UART_ADVFEATURE_MSBFIRST_INIT))Ü
IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))ä
IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))ì
IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))ô
IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))ü
IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))¥IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))¶IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || ((__POLARITY__) == UART_DE_POLARITY_LOW))¿ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.hstm32l0xx_hal_def.hstm32l0xx_hal_uart_ex.h
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM*Û BaudRateY#WordLengthY#StopBitsY#ParityY#ModeY#HwFlowCtlY#OverSamplingY#OneBitSamplingY#PUART_InitTypeDef¿_*ã(AdvFeatureInitY#TxPinLevelInvertY#RxPinLevelInvertY#DataInvertY#SwapY#OverrunDisableY#DMADisableonRxErrorY#AutoBaudRateEnableY#AutoBaudRateModeY# MSBFirstY#$PUART_AdvFeatureInitTypeDefsPHAL_UART_StateTypeDefY±ÈUART_CLOCKSOURCE_PCLK1UART_CLOCKSOURCE_PCLK2UART_CLOCKSOURCE_HSIUART_CLOCKSOURCE_SYSCLKUART_CLOCKSOURCE_LSEUART_CLOCKSOURCE_UNDEFINEDPUART_ClockSourceTypeDef¦¾PHAL_UART_RxTypeTypeDefYÉPHAL_UART_RxEventTypeTypeDefYÔ)®
__UART_HandleTypeDefInstance.#Init[#AdvancedInitc#$pTxBuffPtr:#LTxXferSizeI#PTxXferCount>#RpRxBuffPtrD#TRxXferSizeI#XRxXferCount>#ZMaskI#\ReceptionTypeJ#`RxEventTypeN#dO©    %R"¡RxISR©#hOÂ    %R"ºTxISRÂ#lhdmatxV#phdmarxV#tLock1#xgState\#|RxState\#ErrorCode`#":"4tI":tht"¯"PttYPUART_HandleTypeDef¯óôõ__STM32L0xx_HAL_CONF_H &HAL_MODULE_ENABLED 'HAL_ADC_MODULE_ENABLED /HAL_IWDG_MODULE_ENABLED 1HAL_LPTIM_MODULE_ENABLED 4HAL_SPI_MODULE_ENABLED 5HAL_TIM_MODULE_ENABLED 7HAL_UART_MODULE_ENABLED >HAL_GPIO_MODULE_ENABLED ?HAL_EXTI_MODULE_ENABLED @HAL_DMA_MODULE_ENABLED AHAL_I2C_MODULE_ENABLED BHAL_RCC_MODULE_ENABLED CHAL_FLASH_MODULE_ENABLED DHAL_PWR_MODULE_ENABLED EHAL_CORTEX_MODULE_ENABLED NHSE_VALUE ((uint32_t)8000000U)RHSE_STARTUP_TIMEOUT ((uint32_t)100U)ZMSI_VALUE ((uint32_t)2097000U)cHSI_VALUE ((uint32_t)16000000U)jHSI48_VALUE ((uint32_t)48000000U)sLSI_VALUE ((uint32_t)37000U)|LSE_VALUE ((uint32_t)32768U)LSE_STARTUP_TIMEOUT ((uint32_t)5000U)VDD_VALUE ((uint32_t)3300U)TICK_INT_PRIORITY ((uint32_t)3U)USE_RTOS 0UPREFETCH_ENABLE 0UPREREAD_ENABLE 1UBUFFER_CACHE_DISABLE 0U¢USE_HAL_ADC_REGISTER_CALLBACKS 0U£USE_HAL_COMP_REGISTER_CALLBACKS 0U¤USE_HAL_DAC_REGISTER_CALLBACKS 0U¥USE_HAL_I2C_REGISTER_CALLBACKS 0U¦USE_HAL_I2S_REGISTER_CALLBACKS 0U§USE_HAL_IRDA_REGISTER_CALLBACKS 0U¨USE_HAL_LPTIM_REGISTER_CALLBACKS 0U©USE_HAL_PCD_REGISTER_CALLBACKS 0UªUSE_HAL_RNG_REGISTER_CALLBACKS 0U«USE_HAL_RTC_REGISTER_CALLBACKS 0U¬USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0UUSE_HAL_SMBUS_REGISTER_CALLBACKS 0U®USE_HAL_SPI_REGISTER_CALLBACKS 0U¯USE_HAL_TIM_REGISTER_CALLBACKS 0U°USE_HAL_TSC_REGISTER_CALLBACKS 0U±USE_HAL_UART_REGISTER_CALLBACKS 0U²USE_HAL_USART_REGISTER_CALLBACKS 0U³USE_HAL_WWDG_REGISTER_CALLBACKS 0U»¿ÃÇËÏçë    ó
ûÿ Áassert_param(expr) ((void)0U)´ª ../Core/Inc/../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf.hstm32l0xx_hal_rcc.hstm32l0xx_hal_exti.hstm32l0xx_hal_gpio.hstm32l0xx_hal_dma.hstm32l0xx_hal_cortex.hstm32l0xx_hal_adc.hstm32l0xx_hal_flash.hstm32l0xx_hal_i2c.hstm32l0xx_hal_iwdg.hstm32l0xx_hal_lptim.hstm32l0xx_hal_pwr.hstm32l0xx_hal_spi.hstm32l0xx_hal_tim.hstm32l0xx_hal_uart.h¨
../Core/Inc/stm32l0xx_hal_conf.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM÷øù>RMCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()SMCO1_GPIO_PORT GPIOATMCO1_PIN GPIO_PIN_8VMCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()WMCO2_GPIO_PORT GPIOAXMCO2_PIN GPIO_PIN_9[MCO3_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()\MCO3_GPIO_PORT GPIOB]MCO3_PIN GPIO_PIN_13 ../Drivers/STM32L0xx_HAL_Driver/Inc/../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cstm32l0xx_hal.hÔ
../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMtY"ö""Yû!/!I$>%%%%    %C
%C%% %%%C%C&I(( 1111 I8     I  I8    4! I8     "I#7I$I%I&I    'I(I)*+,-./404142434445.:;9?I6.:;9?7.:;9G8.:;9?I 9.:;9? :.:;9G ;.:;9?I<.:;9?=.:;9G>.:;9?I@?.:;9?@@.:;9G@A.:;9?I@
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K.1L.<4I?M.<4?NIOPI:;9QI4RSTUVW1X4I    ,Y4I    Z4I[4I,\4I]4I    4^4I    ,4_4I4`4I,4a4I4b41    ,c41d41,e41f1g1hI    iIjIkI    4lI    ,4mI4n1    o1p4I    ?q4I?<r4I,s4It5Iu;v=w%x<%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0+ --fpu=SoftVFP --output=l071\stm32l0xx_hal_rcc.o --vfemode=force
Input Comments:p2b1c-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0+ --fpu=SoftVFP --apcs=/interwork/interwork --no_divide stm32l0xx_hal_rcc.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c -ol071\stm32l0xx_hal_rcc.o --depend=l071\stm32l0xx_hal_rcc.d --cpu=Cortex-M0+ --apcs=interwork -O1 -Otime --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../APL -I../FML -I../HAL -I../Middlewares/HIDOLibrary/Include -I../decadriver -I../ExternalDevices -I../algorithm -I.\RTE\_L071 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32L0xx_DFP\2.2.0\Drivers\CMSIS\Device\ST\STM32L0xx\Include -D__MICROLIB -D__UVISION_VERSION=530 -D_RTE_ -DSTM32L071xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32L071xx --omf_browse=l071\stm32l0xx_hal_rcc.crf ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c4444ª4â4ª4Ê4ª44ª4:4ª44    ª4¶    4
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