/*
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******************************************************************************
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* @file lis3dh_reg.c
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* @author Sensors Software Solution Team
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* @brief LIS3DH driver file
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#include "lis3dh_reg.h"
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/**
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* @defgroup LIS3DH
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* @brief This file provides a set of functions needed to drive the
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* lis3dh enanced inertial module.
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* @{
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*
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*/
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/**
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* @defgroup LIS3DH_Interfaces_Functions
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* @brief This section provide a set of functions used to read and
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* write a generic register of the device.
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* MANDATORY: return 0 -> no Error.
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* @{
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*
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*/
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/**
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* @brief Read generic device register
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*
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* @param ctx read / write interface definitions(ptr)
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* @param reg register to read
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* @param data pointer to buffer that store the data read(ptr)
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* @param len number of consecutive register to read
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
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uint16_t len)
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{
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int32_t ret;
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ret = ctx->read_reg(ctx->handle, reg, data, len);
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return ret;
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}
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/**
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* @brief Write generic device register
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*
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* @param ctx read / write interface definitions(ptr)
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* @param reg register to write
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* @param data pointer to data to write in register reg(ptr)
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* @param len number of consecutive register to write
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data,
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uint16_t len)
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{
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int32_t ret;
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ret = ctx->write_reg(ctx->handle, reg, data, len);
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return ret;
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}
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/**
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* @}
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*
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*/
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/**
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* @defgroup LIS3DH_Sensitivity
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* @brief These functions convert raw-data into engineering units.
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* @{
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*
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*/
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float lis3dh_from_fs2_hr_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 16.0f ) * 1.0f;
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}
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float lis3dh_from_fs4_hr_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 16.0f ) * 2.0f;
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}
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float lis3dh_from_fs8_hr_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 16.0f ) * 4.0f;
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}
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float lis3dh_from_fs16_hr_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 16.0f ) * 12.0f;
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}
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float lis3dh_from_lsb_hr_to_celsius(int16_t lsb)
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{
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return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f;
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}
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float lis3dh_from_fs2_nm_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 64.0f ) * 4.0f;
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}
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float lis3dh_from_fs4_nm_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 64.0f ) * 8.0f;
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}
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float lis3dh_from_fs8_nm_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 64.0f ) * 16.0f;
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}
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float lis3dh_from_fs16_nm_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 64.0f ) * 48.0f;
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}
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float lis3dh_from_lsb_nm_to_celsius(int16_t lsb)
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{
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return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f;
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}
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float lis3dh_from_fs2_lp_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 256.0f ) * 16.0f;
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}
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float lis3dh_from_fs4_lp_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 256.0f ) * 32.0f;
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}
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float lis3dh_from_fs8_lp_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 256.0f ) * 64.0f;
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}
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float lis3dh_from_fs16_lp_to_mg(int16_t lsb)
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{
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return ( (float)lsb / 256.0f ) * 192.0f;
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}
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float lis3dh_from_lsb_lp_to_celsius(int16_t lsb)
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{
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return ( ( (float)lsb / 256.0f ) * 1.0f ) + 25.0f;
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}
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/**
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* @}
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*
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*/
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/**
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* @defgroup LIS3DH_Data_generation
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* @brief This section group all the functions concerning data generation.
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* @{
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*
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*/
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/**
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* @brief Temperature status register.[get]
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*
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* @param ctx read / write interface definitions
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* @param buff buffer that stores data read
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
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{
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX, buff, 1);
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return ret;
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}
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/**
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* @brief Temperature data available.[get]
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*
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* @param ctx read / write interface definitions
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* @param val change the values of tda in reg STATUS_REG_AUX
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
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{
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lis3dh_status_reg_aux_t status_reg_aux;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
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(uint8_t*)&status_reg_aux, 1);
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*val = status_reg_aux._3da;
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return ret;
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}
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/**
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* @brief Temperature data overrun.[get]
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*
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* @param ctx read / write interface definitions
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* @param val change the values of tor in reg STATUS_REG_AUX
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
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{
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lis3dh_status_reg_aux_t status_reg_aux;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
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(uint8_t*)&status_reg_aux, 1);
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*val = status_reg_aux._3or;
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return ret;
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}
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/**
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* @brief Temperature output value.[get]
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*
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* @param ctx read / write interface definitions
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* @param buff buffer that stores data read
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, uint16_t *buff)
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{
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int32_t ret;
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uint8_t dummy[2];
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ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC3_L, dummy, 2);
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*buff = dummy[1];
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*buff = *buff * 256;
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*buff += dummy[0];
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return ret;
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}
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/**
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* @brief ADC output value.[get]
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* Sample frequency: the same as the ODR CTRL_REG1
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* The resolution:
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* 10bit if LPen bit in CTRL_REG1 (20h) is clear
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* 8bit if LPen bit in CTRL_REG1 (20h) is set
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* Data Format:
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* Outputs are Left Justified in 2¡¯ complements
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* range 800mV
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* code zero means an analogue value of about 1.2V
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* Voltage values smaller than centre values are positive
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* (Example: 800mV = 7Fh / 127 dec)
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* Voltage values bigger than centre values are negative
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* (Example: 1600mV = 80h / -128 dec)
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*
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* @param ctx read / write interface definitions
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* @param buff buffer that stores data read
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
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{
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC1_L, buff, 6);
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return ret;
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}
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/**
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* @brief Auxiliary ADC.[set]
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*
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* @param ctx read / write interface definitions
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* @param val configure the auxiliary ADC
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val)
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{
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lis3dh_temp_cfg_reg_t temp_cfg_reg;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
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if (ret == 0) {
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if (val != LIS3DH_AUX_DISABLE){
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/* Required in order to use auxiliary adc */
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ret = lis3dh_block_data_update_set(ctx, PROPERTY_ENABLE);
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}
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}
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if (ret == 0) {
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temp_cfg_reg.temp_en = ( (uint8_t) val & 0x02U) >> 1;
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temp_cfg_reg.adc_pd = (uint8_t) val & 0x01U;
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ret = lis3dh_write_reg(ctx, LIS3DH_TEMP_CFG_REG,
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(uint8_t*)&temp_cfg_reg, 1);
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}
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return ret;
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}
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/**
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* @brief Auxiliary ADC.[get]
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*
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* @param ctx read / write interface definitions
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* @param val configure the auxiliary ADC
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val)
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{
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lis3dh_temp_cfg_reg_t temp_cfg_reg;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1);
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if ( ( temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd ) == PROPERTY_ENABLE ){
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*val = LIS3DH_AUX_ON_TEMPERATURE;
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}
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if ( ( temp_cfg_reg.temp_en == PROPERTY_DISABLE ) &&
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( temp_cfg_reg.adc_pd == PROPERTY_ENABLE ) ) {
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*val = LIS3DH_AUX_ON_PADS;
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} else {
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*val = LIS3DH_AUX_DISABLE;
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}
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return ret;
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}
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/**
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* @brief Operating mode selection.[set]
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*
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* @param ctx read / write interface definitions
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* @param val change the values of lpen in reg CTRL_REG1
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* and HR in reg CTRL_REG4
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, lis3dh_op_md_t val)
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{
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lis3dh_ctrl_reg1_t ctrl_reg1;
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lis3dh_ctrl_reg4_t ctrl_reg4;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1,
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(uint8_t*)&ctrl_reg1, 1);
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if (ret == 0) {
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4,
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(uint8_t*)&ctrl_reg4, 1);
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}
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if (ret == 0) {
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if ( val == LIS3DH_HR_12bit ) {
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ctrl_reg1.lpen = 0;
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ctrl_reg4.hr = 1;
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}
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if (val == LIS3DH_NM_10bit) {
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ctrl_reg1.lpen = 0;
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ctrl_reg4.hr = 0;
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}
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if (val == LIS3DH_LP_8bit) {
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ctrl_reg1.lpen = 1;
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ctrl_reg4.hr = 0;
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}
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ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
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}
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if (ret == 0) {
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ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
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}
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return ret;
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}
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/**
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* @brief Operating mode selection.[get]
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*
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* @param ctx read / write interface definitions
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* @param val change the values of lpen in reg CTRL_REG1
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx, lis3dh_op_md_t *val)
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{
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lis3dh_ctrl_reg1_t ctrl_reg1;
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lis3dh_ctrl_reg4_t ctrl_reg4;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
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if (ret == 0) {
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
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if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) {
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*val = LIS3DH_LP_8bit;
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} else if (ctrl_reg4.hr == PROPERTY_ENABLE ) {
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*val = LIS3DH_HR_12bit;
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} else {
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*val = LIS3DH_NM_10bit;
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}
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}
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return ret;
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}
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/**
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* @brief Output data rate selection.[set]
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*
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* @param ctx read / write interface definitions
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* @param val change the values of odr in reg CTRL_REG1
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val)
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{
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lis3dh_ctrl_reg1_t ctrl_reg1;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
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if (ret == 0) {
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ctrl_reg1.odr = (uint8_t)val;
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ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
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}
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return ret;
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}
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/**
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* @brief Output data rate selection.[get]
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*
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* @param ctx read / write interface definitions
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* @param val get the values of odr in reg CTRL_REG1
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* @retval interface status (MANDATORY: return 0 -> no Error)
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*
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*/
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int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val)
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{
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lis3dh_ctrl_reg1_t ctrl_reg1;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
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switch (ctrl_reg1.odr) {
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case LIS3DH_POWER_DOWN:
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*val = LIS3DH_POWER_DOWN;
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break;
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case LIS3DH_ODR_1Hz:
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*val = LIS3DH_ODR_1Hz;
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break;
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case LIS3DH_ODR_10Hz:
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*val = LIS3DH_ODR_10Hz;
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break;
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case LIS3DH_ODR_25Hz:
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*val = LIS3DH_ODR_25Hz;
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break;
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case LIS3DH_ODR_50Hz:
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*val = LIS3DH_ODR_50Hz;
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break;
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case LIS3DH_ODR_100Hz:
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*val = LIS3DH_ODR_100Hz;
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break;
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case LIS3DH_ODR_200Hz:
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*val = LIS3DH_ODR_200Hz;
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break;
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case LIS3DH_ODR_400Hz:
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*val = LIS3DH_ODR_400Hz;
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break;
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case LIS3DH_ODR_1kHz620_LP:
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*val = LIS3DH_ODR_1kHz620_LP;
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break;
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case LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP:
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*val = LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP;
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break;
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default:
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*val = LIS3DH_POWER_DOWN;
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break;
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}
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return ret;
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}
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/**
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* @brief High pass data from internal filter sent to output register
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* and FIFO.
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*
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* @param ctx read / write interface definitions
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* @param val change the values of fds in reg CTRL_REG2
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* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
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*/
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int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, uint8_t val)
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{
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lis3dh_ctrl_reg2_t ctrl_reg2;
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int32_t ret;
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
if (ret == 0) {
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ctrl_reg2.fds = val;
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ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
}
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return ret;
|
}
|
|
/**
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* @brief High pass data from internal filter sent to output register
|
* and FIFO.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fds in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
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lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
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ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
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*val = (uint8_t)ctrl_reg2.fds;
|
|
return ret;
|
}
|
|
/**
|
* @brief High-pass filter cutoff frequency selection.[set]
|
*
|
* HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
|
* AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
|
* STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
|
* MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
|
* LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of hpcf in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
|
lis3dh_hpcf_t val)
|
{
|
lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
if (ret == 0) {
|
ctrl_reg2.hpcf = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief High-pass filter cutoff frequency selection.[get]
|
*
|
* HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
|
* AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
|
* STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
|
* MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
|
* LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
|
*
|
* @param ctx read / write interface definitions
|
* @param val get the values of hpcf in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
|
lis3dh_hpcf_t *val)
|
{
|
lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
switch (ctrl_reg2.hpcf) {
|
case LIS3DH_AGGRESSIVE:
|
*val = LIS3DH_AGGRESSIVE;
|
break;
|
case LIS3DH_STRONG:
|
*val = LIS3DH_STRONG;
|
break;
|
case LIS3DH_MEDIUM:
|
*val = LIS3DH_MEDIUM;
|
break;
|
case LIS3DH_LIGHT:
|
*val = LIS3DH_LIGHT;
|
break;
|
default:
|
*val = LIS3DH_LIGHT;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief High-pass filter mode selection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of hpm in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val)
|
{
|
lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
if (ret == 0) {
|
ctrl_reg2.hpm = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief High-pass filter mode selection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val get the values of hpm in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, lis3dh_hpm_t *val)
|
{
|
lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
switch (ctrl_reg2.hpm) {
|
case LIS3DH_NORMAL_WITH_RST:
|
*val = LIS3DH_NORMAL_WITH_RST;
|
break;
|
case LIS3DH_REFERENCE_MODE:
|
*val = LIS3DH_REFERENCE_MODE;
|
break;
|
case LIS3DH_NORMAL:
|
*val = LIS3DH_NORMAL;
|
break;
|
case LIS3DH_AUTORST_ON_INT:
|
*val = LIS3DH_AUTORST_ON_INT;
|
break;
|
default:
|
*val = LIS3DH_NORMAL_WITH_RST;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Full-scale configuration.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fs in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
if (ret == 0) {
|
ctrl_reg4.fs = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Full-scale configuration.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val get the values of fs in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
switch (ctrl_reg4.fs) {
|
case LIS3DH_2g:
|
*val = LIS3DH_2g;
|
break;
|
case LIS3DH_4g:
|
*val = LIS3DH_4g;
|
break;
|
case LIS3DH_8g:
|
*val = LIS3DH_8g;
|
break;
|
case LIS3DH_16g:
|
*val = LIS3DH_16g;
|
break;
|
default:
|
*val = LIS3DH_2g;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Block Data Update.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of bdu in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
if (ret == 0) {
|
ctrl_reg4.bdu = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Block Data Update.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of bdu in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
*val = (uint8_t)ctrl_reg4.bdu;
|
|
return ret;
|
}
|
|
/**
|
* @brief Reference value for interrupt generation.[set]
|
* LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param buff buffer that contains data to write
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
|
{
|
int32_t ret;
|
ret = lis3dh_write_reg(ctx, LIS3DH_REFERENCE, buff, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Reference value for interrupt generation.[get]
|
* LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param buff buffer that stores data read
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_REFERENCE, buff, 1);
|
return ret;
|
}
|
/**
|
* @brief Acceleration set of data available.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of zyxda in reg STATUS_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_status_reg_t status_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t*)&status_reg, 1);
|
*val = status_reg.zyxda;
|
|
return ret;
|
}
|
/**
|
* @brief Acceleration set of data overrun.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of zyxor in reg STATUS_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_status_reg_t status_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t*)&status_reg, 1);
|
*val = status_reg.zyxor;
|
|
return ret;
|
}
|
/**
|
* @brief Acceleration output value.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param buff buffer that stores data read
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_OUT_X_L, buff, 6);
|
return ret;
|
}
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Common
|
* @brief This section group common usefull functions
|
* @{
|
*
|
*/
|
|
/**
|
* @brief DeviceWhoamI .[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param buff buffer that stores data read
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_WHO_AM_I, buff, 1);
|
return ret;
|
}
|
/**
|
* @brief Self Test.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of st in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
if (ret == 0) {
|
ctrl_reg4.st = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Self Test.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of st in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
switch (ctrl_reg4.st) {
|
case LIS3DH_ST_DISABLE:
|
*val = LIS3DH_ST_DISABLE;
|
break;
|
case LIS3DH_ST_POSITIVE:
|
*val = LIS3DH_ST_POSITIVE;
|
break;
|
case LIS3DH_ST_NEGATIVE:
|
*val = LIS3DH_ST_NEGATIVE;
|
break;
|
default:
|
*val = LIS3DH_ST_DISABLE;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Big/Little Endian data selection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ble in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
if (ret == 0) {
|
ctrl_reg4.ble = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Big/Little Endian data selection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val get the values of ble in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
switch (ctrl_reg4.ble) {
|
case LIS3DH_LSB_AT_LOW_ADD:
|
*val = LIS3DH_LSB_AT_LOW_ADD;
|
break;
|
case LIS3DH_MSB_AT_LOW_ADD:
|
*val = LIS3DH_MSB_AT_LOW_ADD;
|
break;
|
default:
|
*val = LIS3DH_LSB_AT_LOW_ADD;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Reboot memory content. Reload the calibration parameters.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of boot in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
if (ret == 0) {
|
ctrl_reg5.boot = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Reboot memory content. Reload the calibration parameters.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of boot in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
*val = (uint8_t)ctrl_reg5.boot;
|
|
return ret;
|
}
|
|
/**
|
* @brief Info about device status.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val register STATUS_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Interrupts_generator_1
|
* @brief This section group all the functions that manage the first
|
* interrupts generator
|
* @{
|
*
|
*/
|
|
/**
|
* @brief Interrupt generator 1 configuration register.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val register INT1_CFG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
|
lis3dh_int1_cfg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_write_reg(ctx, LIS3DH_INT1_CFG, (uint8_t*) val, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Interrupt generator 1 configuration register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val register INT1_CFG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
|
lis3dh_int1_cfg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT1_CFG, (uint8_t*) val, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Interrupt generator 1 source register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Registers INT1_SRC
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx,
|
lis3dh_int1_src_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT1_SRC, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief User-defined threshold value for xl interrupt event on
|
* generator 1.[set]
|
* LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ths in reg INT1_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_int1_ths_t int1_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t*)&int1_ths, 1);
|
if (ret == 0) {
|
int1_ths.ths = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_INT1_THS, (uint8_t*)&int1_ths, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief User-defined threshold value for xl interrupt event on
|
* generator 1.[get]
|
* LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ths in reg INT1_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_int1_ths_t int1_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t*)&int1_ths, 1);
|
*val = (uint8_t)int1_ths.ths;
|
|
return ret;
|
}
|
|
/**
|
* @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
|
* recognized.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d in reg INT1_DURATION
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_int1_duration_t int1_duration;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t*)&int1_duration, 1);
|
if (ret == 0) {
|
int1_duration.d = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t*)&int1_duration, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
|
* recognized.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d in reg INT1_DURATION
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_int1_duration_t int1_duration;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t*)&int1_duration, 1);
|
*val = (uint8_t)int1_duration.d;
|
|
return ret;
|
}
|
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Interrupts_generator_2
|
* @brief This section group all the functions that manage the second
|
* interrupts generator
|
* @{
|
*
|
*/
|
|
/**
|
* @brief Interrupt generator 2 configuration register.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers INT2_CFG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
|
lis3dh_int2_cfg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_write_reg(ctx, LIS3DH_INT2_CFG, (uint8_t*) val, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Interrupt generator 2 configuration register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers INT2_CFG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
|
lis3dh_int2_cfg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT2_CFG, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief Interrupt generator 2 source register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers INT2_SRC
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx,
|
lis3dh_int2_src_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT2_SRC, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief User-defined threshold value for xl interrupt event on
|
* generator 2.[set]
|
* LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ths in reg INT2_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_int2_ths_t int2_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t*)&int2_ths, 1);
|
if (ret == 0) {
|
int2_ths.ths = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_INT2_THS, (uint8_t*)&int2_ths, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief User-defined threshold value for xl interrupt event on
|
* generator 2.[get]
|
* LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ths in reg INT2_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_int2_ths_t int2_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t*)&int2_ths, 1);
|
*val = (uint8_t)int2_ths.ths;
|
|
return ret;
|
}
|
|
/**
|
* @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
|
* recognized .[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d in reg INT2_DURATION
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_int2_duration_t int2_duration;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t*)&int2_duration, 1);
|
if (ret == 0) {
|
int2_duration.d = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t*)&int2_duration, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
|
* recognized.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d in reg INT2_DURATION
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_int2_duration_t int2_duration;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t*)&int2_duration, 1);
|
*val = (uint8_t)int2_duration.d;
|
|
return ret;
|
}
|
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Interrupt_pins
|
* @brief This section group all the functions that manage interrup pins
|
* @{
|
*
|
*/
|
|
/**
|
* @brief High-pass filter on interrupts/tap generator.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of hp in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
|
lis3dh_hp_t val)
|
{
|
lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
if (ret == 0) {
|
ctrl_reg2.hp = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief High-pass filter on interrupts/tap generator.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of hp in reg CTRL_REG2
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
|
lis3dh_hp_t *val)
|
{
|
lis3dh_ctrl_reg2_t ctrl_reg2;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
|
switch (ctrl_reg2.hp) {
|
case LIS3DH_DISC_FROM_INT_GENERATOR:
|
*val = LIS3DH_DISC_FROM_INT_GENERATOR;
|
break;
|
case LIS3DH_ON_INT1_GEN:
|
*val = LIS3DH_ON_INT1_GEN;
|
break;
|
case LIS3DH_ON_INT2_GEN:
|
*val = LIS3DH_ON_INT2_GEN;
|
break;
|
case LIS3DH_ON_TAP_GEN:
|
*val = LIS3DH_ON_TAP_GEN;
|
break;
|
case LIS3DH_ON_INT1_INT2_GEN:
|
*val = LIS3DH_ON_INT1_INT2_GEN;
|
break;
|
case LIS3DH_ON_INT1_TAP_GEN:
|
*val = LIS3DH_ON_INT1_TAP_GEN;
|
break;
|
case LIS3DH_ON_INT2_TAP_GEN:
|
*val = LIS3DH_ON_INT2_TAP_GEN;
|
break;
|
case LIS3DH_ON_INT1_INT2_TAP_GEN:
|
*val = LIS3DH_ON_INT1_INT2_TAP_GEN;
|
break;
|
default:
|
*val = LIS3DH_DISC_FROM_INT_GENERATOR;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Int1 pin routing configuration register.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CTRL_REG3
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg3_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t*) val, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Int1 pin routing configuration register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CTRL_REG3
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg3_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
|
* on INT2 pin when 6D bit on
|
* INT2_CFG (34h) is set to 1.
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d4d_int2 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
if (ret == 0) {
|
ctrl_reg5.d4d_int2 = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
|
* INT2_CFG (34h) is set to 1.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d4d_int2 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
*val = (uint8_t)ctrl_reg5.d4d_int2;
|
|
return ret;
|
}
|
|
/**
|
* @brief Latch interrupt request on INT2_SRC (35h) register, with
|
* INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
|
* itself.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of lir_int2 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_lir_int2_t val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
if (ret == 0) {
|
ctrl_reg5.lir_int2 = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Latch interrupt request on INT2_SRC (35h) register, with
|
* INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
|
* itself.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of lir_int2 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_lir_int2_t *val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
switch (ctrl_reg5.lir_int2) {
|
case LIS3DH_INT2_PULSED:
|
*val = LIS3DH_INT2_PULSED;
|
break;
|
case LIS3DH_INT2_LATCHED:
|
*val = LIS3DH_INT2_LATCHED;
|
break;
|
default:
|
*val = LIS3DH_INT2_PULSED;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
|
* on INT1_CFG(30h) is set to 1.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d4d_int1 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
if (ret == 0) {
|
ctrl_reg5.d4d_int1 = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
|
* INT1_CFG(30h) is set to 1.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of d4d_int1 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
*val = (uint8_t)ctrl_reg5.d4d_int1;
|
|
return ret;
|
}
|
|
/**
|
* @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
|
* register cleared by reading INT1_SRC (31h) itself.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of lir_int1 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_lir_int1_t val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
if (ret == 0) {
|
ctrl_reg5.lir_int1 = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
|
* register cleared by reading INT1_SRC (31h) itself.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of lir_int1 in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_lir_int1_t *val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
switch (ctrl_reg5.lir_int1) {
|
case LIS3DH_INT1_PULSED:
|
*val = LIS3DH_INT1_PULSED;
|
break;
|
case LIS3DH_INT1_LATCHED:
|
*val = LIS3DH_INT1_LATCHED;
|
break;
|
default:
|
*val = LIS3DH_INT1_PULSED;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Int2 pin routing configuration register.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CTRL_REG6
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg6_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t*) val, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Int2 pin routing configuration register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CTRL_REG6
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx,
|
lis3dh_ctrl_reg6_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Fifo
|
* @brief This section group all the functions concerning the fifo usage
|
* @{
|
*
|
*/
|
|
/**
|
* @brief FIFO enable.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fifo_en in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
if (ret == 0) {
|
ctrl_reg5.fifo_en = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief FIFO enable.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fifo_en in reg CTRL_REG5
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_ctrl_reg5_t ctrl_reg5;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);
|
*val = (uint8_t)ctrl_reg5.fifo_en;
|
|
return ret;
|
}
|
|
/**
|
* @brief FIFO watermark level selection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fth in reg FIFO_CTRL_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
if (ret == 0) {
|
fifo_ctrl_reg.fth = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief FIFO watermark level selection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fth in reg FIFO_CTRL_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
*val = (uint8_t)fifo_ctrl_reg.fth;
|
|
return ret;
|
}
|
|
/**
|
* @brief Trigger FIFO selection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tr in reg FIFO_CTRL_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
|
lis3dh_tr_t val)
|
{
|
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
if (ret == 0) {
|
fifo_ctrl_reg.tr = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Trigger FIFO selection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of tr in reg FIFO_CTRL_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
|
lis3dh_tr_t *val)
|
{
|
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
switch (fifo_ctrl_reg.tr) {
|
case LIS3DH_INT1_GEN:
|
*val = LIS3DH_INT1_GEN;
|
break;
|
case LIS3DH_INT2_GEN:
|
*val = LIS3DH_INT2_GEN;
|
break;
|
default:
|
*val = LIS3DH_INT1_GEN;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief FIFO mode selection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fm in reg FIFO_CTRL_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val)
|
{
|
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
if (ret == 0) {
|
fifo_ctrl_reg.fm = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief FIFO mode selection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of fm in reg FIFO_CTRL_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val)
|
{
|
lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1);
|
switch (fifo_ctrl_reg.fm) {
|
case LIS3DH_BYPASS_MODE:
|
*val = LIS3DH_BYPASS_MODE;
|
break;
|
case LIS3DH_FIFO_MODE:
|
*val = LIS3DH_FIFO_MODE;
|
break;
|
case LIS3DH_DYNAMIC_STREAM_MODE:
|
*val = LIS3DH_DYNAMIC_STREAM_MODE;
|
break;
|
case LIS3DH_STREAM_TO_FIFO_MODE:
|
*val = LIS3DH_STREAM_TO_FIFO_MODE;
|
break;
|
default:
|
*val = LIS3DH_BYPASS_MODE;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief FIFO status register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers FIFO_SRC_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx,
|
lis3dh_fifo_src_reg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief FIFO stored data level.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of fss in reg FIFO_SRC_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_fifo_src_reg_t fifo_src_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
|
*val = (uint8_t)fifo_src_reg.fss;
|
|
return ret;
|
}
|
/**
|
* @brief Empty FIFO status flag.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of empty in reg FIFO_SRC_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_fifo_src_reg_t fifo_src_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
|
*val = (uint8_t)fifo_src_reg.empty;
|
|
return ret;
|
}
|
/**
|
* @brief FIFO overrun status flag.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_fifo_src_reg_t fifo_src_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
|
*val = (uint8_t)fifo_src_reg.ovrn_fifo;
|
|
return ret;
|
}
|
/**
|
* @brief FIFO watermark status.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of wtm in reg FIFO_SRC_REG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_fifo_src_reg_t fifo_src_reg;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1);
|
*val = (uint8_t)fifo_src_reg.wtm;
|
|
return ret;
|
}
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Tap_generator
|
* @brief This section group all the functions that manage the tap and
|
* double tap event generation
|
* @{
|
*
|
*/
|
|
/**
|
* @brief Tap/Double Tap generator configuration register.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CLICK_CFG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t*) val, 1);
|
return ret;
|
}
|
|
/**
|
* @brief Tap/Double Tap generator configuration register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CLICK_CFG
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief Tap/Double Tap generator source register.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val registers CLICK_SRC
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx, lis3dh_click_src_t *val)
|
{
|
int32_t ret;
|
ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_SRC, (uint8_t*) val, 1);
|
return ret;
|
}
|
/**
|
* @brief User-defined threshold value for Tap/Double Tap event.[set]
|
* 1 LSB = full scale/128
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ths in reg CLICK_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_click_ths_t click_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
|
if (ret == 0) {
|
click_ths.ths = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief User-defined threshold value for Tap/Double Tap event.[get]
|
* 1 LSB = full scale/128
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of ths in reg CLICK_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_click_ths_t click_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
|
*val = (uint8_t)click_ths.ths;
|
|
return ret;
|
}
|
|
/**
|
* @brief If the LIR_Click bit is not set, the interrupt is kept high
|
* for the duration of the latency window.
|
* If the LIR_Click bit is set, the interrupt is kept high until the
|
* CLICK_SRC(39h) register is read.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of lir_click in reg CLICK_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_lir_click_t val)
|
{
|
lis3dh_click_ths_t click_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
|
if (ret == 0) {
|
click_ths.lir_click = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief If the LIR_Click bit is not set, the interrupt is kept high
|
* for the duration of the latency window.
|
* If the LIR_Click bit is set, the interrupt is kept high until the
|
* CLICK_SRC(39h) register is read.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of lir_click in reg CLICK_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_lir_click_t *val)
|
{
|
lis3dh_click_ths_t click_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t*)&click_ths, 1);
|
switch (click_ths.lir_click) {
|
case LIS3DH_TAP_PULSED:
|
*val = LIS3DH_TAP_PULSED;
|
break;
|
case LIS3DH_TAP_LATCHED:
|
*val = LIS3DH_TAP_LATCHED;
|
break;
|
default:
|
*val = LIS3DH_TAP_PULSED;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
|
* between the start of the click-detection procedure and when the
|
* acceleration falls back below the threshold.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tli in reg TIME_LIMIT
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_time_limit_t time_limit;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
|
if (ret == 0) {
|
time_limit.tli = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
|
* the start of the click-detection procedure and when the
|
* acceleration falls back below the threshold.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tli in reg TIME_LIMIT
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_time_limit_t time_limit;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t*)&time_limit, 1);
|
*val = (uint8_t)time_limit.tli;
|
|
return ret;
|
}
|
|
/**
|
* @brief The time (1 LSB = 1/ODR) interval that starts after the first
|
* click detection where the click-detection procedure is
|
* disabled, in cases where the device is configured for
|
* double-click detection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tla in reg TIME_LATENCY
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_time_latency_t time_latency;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
|
if (ret == 0) {
|
time_latency.tla = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief The time (1 LSB = 1/ODR) interval that starts after the first
|
* click detection where the click-detection procedure is
|
* disabled, in cases where the device is configured for
|
* double-click detection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tla in reg TIME_LATENCY
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_time_latency_t time_latency;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t*)&time_latency, 1);
|
*val = (uint8_t)time_latency.tla;
|
|
return ret;
|
}
|
|
/**
|
* @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
|
* after the end of the latency interval in which the click-detection
|
* procedure can start, in cases where the device is configured
|
* for double-click detection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tw in reg TIME_WINDOW
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_time_window_t time_window;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
|
if (ret == 0) {
|
time_window.tw = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
|
* after the end of the latency interval in which the
|
* click-detection procedure can start, in cases where the device
|
* is configured for double-click detection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of tw in reg TIME_WINDOW
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_time_window_t time_window;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t*)&time_window, 1);
|
*val = (uint8_t)time_window.tw;
|
|
return ret;
|
}
|
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Activity_inactivity
|
* @brief This section group all the functions concerning activity
|
* inactivity functionality
|
* @{
|
*
|
*/
|
|
/**
|
* @brief Sleep-to-wake, return-to-sleep activation threshold in
|
* low-power mode.[set]
|
* 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of acth in reg ACT_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_act_ths_t act_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t*)&act_ths, 1);
|
if (ret == 0) {
|
act_ths.acth = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_ACT_THS, (uint8_t*)&act_ths, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
|
* mode.[get]
|
* 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of acth in reg ACT_THS
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_act_ths_t act_ths;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t*)&act_ths, 1);
|
*val = (uint8_t)act_ths.acth;
|
|
return ret;
|
}
|
|
/**
|
* @brief Sleep-to-wake, return-to-sleep.[set]
|
* duration = (8*1[LSb]+1)/ODR
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of actd in reg ACT_DUR
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
|
{
|
lis3dh_act_dur_t act_dur;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t*)&act_dur, 1);
|
if (ret == 0) {
|
act_dur.actd = val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_ACT_DUR, (uint8_t*)&act_dur, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Sleep-to-wake, return-to-sleep.[get]
|
* duration = (8*1[LSb]+1)/ODR
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of actd in reg ACT_DUR
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
|
{
|
lis3dh_act_dur_t act_dur;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t*)&act_dur, 1);
|
*val = (uint8_t)act_dur.actd;
|
|
return ret;
|
}
|
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @defgroup LIS3DH_Serial_interface
|
* @brief This section group all the functions concerning serial
|
* interface management
|
* @{
|
*
|
*/
|
|
/**
|
* @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of sdo_pu_disc in reg CTRL_REG0
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
|
lis3dh_sdo_pu_disc_t val)
|
{
|
lis3dh_ctrl_reg0_t ctrl_reg0;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
|
if (ret == 0) {
|
ctrl_reg0.sdo_pu_disc = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of sdo_pu_disc in reg CTRL_REG0
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
|
lis3dh_sdo_pu_disc_t *val)
|
{
|
lis3dh_ctrl_reg0_t ctrl_reg0;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1);
|
switch (ctrl_reg0.sdo_pu_disc) {
|
case LIS3DH_PULL_UP_DISCONNECT:
|
*val = LIS3DH_PULL_UP_DISCONNECT;
|
break;
|
case LIS3DH_PULL_UP_CONNECT:
|
*val = LIS3DH_PULL_UP_CONNECT;
|
break;
|
default:
|
*val = LIS3DH_PULL_UP_DISCONNECT;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @brief SPI Serial Interface Mode selection.[set]
|
*
|
* @param ctx read / write interface definitions
|
* @param val change the values of sim in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
if (ret == 0) {
|
ctrl_reg4.sim = (uint8_t)val;
|
ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
}
|
return ret;
|
}
|
|
/**
|
* @brief SPI Serial Interface Mode selection.[get]
|
*
|
* @param ctx read / write interface definitions
|
* @param val Get the values of sim in reg CTRL_REG4
|
* @retval interface status (MANDATORY: return 0 -> no Error)
|
*
|
*/
|
int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val)
|
{
|
lis3dh_ctrl_reg4_t ctrl_reg4;
|
int32_t ret;
|
|
ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1);
|
switch (ctrl_reg4.sim) {
|
case LIS3DH_SPI_4_WIRE:
|
*val = LIS3DH_SPI_4_WIRE;
|
break;
|
case LIS3DH_SPI_3_WIRE:
|
*val = LIS3DH_SPI_3_WIRE;
|
break;
|
default:
|
*val = LIS3DH_SPI_4_WIRE;
|
break;
|
}
|
return ret;
|
}
|
|
/**
|
* @}
|
*
|
*/
|
|
/**
|
* @}
|
*
|
*/
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
