XRange_Tag.git - Gitblit

ELF(ä 4(@=Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c -ol071\deca_params_init.o --depend=l071\deca_params_init.d --cpu=Cortex-M0+ --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../APL -I../FML -I../HAL -I../Middlewares/HIDOLibrary/Include -I../decadriver -I../ExternalDevices -I../algorithm -I.\RTE\_L071 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32L0xx_DFP\2.2.0\Drivers\CMSIS\Device\ST\STM32L0xx\Include -D__MICROLIB -D__UVISION_VERSION=530 -D_RTE_ -DSTM32L071xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32L071xx --omf_browse=l071\deca_params_init.crf ..\decadriver\deca_params_init.c@\ \Àl\à?à}©%p
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..\decadriver\deca_params_init.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM..\decadriver\deca_params_init.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMpchan_idxptx_config¼ppll2_configÐprx_configÙpagc_configäpdwnsSFDlenêpsftshpdtune1 pdigital_bb_configplde_replicaCoeff(@7 ..\decadriver\deca_params_init.c__DATE__ "Sep  8 2023"__TIME__ "17:39:51"__STDC__ 1__STDC_VERSION__ 199901L__STDC_HOSTED__ 1__STDC_ISO_10646__ 200607__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060750__TARGET_CPU_CORTEX_M0_ 1__TARGET_FPU_SOFTVFP 1__TARGET_FPU_SOFTVFP 1__MICROLIB 1__UVISION_VERSION 530_RTE_ 1STM32L071xx 1_RTE_ 1USE_HAL_DRIVER 1STM32L071xx 1__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_6S_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 3__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_DMB 1__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0__APCS_INTERWORK 1__thumb 1__thumb__ 1__t32__ 1__OPTIMISE_SPACE 1__OPT_SMALL_ASSERT 1__OPTIMISE_LEVEL 3__SOFTFP__ 1¥chan_idxµtx_configÌpll2_configårx_configüagc_configdwnsSFDlen,sftsh?dtune1Sdigital_bb_configrlde_replicaCoeffÀC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t5-__va_listP__va_list½F*þ__state1#__state2#)±__fpos_t_struct__pos#__mbstateÙ#Pfpos_tþa-__FILEPFILE?lq__stdinGq__stdoutGq__stderrG"Gq__aeabi_stdinq__aeabi_stdoutq__aeabi_stderrLC C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h__stdio_h __ARMCLIB_VERSION 5060037"_ARMABI __declspec(__nothrow)%__STDIO_DECLS '__CLIBNS-__CLIBNS <NULL=NULL 0g_SYS_OPEN 16¥stdin (&__CLIBNS __stdin)§stdout (&__CLIBNS __stdout)©stderr (&__CLIBNS __stderr)¬_IOFBF 0x100_IOLBF 0x200®_IONBF 0x400±BUFSIZ (512)³FOPEN_MAX _SYS_OPEN¹FILENAME_MAX 256¾L_tmpnam FILENAME_MAXÄTMP_MAX 256ÌEOF (-1)ÒSEEK_SET 0ÓSEEK_CUR 1ÔSEEK_END 2Ú_IOBIN 0x04Ü__STDIN_BUFSIZ (64)Ý__STDOUT_BUFSIZ (64)Þ__STDERR_BUFSIZ (16)¿getchar() getc(stdin)àputchar(c) putc(c, stdout)lÄS__stdina__stdoutp__stderr__aeabi_stdin__aeabi_stdout¬__aeabi_stderrÀC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned shortintlonglong longuvoidcharunsigned intPwchar_tP)div_tquot#rem#Pdiv_tå\))·ldiv_tquot£#rem£#Pldiv_t^/)élldiv_tquot«#rem«#Plldiv_tEa2)_rand_stateä8__x#)È_ANSI_rand_state¼__x³#NØ%Ø%àV"¸¾"Ü"ÈP__heapprtäò)£__sdiv32by16quot#rem#P__sdiv32by16úÿ0)á__udiv32by16quotÆ#remÆ#P__udiv32by1689)__sdiv64by32rem#quot#P__sdiv64by32v0Psize_tÆ5XO C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hstdio.h__stdlib_h __ARMCLIB_VERSION 5060037__LONGLONG long long_ARMABI __declspec(__nothrow)_ARMABI_PURE __declspec(__nothrow) __attribute__((const))_ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)_ARMABI_THROW !__STDLIB_DECLS )__USE_C99_STDLIB 1-__CLIBNS4__CLIBNS GNULLHNULL 0mEXIT_FAILURE 1oEXIT_SUCCESS 0RAND_MAX 0x7fffffffMB_CUR_MAX ( __aeabi_MB_CUR_MAX() )¨__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE ¥__fpsr_IXE 0x100000¦__fpsr_UFE 0x80000§__fpsr_OFE 0x40000¨__fpsr_DZE 0x20000©__fpsr_IOE 0x10000«__fpsr_IXC 0x10¬__fpsr_UFC 0x8__fpsr_OFC 0x4®__fpsr_DZC 0x2¯__fpsr_IOC 0x1ý__LONGLONG 
..\decadriver\deca_regs.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARM<1 ..\decadriver\deca_regs.h_DECA_REGS_H_ DEV_ID_ID 0x00DEV_ID_LEN (4)DEV_ID_REV_MASK 0x0000000FULDEV_ID_VER_MASK 0x000000F0ULDEV_ID_MODEL_MASK 0x0000FF00ULDEV_ID_RIDTAG_MASK 0xFFFF0000UL#EUI_64_ID 0x01$EUI_64_LEN (8))PANADR_ID 0x03*PANADR_LEN (4),PANADR_SHORT_ADDR_MASK 0x0000FFFFUL-PANADR_PAN_ID_MASK 0xFFFF00F0UL2REG_05_ID_RESERVED 0x057SYS_CFG_ID 0x048SYS_CFG_LEN (4):SYS_CFG_MASK 0xF047FFFFUL;SYS_CFG_FF_ALL_EN 0x000001FEUL=SYS_CFG_FFE 0x00000001UL>SYS_CFG_FFBC 0x00000002UL?SYS_CFG_FFAB 0x00000004UL@SYS_CFG_FFAD 0x00000008ULASYS_CFG_FFAA 0x00000010ULBSYS_CFG_FFAM 0x00000020ULCSYS_CFG_FFAR 0x00000040ULDSYS_CFG_FFA4 0x00000080ULFSYS_CFG_FFA5 0x00000100ULGSYS_CFG_HIRQ_POL 0x00000200ULHSYS_CFG_SPI_EDGE 0x00000400ULISYS_CFG_DIS_FCE 0x00000800ULJSYS_CFG_DIS_DRXB 0x00001000ULKSYS_CFG_DIS_PHE 0x00002000ULLSYS_CFG_DIS_RSDE 0x00004000ULMSYS_CFG_FCS_INIT2F 0x00008000ULOSYS_CFG_PHR_MODE_00 0x00000000ULPSYS_CFG_PHR_MODE_11 0x00030000ULQSYS_CFG_DIS_STXP 0x00040000ULRSYS_CFG_RXM110K 0x00400000ULTSYS_CFG_RXWTOE 0x10000000ULUSYS_CFG_RXAUTR 0x20000000ULVSYS_CFG_AUTOACK 0x40000000ULWSYS_CFG_AACKPEND 0x80000000UL]SYS_TIME_ID 0x06^SYS_TIME_LEN (5)dREG_07_ID_RESERVED 0x07iTX_FCTRL_ID 0x08jTX_FCTRL_LEN (5)lTX_FCTRL_TFLEN_MASK 0x0000007FULmTX_FCTRL_TFLE_MASK 0x00000380ULnTX_FCTRL_FLE_MASK 0x000003FFULoTX_FCTRL_TXBR_MASK 0x00006000ULpTX_FCTRL_TXPRF_MASK 0x00030000ULqTX_FCTRL_TXPSR_MASK 0x000C0000ULrTX_FCTRL_PE_MASK 0x00300000ULsTX_FCTRL_TXPSR_PE_MASK 0x003C0000ULtTX_FCTRL_SAFE_MASK_32 0xFFFFE3FFULwTX_FCTRL_TXBR_110k 0x00000000ULxTX_FCTRL_TXBR_850k 0x00002000ULyTX_FCTRL_TXBR_6M 0x00004000ULzTX_FCTRL_TXBR_SHFT (13){TX_FCTRL_TR 0x00008000UL|TX_FCTRL_TR_SHFT (15)~TX_FCTRL_TXPRF_SHFT (16)TX_FCTRL_TXPRF_4M 0x00000000ULTX_FCTRL_TXPRF_16M 0x00010000ULTX_FCTRL_TXPRF_64M 0x00020000ULTX_FCTRL_TXPSR_SHFT (18)TX_FCTRL_PE_SHFT (20)TX_FCTRL_TXPSR_PE_16 0x00000000ULTX_FCTRL_TXPSR_PE_64 0x00040000ULTX_FCTRL_TXPSR_PE_128 0x00140000ULTX_FCTRL_TXPSR_PE_256 0x00240000ULTX_FCTRL_TXPSR_PE_512 0x00340000ULTX_FCTRL_TXPSR_PE_1024 0x00080000ULTX_FCTRL_TXPSR_PE_1536 0x00180000ULTX_FCTRL_TXPSR_PE_2048 0x00280000ULTX_FCTRL_TXPSR_PE_4096 0x000C0000ULTX_FCTRL_TXBOFFS_MASK 0xFF000000ULTX_FCTRL_IFSDELAY_MASK 0xFF00000000ULLTX_BUFFER_ID 0x09TX_BUFFER_LEN (1024)DX_TIME_ID 0x0ADX_TIME_LEN (5)¡REG_0B_ID_RESERVED 0x0B¦RX_FWTO_ID 0x0C§RX_FWTO_LEN (2)©RX_FWTO_MASK 0xFFFF®SYS_CTRL_ID 0x0D¯SYS_CTRL_LEN (4)±SYS_CTRL_MASK_32 0x010003CFUL³SYS_CTRL_SFCST 0x00000001UL´SYS_CTRL_TXSTRT 0x00000002ULµSYS_CTRL_TXDLYS 0x00000004UL¶SYS_CTRL_CANSFCS 0x00000008UL·SYS_CTRL_TRXOFF 0x00000040UL¸SYS_CTRL_WAIT4RESP 0x00000080ULºSYS_CTRL_RXENAB 0x00000100UL»SYS_CTRL_RXDLYE 0x00000200UL¾SYS_CTRL_HSRBTOGGLE 0x01000000UL¿SYS_CTRL_HRBT (SYS_CTRL_HSRBTOGGLE)ÀSYS_CTRL_HRBT_OFFSET (3)ÅSYS_MASK_ID 0x0EÆSYS_MASK_LEN (4)ÈSYS_MASK_MASK_32 0x3FF7FFFEULÊSYS_MASK_MCPLOCK 0x00000002ULËSYS_MASK_MESYNCR 0x00000004ULÌSYS_MASK_MAAT 0x00000008ULÍSYS_MASK_MTXFRB 0x00000010ULÎSYS_MASK_MTXPRS 0x00000020ULÏSYS_MASK_MTXPHS 0x00000040ULÐSYS_MASK_MTXFRS 0x00000080ULÒSYS_MASK_MRXPRD 0x00000100ULÓSYS_MASK_MRXSFDD 0x00000200ULÔSYS_MASK_MLDEDONE 0x00000400ULÕSYS_MASK_MRXPHD 0x00000800ULÖSYS_MASK_MRXPHE 0x00001000UL×SYS_MASK_MRXDFR 0x00002000ULØSYS_MASK_MRXFCG 0x00004000ULÙSYS_MASK_MRXFCE 0x00008000ULÛSYS_MASK_MRXRFSL 0x00010000ULÜSYS_MASK_MRXRFTO 0x00020000ULÝSYS_MASK_MLDEERR 0x00040000ULÞSYS_MASK_MRXOVRR 0x00100000ULßSYS_MASK_MRXPTO 0x00200000ULàSYS_MASK_MGPIOIRQ 0x00400000ULáSYS_MASK_MSLP2INIT 0x00800000ULãSYS_MASK_MRFPLLLL 0x01000000ULäSYS_MASK_MCPLLLL 0x02000000ULåSYS_MASK_MRXSFDTO 0x04000000ULæSYS_MASK_MHPDWARN 0x08000000ULçSYS_MASK_MTXBERR 0x10000000ULèSYS_MASK_MAFFREJ 0x20000000ULíSYS_STATUS_ID 0x0FîSYS_STATUS_LEN (5)ðSYS_STATUS_MASK_32 0xFFF7FFFFULòSYS_STATUS_IRQS 0x00000001ULóSYS_STATUS_CPLOCK 0x00000002ULôSYS_STATUS_ESYNCR 0x00000004ULõSYS_STATUS_AAT 0x00000008ULöSYS_STATUS_TXFRB 0x00000010UL÷SYS_STATUS_TXPRS 0x00000020ULøSYS_STATUS_TXPHS 0x00000040ULùSYS_STATUS_TXFRS 0x00000080ULûSYS_STATUS_RXPRD 0x00000100ULüSYS_STATUS_RXSFDD 0x00000200ULýSYS_STATUS_LDEDONE 0x00000400ULþSYS_STATUS_RXPHD 0x00000800ULÿSYS_STATUS_RXPHE 0x00001000ULSYS_STATUS_RXDFR 0x00002000ULSYS_STATUS_RXFCG 0x00004000ULSYS_STATUS_RXFCE 0x00008000ULSYS_STATUS_RXRFSL 0x00010000ULSYS_STATUS_RXRFTO 0x00020000ULSYS_STATUS_LDEERR 0x00040000ULSYS_STATUS_reserved 0x00080000ULSYS_STATUS_RXOVRR 0x00100000ULSYS_STATUS_RXPTO 0x00200000ULSYS_STATUS_GPIOIRQ 0x00400000ULSYS_STATUS_SLP2INIT 0x00800000ULSYS_STATUS_RFPLL_LL 0x01000000ULSYS_STATUS_CLKPLL_LL 0x02000000ULSYS_STATUS_RXSFDTO 0x04000000ULSYS_STATUS_HPDWARN 0x08000000ULSYS_STATUS_TXBERR 0x10000000ULSYS_STATUS_AFFREJ 0x20000000ULSYS_STATUS_HSRBP 0x40000000ULSYS_STATUS_ICRBP 0x80000000ULSYS_STATUS_RXRSCS 0x0100000000ULLSYS_STATUS_RXPREJ 0x0200000000ULLSYS_STATUS_TXPUTE 0x0400000000ULLSYS_STATUS_TXERR (0x0408)SYS_STATUS_ALL_RX_GOOD (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG | SYS_STATUS_RXPRD | SYS_STATUS_RXSFDD | SYS_STATUS_RXPHD | SYS_STATUS_LDEDONE)¡SYS_STATUS_ALL_DBLBUFF (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG)¤SYS_STATUS_ALL_RX_ERR (SYS_STATUS_RXPHE | SYS_STATUS_RXFCE | SYS_STATUS_RXRFSL | SYS_STATUS_RXSFDTO | SYS_STATUS_RXRFTO | SYS_STATUS_RXPTO | SYS_STATUS_AFFREJ | SYS_STATUS_LDEERR)¨SYS_STATUS_ALL_TX (SYS_STATUS_AAT | SYS_STATUS_TXFRB | SYS_STATUS_TXPRS | SYS_STATUS_TXPHS | SYS_STATUS_TXFRS )¯RX_FINFO_ID 0x10°RX_FINFO_LEN (4)²RX_FINFO_MASK_32 0xFFFFFBFFUL³RX_FINFO_RXFLEN_MASK 0x0000007FUL´RX_FINFO_RXFLE_MASK 0x00000380ULµRX_FINFO_RXFL_MASK_1023 0x000003FFUL·RX_FINFO_RXNSPL_MASK 0x00001800UL¸RX_FINFO_RXPSR_MASK 0x000C0000ULºRX_FINFO_RXPEL_MASK 0x000C1800UL»RX_FINFO_RXPEL_64 0x00040000UL¼RX_FINFO_RXPEL_128 0x00040800UL½RX_FINFO_RXPEL_256 0x00041000UL¾RX_FINFO_RXPEL_512 0x00041800UL¿RX_FINFO_RXPEL_1024 0x00080000ULÀRX_FINFO_RXPEL_1536 0x00080800ULÁRX_FINFO_RXPEL_2048 0x00081000ULÂRX_FINFO_RXPEL_4096 0x000C0000ULÄRX_FINFO_RXBR_MASK 0x00006000ULÅRX_FINFO_RXBR_110k 0x00000000ULÆRX_FINFO_RXBR_850k 0x00002000ULÇRX_FINFO_RXBR_6M 0x00004000ULÈRX_FINFO_RXBR_SHIFT (13)ÊRX_FINFO_RNG 0x00008000ULËRX_FINFO_RNG_SHIFT (15)ÍRX_FINFO_RXPRF_MASK 0x00030000ULÎRX_FINFO_RXPRF_16M 0x00010000ULÏRX_FINFO_RXPRF_64M 0x00020000ULÐRX_FINFO_RXPRF_SHIFT (16)ÒRX_FINFO_RXPACC_MASK 0xFFF00000ULÓRX_FINFO_RXPACC_SHIFT (20)ÙRX_BUFFER_ID 0x11ÚRX_BUFFER_LEN (1024)àRX_FQUAL_ID 0x12áRX_FQUAL_LEN (8)äRX_EQUAL_STD_NOISE_MASK 0x0000FFFFULLåRX_EQUAL_STD_NOISE_SHIFT (0)æSTD_NOISE_MASK RX_EQUAL_STD_NOISE_MASKçSTD_NOISE_SHIFT RX_EQUAL_STD_NOISE_SHIFTéRX_EQUAL_FP_AMPL2_MASK 0xFFFF0000ULLêRX_EQUAL_FP_AMPL2_SHIFT (16)ëFP_AMPL2_MASK RX_EQUAL_FP_AMPL2_MASKìFP_AMPL2_SHIFT RX_EQUAL_FP_AMPL2_SHIFTîRX_EQUAL_PP_AMPL3_MASK 0x0000FFFF00000000ULLïRX_EQUAL_PP_AMPL3_SHIFT (32)ðPP_AMPL3_MASK RX_EQUAL_PP_AMPL3_MASKñPP_AMPL3_SHIFT RX_EQUAL_PP_AMPL3_SHIFTóRX_EQUAL_CIR_MXG_MASK 0xFFFF000000000000ULLôRX_EQUAL_CIR_MXG_SHIFT (48)õCIR_MXG_MASK RX_EQUAL_CIR_MXG_MASKöCIR_MXG_SHIFT RX_EQUAL_CIR_MXG_SHIFTRX_TTCKI_ID 0x13RX_TTCKI_LEN (4)RX_TTCKO_ID 0x14RX_TTCKO_LEN (5)RX_TTCKO_MASK_32 0xFF07FFFFULRX_TTCKO_RXTOFS_MASK 0x0007FFFFULRX_TTCKO_RSMPDEL_MASK 0xFF000000ULRX_TTCKO_RCPHASE_MASK 0x7F0000000000ULLRX_TIME_ID 0x15RX_TIME_LLEN (14)RX_TIME_RX_STAMP_LEN (5)RX_STAMP_LEN RX_TIME_RX_STAMP_LENRX_TIME_RX_STAMP_OFFSET (0)RX_TIME_FP_INDEX_OFFSET (5)RX_TIME_FP_AMPL1_OFFSET (7)RX_TIME_FP_RAWST_OFFSET (9)¥REG_16_ID_RESERVED 0x16«TX_TIME_ID 0x17¬TX_TIME_LLEN (10)TX_TIME_TX_STAMP_LEN (5)®TX_STAMP_LEN TX_TIME_TX_STAMP_LEN°TX_TIME_TX_STAMP_OFFSET (0)±TX_TIME_TX_RAWST_OFFSET (5)¹TX_ANTD_ID 0x18ºTX_ANTD_LEN (2)ÄSYS_STATE_ID 0x19ÅSYS_STATE_LEN (5)ËACK_RESP_T_ID 0x1AÌACK_RESP_T_LEN (4)ÎACK_RESP_T_MASK 0xFF0FFFFFULÏACK_RESP_T_W4R_TIM_MASK 0x000FFFFFULÐW4R_TIM_MASK ACK_RESP_T_W4R_TIM_MASKÑACK_RESP_T_ACK_TIM_MASK 0xFF000000ULÒACK_TIM_MASK ACK_RESP_T_ACK_TIM_MASKÙREG_1B_ID_RESERVED 0x1BÚREG_1C_ID_RESERVED 0x1CàRX_SNIFF_ID 0x1DáRX_SNIFF_LEN (4)ãRX_SNIFF_MASK 0x0000FF0FULäRX_SNIFF_SNIFF_ONT_MASK 0x0000000FULåSNIFF_ONT_MASK RX_SNIFF_SNIFF_ONT_MASKæRX_SNIFF_SNIFF_OFFT_MASK 0x0000FF00ULçSNIFF_OFFT_MASK RX_SNIFF_SNIFF_OFFT_MASKîTX_POWER_ID 0x1EïTX_POWER_LEN (4)ñTX_POWER_BOOSTNORM_MASK 0x00000000ULòBOOSTNORM_MASK TX_POWER_BOOSTNORM_MASKóTX_POWER_BOOSTNORM_SHIFT (0)ôTX_POWER_BOOSTP500_MASK 0x00000000ULõBOOSTP500_MASK TX_POWER_BOOSTP500_MASKöTX_POWER_BOOSTP500_SHIFT (8)÷TX_POWER_BOOSTP250_MASK 0x00000000ULøBOOSTP250_MASK TX_POWER_BOOSTP250_MASKùTX_POWER_BOOSTP250_SHIFT (16)úTX_POWER_BOOSTP125_MASK 0x00000000ULûBOOSTP125_MASK TX_POWER_BOOSTP125_MASKüTX_POWER_BOOSTP125_SHIFT (24)þTX_POWER_MAN_DEFAULT 0x0E080222ULÿTX_POWER_TXPOWPHR_MASK 0x0000FF00ULTX_POWER_TXPOWSD_MASK 0x00FF0000ULCHAN_CTRL_ID 0x1FCHAN_CTRL_LEN (4)CHAN_CTRL_MASK 0xFFFF00FFULCHAN_CTRL_TX_CHAN_MASK 0x0000000FULCHAN_CTRL_TX_CHAN_SHIFT (0)CHAN_CTRL_RX_CHAN_MASK 0x000000F0ULCHAN_CTRL_RX_CHAN_SHIFT (4)CHAN_CTRL_RXFPRF_MASK 0x000C0000ULCHAN_CTRL_RXFPRF_SHIFT (18)CHAN_CTRL_RXFPRF_4 0x00000000ULCHAN_CTRL_RXFPRF_16 0x00040000ULCHAN_CTRL_RXFPRF_64 0x00080000ULCHAN_CTRL_TX_PCOD_MASK 0x07C00000ULCHAN_CTRL_TX_PCOD_SHIFT (22)CHAN_CTRL_RX_PCOD_MASK 0xF8000000ULCHAN_CTRL_RX_PCOD_SHIFT (27)CHAN_CTRL_DWSFD 0x00020000ULCHAN_CTRL_DWSFD_SHIFT (17)CHAN_CTRL_TNSSFD 0x00100000ULCHAN_CTRL_TNSSFD_SHIFT (20)CHAN_CTRL_RNSSFD 0x00200000UL CHAN_CTRL_RNSSFD_SHIFT (21)¨REG_20_ID_RESERVED 0x20®USR_SFD_ID 0x21¯USR_SFD_LEN (41)µREG_22_ID_RESERVED 0x22»AGC_CTRL_ID 0x23¼AGC_CTRL_LEN (32)½AGC_CFG_STS_ID AGC_CTRL_ID¿AGC_CTRL1_OFFSET (0x02)ÀAGC_CTRL1_LEN (2)ÁAGC_CTRL1_MASK 0x0001ÂAGC_CTRL1_DIS_AM 0x0001ÅAGC_TUNE1_OFFSET (0x04)ÆAGC_TUNE1_LEN (2)ÇAGC_TUNE1_MASK 0xFFFFÈAGC_TUNE1_16M 0x8870ÉAGC_TUNE1_64M 0x889BÌAGC_TUNE2_OFFSET (0x0C)ÍAGC_TUNE2_LEN (4)ÎAGC_TUNE2_MASK 0xFFFFFFFFULÏAGC_TUNE2_VAL 0X2502A907ULÒAGC_TUNE3_OFFSET (0x12)ÓAGC_TUNE3_LEN (2)ÔAGC_TUNE3_MASK 0xFFFFÕAGC_TUNE3_VAL 0X0055×AGC_STAT1_OFFSET (0x1E)ØAGC_STAT1_LEN (3)ÙAGC_STAT1_MASK 0x0FFFFFÚAGC_STAT1_EDG1_MASK 0x0007C0ÛAGC_STAT1_EDG2_MASK 0x0FF800àEXT_SYNC_ID 0x24áEXT_SYNC_LEN (12)ãEC_CTRL_OFFSET (0x00)äEC_CTRL_LEN (4)åEC_CTRL_MASK 0x00000FFBULæEC_CTRL_OSTSM 0x00000001ULçEC_CTRL_OSRSM 0x00000002ULèEC_CTRL_PLLLCK 0x04éEC_CTRL_OSTRM 0x00000800ULêEC_CTRL_WAIT_MASK 0x000007F8ULìEC_RXTC_OFFSET (0x04)íEC_RXTC_LEN (4)îEC_RXTC_MASK 0xFFFFFFFFULðEC_GOLP (0x08)ñEC_GOLP_LEN (4)òEC_GOLP_MASK 0x0000003FULóEC_GOLP_OFFSET_EXT_MASK 0x0000003FULùACC_MEM_ID 0x25úACC_MEM_LEN (4064)GPIO_CTRL_ID 0x26GPIO_CTRL_LEN (44)GPIO_MODE_OFFSET 0x00GPIO_MODE_LEN (4)GPIO_MODE_MASK 0x00FFFFC0ULGPIO_MSGP0_MASK 0x000000C0ULGPIO_MSGP1_MASK 0x00000300ULGPIO_MSGP2_MASK 0x00000C00ULGPIO_MSGP3_MASK 0x00003000ULGPIO_MSGP4_MASK 0x0000C000ULGPIO_MSGP5_MASK 0x00030000ULGPIO_MSGP6_MASK 0x000C0000ULGPIO_MSGP7_MASK 0x00300000ULGPIO_MSGP8_MASK 0x00C00000ULGPIO_PIN5_EXTTXE 0x00010000ULGPIO_PIN6_EXTRXE 0x00040000ULGPIO_LNA_BYTE_NUM (2)GPIO_PIN5_EXTTXE_8 0x01GPIO_PIN6_EXTRXE_8 0x04GPIO_DIR_OFFSET 0x08GPIO_DIR_LEN (3)GPIO_DIR_MASK 0x0011FFFFULGxP0 0x00000001ULGxP1 0x00000002UL GxP2 0x00000004UL¡GxP3 0x00000008UL¢GxP4 0x00000100UL£GxP5 0x00000200UL¤GxP6 0x00000400UL¥GxP7 0x00000800UL¦GxP8 0x00010000UL¨GxM0 0x00000010UL©GxM1 0x00000020ULªGxM2 0x00000040UL«GxM3 0x00000080UL¬GxM4 0x00001000ULGxM5 0x00002000UL®GxM6 0x00004000UL¯GxM7 0x00008000UL°GxM8 0x00100000UL²GDP0 GxP0³GDP1 GxP1´GDP2 GxP2µGDP3 GxP3¶GDP4 GxP4·GDP5 GxP5¸GDP6 GxP6¹GDP7 GxP7ºGDP8 GxP8¼GDM0 GxM0½GDM1 GxM1¾GDM2 GxM2¿GDM3 GxM3ÀGDM4 GxM4ÁGDM5 GxM5ÂGDM6 GxM6ÃGDM7 GxM7ÄGDM8 GxM8ÇGPIO_DOUT_OFFSET 0x0CÈGPIO_DOUT_LEN (3)ÉGPIO_DOUT_MASK GPIO_DIR_MASKÌGPIO_IRQE_OFFSET 0x10ÍGPIO_IRQE_LEN (4)ÎGPIO_IRQE_MASK 0x000001FFULÏGIRQx0 0x00000001ULÐGIRQx1 0x00000002ULÑGIRQx2 0x00000004ULÒGIRQx3 0x00000008ULÓGIRQx4 0x00000010ULÔGIRQx5 0x00000020ULÕGIRQx6 0x00000040ULÖGIRQx7 0x00000080UL×GIRQx8 0x00000100ULØGIRQE0 GIRQx0ÙGIRQE1 GIRQx1ÚGIRQE2 GIRQx2ÛGIRQE3 GIRQx3ÜGIRQE4 GIRQx4ÝGIRQE5 GIRQx5ÞGIRQE6 GIRQx6ßGIRQE7 GIRQx7àGIRQE8 GIRQx8ãGPIO_ISEN_OFFSET 0x14äGPIO_ISEN_LEN (4)åGPIO_ISEN_MASK GPIO_IRQE_MASKæGISEN0 GIRQx0çGISEN1 GIRQx1èGISEN2 GIRQx2éGISEN3 GIRQx3êGISEN4 GIRQx4ëGISEN5 GIRQx5ìGISEN6 GIRQx6íGISEN7 GIRQx7îGISEN8 GIRQx8ñGPIO_IMODE_OFFSET 0x18òGPIO_IMODE_LEN (4)óGPIO_IMODE_MASK GPIO_IRQE_MASKôGIMOD0 GIRQx0õGIMOD1 GIRQx1öGIMOD2 GIRQx2÷GIMOD3 GIRQx3øGIMOD4 GIRQx4ùGIMOD5 GIRQx5úGIMOD6 GIRQx6ûGIMOD7 GIRQx7üGIMOD8 GIRQx8ÿGPIO_IBES_OFFSET 0x1CGPIO_IBES_LEN (4)GPIO_IBES_MASK GPIO_IRQE_MASKGIBES0 GIRQx0GIBES1 GIRQx1GIBES2 GIRQx2GIBES3 GIRQx3GIBES4 GIRQx4GIBES5 GIRQx5GIBES6 GIRQx6GIBES7 GIRQx7GIBES8 GIRQx8GPIO_ICLR_OFFSET 0x20GPIO_ICLR_LEN (4)GPIO_ICLR_MASK GPIO_IRQE_MASKGICLR0 GIRQx0GICLR1 GIRQx1GICLR2 GIRQx2GICLR3 GIRQx3GICLR4 GIRQx4GICLR5 GIRQx5GICLR6 GIRQx6GICLR7 GIRQx7GICLR8 GIRQx8GPIO_IDBE_OFFSET 0x24GPIO_IDBE_LEN (4)GPIO_IDBE_MASK GPIO_IRQE_MASKGIDBE0 GIRQx0GIDBE1 GIRQx1 GIDBE2 GIRQx2¡GIDBE3 GIRQx3¢GIDBE4 GIRQx4£GIDBE5 GIRQx5¤GIDBE6 GIRQx6¥GIDBE7 GIRQx7¦GIDBE8 GIRQx8©GPIO_RAW_OFFSET 0x28ªGPIO_RAW_LEN (4)«GPIO_RAW_MASK GPIO_IRQE_MASK¬GRAWP0 GIRQx0GRAWP1 GIRQx1®GRAWP2 GIRQx2¯GRAWP3 GIRQx3°GRAWP4 GIRQx4±GRAWP5 GIRQx5²GRAWP6 GIRQx6³GRAWP7 GIRQx7´GRAWP8 GIRQx8ºDRX_CONF_ID 0x27»DRX_CONF_LEN (44)½DRX_TUNE0b_OFFSET (0x02)¾DRX_TUNE0b_LEN (2)¿DRX_TUNE0b_MASK 0xFFFFÂDRX_TUNE1a_OFFSET 0x04ÃDRX_TUNE1a_LEN (2)ÄDRX_TUNE1a_MASK 0xFFFFÇDRX_TUNE1b_OFFSET 0x06ÈDRX_TUNE1b_LEN (2)ÉDRX_TUNE1b_MASK 0xFFFFÌDRX_TUNE2_OFFSET 0x08ÍDRX_TUNE2_LEN (4)ÎDRX_TUNE2_MASK 0xFFFFFFFFULÔDRX_SFDTOC_OFFSET 0x20ÕDRX_SFDTOC_LEN (2)ÖDRX_SFDTOC_MASK 0xFFFFÙDRX_PRETOC_OFFSET 0x24ÚDRX_PRETOC_LEN (2)ÛDRX_PRETOC_MASK 0xFFFFÞDRX_DRX_TUNE4HOFFSET 0x26ßDRX_DRX_TUNE4H_LEN (2)àDRX_DRX_TUNE4H_MASK 0xFFFFéRF_CONF_ID 0x28êRF_CONF_LEN (58)ëRF_CONF_TXEN_MASK 0x00400000ULìRF_CONF_RXEN_MASK 0x00200000ULíRF_CONF_TXPOW_MASK 0x001F0000ULîRF_CONF_PLLEN_MASK 0x0000E000ULïRF_CONF_TXBLOCKSEN_MASK 0x00001F00ULðRF_CONF_TXPLLPOWEN_MASK (RF_CONF_PLLEN_MASK | RF_CONF_TXPOW_MASK)ñRF_CONF_TXALLEN_MASK (RF_CONF_TXEN_MASK | RF_CONF_TXPOW_MASK | RF_CONF_PLLEN_MASK | RF_CONF_TXBLOCKSEN_MASK)óRF_RXCTRLH_OFFSET 0x0BõRF_TXCTRL_OFFSET 0x0CöRF_TXCTRL_LEN (4)÷RF_TXCTRL_TXMTUNE_MASK 0x000001E0ULøRF_TXCTRL_TXTXMQ_MASK 0x00000E00ULùRF_TXCTRL_CH1 0x00005C40ULúRF_TXCTRL_CH2 0x00045CA0ULûRF_TXCTRL_CH3 0x00086CC0ULüRF_TXCTRL_CH4 0x00045C80ULýRF_TXCTRL_CH5 0x001E3FE0ULþRF_TXCTRL_CH7 0x001E7DE0ULRF_STATUS_OFFSET 0x2CREG_29_ID_RESERVED 0x29TX_CAL_ID 0x2ATX_CAL_LEN (52)TC_SARL_SAR_C (0)TC_SARL_SAR_LVBAT_OFFSET (3)TC_SARL_SAR_LTEMP_OFFSET (4)TC_SARW_SAR_WTEMP_OFFSET 0x06TC_SARW_SAR_WVBAT_OFFSET 0x07TC_PGDELAY_OFFSET 0x0BTC_PGDELAY_LEN (1) TC_PGDELAY_CH1 0xC9¡TC_PGDELAY_CH2 0xC2¢TC_PGDELAY_CH3 0xC5£TC_PGDELAY_CH4 0x95¤TC_PGDELAY_CH5 0xC0¥TC_PGDELAY_CH7 0x93§TC_PGTEST_OFFSET 0x0C¨TC_PGTEST_LEN (1)©TC_PGTEST_NORMAL 0x00ªTC_PGTEST_CW 0x13°FS_CTRL_ID 0x2B±FS_CTRL_LEN (21)³FS_RES1_OFFSET 0x00´FS_RES1_LEN (7)¶FS_PLLCFG_OFFSET 0x07·FS_PLLCFG_LEN (5)¸FS_PLLCFG_CH1 0x09000407UL¹FS_PLLCFG_CH2 0x08400508ULºFS_PLLCFG_CH3 0x08401009UL»FS_PLLCFG_CH4 0x08400508UL¼FS_PLLCFG_CH5 0x0800041DUL½FS_PLLCFG_CH7 0x0800041DUL¿FS_PLLTUNE_OFFSET 0x0BÀFS_PLLTUNE_LEN (1)ÁFS_PLLTUNE_CH1 0x1EÂFS_PLLTUNE_CH2 0x26ÃFS_PLLTUNE_CH3 0x5EÄFS_PLLTUNE_CH4 0x26ÅFS_PLLTUNE_CH5 0xA6ÆFS_PLLTUNE_CH7 0xA6ÈFS_RES2_OFFSET 0x0CÉFS_RES2_LEN (2)ËFS_XTALT_OFFSET 0x0EÌFS_XTALT_LEN (1)ÍFS_XTALT_MASK 0x1FÎFS_XTALT_MIDRANGE 0x10ÐFS_RES3_OFFSET 0x0FÑFS_RES3_LEN (6)ÖAON_ID 0x2C×AON_LEN (12)ÙAON_WCFG_OFFSET 0x00ÚAON_WCFG_LEN (2)ÛAON_WCFG_MASK 0x09CBÜAON_WCFG_ONW_RADC 0x0001ÝAON_WCFG_ONW_RX 0x0002ÞAON_WCFG_ONW_LEUI 0x0008ßAON_WCFG_ONW_LDC 0x0040àAON_WCFG_ONW_L64P 0x0080áAON_WCFG_PRES_SLEEP 0x0100âAON_WCFG_ONW_LLDE 0x0800ãAON_WCFG_ONW_LLDO 0x1000åAON_CTRL_OFFSET 0x02æAON_CTRL_LEN (1)çAON_CTRL_MASK 0x8FèAON_CTRL_RESTORE 0x01éAON_CTRL_SAVE 0x02êAON_CTRL_UPL_CFG 0x04ëAON_CTRL_DCA_READ 0x08ìAON_CTRL_DCA_ENAB 0x80îAON_RDAT_OFFSET 0x03ïAON_RDAT_LEN (1)ñAON_ADDR_OFFSET 0x04òAON_ADDR_LEN (1)õAON_CFG0_OFFSET 0x06öAON_CFG0_LEN (4)÷AON_CFG0_SLEEP_EN 0x00000001ULøAON_CFG0_WAKE_PIN 0x00000002ULùAON_CFG0_WAKE_SPI 0x00000004ULúAON_CFG0_WAKE_CNT 0x00000008ULûAON_CFG0_LPDIV_EN 0x00000010ULüAON_CFG0_LPCLKDIVA_MASK 0x0000FFE0ULýAON_CFG0_LPCLKDIVA_SHIFT (5)þAON_CFG0_SLEEP_TIM 0xFFFF0000ULÿAON_CFG0_SLEEP_SHIFT (16)AON_CFG1_OFFSET 0x0AAON_CFG1_LEN (2)AON_CFG1_MASK 0x0007AON_CFG1_SLEEP_CEN 0x0001AON_CFG1_SMXX 0x0002AON_CFG1_LPOSC_CAL 0x0004OTP_IF_ID 0x2DOTP_IF_LEN (18)OTP_WDAT 0x00OTP_WDAT_LEN (4)OTP_ADDR 0x04OTP_ADDR_LEN (2)OTP_ADDR_MASK 0x07FFOTP_CTRL 0x06OTP_CTRL_LEN (2)OTP_CTRL_MASK 0x8002OTP_CTRL_OTPRDEN 0x0001OTP_CTRL_OTPREAD 0x0002OTP_CTRL_LDELOAD 0x8000OTP_CTRL_OTPPROG 0x0040OTP_STAT 0x08OTP_STAT_LEN (2) OTP_STAT_MASK 0x0003¡OTP_STAT_OTPPRGD 0x0001¤OTP_RDAT 0x0A¥OTP_RDAT_LEN (4)§OTP_SRDAT 0x0E¨OTP_SRDAT_LEN (4)ªOTP_SF 0x12«OTP_SF_LEN (1)¬OTP_SF_MASK 0x63OTP_SF_OPS_KICK 0x01®OTP_SF_LDO_KICK 0x02¯OTP_SF_OPS_SEL_L64 0x00°OTP_SF_OPS_SEL_TIGHT 0x40¹LDE_IF_ID 0x2EºLDE_IF_LEN (0)¼LDE_THRESH_OFFSET 0x0000½LDE_THRESH_LEN (2)¿LDE_CFG1_OFFSET 0x0806ÀLDE_CFG1_LEN (1)ÁLDE_CFG1_NSTDEV_MASK 0x1FÂLDE_CFG1_PMULT_MASK 0xE0ÄLDE_PPINDX_OFFSET 0x1000ÅLDE_PPINDX_LEN (2)ÇLDE_PPAMPL_OFFSET 0x1002ÈLDE_PPAMPL_LEN (2)ÊLDE_RXANTD_OFFSET 0x1804ËLDE_RXANTD_LEN (2)ÍLDE_CFG2_OFFSET 0x1806ÎLDE_CFG2_LEN (2)ÐLDE_REPC_OFFSET 0x2804ÑLDE_REPC_LEN (2)ØDIG_DIAG_ID 0x2FÙDIG_DIAG_LEN (41)ÜEVC_CTRL_OFFSET 0x00ÝEVC_CTRL_LEN (4)ÞEVC_CTRL_MASK 0x00000003ULßEVC_EN 0x00000001ULàEVC_CLR 0x00000002ULãEVC_PHE_OFFSET 0x04äEVC_PHE_LEN (2)åEVC_PHE_MASK 0x0FFFçEVC_RSE_OFFSET 0x06èEVC_RSE_LEN (2)éEVC_RSE_MASK 0x0FFFìEVC_FCG_OFFSET 0x08íEVC_FCG_LEN (2)îEVC_FCG_MASK 0x0FFFðEVC_FCE_OFFSET 0x0AñEVC_FCE_LEN (2)òEVC_FCE_MASK 0x0FFFõEVC_FFR_OFFSET 0x0CöEVC_FFR_LEN (2)÷EVC_FFR_MASK 0x0FFFùEVC_OVR_OFFSET 0x0EúEVC_OVR_LEN (2)ûEVC_OVR_MASK 0x0FFFþEVC_STO_OFFSET 0x10ÿEVC_OVR_LEN (2)    EVC_OVR_MASK 0x0FFF    EVC_PTO_OFFSET 0x12    EVC_PTO_LEN (2)    EVC_PTO_MASK 0x0FFF    EVC_FWTO_OFFSET 0x14    EVC_FWTO_LEN (2)    EVC_FWTO_MASK 0x0FFF    EVC_TXFS_OFFSET 0x16    EVC_TXFS_LEN (2)    EVC_TXFS_MASK 0x0FFF    EVC_HPW_OFFSET 0x18    EVC_HPW_LEN (2)    EVC_HPW_MASK 0x0FFF    EVC_TPW_OFFSET 0x1A    EVC_TPW_LEN (2)    EVC_TPW_MASK 0x0FFF    EVC_RES1_OFFSET 0x1C    DIAG_TMC_OFFSET 0x24    DIAG_TMC_LEN (2)    DIAG_TMC_MASK 0x0010    DIAG_TMC_TX_PSTM 0x0010¦    REG_30_ID_RESERVED 0x30§    REG_31_ID_RESERVED 0x31¨    REG_32_ID_RESERVED 0x32©    REG_33_ID_RESERVED 0x33ª    REG_34_ID_RESERVED 0x34«    REG_35_ID_RESERVED 0x35°    PMSC_ID 0x36±    PMSC_LEN (48)³    PMSC_CTRL0_OFFSET 0x00´    PMSC_CTRL0_LEN (4)µ    PMSC_CTRL0_MASK 0xF08F847FUL¶    PMSC_CTRL0_SYSCLKS_AUTO 0x00000000UL·    PMSC_CTRL0_SYSCLKS_19M 0x00000001UL¸    PMSC_CTRL0_SYSCLKS_125M 0x00000002UL¹    PMSC_CTRL0_RXCLKS_AUTO 0x00000000ULº    PMSC_CTRL0_RXCLKS_19M 0x00000004UL»    PMSC_CTRL0_RXCLKS_125M 0x00000008UL¼    PMSC_CTRL0_RXCLKS_OFF 0x0000000CUL½    PMSC_CTRL0_TXCLKS_AUTO 0x00000000UL¾    PMSC_CTRL0_TXCLKS_19M 0x00000010UL¿    PMSC_CTRL0_TXCLKS_125M 0x00000020ULÀ    PMSC_CTRL0_TXCLKS_OFF 0x00000030ULÁ    PMSC_CTRL0_FACE 0x00000040ULÃ    PMSC_CTRL1_OFFSET 0x04Ä    PMSC_CTRL1_LEN (4)Å    PMSC_CTRL1_MASK 0xFC02F802ULÆ    PMSC_CTRL1_ARX2INIT 0x00000002ULÇ    PMSC_CTRL1_ATXSLP 0x00000800ULÈ    PMSC_CTRL1_ARXSLP 0x00001000ULÉ    PMSC_CTRL1_SNOZE 0x00002000ULÊ    PMSC_CTRL1_SNOZR 0x00004000ULË    PMSC_CTRL1_PLLSYN 0x00008000ULÌ    PMSC_CTRL1_LDERUNE 0x00020000ULÍ    PMSC_CTRL1_KHZCLKDIV_MASK 0xFC000000ULÎ    PMSC_CTRL1_PKTSEQ_DISABLE 0x00Ï    PMSC_CTRL1_PKTSEQ_ENABLE 0xE7Ñ    PMSC_RES1_OFFSET 0x08Ó    PMSC_SNOZT_OFFSET 0x0CÔ    PMSC_SNOZT_LEN (1)Ö    PMSC_RES2_OFFSET 0x10Ø    PMSC_RES3_OFFSET 0x24Ú    PMSC_TXFINESEQ_OFFSET 0x26Û    PMSC_TXFINESEQ_DIS_MASK (0x0)Ü    PMSC_TXFINESEQ_EN_MASK (0B74)Þ    PMSC_LEDC_OFFSET 0x28ß    PMSC_LEDC_LEN (4)à    PMSC_LEDC_MASK 0x000001FFULá    PMSC_LEDC_BLINK_TIM_MASK 0x000000FFULâ    PMSC_LEDC_BLNKEN 0x00000100ULè    REG_37_ID_RESERVED 0x37é    REG_38_ID_RESERVED 0x38ê    REG_39_ID_RESERVED 0x39ë    REG_3A_ID_RESERVED 0x3Aì    REG_3B_ID_RESERVED 0x3Bí    REG_3C_ID_RESERVED 0x3Cî    REG_3D_ID_RESERVED 0x3Dï    REG_3E_ID_RESERVED 0x3Eð    REG_3F_ID_RESERVED 0x3F"! C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t¢: Pint64_t©; Puint8_t¶> Puint16_tÇ? Puint32_tÙ@ Puint64_téA Pint_least8_tG Pint_least16_tH Pint_least32_t¢I Pint_least64_t©J Puint_least8_t¶M Puint_least16_tÇN Puint_least32_tÙO Puint_least64_téP Pint_fast8_t¢U Pint_fast16_t¢V Pint_fast32_t¢W Pint_fast64_t©X Puint_fast8_tÙ[ Puint_fast16_tÙ\ Puint_fast32_tÙ] Puint_fast64_té^ Pintptr_t¢e Puintptr_tÙf Pintmax_t©j!Puintmax_ték!PD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h__stdint_h __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)INT_FAST8_MIN (~0x7fffffff)INT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)¡INT_FAST8_MAX 2147483647¢INT_FAST16_MAX 2147483647£INT_FAST32_MAX 2147483647¤INT_FAST64_MAX __INT64_C(9223372036854775807)§UINT_FAST8_MAX 4294967295u¨UINT_FAST16_MAX 4294967295u©UINT_FAST32_MAX 4294967295uªUINT_FAST64_MAX __UINT64_C(18446744073709551615)²INTPTR_MIN INT32_MIN¹INTPTR_MAX INT32_MAXÀUINTPTR_MAX UINT32_MAXÆINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)ÉINTMAX_MAX __ESCAPE__(9223372036854775807ll)ÌUINTMAX_MAX __ESCAPE__(18446744073709551615ull)ÕPTRDIFF_MIN INT32_MINÖPTRDIFF_MAX INT32_MAXÚSIG_ATOMIC_MIN (~0x7fffffff)ÛSIG_ATOMIC_MAX 2147483647áSIZE_MAX UINT32_MAXçWCHAR_MINèWCHAR_MAXîWCHAR_MIN 0ïWCHAR_MAX 65535óWINT_MIN (~0x7fffffff)ôWINT_MAX 2147483647ûINT8_C(x) (x)üINT16_C(x) (x)ýINT32_C(x) (x)þINT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)²__INT64³__LONGLONG&%$d
..\decadriver\deca_device_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git\XRange_Tag - å°å·æºåº\MDK-ARMintPdwt_callback_data_tLPeCHAN½Pdwt_config_tFPdwt_txconfig_tî»Pdwt_rxdiag_tËPdwt_deviceentcnts_t¾ÞPdecaIrqStatus_t¦î *½statusY#event:#aatset:#datalengthI#:fctrl#dblbuff:#
ÆCHAN_CTRL_TXCHAN_1CHAN_CTRL_TXCHAN_2CHAN_CTRL_TXCHAN_3CHAN_CTRL_TXCHAN_4CHAN_CTRL_TXCHAN_5CHAN_CTRL_TXCHAN_7*îchan:#prf:#txPreambLength:#rxPAC:#txCode:#rxCode:#nsSFD:#dataRate:#phrMode:#sfdTOI#    *PGdly:#powerY#*¾maxNoiseI#firstPathAmp1I#stdNoiseI#firstPathAmp2I#firstPathAmp3I#maxGrowthCIRI#
rxPreamCountI#firstPathI#*åPHEI#RSLI#CRCGI#CRCBI#ARFEI#OVERI#
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