电池标签L051工程
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2023-08-30 72d5e74bf1969d0a1429a14a4f409eddf938d66d 
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Ø    0½_ÐÙ../Core/Inc/main.h꨼§1Ù@4../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.hÅצcÙ-!../Core/Inc/stm32l0xx_hal_conf.h¯†»§:ÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.hÅצÄÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.hÅצÍÙE9../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.hÅצ?ÙG;../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.hÅצÓÙ4(../Drivers/CMSIS/Include/core_cm0plus.h¼×¦,Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$Ù5)../Drivers/CMSIS/Include/cmsis_version.h¼×¦rÙ6*../Drivers/CMSIS/Include/cmsis_compiler.h¼×¦Ù3'../Drivers/CMSIS/Include/cmsis_armcc.h¼×¦vÙ1%../Drivers/CMSIS/Include/mpu_armv7.h¼×¦`ÙL@../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.hÅצ-Ù@4../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.hÅצcÙJ>../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hÅצƒÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@ÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.hÅצ‚ÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.hÅצ@ÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.hÅצKÙH<../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.hÅצ    ÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.hÅצÊÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.hÅצaÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.hÅצÔÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.hÅצ’ÙF:../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.hÅצêÙI=../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.hÅצ¨ÙNB../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.hÅצÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.hÅצþÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.hÅצ¼ÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.hÅצOÙF:../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.hÅצÒÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.hÅצ£ÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.hÅצaÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.hÅצ°ÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.hÅצ²ÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.hÅצpÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.hÅצ>ÙH<../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.hÅצüÙ'../APL/serial_at_cmd_app.hÜן‹ìÙ../Core/Inc/main.h꨼§1Ù../APL/dw_app.hû摧2Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hÜ Íò#Ù ../HAL/ADC.hõ›ÝšÙ>2../Middlewares/HIDOLibrary/Include/HIDO_TypeDef.hõ›Ýš˜Ù(../algorithm/TrackingDiff.hÜן‹;Ù"../APL/global_param.h·×ü¦©Ù, ../Core/Src/stm32l0xx_hal_msp.c¾Çë¦ÚP    __MAIN_H1ÚP__cplusplus


ÚP__STM32L0xx_HAL_HKÚP__STM32L0xx_HAL_CONF_H¼ÚPHAL_MODULE_ENABLEDcÚPHAL_ADC_MODULE_ENABLED4Ú PHAL_IWDG_MODULE_ENABLEDÏÚ!PHAL_LPTIM_MODULE_ENABLEDrÚPHAL_SPI_MODULE_ENABLEDÚPHAL_TIM_MODULE_ENABLEDÚ PHAL_UART_MODULE_ENABLED¾Ú PHAL_GPIO_MODULE_ENABLEDËÚ PHAL_EXTI_MODULE_ENABLEDÀÚPHAL_DMA_MODULE_ENABLED*ÚPHAL_I2C_MODULE_ENABLED>ÚPHAL_RCC_MODULE_ENABLED$Ú!PHAL_FLASH_MODULE_ENABLEDŠÚPHAL_PWR_MODULE_ENABLEDÚ"PHAL_CORTEX_MODULE_ENABLED!ÚP


HSE_VALUEýÚPHSE_STARTUP_TIMEOUT­ÚP


MSI_VALUEôÚP


HSI_VALUEùÚPHSI48_VALUE‰ÚP


LSI_VALUEõÚP


LSE_VALUEùÚPLSE_STARTUP_TIMEOUT©ÚP


VDD_VALUEÿÚPTICK_INT_PRIORITYSÚP    USE_RTOS'ÚPPREFETCH_ENABLEVÚPPREREAD_ENABLE¦ÚPBUFFER_CACHE_DISABLEãÚ'PUSE_HAL_ADC_REGISTER_CALLBACKS¤Ú(P USE_HAL_COMP_REGISTER_CALLBACKS;Ú'PUSE_HAL_DAC_REGISTER_CALLBACKS¤Ú'PUSE_HAL_I2C_REGISTER_CALLBACKS®Ú'PUSE_HAL_I2S_REGISTER_CALLBACKSžÚ(P USE_HAL_IRDA_REGISTER_CALLBACKSJÚ)P!USE_HAL_LPTIM_REGISTER_CALLBACKSâÚ'PUSE_HAL_PCD_REGISTER_CALLBACKS•Ú'PUSE_HAL_RNG_REGISTER_CALLBACKS…Ú'PUSE_HAL_RTC_REGISTER_CALLBACKSƒÚ-P%USE_HAL_SMARTCARD_REGISTER_CALLBACKS¿Ú)P!USE_HAL_SMBUS_REGISTER_CALLBACKSÞÚ'PUSE_HAL_SPI_REGISTER_CALLBACKS€Ú'PUSE_HAL_TIM_REGISTER_CALLBACKS‚Ú'PUSE_HAL_TSC_REGISTER_CALLBACKS‚Ú(P USE_HAL_UART_REGISTER_CALLBACKS.Ú)P!USE_HAL_USART_REGISTER_CALLBACKSÙÚ(P USE_HAL_WWDG_REGISTER_CALLBACKS1ÚP__STM32L0xx_HAL_RCC_HÚP__STM32L0xx_HAL_DEFÀÚP__STM32L0xx_H‡ÚPSTM32L0èÚPSTM32L071xx†ÚPUSE_HAL_DRIVERaÚ'P__STM32L0xx_CMSIS_VERSION_MAIN%Ú'P__STM32L0xx_CMSIS_VERSION_SUB1/Ú'P__STM32L0xx_CMSIS_VERSION_SUB2.Ú%P__STM32L0xx_CMSIS_VERSION_RC¹Ú"P__STM32L0xx_CMSIS_VERSION³ÚP__STM32L071xx_HÚP__CM0PLUS_REV£ÚP__MPU_PRESENTÚP__VTOR_PRESENT&ÚP__NVIC_PRIO_BITS“ÚP__Vendor_SysTickConfigôÚNonMaskableInt_IRQn¨ÚHardFault_IRQn­ÚSVCall_IRQn    ÚPendSV_IRQnþÚ SysTick_IRQnbÚ


WWDG_IRQnùÚ    PVD_IRQnJÚ    RTC_IRQnKÚFLASH_IRQnÂÚ    RCC_IRQn\Ú EXTI0_1_IRQn2Ú EXTI2_3_IRQn.ÚEXTI4_15_IRQn÷ÚDMA1_Channel1_IRQnÔÚDMA1_Channel2_3_IRQn=Ú!DMA1_Channel4_5_6_7_IRQnÚADC1_COMP_IRQn¡ÚLPTIM1_IRQnwÚUSART4_5_IRQnÓÚ


TIM2_IRQnÚ


TIM3_IRQnÚ


TIM6_IRQnÚ


TIM7_IRQnÚTIM21_IRQnãÚ


I2C3_IRQnAÚTIM22_IRQnâÚ


I2C1_IRQnCÚ


I2C2_IRQnBÚ


SPI1_IRQnÚ


SPI2_IRQnÚUSART1_IRQnnÚUSART2_IRQnmÚ LPUART1_IRQn#Ú


IRQn_Type”Ú!P__CORE_CM0PLUS_H_GENERICNÚP__stdint_hœÚP__ARMCLIB_VERSIONlÚP__INT64_TYPE__;ÚP__INT64ªÚP__INT64_C_SUFFIX__ÚP    __PASTE2NÚP__PASTE‚ÚP


__INT64_CÚP__UINT64_C­ÚP__ARMCC_VERSIONÚP__LONGLONG™ÚP__STDINT_DECLSQÚP    __CLIBNSBÚint8_tŸÚint16_tnÚint32_tpÚint64_tkÚuint8_t(Ú    uint16_t÷Ú    uint32_tùÚ    uint64_tôÚ int_least8_tÚint_least16_têÚint_least32_tìÚint_least64_tçÚuint_least8_t¤Úuint_least16_tsÚuint_least32_tuÚuint_least64_tpÚint_fast8_tˆÚ int_fast16_tWÚ int_fast32_tYÚ int_fast64_tTÚ uint_fast8_tÚuint_fast16_tàÚuint_fast32_tâÚuint_fast64_tÝÚP __sizeof_ptr®Ú    intptr_t}Ú


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"˜CR‘Ú 


"˜CFRIÚ  


"˜SRÚ WWDG_TypeDef ÚPFLASH_BASEÏÚPDATA_EEPROM_BASEðÚPDATA_EEPROM_BANK2_BASE7ÚPDATA_EEPROM_BANK1_END~ÚPDATA_EEPROM_BANK2_END}ÚP


SRAM_BASEÚPSRAM_SIZE_MAXŸÚPPERIPH_BASEsÚPAPBPERIPH_BASEšÚPAHBPERIPH_BASE¢ÚPIOPPERIPH_BASE…ÚP


TIM2_BASE#ÚP


TIM3_BASE"ÚP


TIM6_BASEÚP


TIM7_BASEÚP    RTC_BASEXÚP


WWDG_BASEÚP


IWDG_BASEÚP


SPI2_BASE!ÚPUSART2_BASEzÚP LPUART1_BASE0ÚPUSART4_BASExÚPUSART5_BASEwÚP


I2C1_BASEPÚP


I2C2_BASEOÚP    PWR_BASEHÚPLPTIM1_BASE„ÚP


I2C3_BASENÚPSYSCFG_BASElÚPCOMP1_BASEÝÚPCOMP2_BASEÜÚPCOMP12_COMMON÷ÚP


EXTI_BASEÚPTIM21_BASEðÚPTIM22_BASEïÚPFIREWALL_BASEáÚP


ADC1_BASEFÚP    ADC_BASEyÚP


SPI1_BASE"ÚPUSART1_BASE{ÚPDBGMCU_BASE‰ÚP


DMA1_BASE<ÚPDMA1_Channel1_BASEáÚPDMA1_Channel2_BASEàÚPDMA1_Channel3_BASEßÚPDMA1_Channel4_BASEÞÚPDMA1_Channel5_BASEÝÚPDMA1_Channel6_BASEÜÚPDMA1_Channel7_BASEÛÚPDMA1_CSELR_BASEXÚP    RCC_BASEiÚP FLASH_R_BASEÚPOB_BASE²ÚPFLASHSIZE_BASEŒÚP    UID_BASE_ÚP    CRC_BASEiÚPGPIOA_BASEÍÚPGPIOB_BASEÌÚPGPIOC_BASEËÚPGPIOD_BASEÊÚPGPIOE_BASEÉÚPGPIOH_BASEÆÚ PTIM2§Ú PTIM3¦Ú PTIM6£Ú PTIM7¢ÚPRTCÜÚ PWWDGŠÚ PIWDG˜Ú PSPI2¥ÚPUSART2þÚPLPUART1´Ú PI2C1ÔÚ PI2C2ÓÚ PI2C3ÒÚPPWRÌÚPLPTIM1ÚPUSART4üÚPUSART5ûÚPSYSCFGðÚPCOMP1aÚPCOMP2`Ú PEXTI‰ÚPTIM21tÚPTIM22sÚP    FIREWALLeÚ PADC1ÊÚPADC1_COMMON”ÚPADCýÚ PSPI1¦ÚPUSART1ÿÚPDBGMCU Ú PDMA1ÀÚPDMA1_Channel1eÚPDMA1_Channel2dÚPDMA1_Channel3cÚPDMA1_Channel4bÚPDMA1_Channel5aÚPDMA1_Channel6`ÚPDMA1_Channel7_ÚPDMA1_CSELRÜÚPFLASHSÚPOB6ÚPRCCíÚPCRCíÚPGPIOAQÚPGPIOBPÚPGPIOCOÚPGPIODNÚPGPIOEMÚPGPIOHJÚPLSI_STARTUP_TIME£ÚPADC_ISR_EOCAL_Pos@ÚPADC_ISR_EOCAL_MskGÚPADC_ISR_EOCALÙÚPADC_ISR_AWD_PosÌÚPADC_ISR_AWD_MskÓÚPADC_ISR_AWDeÚPADC_ISR_OVR_Pos±ÚPADC_ISR_OVR_Msk¸ÚPADC_ISR_OVRJÚPADC_ISR_EOSEQ_Pos'ÚPADC_ISR_EOSEQ_Msk.ÚPADC_ISR_EOSEQÀÚPADC_ISR_EOC_PosÑÚPADC_ISR_EOC_MskØÚPADC_ISR_EOCjÚPADC_ISR_EOSMP_Pos ÚPADC_ISR_EOSMP_Msk'ÚPADC_ISR_EOSMP¹ÚPADC_ISR_ADRDY_Pos0ÚPADC_ISR_ADRDY_Msk7ÚPADC_ISR_ADRDYÉÚPADC_ISR_EOSZÚPADC_IER_EOCALIE_Pos¼ÚPADC_IER_EOCALIE_MskÃÚPADC_IER_EOCALIEUÚPADC_IER_AWDIE_PosHÚPADC_IER_AWDIE_MskOÚPADC_IER_AWDIEáÚPADC_IER_OVRIE_Pos-ÚPADC_IER_OVRIE_Msk4ÚPADC_IER_OVRIEÆÚPADC_IER_EOSEQIE_Pos£ÚPADC_IER_EOSEQIE_MskªÚPADC_IER_EOSEQIE<ÚPADC_IER_EOCIE_PosMÚPADC_IER_EOCIE_MskTÚPADC_IER_EOCIEæÚPADC_IER_EOSMPIE_PosœÚPADC_IER_EOSMPIE_Msk£ÚPADC_IER_EOSMPIE5ÚPADC_IER_ADRDYIE_Pos¬ÚPADC_IER_ADRDYIE_Msk³ÚPADC_IER_ADRDYIEEÚPADC_IER_EOSIEÖÚPADC_CR_ADCAL_PosªÚPADC_CR_ADCAL_Msk±ÚP ADC_CR_ADCALCÚPADC_CR_ADVREGEN_Pos­ÚPADC_CR_ADVREGEN_Msk´ÚPADC_CR_ADVREGENFÚPADC_CR_ADSTP_PosƒÚPADC_CR_ADSTP_MskŠÚP ADC_CR_ADSTPÚPADC_CR_ADSTART_PosèÚPADC_CR_ADSTART_MskïÚPADC_CR_ADSTARTÚPADC_CR_ADDIS_PosšÚPADC_CR_ADDIS_Msk¡ÚP ADC_CR_ADDIS3ÚPADC_CR_ADEN_PoséÚPADC_CR_ADEN_MskðÚPADC_CR_ADEN‚ÚPADC_CFGR1_AWDCH_PosÔÚPADC_CFGR1_AWDCH_MskÛÚPADC_CFGR1_AWDCHmÚPADC_CFGR1_AWDCH_0ÚÚPADC_CFGR1_AWDCH_1ÙÚPADC_CFGR1_AWDCH_2ØÚPADC_CFGR1_AWDCH_3×ÚPADC_CFGR1_AWDCH_4ÖÚPADC_CFGR1_AWDEN_PosÌÚPADC_CFGR1_AWDEN_MskÓÚPADC_CFGR1_AWDENeÚPADC_CFGR1_AWDSGL_PoswÚPADC_CFGR1_AWDSGL_Msk~ÚPADC_CFGR1_AWDSGLÚPADC_CFGR1_DISCEN_PosƒÚPADC_CFGR1_DISCEN_MskŠÚPADC_CFGR1_DISCENÚPADC_CFGR1_AUTOFF_PostÚPADC_CFGR1_AUTOFF_Msk{ÚPADC_CFGR1_AUTOFF ÚPADC_CFGR1_WAIT_PosÚPADC_CFGR1_WAIT_MskÚPADC_CFGR1_WAIT¡ÚPADC_CFGR1_CONT_Pos    ÚPADC_CFGR1_CONT_MskÚPADC_CFGR1_CONT¢ÚPADC_CFGR1_OVRMOD_PosbÚPADC_CFGR1_OVRMOD_MskiÚPADC_CFGR1_OVRMODûÚPADC_CFGR1_EXTEN_Pos·ÚPADC_CFGR1_EXTEN_Msk¾ÚPADC_CFGR1_EXTENPÚPADC_CFGR1_EXTEN_0½ÚPADC_CFGR1_EXTEN_1¼ÚPADC_CFGR1_EXTSEL_PosdÚPADC_CFGR1_EXTSEL_MskkÚPADC_CFGR1_EXTSELýÚPADC_CFGR1_EXTSEL_0jÚPADC_CFGR1_EXTSEL_1iÚPADC_CFGR1_EXTSEL_2hÚPADC_CFGR1_ALIGN_PosÐÚPADC_CFGR1_ALIGN_Msk×ÚPADC_CFGR1_ALIGNiÚPADC_CFGR1_RES_PosUÚPADC_CFGR1_RES_Msk\ÚPADC_CFGR1_RESîÚPADC_CFGR1_RES_0[ÚPADC_CFGR1_RES_1ZÚPADC_CFGR1_SCANDIR_Pos3ÚPADC_CFGR1_SCANDIR_Msk:ÚPADC_CFGR1_SCANDIRÌÚPADC_CFGR1_DMACFG_Pos—ÚPADC_CFGR1_DMACFG_MskžÚPADC_CFGR1_DMACFG0ÚPADC_CFGR1_DMAEN_PosÖÚPADC_CFGR1_DMAEN_MskÝÚPADC_CFGR1_DMAENoÚPADC_CFGR1_AUTDLYÿÚPADC_CFGR2_TOVS_PosðÚPADC_CFGR2_TOVS_Msk÷ÚPADC_CFGR2_TOVS‰ÚPADC_CFGR2_OVSS_PosñÚPADC_CFGR2_OVSS_MskøÚPADC_CFGR2_OVSSŠÚPADC_CFGR2_OVSS_0÷ÚPADC_CFGR2_OVSS_1öÚPADC_CFGR2_OVSS_2õÚPADC_CFGR2_OVSS_3ôÚPADC_CFGR2_OVSR_PosòÚPADC_CFGR2_OVSR_MskùÚPADC_CFGR2_OVSR‹ÚPADC_CFGR2_OVSR_0øÚPADC_CFGR2_OVSR_1÷ÚPADC_CFGR2_OVSR_2öÚPADC_CFGR2_OVSE_PosÿÚPADC_CFGR2_OVSE_MskÚPADC_CFGR2_OVSE˜ÚPADC_CFGR2_CKMODE_Pos…ÚPADC_CFGR2_CKMODE_MskŒÚPADC_CFGR2_CKMODEÚPADC_CFGR2_CKMODE_0‹ÚPADC_CFGR2_CKMODE_1ŠÚPADC_SMPR_SMP_PosbÚPADC_SMPR_SMP_MskiÚP ADC_SMPR_SMPûÚPADC_SMPR_SMP_0hÚPADC_SMPR_SMP_1gÚPADC_SMPR_SMP_2fÚPADC_SMPR_SMPR§ÚPADC_SMPR_SMPR_0ÚPADC_SMPR_SMPR_1ÚPADC_SMPR_SMPR_2ÚPADC_TR_HT_PosXÚPADC_TR_HT_Msk_ÚP


ADC_TR_HTñÚPADC_TR_LT_PosTÚPADC_TR_LT_Msk[ÚP


ADC_TR_LTíÚPADC_CHSELR_CHSEL_Pos\ÚPADC_CHSELR_CHSEL_MskcÚPADC_CHSELR_CHSELõÚPADC_CHSELR_CHSEL18_PosïÚPADC_CHSELR_CHSEL18_MsköÚPADC_CHSELR_CHSEL18ˆÚPADC_CHSELR_CHSEL17_PosðÚPADC_CHSELR_CHSEL17_Msk÷ÚPADC_CHSELR_CHSEL17‰ÚPADC_CHSELR_CHSEL15_PosòÚPADC_CHSELR_CHSEL15_MskùÚPADC_CHSELR_CHSEL15‹ÚPADC_CHSELR_CHSEL14_PosóÚPADC_CHSELR_CHSEL14_MskúÚPADC_CHSELR_CHSEL14ŒÚPADC_CHSELR_CHSEL13_PosôÚPADC_CHSELR_CHSEL13_MskûÚPADC_CHSELR_CHSEL13ÚPADC_CHSELR_CHSEL12_PosõÚPADC_CHSELR_CHSEL12_MsküÚPADC_CHSELR_CHSEL12ŽÚPADC_CHSELR_CHSEL11_PosöÚPADC_CHSELR_CHSEL11_MskýÚPADC_CHSELR_CHSEL11ÚPADC_CHSELR_CHSEL10_Pos÷ÚPADC_CHSELR_CHSEL10_MskþÚPADC_CHSELR_CHSEL10ÚPADC_CHSELR_CHSEL9_Pos!ÚPADC_CHSELR_CHSEL9_Msk(ÚPADC_CHSELR_CHSEL9ºÚPADC_CHSELR_CHSEL8_Pos"ÚPADC_CHSELR_CHSEL8_Msk)ÚPADC_CHSELR_CHSEL8»ÚPADC_CHSELR_CHSEL7_Pos#ÚPADC_CHSELR_CHSEL7_Msk*ÚPADC_CHSELR_CHSEL7¼ÚPADC_CHSELR_CHSEL6_Pos$ÚPADC_CHSELR_CHSEL6_Msk+ÚPADC_CHSELR_CHSEL6½ÚPADC_CHSELR_CHSEL5_Pos%ÚPADC_CHSELR_CHSEL5_Msk,ÚPADC_CHSELR_CHSEL5¾ÚPADC_CHSELR_CHSEL4_Pos&ÚPADC_CHSELR_CHSEL4_Msk-ÚPADC_CHSELR_CHSEL4¿ÚPADC_CHSELR_CHSEL3_Pos'ÚPADC_CHSELR_CHSEL3_Msk.ÚPADC_CHSELR_CHSEL3ÀÚPADC_CHSELR_CHSEL2_Pos(ÚPADC_CHSELR_CHSEL2_Msk/ÚPADC_CHSELR_CHSEL2ÁÚPADC_CHSELR_CHSEL1_Pos)ÚPADC_CHSELR_CHSEL1_Msk0ÚPADC_CHSELR_CHSEL1ÂÚPADC_CHSELR_CHSEL0_Pos*ÚPADC_CHSELR_CHSEL0_Msk1ÚPADC_CHSELR_CHSEL0ÃÚPADC_DR_DATA_PosæÚPADC_DR_DATA_MskíÚPADC_DR_DATAÚ PADC_CALFACT_CALFACT_PosªÚ PADC_CALFACT_CALFACT_Msk±ÚPADC_CALFACT_CALFACTCÚPADC_CCR_LFMEN_PosHÚPADC_CCR_LFMEN_MskOÚPADC_CCR_LFMENáÚPADC_CCR_TSEN_Pos‚ÚPADC_CCR_TSEN_Msk‰ÚP ADC_CCR_TSENÚPADC_CCR_VREFEN_PosòÚPADC_CCR_VREFEN_MskùÚPADC_CCR_VREFEN‹ÚPADC_CCR_PRESC_Pos=ÚPADC_CCR_PRESC_MskDÚPADC_CCR_PRESCÖÚPADC_CCR_PRESC_0CÚPADC_CCR_PRESC_1BÚPADC_CCR_PRESC_2AÚPADC_CCR_PRESC_3@ÚPCOMP_CSR_COMP1EN_PosJÚPCOMP_CSR_COMP1EN_MskQÚPCOMP_CSR_COMP1ENãÚ!PCOMP_CSR_COMP1INNSEL_PosÚ!PCOMP_CSR_COMP1INNSEL_MskÚPCOMP_CSR_COMP1INNSEL¥ÚPCOMP_CSR_COMP1INNSEL_0ÚPCOMP_CSR_COMP1INNSEL_1ÚPCOMP_CSR_COMP1WM_Pos9ÚPCOMP_CSR_COMP1WM_Msk@ÚPCOMP_CSR_COMP1WMÒÚ$PCOMP_CSR_COMP1LPTIM1IN1_PosPÚ$PCOMP_CSR_COMP1LPTIM1IN1_MskWÚ PCOMP_CSR_COMP1LPTIM1IN1éÚ#PCOMP_CSR_COMP1POLARITY_Pos]Ú#PCOMP_CSR_COMP1POLARITY_MskdÚPCOMP_CSR_COMP1POLARITYöÚ PCOMP_CSR_COMP1VALUE_PosZÚ PCOMP_CSR_COMP1VALUE_MskaÚPCOMP_CSR_COMP1VALUEóÚPCOMP_CSR_COMP1LOCK_Pos°ÚPCOMP_CSR_COMP1LOCK_Msk·ÚPCOMP_CSR_COMP1LOCKIÚPCOMP_CSR_COMP2EN_PosIÚPCOMP_CSR_COMP2EN_MskPÚPCOMP_CSR_COMP2ENâÚ PCOMP_CSR_COMP2SPEED_PoseÚ PCOMP_CSR_COMP2SPEED_MsklÚPCOMP_CSR_COMP2SPEEDþÚ!PCOMP_CSR_COMP2INNSEL_PosÚ!PCOMP_CSR_COMP2INNSEL_MskÚPCOMP_CSR_COMP2INNSEL¤ÚPCOMP_CSR_COMP2INNSEL_0ÚPCOMP_CSR_COMP2INNSEL_1ÚPCOMP_CSR_COMP2INNSEL_2Ú!PCOMP_CSR_COMP2INPSEL_Pos    Ú!PCOMP_CSR_COMP2INPSEL_MskÚPCOMP_CSR_COMP2INPSEL¢ÚPCOMP_CSR_COMP2INPSEL_0ÚPCOMP_CSR_COMP2INPSEL_1ÚPCOMP_CSR_COMP2INPSEL_2 Ú$PCOMP_CSR_COMP2LPTIM1IN2_PosNÚ$PCOMP_CSR_COMP2LPTIM1IN2_MskUÚ PCOMP_CSR_COMP2LPTIM1IN2çÚ$PCOMP_CSR_COMP2LPTIM1IN1_PosOÚ$PCOMP_CSR_COMP2LPTIM1IN1_MskVÚ PCOMP_CSR_COMP2LPTIM1IN1èÚ#PCOMP_CSR_COMP2POLARITY_Pos\Ú#PCOMP_CSR_COMP2POLARITY_MskcÚPCOMP_CSR_COMP2POLARITYõÚ PCOMP_CSR_COMP2VALUE_PosYÚ PCOMP_CSR_COMP2VALUE_Msk`ÚPCOMP_CSR_COMP2VALUEòÚPCOMP_CSR_COMP2LOCK_Pos¯ÚPCOMP_CSR_COMP2LOCK_Msk¶ÚPCOMP_CSR_COMP2LOCKHÚPCOMP_CSR_COMPxEN_PosÚPCOMP_CSR_COMPxEN_Msk


ÚPCOMP_CSR_COMPxENœÚ#PCOMP_CSR_COMPxPOLARITY_PosÚ#PCOMP_CSR_COMPxPOLARITY_MskÚPCOMP_CSR_COMPxPOLARITY¯Ú#PCOMP_CSR_COMPxOUTVALUE_PosÚ#PCOMP_CSR_COMPxOUTVALUE_MskÚPCOMP_CSR_COMPxOUTVALUE®ÚPCOMP_CSR_COMPxLOCK_PosiÚPCOMP_CSR_COMPxLOCK_MskpÚPCOMP_CSR_COMPxLOCKÚPCOMP_CSR_WINMODEÃÚPCRC_DR_DR_Pos^ÚPCRC_DR_DR_MskeÚP


CRC_DR_DR÷ÚPCRC_IDR_IDRaÚPCRC_CR_RESET_PoslÚPCRC_CR_RESET_MsksÚP CRC_CR_RESETÚPCRC_CR_POLYSIZE_PosjÚPCRC_CR_POLYSIZE_MskqÚPCRC_CR_POLYSIZEÚPCRC_CR_POLYSIZE_0pÚPCRC_CR_POLYSIZE_1oÚPCRC_CR_REV_IN_Pos


ÚPCRC_CR_REV_IN_MskÚPCRC_CR_REV_IN£ÚPCRC_CR_REV_IN_0ÚPCRC_CR_REV_IN_1ÚPCRC_CR_REV_OUT_Pos§ÚPCRC_CR_REV_OUT_Msk®ÚPCRC_CR_REV_OUT@ÚPCRC_INIT_INIT_PosÚPCRC_INIT_INIT_Msk!ÚPCRC_INIT_INIT³ÚPCRC_POL_POL_Pos°ÚPCRC_POL_POL_Msk·ÚPCRC_POL_POLIÚ!PDBGMCU_IDCODE_DEV_ID_Pos'Ú!PDBGMCU_IDCODE_DEV_ID_Msk.ÚPDBGMCU_IDCODE_DEV_IDÀÚ!PDBGMCU_IDCODE_REV_ID_PosÚ!PDBGMCU_IDCODE_REV_ID_Msk ÚPDBGMCU_IDCODE_REV_ID²ÚPDBGMCU_IDCODE_REV_ID_0ÚPDBGMCU_IDCODE_REV_ID_1ÚPDBGMCU_IDCODE_REV_ID_2ÚPDBGMCU_IDCODE_REV_ID_3ÚPDBGMCU_IDCODE_REV_ID_4ÚPDBGMCU_IDCODE_REV_ID_5ÚPDBGMCU_IDCODE_REV_ID_6ÚPDBGMCU_IDCODE_REV_ID_7ÚPDBGMCU_IDCODE_REV_ID_8ÚPDBGMCU_IDCODE_REV_ID_9Ú PDBGMCU_IDCODE_REV_ID_10ìÚ PDBGMCU_IDCODE_REV_ID_11ëÚ PDBGMCU_IDCODE_REV_ID_12êÚ PDBGMCU_IDCODE_REV_ID_13éÚ PDBGMCU_IDCODE_REV_ID_14èÚ PDBGMCU_IDCODE_REV_ID_15çÚPDBGMCU_CR_DBG_PosFÚPDBGMCU_CR_DBG_MskMÚPDBGMCU_CR_DBGßÚ PDBGMCU_CR_DBG_SLEEP_PosbÚ PDBGMCU_CR_DBG_SLEEP_MskiÚPDBGMCU_CR_DBG_SLEEPûÚPDBGMCU_CR_DBG_STOP_Pos—ÚPDBGMCU_CR_DBG_STOP_MskžÚPDBGMCU_CR_DBG_STOP0Ú"PDBGMCU_CR_DBG_STANDBY_PosÂÚ"PDBGMCU_CR_DBG_STANDBY_MskÉÚPDBGMCU_CR_DBG_STANDBY[Ú)P!DBGMCU_APB1_FZ_DBG_TIM2_STOP_PosšÚ)P!DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk¡Ú%PDBGMCU_APB1_FZ_DBG_TIM2_STOP3Ú)P!DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos™Ú)P!DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk Ú%PDBGMCU_APB1_FZ_DBG_TIM3_STOP2Ú)P!DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos–Ú)P!DBGMCU_APB1_FZ_DBG_TIM6_STOP_MskÚ%PDBGMCU_APB1_FZ_DBG_TIM6_STOP/Ú)P!DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos•Ú)P!DBGMCU_APB1_FZ_DBG_TIM7_STOP_MskœÚ%PDBGMCU_APB1_FZ_DBG_TIM7_STOP.Ú(P DBGMCU_APB1_FZ_DBG_RTC_STOP_PosÏÚ(P DBGMCU_APB1_FZ_DBG_RTC_STOP_MskÖÚ$PDBGMCU_APB1_FZ_DBG_RTC_STOPhÚ)P!DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos}Ú)P!DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk„Ú%PDBGMCU_APB1_FZ_DBG_WWDG_STOPÚ)P!DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos‹Ú)P!DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk’Ú%PDBGMCU_APB1_FZ_DBG_IWDG_STOP$Ú)P!DBGMCU_APB1_FZ_DBG_I2C1_STOP_PosÇÚ)P!DBGMCU_APB1_FZ_DBG_I2C1_STOP_MskÎÚ%PDBGMCU_APB1_FZ_DBG_I2C1_STOP`Ú)P!DBGMCU_APB1_FZ_DBG_I2C2_STOP_PosÆÚ)P!DBGMCU_APB1_FZ_DBG_I2C2_STOP_MskÍÚ%PDBGMCU_APB1_FZ_DBG_I2C2_STOP_Ú)P!DBGMCU_APB1_FZ_DBG_I2C3_STOP_PosÅÚ)P!DBGMCU_APB1_FZ_DBG_I2C3_STOP_MskÌÚ%PDBGMCU_APB1_FZ_DBG_I2C3_STOP^Ú,P$DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos“Ú,P$DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_MskšÚ(P DBGMCU_APB1_FZ_DBG_LPTIMER_STOP,Ú*P"DBGMCU_APB2_FZ_DBG_TIM22_STOP_PoseÚ*P"DBGMCU_APB2_FZ_DBG_TIM22_STOP_MsklÚ&PDBGMCU_APB2_FZ_DBG_TIM22_STOPþÚ*P"DBGMCU_APB2_FZ_DBG_TIM21_STOP_PosfÚ*P"DBGMCU_APB2_FZ_DBG_TIM21_STOP_MskmÚ&PDBGMCU_APB2_FZ_DBG_TIM21_STOPÿÚPDMA_ISR_GIF1_Pos•ÚPDMA_ISR_GIF1_MskœÚP DMA_ISR_GIF1.ÚPDMA_ISR_TCIF1_PosCÚPDMA_ISR_TCIF1_MskJÚPDMA_ISR_TCIF1ÜÚPDMA_ISR_HTIF1_Pos>ÚPDMA_ISR_HTIF1_MskEÚPDMA_ISR_HTIF1×ÚPDMA_ISR_TEIF1_PosAÚPDMA_ISR_TEIF1_MskHÚPDMA_ISR_TEIF1ÚÚPDMA_ISR_GIF2_Pos”ÚPDMA_ISR_GIF2_Msk›ÚP DMA_ISR_GIF2-ÚPDMA_ISR_TCIF2_PosBÚPDMA_ISR_TCIF2_MskIÚPDMA_ISR_TCIF2ÛÚPDMA_ISR_HTIF2_Pos=ÚPDMA_ISR_HTIF2_MskDÚPDMA_ISR_HTIF2ÖÚPDMA_ISR_TEIF2_Pos@ÚPDMA_ISR_TEIF2_MskGÚPDMA_ISR_TEIF2ÙÚPDMA_ISR_GIF3_Pos“ÚPDMA_ISR_GIF3_MskšÚP DMA_ISR_GIF3,ÚPDMA_ISR_TCIF3_PosAÚPDMA_ISR_TCIF3_MskHÚPDMA_ISR_TCIF3ÚÚPDMA_ISR_HTIF3_Pos<ÚPDMA_ISR_HTIF3_MskCÚPDMA_ISR_HTIF3ÕÚPDMA_ISR_TEIF3_Pos?ÚPDMA_ISR_TEIF3_MskFÚPDMA_ISR_TEIF3ØÚPDMA_ISR_GIF4_Pos’ÚPDMA_ISR_GIF4_Msk™ÚP DMA_ISR_GIF4+ÚPDMA_ISR_TCIF4_Pos@ÚPDMA_ISR_TCIF4_MskGÚPDMA_ISR_TCIF4ÙÚPDMA_ISR_HTIF4_Pos;ÚPDMA_ISR_HTIF4_MskBÚPDMA_ISR_HTIF4ÔÚPDMA_ISR_TEIF4_Pos>ÚPDMA_ISR_TEIF4_MskEÚPDMA_ISR_TEIF4×ÚPDMA_ISR_GIF5_Pos‘ÚPDMA_ISR_GIF5_Msk˜ÚP DMA_ISR_GIF5*ÚPDMA_ISR_TCIF5_Pos?ÚPDMA_ISR_TCIF5_MskFÚPDMA_ISR_TCIF5ØÚPDMA_ISR_HTIF5_Pos:ÚPDMA_ISR_HTIF5_MskAÚPDMA_ISR_HTIF5ÓÚPDMA_ISR_TEIF5_Pos=ÚPDMA_ISR_TEIF5_MskDÚPDMA_ISR_TEIF5ÖÚPDMA_ISR_GIF6_PosÚPDMA_ISR_GIF6_Msk—ÚP DMA_ISR_GIF6)ÚPDMA_ISR_TCIF6_Pos>ÚPDMA_ISR_TCIF6_MskEÚPDMA_ISR_TCIF6×ÚPDMA_ISR_HTIF6_Pos9ÚPDMA_ISR_HTIF6_Msk@ÚPDMA_ISR_HTIF6ÒÚPDMA_ISR_TEIF6_Pos<ÚPDMA_ISR_TEIF6_MskCÚPDMA_ISR_TEIF6ÕÚPDMA_ISR_GIF7_PosÚPDMA_ISR_GIF7_Msk–ÚP DMA_ISR_GIF7(ÚPDMA_ISR_TCIF7_Pos=ÚPDMA_ISR_TCIF7_MskDÚPDMA_ISR_TCIF7ÖÚPDMA_ISR_HTIF7_Pos8ÚPDMA_ISR_HTIF7_Msk?ÚPDMA_ISR_HTIF7ÑÚPDMA_ISR_TEIF7_Pos;ÚPDMA_ISR_TEIF7_MskBÚPDMA_ISR_TEIF7ÔÚPDMA_IFCR_CGIF1_PosÚPDMA_IFCR_CGIF1_MskÚPDMA_IFCR_CGIF1±ÚPDMA_IFCR_CTCIF1_PosÆÚPDMA_IFCR_CTCIF1_MskÍÚPDMA_IFCR_CTCIF1_ÚPDMA_IFCR_CHTIF1_PosÁÚPDMA_IFCR_CHTIF1_MskÈÚPDMA_IFCR_CHTIF1ZÚPDMA_IFCR_CTEIF1_PosÄÚPDMA_IFCR_CTEIF1_MskËÚPDMA_IFCR_CTEIF1]ÚPDMA_IFCR_CGIF2_PosÚPDMA_IFCR_CGIF2_MskÚPDMA_IFCR_CGIF2°ÚPDMA_IFCR_CTCIF2_PosÅÚPDMA_IFCR_CTCIF2_MskÌÚPDMA_IFCR_CTCIF2^ÚPDMA_IFCR_CHTIF2_PosÀÚPDMA_IFCR_CHTIF2_MskÇÚPDMA_IFCR_CHTIF2YÚPDMA_IFCR_CTEIF2_PosÃÚPDMA_IFCR_CTEIF2_MskÊÚPDMA_IFCR_CTEIF2\ÚPDMA_IFCR_CGIF3_PosÚPDMA_IFCR_CGIF3_MskÚPDMA_IFCR_CGIF3¯ÚPDMA_IFCR_CTCIF3_PosÄÚPDMA_IFCR_CTCIF3_MskËÚPDMA_IFCR_CTCIF3]ÚPDMA_IFCR_CHTIF3_Pos¿ÚPDMA_IFCR_CHTIF3_MskÆÚPDMA_IFCR_CHTIF3XÚPDMA_IFCR_CTEIF3_PosÂÚPDMA_IFCR_CTEIF3_MskÉÚPDMA_IFCR_CTEIF3[ÚPDMA_IFCR_CGIF4_PosÚPDMA_IFCR_CGIF4_MskÚPDMA_IFCR_CGIF4®ÚPDMA_IFCR_CTCIF4_PosÃÚPDMA_IFCR_CTCIF4_MskÊÚPDMA_IFCR_CTCIF4\ÚPDMA_IFCR_CHTIF4_Pos¾ÚPDMA_IFCR_CHTIF4_MskÅÚPDMA_IFCR_CHTIF4WÚPDMA_IFCR_CTEIF4_PosÁÚPDMA_IFCR_CTEIF4_MskÈÚPDMA_IFCR_CTEIF4ZÚPDMA_IFCR_CGIF5_PosÚPDMA_IFCR_CGIF5_MskÚPDMA_IFCR_CGIF5­ÚPDMA_IFCR_CTCIF5_PosÂÚPDMA_IFCR_CTCIF5_MskÉÚPDMA_IFCR_CTCIF5[ÚPDMA_IFCR_CHTIF5_Pos½ÚPDMA_IFCR_CHTIF5_MskÄÚPDMA_IFCR_CHTIF5VÚPDMA_IFCR_CTEIF5_PosÀÚPDMA_IFCR_CTEIF5_MskÇÚPDMA_IFCR_CTEIF5YÚPDMA_IFCR_CGIF6_PosÚPDMA_IFCR_CGIF6_MskÚPDMA_IFCR_CGIF6¬ÚPDMA_IFCR_CTCIF6_PosÁÚPDMA_IFCR_CTCIF6_MskÈÚPDMA_IFCR_CTCIF6ZÚPDMA_IFCR_CHTIF6_Pos¼ÚPDMA_IFCR_CHTIF6_MskÃÚPDMA_IFCR_CHTIF6UÚPDMA_IFCR_CTEIF6_Pos¿ÚPDMA_IFCR_CTEIF6_MskÆÚPDMA_IFCR_CTEIF6XÚPDMA_IFCR_CGIF7_PosÚPDMA_IFCR_CGIF7_MskÚPDMA_IFCR_CGIF7«ÚPDMA_IFCR_CTCIF7_PosÀÚPDMA_IFCR_CTCIF7_MskÇÚPDMA_IFCR_CTCIF7YÚPDMA_IFCR_CHTIF7_Pos»ÚPDMA_IFCR_CHTIF7_MskÂÚPDMA_IFCR_CHTIF7TÚPDMA_IFCR_CTEIF7_Pos¾ÚPDMA_IFCR_CTEIF7_MskÅÚPDMA_IFCR_CTEIF7WÚPDMA_CCR_EN_Pos#ÚPDMA_CCR_EN_Msk*ÚPDMA_CCR_EN¼ÚPDMA_CCR_TCIE_PosÚPDMA_CCR_TCIE_Msk”ÚP DMA_CCR_TCIE&ÚPDMA_CCR_HTIE_PosˆÚPDMA_CCR_HTIE_MskÚP DMA_CCR_HTIE!ÚPDMA_CCR_TEIE_Pos‹ÚPDMA_CCR_TEIE_Msk’ÚP DMA_CCR_TEIE$ÚPDMA_CCR_DIR_PosÕÚPDMA_CCR_DIR_MskÜÚPDMA_CCR_DIRnÚPDMA_CCR_CIRC_Pos‘ÚPDMA_CCR_CIRC_Msk˜ÚP DMA_CCR_CIRC*ÚPDMA_CCR_PINC_PosˆÚPDMA_CCR_PINC_MskÚP DMA_CCR_PINC!ÚPDMA_CCR_MINC_Pos‹ÚPDMA_CCR_MINC_Msk’ÚP DMA_CCR_MINC$ÚPDMA_CCR_PSIZE_Pos%ÚPDMA_CCR_PSIZE_Msk,ÚPDMA_CCR_PSIZE¾ÚPDMA_CCR_PSIZE_0+ÚPDMA_CCR_PSIZE_1*ÚPDMA_CCR_MSIZE_Pos(ÚPDMA_CCR_MSIZE_Msk/ÚPDMA_CCR_MSIZEÁÚPDMA_CCR_MSIZE_0.ÚPDMA_CCR_MSIZE_1-ÚPDMA_CCR_PL_PosÚPDMA_CCR_PL_Msk!ÚPDMA_CCR_PL³ÚP DMA_CCR_PL_0 ÚP DMA_CCR_PL_1ÚPDMA_CCR_MEM2MEM_Pos¼ÚPDMA_CCR_MEM2MEM_MskÃÚPDMA_CCR_MEM2MEMUÚPDMA_CNDTR_NDT_Pos'ÚPDMA_CNDTR_NDT_Msk.ÚPDMA_CNDTR_NDTÀÚPDMA_CPAR_PA_PosÕÚPDMA_CPAR_PA_MskÜÚPDMA_CPAR_PAnÚPDMA_CMAR_MA_PosÛÚPDMA_CMAR_MA_MskâÚPDMA_CMAR_MAtÚPDMA_CSELR_C1S_PosHÚPDMA_CSELR_C1S_MskOÚPDMA_CSELR_C1SáÚPDMA_CSELR_C2S_PosGÚPDMA_CSELR_C2S_MskNÚPDMA_CSELR_C2SàÚPDMA_CSELR_C3S_PosFÚPDMA_CSELR_C3S_MskMÚPDMA_CSELR_C3SßÚPDMA_CSELR_C4S_PosEÚPDMA_CSELR_C4S_MskLÚPDMA_CSELR_C4SÞÚPDMA_CSELR_C5S_PosDÚPDMA_CSELR_C5S_MskKÚPDMA_CSELR_C5SÝÚPDMA_CSELR_C6S_PosCÚPDMA_CSELR_C6S_MskJÚPDMA_CSELR_C6SÜÚPDMA_CSELR_C7S_PosBÚPDMA_CSELR_C7S_MskIÚPDMA_CSELR_C7SÛÚPEXTI_IMR_IM0_PostÚPEXTI_IMR_IM0_Msk{ÚP EXTI_IMR_IM0 ÚPEXTI_IMR_IM1_PossÚPEXTI_IMR_IM1_MskzÚP EXTI_IMR_IM1ÚPEXTI_IMR_IM2_PosrÚPEXTI_IMR_IM2_MskyÚP EXTI_IMR_IM2ÚPEXTI_IMR_IM3_PosqÚPEXTI_IMR_IM3_MskxÚP EXTI_IMR_IM3


ÚPEXTI_IMR_IM4_PospÚPEXTI_IMR_IM4_MskwÚP EXTI_IMR_IM4    ÚPEXTI_IMR_IM5_PosoÚPEXTI_IMR_IM5_MskvÚP EXTI_IMR_IM5ÚPEXTI_IMR_IM6_PosnÚPEXTI_IMR_IM6_MskuÚP EXTI_IMR_IM6ÚPEXTI_IMR_IM7_PosmÚPEXTI_IMR_IM7_MsktÚP EXTI_IMR_IM7ÚPEXTI_IMR_IM8_PoslÚPEXTI_IMR_IM8_MsksÚP EXTI_IMR_IM8ÚPEXTI_IMR_IM9_PoskÚPEXTI_IMR_IM9_MskrÚP EXTI_IMR_IM9ÚPEXTI_IMR_IM10_PosAÚPEXTI_IMR_IM10_MskHÚPEXTI_IMR_IM10ÚÚPEXTI_IMR_IM11_Pos@ÚPEXTI_IMR_IM11_MskGÚPEXTI_IMR_IM11ÙÚPEXTI_IMR_IM12_Pos?ÚPEXTI_IMR_IM12_MskFÚPEXTI_IMR_IM12ØÚPEXTI_IMR_IM13_Pos>ÚPEXTI_IMR_IM13_MskEÚPEXTI_IMR_IM13×ÚPEXTI_IMR_IM14_Pos=ÚPEXTI_IMR_IM14_MskDÚPEXTI_IMR_IM14ÖÚPEXTI_IMR_IM15_Pos<ÚPEXTI_IMR_IM15_MskCÚPEXTI_IMR_IM15ÕÚPEXTI_IMR_IM16_Pos;ÚPEXTI_IMR_IM16_MskBÚPEXTI_IMR_IM16ÔÚPEXTI_IMR_IM17_Pos:ÚPEXTI_IMR_IM17_MskAÚPEXTI_IMR_IM17ÓÚPEXTI_IMR_IM18_Pos9ÚPEXTI_IMR_IM18_Msk@ÚPEXTI_IMR_IM18ÒÚPEXTI_IMR_IM19_Pos8ÚPEXTI_IMR_IM19_Msk?ÚPEXTI_IMR_IM19ÑÚPEXTI_IMR_IM20_Pos@ÚPEXTI_IMR_IM20_MskGÚPEXTI_IMR_IM20ÙÚPEXTI_IMR_IM21_Pos?ÚPEXTI_IMR_IM21_MskFÚPEXTI_IMR_IM21ØÚPEXTI_IMR_IM22_Pos>ÚPEXTI_IMR_IM22_MskEÚPEXTI_IMR_IM22×ÚPEXTI_IMR_IM23_Pos=ÚPEXTI_IMR_IM23_MskDÚPEXTI_IMR_IM23ÖÚPEXTI_IMR_IM24_Pos<ÚPEXTI_IMR_IM24_MskCÚPEXTI_IMR_IM24ÕÚPEXTI_IMR_IM25_Pos;ÚPEXTI_IMR_IM25_MskBÚPEXTI_IMR_IM25ÔÚPEXTI_IMR_IM26_Pos:ÚPEXTI_IMR_IM26_MskAÚPEXTI_IMR_IM26ÓÚPEXTI_IMR_IM28_Pos8ÚPEXTI_IMR_IM28_Msk?ÚPEXTI_IMR_IM28ÑÚPEXTI_IMR_IM29_Pos7ÚPEXTI_IMR_IM29_Msk>ÚPEXTI_IMR_IM29ÐÚPEXTI_IMR_IM_Pos¦ÚPEXTI_IMR_IM_Msk­ÚPEXTI_IMR_IM?ÚPEXTI_EMR_EM0_Pos|ÚPEXTI_EMR_EM0_MskƒÚP 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EXTI_EMR_EM9ÚPEXTI_EMR_EM10_PosIÚPEXTI_EMR_EM10_MskPÚPEXTI_EMR_EM10âÚPEXTI_EMR_EM11_PosHÚPEXTI_EMR_EM11_MskOÚPEXTI_EMR_EM11áÚPEXTI_EMR_EM12_PosGÚPEXTI_EMR_EM12_MskNÚPEXTI_EMR_EM12àÚPEXTI_EMR_EM13_PosFÚPEXTI_EMR_EM13_MskMÚPEXTI_EMR_EM13ßÚPEXTI_EMR_EM14_PosEÚPEXTI_EMR_EM14_MskLÚPEXTI_EMR_EM14ÞÚPEXTI_EMR_EM15_PosDÚPEXTI_EMR_EM15_MskKÚPEXTI_EMR_EM15ÝÚPEXTI_EMR_EM16_PosCÚPEXTI_EMR_EM16_MskJÚPEXTI_EMR_EM16ÜÚPEXTI_EMR_EM17_PosBÚPEXTI_EMR_EM17_MskIÚPEXTI_EMR_EM17ÛÚPEXTI_EMR_EM18_PosAÚPEXTI_EMR_EM18_MskHÚPEXTI_EMR_EM18ÚÚPEXTI_EMR_EM19_Pos@ÚPEXTI_EMR_EM19_MskGÚPEXTI_EMR_EM19ÙÚPEXTI_EMR_EM20_PosHÚPEXTI_EMR_EM20_MskOÚPEXTI_EMR_EM20áÚPEXTI_EMR_EM21_PosGÚPEXTI_EMR_EM21_MskNÚPEXTI_EMR_EM21àÚPEXTI_EMR_EM22_PosFÚPEXTI_EMR_EM22_MskMÚPEXTI_EMR_EM22ßÚPEXTI_EMR_EM23_PosEÚPEXTI_EMR_EM23_MskLÚPEXTI_EMR_EM23ÞÚPEXTI_EMR_EM24_PosDÚPEXTI_EMR_EM24_MskKÚPEXTI_EMR_EM24ÝÚPEXTI_EMR_EM25_PosCÚPEXTI_EMR_EM25_MskJÚPEXTI_EMR_EM25ÜÚPEXTI_EMR_EM26_PosBÚPEXTI_EMR_EM26_MskIÚPEXTI_EMR_EM26ÛÚPEXTI_EMR_EM28_Pos@ÚPEXTI_EMR_EM28_MskGÚPEXTI_EMR_EM28ÙÚPEXTI_EMR_EM29_Pos?ÚPEXTI_EMR_EM29_MskFÚPEXTI_EMR_EM29ØÚPEXTI_RTSR_RT0_PosÿÚPEXTI_RTSR_RT0_MskÚPEXTI_RTSR_RT0˜ÚPEXTI_RTSR_RT1_PosþÚPEXTI_RTSR_RT1_MskÚPEXTI_RTSR_RT1—ÚPEXTI_RTSR_RT2_PosýÚPEXTI_RTSR_RT2_MskÚPEXTI_RTSR_RT2–ÚPEXTI_RTSR_RT3_PosüÚPEXTI_RTSR_RT3_MskÚPEXTI_RTSR_RT3•ÚPEXTI_RTSR_RT4_PosûÚPEXTI_RTSR_RT4_MskÚPEXTI_RTSR_RT4”ÚPEXTI_RTSR_RT5_PosúÚPEXTI_RTSR_RT5_MskÚPEXTI_RTSR_RT5“ÚPEXTI_RTSR_RT6_PosùÚPEXTI_RTSR_RT6_MskÚPEXTI_RTSR_RT6’ÚPEXTI_RTSR_RT7_PosøÚPEXTI_RTSR_RT7_MskÿÚPEXTI_RTSR_RT7‘ÚPEXTI_RTSR_RT8_Pos÷ÚPEXTI_RTSR_RT8_MskþÚPEXTI_RTSR_RT8ÚPEXTI_RTSR_RT9_PosöÚPEXTI_RTSR_RT9_MskýÚPEXTI_RTSR_RT9ÚPEXTI_RTSR_RT10_PosÌÚPEXTI_RTSR_RT10_MskÓÚPEXTI_RTSR_RT10eÚPEXTI_RTSR_RT11_PosËÚPEXTI_RTSR_RT11_MskÒÚPEXTI_RTSR_RT11dÚPEXTI_RTSR_RT12_PosÊÚPEXTI_RTSR_RT12_MskÑÚPEXTI_RTSR_RT12cÚPEXTI_RTSR_RT13_PosÉÚPEXTI_RTSR_RT13_MskÐÚPEXTI_RTSR_RT13bÚPEXTI_RTSR_RT14_PosÈÚPEXTI_RTSR_RT14_MskÏÚPEXTI_RTSR_RT14aÚPEXTI_RTSR_RT15_PosÇÚPEXTI_RTSR_RT15_MskÎÚPEXTI_RTSR_RT15`ÚPEXTI_RTSR_RT16_PosÆÚPEXTI_RTSR_RT16_MskÍÚPEXTI_RTSR_RT16_ÚPEXTI_RTSR_RT17_PosÅÚPEXTI_RTSR_RT17_MskÌÚPEXTI_RTSR_RT17^ÚPEXTI_RTSR_RT19_PosÃÚPEXTI_RTSR_RT19_MskÊÚPEXTI_RTSR_RT19\ÚPEXTI_RTSR_RT20_PosËÚPEXTI_RTSR_RT20_MskÒÚPEXTI_RTSR_RT20dÚPEXTI_RTSR_RT21_PosÊÚPEXTI_RTSR_RT21_MskÑÚPEXTI_RTSR_RT21cÚPEXTI_RTSR_RT22_PosÉÚPEXTI_RTSR_RT22_MskÐÚPEXTI_RTSR_RT22bÚPEXTI_RTSR_TR0˜ÚPEXTI_RTSR_TR1—ÚPEXTI_RTSR_TR2–ÚPEXTI_RTSR_TR3•ÚPEXTI_RTSR_TR4”ÚPEXTI_RTSR_TR5“ÚPEXTI_RTSR_TR6’ÚPEXTI_RTSR_TR7‘ÚPEXTI_RTSR_TR8ÚPEXTI_RTSR_TR9ÚPEXTI_RTSR_TR10eÚPEXTI_RTSR_TR11dÚPEXTI_RTSR_TR12cÚPEXTI_RTSR_TR13bÚPEXTI_RTSR_TR14aÚPEXTI_RTSR_TR15`ÚPEXTI_RTSR_TR16_ÚPEXTI_RTSR_TR17^ÚPEXTI_RTSR_TR19\ÚPEXTI_RTSR_TR20dÚPEXTI_RTSR_TR21cÚPEXTI_RTSR_TR22bÚPEXTI_FTSR_FT0_PosÚPEXTI_FTSR_FT0_MskÚPEXTI_FTSR_FT0°ÚPEXTI_FTSR_FT1_PosÚPEXTI_FTSR_FT1_MskÚPEXTI_FTSR_FT1¯ÚPEXTI_FTSR_FT2_PosÚPEXTI_FTSR_FT2_MskÚPEXTI_FTSR_FT2®ÚPEXTI_FTSR_FT3_PosÚPEXTI_FTSR_FT3_MskÚPEXTI_FTSR_FT3­ÚPEXTI_FTSR_FT4_PosÚPEXTI_FTSR_FT4_MskÚPEXTI_FTSR_FT4¬ÚPEXTI_FTSR_FT5_PosÚPEXTI_FTSR_FT5_MskÚPEXTI_FTSR_FT5«ÚPEXTI_FTSR_FT6_PosÚPEXTI_FTSR_FT6_MskÚPEXTI_FTSR_FT6ªÚPEXTI_FTSR_FT7_PosÚPEXTI_FTSR_FT7_MskÚPEXTI_FTSR_FT7©ÚPEXTI_FTSR_FT8_PosÚPEXTI_FTSR_FT8_MskÚPEXTI_FTSR_FT8¨ÚPEXTI_FTSR_FT9_PosÚPEXTI_FTSR_FT9_MskÚPEXTI_FTSR_FT9§ÚPEXTI_FTSR_FT10_PosäÚPEXTI_FTSR_FT10_MskëÚPEXTI_FTSR_FT10}ÚPEXTI_FTSR_FT11_PosãÚPEXTI_FTSR_FT11_MskêÚPEXTI_FTSR_FT11|ÚPEXTI_FTSR_FT12_PosâÚPEXTI_FTSR_FT12_MskéÚPEXTI_FTSR_FT12{ÚPEXTI_FTSR_FT13_PosáÚPEXTI_FTSR_FT13_MskèÚPEXTI_FTSR_FT13zÚPEXTI_FTSR_FT14_PosàÚPEXTI_FTSR_FT14_MskçÚPEXTI_FTSR_FT14yÚPEXTI_FTSR_FT15_PosßÚPEXTI_FTSR_FT15_MskæÚPEXTI_FTSR_FT15xÚPEXTI_FTSR_FT16_PosÞÚPEXTI_FTSR_FT16_MskåÚPEXTI_FTSR_FT16wÚPEXTI_FTSR_FT17_PosÝÚPEXTI_FTSR_FT17_MskäÚPEXTI_FTSR_FT17vÚPEXTI_FTSR_FT19_PosÛÚPEXTI_FTSR_FT19_MskâÚPEXTI_FTSR_FT19tÚPEXTI_FTSR_FT20_PosãÚPEXTI_FTSR_FT20_MskêÚPEXTI_FTSR_FT20|ÚPEXTI_FTSR_FT21_PosâÚPEXTI_FTSR_FT21_MskéÚPEXTI_FTSR_FT21{ÚPEXTI_FTSR_FT22_PosáÚPEXTI_FTSR_FT22_MskèÚPEXTI_FTSR_FT22zÚPEXTI_FTSR_TR0¤ÚPEXTI_FTSR_TR1£ÚPEXTI_FTSR_TR2¢ÚPEXTI_FTSR_TR3¡ÚPEXTI_FTSR_TR4 ÚPEXTI_FTSR_TR5ŸÚPEXTI_FTSR_TR6žÚPEXTI_FTSR_TR7ÚPEXTI_FTSR_TR8œÚPEXTI_FTSR_TR9›ÚPEXTI_FTSR_TR10qÚPEXTI_FTSR_TR11pÚPEXTI_FTSR_TR12oÚPEXTI_FTSR_TR13nÚPEXTI_FTSR_TR14mÚPEXTI_FTSR_TR15lÚPEXTI_FTSR_TR16kÚPEXTI_FTSR_TR17jÚPEXTI_FTSR_TR19hÚPEXTI_FTSR_TR20pÚPEXTI_FTSR_TR21oÚPEXTI_FTSR_TR22nÚPEXTI_SWIER_SWI0_PosoÚPEXTI_SWIER_SWI0_MskvÚPEXTI_SWIER_SWI0ÚPEXTI_SWIER_SWI1_PosnÚPEXTI_SWIER_SWI1_MskuÚPEXTI_SWIER_SWI1ÚPEXTI_SWIER_SWI2_PosmÚPEXTI_SWIER_SWI2_MsktÚPEXTI_SWIER_SWI2ÚPEXTI_SWIER_SWI3_PoslÚPEXTI_SWIER_SWI3_MsksÚPEXTI_SWIER_SWI3ÚPEXTI_SWIER_SWI4_PoskÚPEXTI_SWIER_SWI4_MskrÚPEXTI_SWIER_SWI4ÚPEXTI_SWIER_SWI5_PosjÚPEXTI_SWIER_SWI5_MskqÚPEXTI_SWIER_SWI5ÚPEXTI_SWIER_SWI6_PosiÚPEXTI_SWIER_SWI6_MskpÚPEXTI_SWIER_SWI6ÚPEXTI_SWIER_SWI7_PoshÚPEXTI_SWIER_SWI7_MskoÚPEXTI_SWIER_SWI7ÚPEXTI_SWIER_SWI8_PosgÚPEXTI_SWIER_SWI8_MsknÚPEXTI_SWIER_SWI8ÚPEXTI_SWIER_SWI9_PosfÚPEXTI_SWIER_SWI9_MskmÚPEXTI_SWIER_SWI9ÿÚPEXTI_SWIER_SWI10_Pos<ÚPEXTI_SWIER_SWI10_MskCÚPEXTI_SWIER_SWI10ÕÚPEXTI_SWI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EXTI_PR_PIF0


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ÚPRCC_CFGR_PPRE2_DIV16ÙÚPRCC_CFGR_STOPWUCK_PosØÚPRCC_CFGR_STOPWUCK_MskßÚPRCC_CFGR_STOPWUCKqÚPRCC_CFGR_PLLSRC_PosŒÚPRCC_CFGR_PLLSRC_Msk“ÚPRCC_CFGR_PLLSRC%ÚPRCC_CFGR_PLLSRC_HSIÚÚPRCC_CFGR_PLLSRC_HSEÞÚPRCC_CFGR_PLLMUL_Pos†ÚPRCC_CFGR_PLLMUL_MskÚPRCC_CFGR_PLLMULÚPRCC_CFGR_PLLMUL_0ŒÚPRCC_CFGR_PLLMUL_1‹ÚPRCC_CFGR_PLLMUL_2ŠÚPRCC_CFGR_PLLMUL_3‰ÚPRCC_CFGR_PLLMUL3êÚPRCC_CFGR_PLLMUL4éÚPRCC_CFGR_PLLMUL6çÚPRCC_CFGR_PLLMUL8åÚPRCC_CFGR_PLLMUL12¸ÚPRCC_CFGR_PLLMUL16´ÚPRCC_CFGR_PLLMUL24µÚPRCC_CFGR_PLLMUL32¶ÚPRCC_CFGR_PLLMUL48¯ÚPRCC_CFGR_PLLDIV_Pos‘ÚPRCC_CFGR_PLLDIV_Msk˜ÚPRCC_CFGR_PLLDIV*ÚPRCC_CFGR_PLLDIV_0—ÚPRCC_CFGR_PLLDIV_1–ÚPRCC_CFGR_PLLDIV2_Pos]ÚPRCC_CFGR_PLLDIV2_MskdÚPRCC_CFGR_PLLDIV2öÚPRCC_CFGR_PLLDIV3_Pos\ÚPRCC_CFGR_PLLDIV3_MskcÚPRCC_CFGR_PLLDIV3õÚPRCC_CFGR_PLLDIV4_Pos[ÚPRCC_CFGR_PLLDIV4_MskbÚPRCC_CFGR_PLLDIV4ôÚPRCC_CFGR_MCOSEL_Pos™ÚPRCC_CFGR_MCOSEL_Msk ÚPRCC_CFGR_MCOSEL2ÚPRCC_CFGR_MCOSEL_0ŸÚPRCC_CFGR_MCOSEL_1žÚPRCC_CFGR_MCOSEL_2ÚPRCC_CFGR_MCOSEL_3œÚ PRCC_CFGR_MCOSEL_NOCLOCKºÚ#PRCC_CFGR_MCOSEL_SYSCLK_PosSÚ#PRCC_CFGR_MCOSEL_SYSCLK_MskZÚPRCC_CFGR_MCOSEL_SYSCLKìÚ PRCC_CFGR_MCOSEL_HSI_PosNÚ PRCC_CFGR_MCOSEL_HSI_MskUÚPRCC_CFGR_MCOSEL_HSIçÚ PRCC_CFGR_MCOSEL_MSI_PosIÚ PRCC_CFGR_MCOSEL_MSI_MskPÚPRCC_CFGR_MCOSEL_MSIâÚ PRCC_CFGR_MCOSEL_HSE_PosRÚ PRCC_CFGR_MCOSEL_HSE_MskYÚPRCC_CFGR_MCOSEL_HSEëÚ PRCC_CFGR_MCOSEL_PLL_PosJÚ PRCC_CFGR_MCOSEL_PLL_MskQÚPRCC_CFGR_MCOSEL_PLLãÚ PRCC_CFGR_MCOSEL_LSI_PosJÚ PRCC_CFGR_MCOSEL_LSI_MskQÚPRCC_CFGR_MCOSEL_LSIãÚ PRCC_CFGR_MCOSEL_LSE_PosNÚ PRCC_CFGR_MCOSEL_LSE_MskUÚPRCC_CFGR_MCOSEL_LSEçÚPRCC_CFGR_MCOPRE_Pos–ÚPRCC_CFGR_MCOPRE_MskÚPRCC_CFGR_MCOPRE/ÚPRCC_CFGR_MCOPRE_0œÚPRCC_CFGR_MCOPRE_1›ÚPRCC_CFGR_MCOPRE_2šÚPRCC_CFGR_MCOPRE_DIV1²ÚPRCC_CFGR_MCOPRE_DIV2±ÚPRCC_CFGR_MCOPRE_DIV4¯ÚPRCC_CFGR_MCOPRE_DIV8«ÚPRCC_CFGR_MCOPRE_DIV16zÚPRCC_CFGR_MCO_NOCLOCK¤ÚPRCC_CFGR_MCO_SYSCLKÖÚPRCC_CFGR_MCO_HSIÑÚPRCC_CFGR_MCO_MSIÌÚPRCC_CFGR_MCO_HSEÕÚPRCC_CFGR_MCO_PLLÍÚPRCC_CFGR_MCO_LSIÍÚPRCC_CFGR_MCO_LSEÑÚPRCC_CFGR_MCOSEL_HSI48uÚPRCC_CFGR_MCO_PREÎÚPRCC_CFGR_MCO_PRE_1:ÚPRCC_CFGR_MCO_PRE_29ÚPRCC_CFGR_MCO_PRE_47ÚPRCC_CFGR_MCO_PRE_83ÚPRCC_CFGR_MCO_PRE_16ÚPRCC_CIER_LSIRDYIE_PosòÚPRCC_CIER_LSIRDYIE_MskùÚPRCC_CIER_LSIRDYIE‹ÚPRCC_CIER_LSERDYIE_PosöÚPRCC_CIER_LSERDYIE_MskýÚPRCC_CIER_LSERDYIEÚPRCC_CIER_HSIRDYIE_PosöÚPRCC_CIER_HSIRDYIE_MskýÚPRCC_CIER_HSIRDYIEÚPRCC_CIER_HSERDYIE_PosúÚPRCC_CIER_HSERDYIE_MskÚPRCC_CIER_HSERDYIE“ÚPRCC_CIER_PLLRDYIE_PosòÚPRCC_CIER_PLLRDYIE_MskùÚPRCC_CIER_PLLRDYIE‹ÚPRCC_CIER_MSIRDYIE_PosñÚPRCC_CIER_MSIRDYIE_MskøÚPRCC_CIER_MSIRDYIEŠÚPRCC_CIER_CSSLSE_PosŽÚPRCC_CIER_CSSLSE_Msk•ÚPRCC_CIER_CSSLSE'ÚPRCC_CIER_LSECSSIE•ÚPRCC_CIFR_LSIRDYF_Pos;ÚPRCC_CIFR_LSIRDYF_MskBÚPRCC_CIFR_LSIRDYFÔÚPRCC_CIFR_LSERDYF_Pos?ÚPRCC_CIFR_LSERDYF_MskFÚPRCC_CIFR_LSERDYFØÚPRCC_CIFR_HSIRDYF_Pos?ÚPRCC_CIFR_HSIRDYF_MskFÚPRCC_CIFR_HSIRDYFØÚPRCC_CIFR_HSERDYF_PosCÚPRCC_CIFR_HSERDYF_MskJÚPRCC_CIFR_HSERDYFÜÚPRCC_CIFR_PLLRDYF_Pos;ÚPRCC_CIFR_PLLRDYF_MskBÚPRCC_CIFR_PLLRDYFÔÚPRCC_CIFR_MSIRDYF_Pos:ÚPRCC_CIFR_MSIRDYF_MskAÚPRCC_CIFR_MSIRDYFÓÚPRCC_CIFR_CSSLSEF_PosEÚPRCC_CIFR_CSSLSEF_MskLÚPRCC_CIFR_CSSLSEFÞÚPRCC_CIFR_CSSHSEF_PosIÚPRCC_CIFR_CSSHSEF_MskPÚPRCC_CIFR_CSSHSEFâÚPRCC_CIFR_LSECSSFÞÚPRCC_CIFR_CSSFÈÚPRCC_CICR_LSIRDYC_PosAÚPRCC_CICR_LSIRDYC_MskHÚPRCC_CICR_LSIRDYCÚÚPRCC_CICR_LSERDYC_PosEÚPRCC_CICR_LSERDYC_MskLÚPRCC_CICR_LSERDYCÞÚPRCC_CICR_HSIRDYC_PosEÚPRCC_CICR_HSIRDYC_MskLÚPRCC_CICR_HSIRDYCÞÚPRCC_CICR_HSERDYC_PosIÚPRCC_CICR_HSERDYC_MskPÚPRCC_CICR_HSERDYCâÚPRCC_CICR_PLLRDYC_PosAÚPRCC_CICR_PLLRDYC_MskHÚPRCC_CICR_PLLRDYCÚÚPRCC_CICR_MSIRDYC_Pos@ÚPRCC_CICR_MSIRDYC_MskGÚPRCC_CICR_MSIRDYCÙÚPRCC_CICR_CSSLSEC_PosKÚPRCC_CICR_CSSLSEC_MskRÚPRCC_CICR_CSSLSECäÚPRCC_CICR_CSSHSEC_PosOÚPRCC_CICR_CSSHSEC_MskVÚPRCC_CICR_CSSHSECèÚPRCC_CICR_LSECSSCäÚPRCC_CICR_CSSCÎÚ PRCC_IOPRSTR_IOPARST_Pos!Ú PRCC_IOPRSTR_IOPARST_Msk(ÚPRCC_IOPRSTR_IOPARSTºÚ PRCC_IOPRSTR_IOPBRST_Pos Ú PRCC_IOPRSTR_IOPBRST_Msk'ÚPRCC_IOPRSTR_IOPBRST¹Ú PRCC_IOPRSTR_IOPCRST_PosÚ PRCC_IOPRSTR_IOPCRST_Msk&ÚPRCC_IOPRSTR_IOPCRST¸Ú PRCC_IOPRSTR_IOPDRST_PosÚ PRCC_IOPRSTR_IOPDRST_Msk%ÚPRCC_IOPRSTR_IOPDRST·Ú PRCC_IOPRSTR_IOPERST_PosÚ PRCC_IOPRSTR_IOPERST_Msk$ÚPRCC_IOPRSTR_IOPERST¶Ú PRCC_IOPRSTR_IOPHRST_PosÚ PRCC_IOPRSTR_IOPHRST_Msk!ÚPRCC_IOPRSTR_IOPHRST³ÚPRCC_IOPRSTR_GPIOARSTqÚPRCC_IOPRSTR_GPIOBRSTpÚPRCC_IOPRSTR_GPIOCRSToÚPRCC_IOPRSTR_GPIODRSTnÚPRCC_IOPRSTR_GPIOERSTmÚPRCC_IOPRSTR_GPIOHRSTjÚPRCC_AHBRSTR_DMARST_Pos—ÚPRCC_AHBRSTR_DMARST_MskžÚPRCC_AHBRSTR_DMARST0ÚPRCC_AHBRSTR_MIFRST_PosÚPRCC_AHBRSTR_MIFRST_Msk”ÚPRCC_AHBRSTR_MIFRST&ÚPRCC_AHBRSTR_CRCRST_Pos‘ÚPRCC_AHBRSTR_CRCRST_Msk˜ÚPRCC_AHBRSTR_CRCRST*ÚPRCC_AHBRSTR_DMA1RSTýÚ#PRCC_APB2RSTR_SYSCFGRST_PosXÚ#PRCC_APB2RSTR_SYSCFGRST_Msk_ÚPRCC_APB2RSTR_SYSCFGRSTñÚ"PRCC_APB2RSTR_TIM21RST_PosÜÚ"PRCC_APB2RSTR_TIM21RST_MskãÚPRCC_APB2RSTR_TIM21RSTuÚ"PRCC_APB2RSTR_TIM22RST_PosÛÚ"PRCC_APB2RSTR_TIM22RST_MskâÚPRCC_APB2RSTR_TIM22RSTtÚ PRCC_APB2RSTR_ADCRST_PoseÚ PRCC_APB2RSTR_ADCRST_MsklÚPRCC_APB2RSTR_ADCRSTþÚ!PRCC_APB2RSTR_SPI1RST_PosÚ!PRCC_APB2RSTR_SPI1RST_MskÚPRCC_APB2RSTR_SPI1RST§Ú#PRCC_APB2RSTR_USART1RST_PosgÚ#PRCC_APB2RSTR_USART1RST_MsknÚPRCC_APB2RSTR_USART1RSTÚ PRCC_APB2RSTR_DBGRST_P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RTC_DR_DTäÚPRTC_DR_DT_0QÚPRTC_DR_DT_1PÚPRTC_DR_DU_PosJÚPRTC_DR_DU_MskQÚP


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ÚPTIM_CCMR1_IC1PSC_0wÚPTIM_CCMR1_IC1PSC_1vÚPTIM_CCMR1_IC1F_PosÚPTIM_CCMR1_IC1F_MskÚPTIM_CCMR1_IC1F®ÚPTIM_CCMR1_IC1F_0ÚPTIM_CCMR1_IC1F_1ÚPTIM_CCMR1_IC1F_2ÚPTIM_CCMR1_IC1F_3ÚPTIM_CCMR1_IC2PSC_PospÚPTIM_CCMR1_IC2PSC_MskwÚPTIM_CCMR1_IC2PSC    ÚPTIM_CCMR1_IC2PSC_0vÚPTIM_CCMR1_IC2PSC_1uÚPTIM_CCMR1_IC2F_PosÚPTIM_CCMR1_IC2F_MskÚPTIM_CCMR1_IC2F­ÚPTIM_CCMR1_IC2F_0ÚPTIM_CCMR1_IC2F_1ÚPTIM_CCMR1_IC2F_2ÚPTIM_CCMR1_IC2F_3ÚPTIM_CCMR2_CC3S_PosÚPTIM_CCMR2_CC3S_MskÚPTIM_CCMR2_CC3S¤ÚPTIM_CCMR2_CC3S_0ÚPTIM_CCMR2_CC3S_1ÚPTIM_CCMR2_OC3FE_PosÅÚPTIM_CCMR2_OC3FE_MskÌÚPTIM_CCMR2_OC3FE^ÚPTIM_CCMR2_OC3PE_Pos»ÚPTIM_CCMR2_OC3PE_MskÂÚPTIM_CCMR2_OC3PETÚPTIM_CCMR2_OC3M_PosÚPTIM_CCMR2_OC3M_MskÚPTIM_CCMR2_OC3MžÚPTIM_CCMR2_OC3M_0ÚPTIM_CCMR2_OC3M_1


ÚPTIM_CCMR2_OC3M_2    ÚPTIM_CCMR2_OC3CE_PosÈÚPTIM_CCMR2_OC3CE_MskÏÚPTIM_CCMR2_OC3CEaÚPTIM_CCMR2_CC4S_Pos


ÚPTIM_CCMR2_CC4S_MskÚPTIM_CCMR2_CC4S£ÚPTIM_CCMR2_CC4S_0ÚPTIM_CCMR2_CC4S_1ÚPTIM_CCMR2_OC4FE_PosÄÚPTIM_CCMR2_OC4FE_MskËÚPTIM_CCMR2_OC4FE]ÚPTIM_CCMR2_OC4PE_PosºÚPTIM_CCMR2_OC4PE_MskÁÚPTIM_CCMR2_OC4PESÚPTIM_CCMR2_OC4M_PosÚPTIM_CCMR2_OC4M_MskÚPTIM_CCMR2_OC4MÚPTIM_CCMR2_OC4M_0


ÚPTIM_CCMR2_OC4M_1    ÚPTIM_CCMR2_OC4M_2ÚPTIM_CCMR2_OC4CE_PosÇÚPTIM_CCMR2_OC4CE_MskÎÚPTIM_CCMR2_OC4CE`ÚPTIM_CCMR2_IC3PSC_PosnÚPTIM_CCMR2_IC3PSC_MskuÚPTIM_CCMR2_IC3PSCÚPTIM_CCMR2_IC3PSC_0tÚPTIM_CCMR2_IC3PSC_1sÚPTIM_CCMR2_IC3F_PosÚPTIM_CCMR2_IC3F_MskÚPTIM_CCMR2_IC3F«ÚPTIM_CCMR2_IC3F_0ÚPTIM_CCMR2_IC3F_1ÚPTIM_CCMR2_IC3F_2ÚPTIM_CCMR2_IC3F_3ÚPTIM_CCMR2_IC4PSC_PosmÚPTIM_CCMR2_IC4PSC_MsktÚPTIM_CCMR2_IC4PSCÚPTIM_CCMR2_IC4PSC_0sÚPTIM_CCMR2_IC4PSC_1rÚPTIM_CCMR2_IC4F_PosÚPTIM_CCMR2_IC4F_MskÚPTIM_CCMR2_IC4FªÚPTIM_CCMR2_IC4F_0ÚPTIM_CCMR2_IC4F_1ÚPTIM_CCMR2_IC4F_2ÚPTIM_CCMR2_IC4F_3ÚPTIM_CCER_CC1E_PosWÚPTIM_CCER_CC1E_Msk^ÚPTIM_CCER_CC1EðÚPTIM_CCER_CC1P_PosLÚPTIM_CCER_CC1P_MskSÚPTIM_CCER_CC1PåÚPTIM_CCER_CC1NP_PosüÚPTIM_CCER_CC1NP_MskÚPTIM_CCER_CC1NP•ÚPTIM_CCER_CC2E_PosVÚPTIM_CCER_CC2E_Msk]ÚPTIM_CCER_CC2EïÚPTIM_CCER_CC2P_PosKÚPTIM_CCER_CC2P_MskRÚPTIM_CCER_CC2PäÚPTIM_CCER_CC2NP_PosûÚPTIM_CCER_CC2NP_MskÚPTIM_CCER_CC2NP”ÚPTIM_CCER_CC3E_PosUÚPTIM_CCER_CC3E_Msk\ÚPTIM_CCER_CC3EîÚPTIM_CCER_CC3P_PosJÚPTIM_CCER_CC3P_MskQÚPTIM_CCER_CC3PãÚPTIM_CCER_CC3NP_PosúÚPTIM_CCER_CC3NP_MskÚPTIM_CCER_CC3NP“ÚPTIM_CCER_CC4E_PosTÚPTIM_CCER_CC4E_Msk[ÚPTIM_CCER_CC4EíÚPTIM_CCER_CC4P_PosIÚPTIM_CCER_CC4P_MskPÚPTIM_CCER_CC4PâÚPTIM_CCER_CC4NP_PosùÚPTIM_CCER_CC4NP_MskÚPTIM_CCER_CC4NP’ÚPTIM_CNT_CNT_PosªÚPTIM_CNT_CNT_Msk±ÚPTIM_CNT_CNTCÚPTIM_PSC_PSC_Pos¨ÚPTIM_PSC_PSC_Msk¯ÚPTIM_PSC_PSCAÚPTIM_ARR_ARR_PosªÚPTIM_ARR_ARR_Msk±ÚPTIM_ARR_ARRCÚPTIM_CCR1_CCR1_Pos^ÚPTIM_CCR1_CCR1_MskeÚPTIM_CCR1_CCR1÷ÚPTIM_CCR2_CCR2_Pos\ÚPTIM_CCR2_CCR2_MskcÚPTIM_CCR2_CCR2õÚPTIM_CCR3_CCR3_PosZÚPTIM_CCR3_CCR3_MskaÚPTIM_CCR3_CCR3óÚPTIM_CCR4_CCR4_PosXÚPTIM_CCR4_CCR4_Msk_ÚPTIM_CCR4_CCR4ñÚPTIM_DCR_DBA_PosÔÚPTIM_DCR_DBA_MskÛÚPTIM_DCR_DBAmÚPTIM_DCR_DBA_0ÚÚPTIM_DCR_DBA_1ÙÚPTIM_DCR_DBA_2ØÚPTIM_DCR_DBA_3×ÚPTIM_DCR_DBA_4ÖÚPTIM_DCR_DBL_PosÉÚPTIM_DCR_DBL_MskÐÚPTIM_DCR_DBLbÚPTIM_DCR_DBL_0ÏÚPTIM_DCR_DBL_1ÎÚPTIM_DCR_DBL_2ÍÚPTIM_DCR_DBL_3ÌÚPTIM_DCR_DBL_4ËÚPTIM_DMAR_DMAB_Pos8ÚPTIM_DMAR_DMAB_Msk?ÚPTIM_DMAR_DMABÑÚPTIM2_OR_ETR_RMP_Pos`ÚPTIM2_OR_ETR_RMP_MskgÚPTIM2_OR_ETR_RMPùÚPTIM2_OR_ETR_RMP_0fÚPTIM2_OR_ETR_RMP_1eÚPTIM2_OR_ETR_RMP_2dÚPTIM2_OR_TI4_RMP_PoszÚPTIM2_OR_TI4_RMP_MskÚPTIM2_OR_TI4_RMPÚPTIM2_OR_TI4_RMP_0€ÚPTIM2_OR_TI4_RMP_1ÚPTIM21_OR_ETR_RMP_Pos-ÚPTIM21_OR_ETR_RMP_Msk4ÚPTIM21_OR_ETR_RMPÆÚPTIM21_OR_ETR_RMP_03ÚPTIM21_OR_ETR_RMP_12ÚPTIM21_OR_TI1_RMP_PosJÚPTIM21_OR_TI1_RMP_MskQÚPTIM21_OR_TI1_RMPãÚPTIM21_OR_TI1_RMP_0PÚPTIM21_OR_TI1_RMP_1OÚPTIM21_OR_TI1_RMP_2NÚPTIM21_OR_TI2_RMP_PosIÚPTIM21_OR_TI2_RMP_MskPÚPTIM21_OR_TI2_RMPâÚPTIM22_OR_ETR_RMP_Pos,ÚPTIM22_OR_ETR_RMP_Msk3ÚPTIM22_OR_ETR_RMPÅÚPTIM22_OR_ETR_RMP_02ÚPTIM22_OR_ETR_RMP_11ÚPTIM22_OR_TI1_RMP_PosIÚPTIM22_OR_TI1_RMP_MskPÚPTIM22_OR_TI1_RMPâÚPTIM22_OR_TI1_RMP_0OÚPTIM22_OR_TI1_RMP_1NÚPTIM3_OR_ETR_RMP_Pos_ÚPTIM3_OR_ETR_RMP_MskfÚPTIM3_OR_ETR_RMPøÚPTIM3_OR_ETR_RMP_0eÚPTIM3_OR_ETR_RMP_1dÚPTIM3_OR_TI1_RMP_Pos|ÚPTIM3_OR_TI1_RMP_MskƒÚPTIM3_OR_TI1_RMPÚPTIM3_OR_TI2_RMP_Pos{ÚPTIM3_OR_TI2_RMP_Msk‚ÚPTIM3_OR_TI2_RMPÚPTIM3_OR_TI4_RMP_PosyÚPTIM3_OR_TI4_RMP_Msk€ÚPTIM3_OR_TI4_RMPÚPUSART_CR1_UE_PosmÚPUSART_CR1_UE_MsktÚP USART_CR1_UEÚPUSART_CR1_UESM_PosÉÚPUSART_CR1_UESM_MskÐÚPUSART_CR1_UESMbÚPUSART_CR1_RE_PospÚPUSART_CR1_RE_MskwÚP USART_CR1_RE    ÚPUSART_CR1_TE_PosnÚPUSART_CR1_TE_MskuÚP USART_CR1_TEÚPUSART_CR1_IDLEIE_PosSÚPUSART_CR1_IDLEIE_MskZÚPUSART_CR1_IDLEIEìÚPUSART_CR1_RXNEIE_Pos4ÚPUSART_CR1_RXNEIE_Msk;ÚPUSART_CR1_RXNEIEÍÚPUSART_CR1_TCIE_PosÞÚPUSART_CR1_TCIE_MskåÚPUSART_CR1_TCIEwÚPUSART_CR1_TXEIE_Pos‚ÚPUSART_CR1_TXEIE_Msk‰ÚPUSART_CR1_TXEIEÚPUSART_CR1_PEIE_PosàÚPUSART_CR1_PEIE_MskçÚPUSART_CR1_PEIEyÚPUSART_CR1_PS_PosdÚPUSART_CR1_PS_MskkÚP USART_CR1_PSýÚPUSART_CR1_PCE_Pos-ÚPUSART_CR1_PCE_Msk4ÚPUSART_CR1_PCEÆÚPUSART_CR1_WAKE_PosÛÚPUSART_CR1_WAKE_MskâÚPUSART_CR1_WAKEtÚPUSART_CR1_M_Pos¼ÚPUSART_CR1_M_MskÃÚPUSART_CR1_MUÚPUSART_CR1_M0_PosŠÚPUSART_CR1_M0_Msk‘ÚP USART_CR1_M0#ÚPUSART_CR1_MME_Pos&ÚPUSART_CR1_MME_Msk-ÚPUSART_CR1_MME¿ÚPUSART_CR1_CMIE_PosåÚPUSART_CR1_CMIE_MskìÚPUSART_CR1_CMIE~ÚPUSART_CR1_OVER8_PosÚPUSART_CR1_OVER8_Msk”ÚPUSART_CR1_OVER8&ÚPUSART_CR1_DEDT_PosâÚPUSART_CR1_DEDT_MskéÚPUSART_CR1_DEDT{ÚPUSART_CR1_DEDT_0èÚPUSART_CR1_DEDT_1çÚPUSART_CR1_DEDT_2æÚPUSART_CR1_DEDT_3åÚPUSART_CR1_DEDT_4äÚPUSART_CR1_DEAT_PosåÚPUSART_CR1_DEAT_MskìÚPUSART_CR1_DEAT~ÚPUSART_CR1_DEAT_0ëÚPUSART_CR1_DEAT_1êÚPUSART_CR1_DEAT_2éÚPUSART_CR1_DEAT_3èÚPUSART_CR1_DEAT_4çÚPUSART_CR1_RTOIE_Pos~ÚPUSART_CR1_RTOIE_Msk…ÚPUSART_CR1_RTOIEÚPUSART_CR1_EOBIE_PosÚPUSART_CR1_EOBIE_Msk¤ÚPUSART_CR1_EOBIE6ÚPUSART_CR1_M1_Pos‰ÚPUSART_CR1_M1_MskÚP USART_CR1_M1"ÚPUSART_CR2_ADDM7_Pos³ÚPUSART_CR2_ADDM7_MskºÚPUSART_CR2_ADDM7LÚPUSART_CR2_LBDL_PosäÚPUSART_CR2_LBDL_MskëÚPUSART_CR2_LBDL}ÚPUSART_CR2_LBDIE_Pos ÚPUSART_CR2_LBDIE_Msk§ÚPUSART_CR2_LBDIE9ÚPUSART_CR2_LBCL_PosåÚPUSART_CR2_LBCL_MskìÚPUSART_CR2_LBCL~ÚPUSART_CR2_CPHA_PosæÚPUSART_CR2_CPHA_MskíÚPUSART_CR2_CPHAÚPUSART_CR2_CPOL_PosÔÚPUSART_CR2_CPOL_MskÛÚPUSART_CR2_CPOLmÚPUSART_CR2_CLKEN_Pos“ÚPUSART_CR2_CLKEN_MskšÚPUSART_CR2_CLKEN,ÚPUSART_CR2_STOP_Pos¼ÚPUSART_CR2_STOP_MskÃÚPUSART_CR2_STOPUÚPUSART_CR2_STOP_0ÂÚPUSART_CR2_STOP_1ÁÚPUSART_CR2_LINEN_PosŠÚPUSART_CR2_LINEN_Msk‘ÚPUSART_CR2_LINEN#ÚPUSART_CR2_SWAP_PosÇÚPUSART_CR2_SWAP_MskÎÚPUSART_CR2_SWAP`ÚPUSART_CR2_RXINV_PosiÚPUSART_CR2_RXINV_MskpÚPUSART_CR2_RXINVÚPUSART_CR2_TXINV_PosgÚPUSART_CR2_TXINV_MsknÚPUSART_CR2_TXINVÚPUSART_CR2_DATAINV_PosõÚPUSART_CR2_DATAINV_MsküÚPUSART_CR2_DATAINVŽÚPUSART_CR2_MSBFIRST_PosÚPUSART_CR2_MSBFIRST_Msk—ÚPUSART_CR2_MSBFIRST)ÚPUSART_CR2_ABREN_Pos˜ÚPUSART_CR2_ABREN_MskŸÚPUSART_CR2_ABREN1ÚPUSART_CR2_ABRMODE_PosÚPUSART_CR2_ABRMODE_Msk    ÚPUSART_CR2_ABRMODE›ÚPUSART_CR2_ABRMODE_0ÚPUSART_CR2_ABRMODE_1ÚPUSART_CR2_RTOEN_PosxÚPUSART_CR2_RTOEN_MskÚPUSART_CR2_RTOENÚPUSART_CR2_ADD_Pos;ÚPUSART_CR2_ADD_MskBÚPUSART_CR2_ADDÔÚPUSART_CR3_EIE_Pos0ÚPUSART_CR3_EIE_Msk7ÚPUSART_CR3_EIEÉÚPUSART_CR3_IREN_PosÓÚPUSART_CR3_IREN_MskÚÚPUSART_CR3_IRENlÚPUSART_CR3_IRLP_PosÊÚPUSART_CR3_IRLP_MskÑÚPUSART_CR3_IRLPcÚPUSART_CR3_HDSEL_PosÚPUSART_CR3_HDSEL_Msk–ÚPUSART_CR3_HDSEL(ÚPUSART_CR3_NACK_PosäÚPUSART_CR3_NACK_MskëÚPUSART_CR3_NACK}ÚPUSART_CR3_SCEN_PosØÚPUSART_CR3_SCEN_MskßÚPUSART_CR3_SCENqÚPUSART_CR3_DMAR_PosÝÚPUSART_CR3_DMAR_MskäÚPUSART_CR3_DMARvÚPUSART_CR3_DMAT_PosÛÚPUSART_CR3_DMAT_MskâÚPUSART_CR3_DMATtÚPUSART_CR3_RTSE_PosÃÚPUSART_CR3_RTSE_MskÊÚPUSART_CR3_RTSE\ÚPUSART_CR3_CTSE_PosÒÚPUSART_CR3_CTSE_MskÙÚPUSART_CR3_CTSEkÚPUSART_CR3_CTSIE_Pos‡ÚPUSART_CR3_CTSIE_MskŽÚPUSART_CR3_CTSIE ÚPUSART_CR3_ONEBIT_Pos<ÚPUSART_CR3_ONEBIT_MskCÚPUSART_CR3_ONEBITÕÚPUSART_CR3_OVRDIS_Pos&ÚPUSART_CR3_OVRDIS_Msk-ÚPUSART_CR3_OVRDIS¿ÚPUSART_CR3_DDRE_PosâÚPUSART_CR3_DDRE_MskéÚPUSART_CR3_DDRE{ÚPUSART_CR3_DEM_Pos-ÚPUSART_CR3_DEM_Msk4ÚPUSART_CR3_DEMÆÚPUSART_CR3_DEP_Pos*ÚPUSART_CR3_DEP_Msk1ÚPUSART_CR3_DEPÃÚPUSART_CR3_SCARCNT_PosíÚPUSART_CR3_SCARCNT_MskôÚPUSART_CR3_SCARCNT†ÚPUSART_CR3_SCARCNT_0óÚPUSART_CR3_SCARCNT_1òÚPUSART_CR3_SCARCNT_2ñÚPUSART_CR3_WUS_PosÚPUSART_CR3_WUS_MskÚPUSART_CR3_WUSÚPUSART_CR3_WUS_0


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IS_TYPEERASEÚP IS_NBSECTORSÚPIS_OB_WDG_SOURCE®ÚP__HAL_I2C_RESET_CR2íÚ!P__HAL_I2C_GENERATE_STARTTÚP__HAL_I2C_FREQ_RANGEšÚP__HAL_I2C_RISE_TIMEÕÚ!P__HAL_I2C_SPEED_STANDARDkÚP__HAL_I2C_SPEED_FAST–ÚP__HAL_I2C_SPEED-Ú!P__HAL_I2C_7BIT_ADD_WRITEdÚ P__HAL_I2C_7BIT_ADD_READÕÚ P__HAL_I2C_10BIT_ADDRESSéÚ%P__HAL_I2C_10BIT_HEADER_WRITERÚ$P__HAL_I2C_10BIT_HEADER_READÃÚP__HAL_I2C_MEM_ADD_MSBJÚP__HAL_I2C_MEM_ADD_LSBKÚP__HAL_I2C_FREQRANGEûÚPIS_I2S_INSTANCE0ÚPIS_I2S_INSTANCE_EXTØÚP__IRDA_DISABLE~ÚP__IRDA_ENABLEÍÚ"P__HAL_IRDA_GETCLOCKSOURCEÚ$P__HAL_IRDA_MASK_COMPUTATIONFÚP__IRDA_GETCLOCKSOURCEGÚ P__IRDA_MASK_COMPUTATION‚ÚPIS_IRDA_ONEBIT_SAMPLEEÚ'P__HAL_IWDG_ENABLE_WRITE_ACCESSqÚ(P __HAL_IWDG_DISABLE_WRITE_ACCESS"Ú%P__HAL_LPTIM_ENABLE_INTERRUPTéÚ&P__HAL_LPTIM_DISABLE_INTERRUPTšÚ!P__HAL_LPTIM_GET_ITSTATUSÚP__OPAMP_CSR_OPAXPDúÚP__OPAMP_CSR_S3SELXÚP__OPAMP_CSR_S4SELXÚP__OPAMP_CSR_S5SELXÚP__OPAMP_CSR_S6SELXÚP__OPAMP_CSR_OPAXCAL_L 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ÚP__COMP_RELEASE_RESETtÚ P__COMP_CLK_SLEEP_ENABLE™Ú!P__COMP_CLK_SLEEP_DISABLEJÚP__CEC_FORCE_RESETpÚP__CEC_RELEASE_RESETÚÚP__CRC_CLK_DISABLE‡ÚP__CRC_CLK_ENABLEÖÚ P__CRC_CLK_SLEEP_DISABLE£ÚP__CRC_CLK_SLEEP_ENABLEòÚP__CRC_FORCE_RESETcÚP__CRC_RELEASE_RESETÍÚP__DAC_CLK_DISABLE—ÚP__DAC_CLK_ENABLEæÚP__DAC_FORCE_RESETsÚP__DAC_RELEASE_RESETÝÚP__DAC1_CLK_DISABLEdÚP__DAC1_CLK_ENABLE³Ú!P__DAC1_CLK_SLEEP_DISABLE€Ú P__DAC1_CLK_SLEEP_ENABLEÏÚP__DAC1_FORCE_RESET@ÚP__DAC1_RELEASE_RESETªÚP__DBGMCU_CLK_ENABLEöÚP__DBGMCU_CLK_DISABLE§ÚP__DBGMCU_FORCE_RESETƒÚP__DBGMCU_RELEASE_RESETíÚP__DFSDM_CLK_DISABLEíÚP__DFSDM_CLK_ENABLE<Ú"P__DFSDM_CLK_SLEEP_DISABLE    Ú!P__DFSDM_CLK_SLEEP_ENABLEXÚP__DFSDM_FORCE_RESETÉÚP__DFSDM_RELEASE_RESET3ÚP__DMA1_CLK_DISABLEZÚP__DMA1_CLK_ENABLE©Ú!P__DMA1_CLK_SLEEP_DISABLEvÚ P__DMA1_CLK_SLEEP_ENABLEÅÚP__DMA1_FORCE_RESET6ÚP__DMA1_RELEASE_RESET ÚP__DMA2_CLK_DISABLEYÚP__DMA2_CLK_ENABLE¨Ú!P__DMA2_CLK_SLEEP_DISABLEuÚ P__DMA2_CLK_SLEEP_ENABLEÄÚP__DMA2_FORCE_RESET5ÚP__DMA2_RELEASE_RESETŸÚP__ETHMAC_CLK_DISABLE§ÚP__ETHMAC_CLK_ENABLEöÚP__ETHMAC_FORCE_RESETƒÚP__ETHMAC_RELEASE_RESETíÚP__ETHMACRX_CLK_DISABLEùÚP__ETHMACRX_CLK_ENABLEHÚP__ETHMACTX_CLK_DISABLE÷ÚP__ETHMACTX_CLK_ENABLEFÚP__FIREWALL_CLK_DISABLEÿÚP__FIREWALL_CLK_ENABLENÚP__FLASH_CLK_DISABLEíÚP__FLASH_CLK_ENABLE<Ú"P__FLASH_CLK_SLEEP_DISABLE    Ú!P__FLASH_CLK_SLEEP_ENABLEXÚP__FLASH_FORCE_RESETÉÚP__FLASH_RELEASE_RESET3ÚP__FLITF_CLK_DISABLEæÚP__FLITF_CLK_ENABLE5ÚP__FLITF_FORCE_RESETÂÚP__FLITF_RELEASE_RESET,Ú!P__FLITF_CLK_SLEEP_ENABLEQÚ"P__FLITF_CLK_SLEEP_DISABLEÚP__FMC_CLK_DISABLE‰ÚP__FMC_CLK_ENABLEØÚ P__FMC_CLK_SLEEP_DISABLE¥ÚP__FMC_CLK_SLEEP_ENABLEôÚP__FMC_FORCE_RESETeÚP__FMC_RELEASE_RESETÏÚP__FSMC_CLK_DISABLE4ÚP__FSMC_CLK_ENABLEƒÚP__GPIOA_CLK_DISABLEëÚP__GPIOA_CLK_ENABLE:Ú"P__GPIOA_CLK_SLEEP_DISABLEÚ!P__GPIOA_CLK_SLEEP_ENABLEVÚP__GPIOA_FORCE_RESETÇÚP__GPIOA_RELEASE_RESET1ÚP__GPIOB_CLK_DISABLEêÚP__GPIOB_CLK_ENABLE9Ú"P__GPIOB_CLK_SLEEP_DISABLEÚ!P__GPIOB_CLK_SLEEP_ENABLEUÚP__GPIOB_FORCE_RESETÆÚP__GPIOB_RELEASE_RESET0ÚP__GPIOC_CLK_DISABLEéÚP__GPIOC_CLK_ENABLE8Ú"P__GPIOC_CLK_SLEEP_DISABLEÚ!P__GPIOC_CLK_SLEEP_ENABLETÚP__GPIOC_FORCE_RESETÅÚP__GPIOC_RELEASE_RESET/ÚP__GPIOD_CLK_DISABLEèÚP__GPIOD_CLK_ENABLE7Ú"P__GPIOD_CLK_SLEEP_DISABLEÚ!P__GPIOD_CLK_SLEEP_ENABLESÚP__GPIOD_FORCE_RESETÄÚP__GPIOD_RELEASE_RESET.ÚP__GPIOE_CLK_DISABLEçÚP__GPIOE_CLK_ENABLE6Ú"P__GPIOE_CLK_SLEEP_DISABLEÚ!P__GPIOE_CLK_SLEEP_ENABLERÚP__GPIOE_FORCE_RESETÃÚP__GPIOE_RELEASE_RESET-ÚP__GPIOF_CLK_DISABLEæÚP__GPIOF_CLK_ENABLE5Ú"P__GPIOF_CLK_SLEEP_DISABLEÚ!P__GPIOF_CLK_SLEEP_ENABLEQÚP__GPIOF_FORCE_RESETÂÚP__GPIOF_RELEASE_RESET,ÚP__GPIOG_CLK_DISABLEåÚP__GPIOG_CLK_ENABLE4Ú"P__GPIOG_CLK_SLEEP_DISABLEÚ!P__GPIOG_CLK_SLEEP_ENABLEPÚP__GPIOG_FORCE_RESETÁÚP__GPIOG_RELEASE_RESET+ÚP__GPIOH_CLK_DISABLEäÚP__GPIOH_CLK_ENABLE3Ú"P__GPIOH_CLK_SLEEP_DISABLEÚ!P__GPIOH_CLK_SLEEP_ENABLEOÚP__GPIOH_FORCE_RESETÀÚP__GPIOH_RELEASE_RESET*ÚP__I2C1_CLK_DISABLEnÚP__I2C1_CLK_ENABLE½Ú!P__I2C1_CLK_SLEEP_DISABLEŠÚ P__I2C1_CLK_SLEEP_ENABLEÙÚP__I2C1_FORCE_RESETJÚP__I2C1_RELEASE_RESET´ÚP__I2C2_CLK_DISABLEmÚP__I2C2_CLK_ENABLE¼Ú!P__I2C2_CLK_SLEEP_DISABLE‰Ú P__I2C2_CLK_SLEEP_ENABLEØÚP__I2C2_FORCE_RESETIÚP__I2C2_RELEASE_RESET³ÚP__I2C3_CLK_DISABLElÚP__I2C3_CLK_ENABLE»Ú!P__I2C3_CLK_SLEEP_DISABLEˆÚ P__I2C3_CLK_SLEEP_ENABLE×ÚP__I2C3_FORCE_RESETHÚP__I2C3_RELEASE_RESET²ÚP__LCD_CLK_DISABLEŒÚP__LCD_CLK_ENABLEÛÚ P__LCD_CLK_SLEEP_DISABLE¨ÚP__LCD_CLK_SLEEP_ENABLE÷ÚP__LCD_FORCE_RESEThÚP__LCD_RELEASE_RESETÒÚP__LPTIM1_CLK_DISABLE¢ÚP__LPTIM1_CLK_ENABLEñÚ#P__LPTIM1_CLK_SLEEP_DISABLE¾Ú"P__LPTIM1_CLK_SLEEP_ENABLE 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HAL_ERROR-Ú    HAL_BUSYvÚHAL_TIMEOUTŒÚHAL_StatusTypeDefvÚ HAL_UNLOCKED\ÚHAL_LOCKEDÚHAL_LockTypeDefuÚPUNUSEDëÚPHAL_MAX_DELAYÉÚPHAL_IS_BIT_SETVÚPHAL_IS_BIT_CLRaÚP__HAL_LINKDMA¿Ú!P__HAL_RESET_HANDLE_STATE;ÚP__HAL_LOCKœÚP __HAL_UNLOCKõÚP__ALIGN_ENDVÚP__ALIGN_BEGINÄÚP__RAM_FUNCŽÚP__NOINLINEÚPRCC_DBP_TIMEOUT_VALUE2ÚPRCC_LSE_TIMEOUT_VALUE$Ú"PCLOCKSWITCH_TIMEOUT_VALUEùÚPHSE_TIMEOUT_VALUEgÚPMSI_TIMEOUT_VALUE^ÚPHSI_TIMEOUT_VALUEcÚPLSI_TIMEOUT_VALUE_ÚPPLL_TIMEOUT_VALUE_ÚPRCC_OFFSET¹ÚPRCC_CR_OFFSET¿ÚPRCC_CFGR_OFFSET.ÚPRCC_CSR_OFFSETjÚPRCC_CR_BYTE2_ADDRESS­ÚPCIER_BYTE0_ADDRESS\ÚP CR_REG_INDEX


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"‚>    HSIStateÚ 


"‚>HSICalibrationValuešÚ 


"‚>    LSIStateÚ 


"‚>    MSIStateÚ 


"‚>MSICalibrationValue•Ú 


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"Ž>APB1CLKDivider<Ú 


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RCC_PLL_NONEÚPRCC_PLL_OFF\ÚPRCC_PLL_ONœÚPRCC_CLOCKTYPE_SYSCLK†ÚPRCC_CLOCKTYPE_HCLKAÚPRCC_CLOCKTYPE_PCLK1ÚPRCC_CLOCKTYPE_PCLK2ÚPRCC_SYSCLKSOURCE_MSIzÚPRCC_SYSCLKSOURCE_HSIÚPRCC_SYSCLKSOURCE_HSEƒÚ PRCC_SYSCLKSOURCE_PLLCLK›Ú$PRCC_SYSCLKSOURCE_STATUS_MSI)Ú$PRCC_SYSCLKSOURCE_STATUS_HSI.Ú$PRCC_SYSCLKSOURCE_STATUS_HSE2Ú'PRCC_SYSCLKSOURCE_STATUS_PLLCLKJÚPRCC_SYSCLK_DIV1*ÚPRCC_SYSCLK_DIV2)ÚPRCC_SYSCLK_DIV4'ÚPRCC_SYSCLK_DIV8#ÚPRCC_SYSCLK_DIV16òÚPRCC_SYSCLK_DIV64ïÚPRCC_SYSCLK_DIV128¼ÚPRCC_SYSCLK_DIV256ºÚPRCC_SYSCLK_DIV512¿ÚPRCC_HCLK_DIV1åÚPRCC_HCLK_DIV2äÚPRCC_HCLK_DIV4âÚPRCC_HCLK_DIV8ÞÚPRCC_HCLK_DIV16­ÚPRCC_RTC_HSE_DIV_2wÚPRCC_RTC_HSE_DIV_4uÚPRCC_RTC_HSE_DIV_8qÚPRCC_RTC_HSE_DIV_16@Ú PRCC_RTCCLKSOURCE_NO_CLKÚPRCC_RTCCLKSOURCE_LSE•ÚPRCC_RTCCLKSOURCE_LSI‘Ú"PRCC_RTCCLKSOURCE_HSE_DIVXõÚ"PRCC_RTCCLKSOURCE_HSE_DIV2Ú"PRCC_RTCCLKSOURCE_HSE_DIV4Ú"PRCC_RTCCLKSOURCE_HSE_DIV8Ú#PRCC_RTCCLKSOURCE_HSE_DIV16äÚP RCC_PLL_DIV2 ÚP RCC_PLL_DIV3ÚP RCC_PLL_DIV4ÚP RCC_PLL_MUL3ÚP RCC_PLL_MUL4ÚP RCC_PLL_MUL6ÚP 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RCC_MCODIV_8#ÚPRCC_MCODIV_16òÚPRCC_MCO1SOURCE_NOCLOCKÚPRCC_MCO1SOURCE_SYSCLKQÚPRCC_MCO1SOURCE_MSIGÚPRCC_MCO1SOURCE_HSILÚPRCC_MCO1SOURCE_LSELÚPRCC_MCO1SOURCE_LSIHÚPRCC_MCO1SOURCE_HSEPÚPRCC_MCO1SOURCE_PLLCLKhÚPRCC_IT_LSIRDY§ÚPRCC_IT_LSERDY«ÚPRCC_IT_HSIRDY«ÚPRCC_IT_HSERDY¯ÚPRCC_IT_PLLRDY§ÚPRCC_IT_MSIRDY¦ÚPRCC_IT_LSECSS±ÚPRCC_IT_CSS›ÚPRCC_FLAG_HSIRDY*ÚPRCC_FLAG_HSIDIV6ÚPRCC_FLAG_MSIRDY%ÚPRCC_FLAG_HSERDY.ÚPRCC_FLAG_PLLRDY&ÚPRCC_FLAG_LSIRDY&ÚPRCC_FLAG_LSERDY*ÚPRCC_FLAG_LSECSS0ÚPRCC_FLAG_OBLRST'ÚPRCC_FLAG_PINRSTÚPRCC_FLAG_PORRSTÚPRCC_FLAG_SFTRSTÚPRCC_FLAG_IWDGRST×ÚPRCC_FLAG_WWDGRSTÉÚPRCC_FLAG_LPWRRST½ÚPRCC_FLAG_FWRSTiÚ"P__HAL_RCC_DMA1_CLK_ENABLE.Ú!P__HAL_RCC_MIF_CLK_ENABLEWÚ!P__HAL_RCC_CRC_CLK_ENABLE[Ú#P__HAL_RCC_DMA1_CLK_DISABLEßÚ"P__HAL_RCC_MIF_CLK_DISABLEÚ"P__HAL_RCC_CRC_CLK_DISABLEÚ#P__HAL_RCC_GPIOA_CLK_ENABLE¿Ú#P__HAL_RCC_GPIOB_CLK_ENABLE¾Ú#P__HAL_RCC_GPIOC_CLK_ENABLE½Ú#P__HAL_RCC_GPIOH_CLK_ENABLE¸Ú$P__HAL_RCC_GPIOA_CLK_DISABLEpÚ$P__HAL_RCC_GPIOB_CLK_DISABLEoÚ$P__HAL_RCC_GPIOC_CLK_DISABLEnÚ$P__HAL_RCC_GPIOH_CLK_DISABLEiÚ"P__HAL_RCC_WWDG_CLK_ENABLEøÚ!P__HAL_RCC_PWR_CLK_ENABLE:Ú#P__HAL_RCC_WWDG_CLK_DISABLE©Ú"P__HAL_RCC_PWR_CLK_DISABLEëÚ$P__HAL_RCC_SYSCFG_CLK_ENABLE^Ú$P__HAL_RCC_DBGMCU_CLK_ENABLE{Ú%P__HAL_RCC_SYSCFG_CLK_DISABLEÚ%P__HAL_RCC_DBGMCU_CLK_DISABLE,Ú&P__HAL_RCC_DMA1_IS_CLK_ENABLEDçÚ%P__HAL_RCC_MIF_IS_CLK_ENABLEDÚ%P__HAL_RCC_CRC_IS_CLK_ENABLEDÚ'P__HAL_RCC_DMA1_IS_CLK_DISABLED˜Ú&P__HAL_RCC_MIF_IS_CLK_DISABLEDÁÚ&P__HAL_RCC_CRC_IS_CLK_DISABLEDÅÚ'P__HAL_RCC_GPIOA_IS_CLK_ENABLEDxÚ'P__HAL_RCC_GPIOB_IS_CLK_ENABLEDwÚ'P__HAL_RCC_GPIOC_IS_CLK_ENABLEDvÚ'P__HAL_RCC_GPIOH_IS_CLK_ENABLEDqÚ(P __HAL_RCC_GPIOA_IS_CLK_DISABLED)Ú(P __HAL_RCC_GPIOB_IS_CLK_DISABLED(Ú(P __HAL_RCC_GPIOC_IS_CLK_DISABLED'Ú(P __HAL_RCC_GPIOH_IS_CLK_DISABLED"Ú&P__HAL_RCC_WWDG_IS_CLK_ENABLED±Ú%P__HAL_RCC_PWR_IS_CLK_ENABLEDóÚ'P__HAL_RCC_WWDG_IS_CLK_DISABLEDbÚ&P__HAL_RCC_PWR_IS_CLK_DISABLED¤Ú(P __HAL_RCC_SYSCFG_IS_CLK_ENABLEDÚ(P __HAL_RCC_DBGMCU_IS_CLK_ENABLED4Ú)P!__HAL_RCC_SYSCFG_IS_CLK_DISABLEDÈÚ)P!__HAL_RCC_DBGMCU_IS_CLK_DISABLEDåÚ"P__HAL_RCC_AHB_FORCE_RESETõÚ#P__HAL_RCC_DMA1_FORCE_RESET»Ú"P__HAL_RCC_MIF_FORCE_RESETäÚ"P__HAL_RCC_CRC_FORCE_RESETèÚ$P__HAL_RCC_AHB_RELEASE_RESET_Ú$P__HAL_RCC_CRC_RELEASE_RESETRÚ%P__HAL_RCC_DMA1_RELEASE_RESET%Ú$P__HAL_RCC_MIF_RELEASE_RESETNÚ"P__HAL_RCC_IOP_FORCE_RESETØÚ$P__HAL_RCC_GPIOA_FORCE_RESETLÚ$P__HAL_RCC_GPIOB_FORCE_RESETKÚ$P__HAL_RCC_GPIOC_FORCE_RESETJÚ$P__HAL_RCC_GPIOH_FORCE_RESETEÚ$P__HAL_RCC_IOP_RELEASE_RESETBÚ&P__HAL_RCC_GPIOA_RELEASE_RESET¶Ú&P__HAL_RCC_GPIOB_RELEASE_RESETµÚ&P__HAL_RCC_GPIOC_RELEASE_RESET´Ú&P__HAL_RCC_GPIOH_RELEASE_RESET¯Ú#P__HAL_RCC_APB1_FORCE_RESETºÚ#P__HAL_RCC_WWDG_FORCE_RESET…Ú"P__HAL_RCC_PWR_FORCE_RESETÇÚ%P__HAL_RCC_APB1_RELEASE_RESET$Ú%P__HAL_RCC_WWDG_RELEASE_RESETïÚ$P__HAL_RCC_PWR_RELEASE_RESET1Ú#P__HAL_RCC_APB2_FORCE_RESET¹Ú%P__HAL_RCC_DBGMCU_FORCE_RESETÚ%P__HAL_RCC_SYSCFG_FORCE_RESETëÚ%P__HAL_RCC_APB2_RELEASE_RESET#Ú'P__HAL_RCC_DBGMCU_RELEASE_RESETrÚ'P__HAL_RCC_SYSCFG_RELEASE_RESETUÚ'P__HAL_RCC_CRC_CLK_SLEEP_ENABLEwÚ'P__HAL_RCC_MIF_CLK_SLEEP_ENABLEsÚ(P __HAL_RCC_SRAM_CLK_SLEEP_ENABLEÚ(P __HAL_RCC_DMA1_CLK_SLEEP_ENABLEJÚ(P __HAL_RCC_CRC_CLK_SLEEP_DISABLE(Ú(P __HAL_RCC_MIF_CLK_SLEEP_DISABLE$Ú)P!__HAL_RCC_SRAM_CLK_SLEEP_DISABLEËÚ)P!__HAL_RCC_DMA1_CLK_SLEEP_DISABLEûÚ)P!__HAL_RCC_GPIOA_CLK_SLEEP_ENABLEÛÚ)P!__HAL_RCC_GPIOB_CLK_SLEEP_ENABLEÚÚ)P!__HAL_RCC_GPIOC_CLK_SLEEP_ENABLEÙÚ)P!__HAL_RCC_GPIOH_CLK_SLEEP_ENABLEÔÚ*P"__HAL_RCC_GPIOA_CLK_SLEEP_DISABLEŒÚ*P"__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE‹Ú*P"__HAL_RCC_GPIOC_CLK_SLEEP_DISABLEŠÚ*P"__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE…Ú(P __HAL_RCC_WWDG_CLK_SLEEP_ENABLEÚ'P__HAL_RCC_PWR_CLK_SLEEP_ENABLEVÚ)P!__HAL_RCC_WWDG_CLK_SLEEP_DISABLEÅÚ(P __HAL_RCC_PWR_CLK_SLEEP_DISABLEÚ*P"__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLEzÚ*P"__HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE—Ú+P#__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE+Ú+P#__HAL_RCC_DBGMCU_CLK_SLEEP_DISABLEHÚ+P#__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED0Ú+P#__HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED,Ú,P$__HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLEDÓÚ,P$__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLEDÚ,P$__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLEDáÚ,P$__HAL_RCC_MIF_IS_CLK_SLEEP_DISABLEDÝÚ-P%__HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED„Ú-P%__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED´Ú-P%__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED”Ú-P%__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED“Ú-P%__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED’Ú-P%__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLEDÚ.P&__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLEDEÚ.P&__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLEDDÚ.P&__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLEDCÚ.P&__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED>Ú,P$__HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLEDÍÚ+P#__HAL_RCC_PWR_IS_CLK_SLEEP_ENABLEDÚ-P%__HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED~Ú,P$__HAL_RCC_PWR_IS_CLK_SLEEP_DISABLEDÀÚ.P&__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED3Ú.P&__HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLEDPÚ/P'__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLEDäÚ/P'__HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLEDÚP__HAL_RCC_HSI_CONFIGÚP__HAL_RCC_HSI_ENABLEÚP__HAL_RCC_HSI_DISABLEAÚ.P&__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUSTFÚP__HAL_RCC_LSI_ENABLEŒÚP__HAL_RCC_LSI_DISABLE=ÚP__HAL_RCC_HSE_CONFIG…ÚP__HAL_RCC_LSE_CONFIGÚP__HAL_RCC_MSI_ENABLE‹ÚP__HAL_RCC_MSI_DISABLE<Ú.P&__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUSTAÚ#P__HAL_RCC_MSI_RANGE_CONFIG¤Ú P__HAL_RCC_GET_MSI_RANGE€ÚP__HAL_RCC_PLL_ENABLEŒÚP__HAL_RCC_PLL_DISABLE=ÚP__HAL_RCC_PLL_CONFIG}Ú$P__HAL_RCC_GET_PLL_OSCSOURCE0Ú P__HAL_RCC_SYSCLK_CONFIG†Ú$P__HAL_RCC_GET_SYSCLK_SOURCE$ÚP__HAL_RCC_MCO1_CONFIGSÚ#P__HAL_RCC_RTC_CLKPRESCALER«ÚP__HAL_RCC_RTC_CONFIG|Ú!P__HAL_RCC_GET_RTC_SOURCEÚ(P __HAL_RCC_GET_RTC_HSE_PRESCALERýÚP__HAL_RCC_RTC_ENABLE‹ÚP__HAL_RCC_RTC_DISABLE<Ú$P__HAL_RCC_BACKUPRESET_FORCEeÚ&P__HAL_RCC_BACKUPRESET_RELEASEÏÚP__HAL_RCC_ENABLE_ITÙÚP__HAL_RCC_DISABLE_ITŠÚP__HAL_RCC_CLEAR_ITÚP__HAL_RCC_GET_IT¦Ú$P__HAL_RCC_CLEAR_RESET_FLAGSWÚP__HAL_RCC_GET_FLAG%Ú!P__STM32L0xx_HAL_RCC_EX_H


ÚPIS_RCC_PERIPHCLOCKAÚPIS_RCC_USART1CLKSOURCEÚPIS_RCC_USART2CLKSOURCEÚ PIS_RCC_LPUART1CLKSOURCE·ÚPIS_RCC_I2C1CLKSOURCE×ÚPIS_RCC_I2C3CLKSOURCEÕÚPIS_RCC_LPTIMCLKÚ PIS_RCC_STOPWAKEUP_CLOCKÚPIS_RCC_LSE_DRIVE¼Ú8


<unnamed>QÚ 


"¸@PeriphClockSelection¯Ú 


"¸@RTCClockSelection4Ú 


"¸@Usart1ClockSelection×Ú 


"¸@Usart2ClockSelectionÖÚ  


"¸@Lpuart1ClockSelectionlÚ 


"¸@I2c1ClockSelectionÚ 


"¸@I2c3ClockSelection


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"¸@LptimClockSelectionÚ!RCC_PeriphCLKInitTypeDefÚPRCC_EXTI_LINE_LSECSSÚPRCC_PERIPHCLK_USART1«ÚPRCC_PERIPHCLK_USART2ªÚPRCC_PERIPHCLK_LPUART1`ÚPRCC_PERIPHCLK_I2C1€ÚPRCC_PERIPHCLK_I2C2ÚPRCC_PERIPHCLK_RTCˆÚPRCC_PERIPHCLK_LPTIM1´ÚPRCC_PERIPHCLK_I2C3~Ú"PRCC_USART1CLKSOURCE_PCLK2<Ú#PRCC_USART1CLKSOURCE_SYSCLK½Ú PRCC_USART1CLKSOURCE_HSI¸Ú PRCC_USART1CLKSOURCE_LSE¸Ú"PRCC_USART2CLKSOURCE_PCLK1<Ú#PRCC_USART2CLKSOURCE_SYSCLK¼Ú PRCC_USART2CLKSOURCE_HSI·Ú PRCC_USART2CLKSOURCE_LSE·Ú#PRCC_LPUART1CLKSOURCE_PCLK1òÚ$PRCC_LPUART1CLKSOURCE_SYSCLKrÚ!PRCC_LPUART1CLKSOURCE_HSImÚ!PRCC_LPUART1CLKSOURCE_LSEmÚ PRCC_I2C1CLKSOURCE_PCLK1Ú!PRCC_I2C1CLKSOURCE_SYSCLK’ÚPRCC_I2C1CLKSOURCE_HSIÚ PRCC_I2C3CLKSOURCE_PCLK1Ú!PRCC_I2C3CLKSOURCE_SYSCLKÚPRCC_I2C3CLKSOURCE_HSI‹Ú!PRCC_TIMPRES_DESACTIVATEDpÚPRCC_TIMPRES_ACTIVATEDRÚ"PRCC_LPTIM1CLKSOURCE_PCLK1FÚ PRCC_LPTIM1CLKSOURCE_LSI½Ú PRCC_LPTIM1CLKSOURCE_HSIÁÚ PRCC_LPTIM1CLKSOURCE_LSEÁÚ!PRCC_STOP_WAKEUPCLOCK_MSI>Ú!PRCC_STOP_WAKEUPCLOCK_HSICÚPRCC_LSEDRIVE_LOWÅÚPRCC_LSEDRIVE_MEDIUMLOWøÚ PRCC_LSEDRIVE_MEDIUMHIGHÈÚPRCC_LSEDRIVE_HIGH•Ú#P__HAL_RCC_GPIOE_CLK_ENABLE»Ú$P__HAL_RCC_GPIOE_CLK_DISABLElÚ'P__HAL_RCC_GPIOE_IS_CLK_ENABLEDtÚ(P __HAL_RCC_GPIOE_IS_CLK_DISABLED%Ú#P__HAL_RCC_GPIOD_CLK_ENABLE¼Ú$P__HAL_RCC_GPIOD_CLK_DISABLEmÚ'P__HAL_RCC_GPIOD_IS_CLK_ENABLEDuÚ(P __HAL_RCC_GPIOD_IS_CLK_DISABLED&Ú"P__HAL_RCC_TIM2_CLK_ENABLEÚ"P__HAL_RCC_TIM3_CLK_ENABLEÚ"P__HAL_RCC_TIM6_CLK_ENABLEÚ"P__HAL_RCC_TIM7_CLK_ENABLEÚ"P__HAL_RCC_SPI2_CLK_ENABLEÚ$P__HAL_RCC_USART2_CLK_ENABLElÚ$P__HAL_RCC_USART4_CLK_ENABLEjÚ$P__HAL_RCC_USART5_CLK_ENABLEiÚ%P__HAL_RCC_LPUART1_CLK_ENABLE"Ú"P__HAL_RCC_I2C1_CLK_ENABLEBÚ"P__HAL_RCC_I2C2_CLK_ENABLEAÚ"P__HAL_RCC_I2C3_CLK_ENABLE@Ú!P__HAL_RCC_DAC_CLK_ENABLEkÚ$P__HAL_RCC_LPTIM1_CLK_ENABLEvÚ#P__HAL_RCC_TIM2_CLK_DISABLEÆÚ#P__HAL_RCC_TIM3_CLK_DISABLEÅÚ#P__HAL_RCC_TIM6_CLK_DISABLEÂÚ#P__HAL_RCC_TIM7_CLK_DISABLEÁÚ#P__HAL_RCC_SPI2_CLK_DISABLEÄÚ%P__HAL_RCC_USART2_CLK_DISABLEÚ%P__HAL_RCC_USART4_CLK_DISABLEÚ%P__HAL_RCC_USART5_CLK_DISABLEÚ&P__HAL_RCC_LPUART1_CLK_DISABLEÓÚ#P__HAL_RCC_I2C1_CLK_DISABLEóÚ#P__HAL_RCC_I2C2_CLK_DISABLEòÚ#P__HAL_RCC_I2C3_CLK_DISABLEñÚ"P__HAL_RCC_DAC_CLK_DISABLEÚ%P__HAL_RCC_LPTIM1_CLK_DISABLE'Ú&P__HAL_RCC_TIM2_IS_CLK_ENABLEDÎÚ&P__HAL_RCC_TIM3_IS_CLK_ENABLEDÍÚ&P__HAL_RCC_TIM6_IS_CLK_ENABLEDÊÚ&P__HAL_RCC_TIM7_IS_CLK_ENABLEDÉÚ&P__HAL_RCC_SPI2_IS_CLK_ENABLEDÌÚ(P __HAL_RCC_USART2_IS_CLK_ENABLED%Ú(P __HAL_RCC_USART4_IS_CLK_ENABLED#Ú(P __HAL_RCC_USART5_IS_CLK_ENABLED"Ú)P!__HAL_RCC_LPUART1_IS_CLK_ENABLEDÛÚ&P__HAL_RCC_I2C1_IS_CLK_ENABLEDûÚ&P__HAL_RCC_I2C2_IS_CLK_ENABLEDúÚ&P__HAL_RCC_I2C3_IS_CLK_ENABLEDùÚ%P__HAL_RCC_DAC_IS_CLK_ENABLED$Ú(P __HAL_RCC_LPTIM1_IS_CLK_ENABLED/Ú'P__HAL_RCC_TIM2_IS_CLK_DISABLEDÚ'P__HAL_RCC_TIM3_IS_CLK_DISABLED~Ú'P__HAL_RCC_TIM6_IS_CLK_DISABLED{Ú'P__HAL_RCC_TIM7_IS_CLK_DISABLEDzÚ'P__HAL_RCC_SPI2_IS_CLK_DISABLED}Ú)P!__HAL_RCC_USART2_IS_CLK_DISABLEDÖÚ)P!__HAL_RCC_USART4_IS_CLK_DISABLEDÔÚ)P!__HAL_RCC_USART5_IS_CLK_DISABLEDÓÚ*P"__HAL_RCC_LPUART1_IS_CLK_DISABLEDŒÚ'P__HAL_RCC_I2C1_IS_CLK_DISABLED¬Ú'P__HAL_RCC_I2C2_IS_CLK_DISABLED«Ú'P__HAL_RCC_I2C3_IS_CLK_DISABLEDªÚ&P__HAL_RCC_DAC_IS_CLK_DISABLEDÕÚ)P!__HAL_RCC_LPTIM1_IS_CLK_DISABLEDàÚ#P__HAL_RCC_TIM21_CLK_ENABLEâÚ#P__HAL_RCC_TIM22_CLK_ENABLEáÚ"P__HAL_RCC_ADC1_CLK_ENABLE8Ú"P__HAL_RCC_SPI1_CLK_ENABLEÚ$P__HAL_RCC_USART1_CLK_ENABLEmÚ$P__HAL_RCC_TIM21_CLK_DISABLE“Ú$P__HAL_RCC_TIM22_CLK_DISABLE’Ú#P__HAL_RCC_ADC1_CLK_DISABLEéÚ#P__HAL_RCC_SPI1_CLK_DISABLEÅÚ%P__HAL_RCC_USART1_CLK_DISABLEÚ&P__HAL_RCC_FIREWALL_CLK_ENABLEÓÚ'P__HAL_RCC_FIREWALL_CLK_DISABLE„Ú'P__HAL_RCC_TIM21_IS_CLK_ENABLED›Ú'P__HAL_RCC_TIM22_IS_CLK_ENABLEDšÚ&P__HAL_RCC_ADC1_IS_CLK_ENABLEDñÚ&P__HAL_RCC_SPI1_IS_CLK_ENABLEDÍÚ(P __HAL_RCC_USART1_IS_CLK_ENABLED&Ú(P __HAL_RCC_TIM21_IS_CLK_DISABLEDLÚ(P __HAL_RCC_TIM22_IS_CLK_DISABLEDKÚ'P__HAL_RCC_ADC1_IS_CLK_DISABLED¢Ú'P__HAL_RCC_SPI1_IS_CLK_DISABLED~Ú)P!__HAL_RCC_USART1_IS_CLK_DISABLED×Ú*P"__HAL_RCC_FIREWALL_IS_CLK_ENABLEDŒÚ+P#__HAL_RCC_FIREWALL_IS_CLK_DISABLED=Ú$P__HAL_RCC_GPIOE_FORCE_RESETHÚ&P__HAL_RCC_GPIOE_RELEASE_RESET²Ú$P__HAL_RCC_GPIOD_FORCE_RESETIÚ&P__HAL_RCC_GPIOD_RELEASE_RESET³Ú#P__HAL_RCC_TIM2_FORCE_RESET¢Ú#P__HAL_RCC_TIM3_FORCE_RESET¡Ú#P__HAL_RCC_TIM6_FORCE_RESETžÚ#P__HAL_RCC_TIM7_FORCE_RESETÚ%P__HAL_RCC_LPTIM1_FORCE_RESETÚ#P__HAL_RCC_I2C1_FORCE_RESETÏÚ#P__HAL_RCC_I2C2_FORCE_RESETÎÚ#P__HAL_RCC_I2C3_FORCE_RESETÍÚ%P__HAL_RCC_USART2_FORCE_RESETùÚ%P__HAL_RCC_USART4_FORCE_RESET÷Ú%P__HAL_RCC_USART5_FORCE_RESETöÚ&P__HAL_RCC_LPUART1_FORCE_RESET¯Ú#P__HAL_RCC_SPI2_FORCE_RESET Ú"P__HAL_RCC_DAC_FORCE_RESETøÚ%P__HAL_RCC_TIM2_RELEASE_RESETÚ%P__HAL_RCC_TIM3_RELEASE_RESETÚ%P__HAL_RCC_TIM6_RELEASE_RESETÚ%P__HAL_RCC_TIM7_RELEASE_RESETÚ'P__HAL_RCC_LPTIM1_RELEASE_RESETmÚ%P__HAL_RCC_I2C1_RELEASE_RESET9Ú%P__HAL_RCC_I2C2_RELEASE_RESET8Ú%P__HAL_RCC_I2C3_RELEASE_RESET7Ú'P__HAL_RCC_USART2_RELEASE_RESETcÚ'P__HAL_RCC_USART4_RELEASE_RESETaÚ'P__HAL_RCC_USART5_RELEASE_RESET`Ú(P __HAL_RCC_LPUART1_RELEASE_RESETÚ%P__HAL_RCC_SPI2_RELEASE_RESET


Ú$P__HAL_RCC_DAC_RELEASE_RESETbÚ%P__HAL_RCC_USART1_FORCE_RESETúÚ#P__HAL_RCC_ADC1_FORCE_RESETÅÚ#P__HAL_RCC_SPI1_FORCE_RESET¡Ú$P__HAL_RCC_TIM21_FORCE_RESEToÚ$P__HAL_RCC_TIM22_FORCE_RESETnÚ'P__HAL_RCC_USART1_RELEASE_RESETdÚ%P__HAL_RCC_ADC1_RELEASE_RESET/Ú%P__HAL_RCC_SPI1_RELEASE_RESETÚ&P__HAL_RCC_TIM21_RELEASE_RESETÙÚ&P__HAL_RCC_TIM22_RELEASE_RESETØÚ)P!__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE×Ú*P"__HAL_RCC_GPIOE_CLK_SLEEP_DISABLEˆÚ-P%__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLEDÚ.P&__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLEDAÚ)P!__HAL_RCC_GPIOD_CLK_SLEEP_ENABLEØÚ*P"__HAL_RCC_GPIOD_CLK_SLEEP_DISABLE‰Ú-P%__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED‘Ú.P&__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLEDBÚ(P __HAL_RCC_TIM2_CLK_SLEEP_ENABLE1Ú(P __HAL_RCC_TIM3_CLK_SLEEP_ENABLE0Ú(P __HAL_RCC_TIM6_CLK_SLEEP_ENABLE-Ú(P __HAL_RCC_TIM7_CLK_SLEEP_ENABLE,Ú(P __HAL_RCC_SPI2_CLK_SLEEP_ENABLE/Ú*P"__HAL_RCC_USART2_CLK_SLEEP_ENABLEˆÚ*P"__HAL_RCC_USART4_CLK_SLEEP_ENABLE†Ú*P"__HAL_RCC_USART5_CLK_SLEEP_ENABLE…Ú+P#__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE>Ú(P __HAL_RCC_I2C1_CLK_SLEEP_ENABLE^Ú(P __HAL_RCC_I2C2_CLK_SLEEP_ENABLE]Ú(P __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\Ú'P__HAL_RCC_DAC_CLK_SLEEP_ENABLE‡Ú*P"__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE’Ú)P!__HAL_RCC_TIM2_CLK_SLEEP_DISABLEâÚ)P!__HAL_RCC_TIM3_CLK_SLEEP_DISABLEáÚ)P!__HAL_RCC_TIM6_CLK_SLEEP_DISABLEÞÚ)P!__HAL_RCC_TIM7_CLK_SLEEP_DISABLEÝÚ)P!__HAL_RCC_SPI2_CLK_SLEEP_DISABLEàÚ+P#__HAL_RCC_USART2_CLK_SLEEP_DISABLE9Ú+P#__HAL_RCC_USART4_CLK_SLEEP_DISABLE7Ú+P#__HAL_RCC_USART5_CLK_SLEEP_DISABLE6Ú,P$__HAL_RCC_LPUART1_CLK_SLEEP_DISABLEïÚ)P!__HAL_RCC_I2C1_CLK_SLEEP_DISABLEÚ)P!__HAL_RCC_I2C2_CLK_SLEEP_DISABLEÚ)P!__HAL_RCC_I2C3_CLK_SLEEP_DISABLE Ú(P __HAL_RCC_DAC_CLK_SLEEP_DISABLE8Ú+P#__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLECÚ,P$__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLEDêÚ,P$__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLEDéÚ,P$__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLEDæÚ,P$__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLEDåÚ,P$__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLEDèÚ.P&__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLEDAÚ.P&__HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED?Ú.P&__HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED>Ú/P'__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED÷Ú,P$__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLEDÚ,P$__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLEDÚ,P$__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLEDÚ+P#__HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED@Ú.P&__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLEDKÚ-P%__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED›Ú-P%__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLEDšÚ-P%__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED—Ú-P%__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED–Ú-P%__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED™Ú/P'__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLEDòÚ/P'__HAL_RCC_USART4_IS_CLK_SLEEP_DISABLEDðÚ/P'__HAL_RCC_USART5_IS_CLK_SLEEP_DISABLEDïÚ0P(__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED¨Ú-P%__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLEDÈÚ-P%__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLEDÇÚ-P%__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLEDÆÚ,P$__HAL_RCC_DAC_IS_CLK_SLEEP_DISABLEDñÚ/P'__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLEDüÚ)P!__HAL_RCC_TIM21_CLK_SLEEP_ENABLEþÚ)P!__HAL_RCC_TIM22_CLK_SLEEP_ENABLEýÚ(P __HAL_RCC_ADC1_CLK_SLEEP_ENABLETÚ(P __HAL_RCC_SPI1_CLK_SLEEP_ENABLE0Ú*P"__HAL_RCC_USART1_CLK_SLEEP_ENABLE‰Ú*P"__HAL_RCC_TIM21_CLK_SLEEP_DISABLE¯Ú*P"__HAL_RCC_TIM22_CLK_SLEEP_DISABLE®Ú)P!__HAL_RCC_ADC1_CLK_SLEEP_DISABLEÚ)P!__HAL_RCC_SPI1_CLK_SLEEP_DISABLEáÚ+P#__HAL_RCC_USART1_CLK_SLEEP_DISABLE:Ú-P%__HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED·Ú-P%__HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED¶Ú,P$__HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED Ú,P$__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLEDéÚ.P&__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLEDBÚ.P&__HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLEDhÚ.P&__HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLEDgÚ-P%__HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED¾Ú-P%__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLEDšÚ/P'__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLEDóÚ(P __HAL_RCC_LSECSS_EXTI_ENABLE_ITüÚ)P!__HAL_RCC_LSECSS_EXTI_DISABLE_IT­Ú+P#__HAL_RCC_LSECSS_EXTI_ENABLE_EVENTÚ,P$__HAL_RCC_LSECSS_EXTI_DISABLE_EVENTÂÚ2P*__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGEÚ3P+__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGEÅÚ1P)__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGEGÚ2P*__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGEøÚ9P1__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGEÛÚ:P2__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGEŒÚ'P__HAL_RCC_LSECSS_EXTI_GET_FLAGHÚ)P!__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG½Ú,P$__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT¦ÚP__HAL_RCC_I2C1_CONFIGtÚ"P__HAL_RCC_GET_I2C1_SOURCEÚP__HAL_RCC_I2C3_CONFIGrÚ"P__HAL_RCC_GET_I2C3_SOURCEÚ P__HAL_RCC_USART1_CONFIGŸÚ$P__HAL_RCC_GET_USART1_SOURCE=Ú P__HAL_RCC_USART2_CONFIGžÚ$P__HAL_RCC_GET_USART2_SOURCE<Ú!P__HAL_RCC_LPUART1_CONFIGTÚ%P__HAL_RCC_GET_LPUART1_SOURCEòÚ P__HAL_RCC_LPTIM1_CONFIG¨Ú$P__HAL_RCC_GET_LPTIM1_SOURCEFÚ!P__HAL_RCC_HSISTOP_ENABLEBÚ"P__HAL_RCC_HSISTOP_DISABLEóÚ"P__HAL_RCC_LSEDRIVE_CONFIGýÚ(P __HAL_RCC_WAKEUPSTOP_CLK_CONFIGÚ!P__HAL_RCC_HSI_OUT_ENABLE1Ú"P__HAL_RCC_HSI_OUT_DISABLEâÚ,PeriphClkInit¡Ú"HAL_RCCEx_PeriphCLKConfigöÚ,PeriphClkInit¡Ú%HAL_RCCEx_GetPeriphCLKConfigÐÚ,


 


PeriphClkKÚ#HAL_RCCEx_GetPeriphCLKFreqœÚHAL_RCCEx_EnableLSECSS€Ú HAL_RCCEx_DisableLSECSSÚ"HAL_RCCEx_EnableLSECSS_IT~Ú$HAL_RCCEx_LSECSS_IRQHandler´Ú"HAL_RCCEx_LSECSS_CallbackUÚHAL_RCC_DeInit$Ú,RCC_OscInitStruct:ÚHAL_RCC_OscConfigàÚ,RCC_ClkInitStructEÚ,


    FLatency¹ÚHAL_RCC_ClockConfigÚ,


    RCC_MCOxAÚ,


RCC_MCOSource>Ú,


RCC_MCODiv’ÚHAL_RCC_MCOConfig&ÚHAL_RCC_EnableCSS+ÚHAL_RCC_NMI_IRQHandlerdÚHAL_RCC_CSSCallbackaÚ HAL_RCC_GetSysClockFreqvÚHAL_RCC_GetHCLKFreq‡ÚHAL_RCC_GetPCLK1FreqLÚHAL_RCC_GetPCLK2FreqKÚ,RCC_OscInitStruct:ÚHAL_RCC_GetOscConfigºÚ,RCC_ClkInitStructEÚ,


pFLatency9ÚHAL_RCC_GetClockConfigïÚP__STM32L0xx_HAL_EXTI_H¨ÚHAL_EXTI_COMMON_CB_IDmÚHAL_EXTI_RISING_CB_IDjÚHAL_EXTI_FALLING_CB_ID7ÚEXTI_CallbackIDTypeDefñÚ8


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"„CLinerÚ "„CPendingCallbackÚEXTI_HandleTypeDefGÚ8


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"ˆCLinenÚ 


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"ˆCGPIOSelÚEXTI_ConfigTypeDef=ÚPEXTI_LINE_0eÚPEXTI_LINE_1dÚPEXTI_LINE_2cÚPEXTI_LINE_3bÚPEXTI_LINE_4aÚPEXTI_LINE_5`ÚPEXTI_LINE_6_ÚPEXTI_LINE_7^ÚPEXTI_LINE_8]ÚPEXTI_LINE_9\ÚP EXTI_LINE_102ÚP EXTI_LINE_111ÚP EXTI_LINE_120ÚP EXTI_LINE_13/ÚP EXTI_LINE_14.ÚP EXTI_LINE_15-ÚP EXTI_LINE_16,ÚP EXTI_LINE_17+ÚP EXTI_LINE_18*ÚP EXTI_LINE_19)ÚP EXTI_LINE_201ÚP EXTI_LINE_210ÚP EXTI_LINE_22/ÚP EXTI_LINE_23.ÚP EXTI_LINE_24-ÚP EXTI_LINE_25,ÚP EXTI_LINE_26+ÚP EXTI_LINE_27*ÚP EXTI_LINE_28)ÚP EXTI_LINE_29(ÚPEXTI_MODE_NONEbÚPEXTI_MODE_INTERRUPT»ÚPEXTI_MODE_EVENTÚPEXTI_TRIGGER_NONEmÚPEXTI_TRIGGER_RISINGÍÚPEXTI_TRIGGER_FALLINGšÚ$PEXTI_TRIGGER_RISING_FALLINGaÚPEXTI_GPIOA®ÚPEXTI_GPIOB­ÚPEXTI_GPIOC¬ÚPEXTI_GPIOD«ÚPEXTI_GPIOEªÚPEXTI_GPIOH§ÚPEXTI_PROPERTY_SHIFTªÚPEXTI_DIRECTaÚPEXTI_CONFIGfÚP


EXTI_GPIOñÚPEXTI_RESERVED¸ÚPEXTI_PROPERTY_MASKþÚPEXTI_PIN_MASK¦ÚPEXTI_MODE_MASKfÚPEXTI_TRIGGER_MASKqÚP EXTI_LINE_NBÚP IS_EXTI_LINE÷ÚP IS_EXTI_MODEúÚPIS_EXTI_TRIGGERÚPIS_EXTI_PENDING_EDGE–ÚPIS_EXTI_CONFIG_LINEÔÚPIS_EXTI_GPIO_PORTBÚPIS_EXTI_GPIO_PIN¢Ú,hexti¥Ú,pExtiConfig[ÚHAL_EXTI_SetConfigLineåÚ,hexti¥Ú,pExtiConfig[ÚHAL_EXTI_GetConfigLineñÚ,hexti¥Ú!HAL_EXTI_ClearConfigLine&Ú,hexti¥Ú,"CallbackIDÚ, pPendingCbfnÚ"HAL_EXTI_RegisterCallback—Ú,hexti¥Ú,


    ExtiLine­ÚHAL_EXTI_GetHandle‹Ú,hexti¥ÚHAL_EXTI_IRQHandlerKÚ,hexti¥Ú ,


EdgebÚHAL_EXTI_GetPendingÚ,hexti¥Ú ,


EdgebÚHAL_EXTI_ClearPendingEÚ,hexti¥ÚHAL_EXTI_GenerateSWIÕÚP__STM32L0xx_HAL_GPIO_H³Ú8


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AlternateðÚGPIO_InitTypeDefÚGPIO_PIN_RESETŠÚ GPIO_PIN_SET%ÚGPIO_PinState1ÚPIS_GPIO_PIN_ACTIONÚPGPIO_PIN_0³ÚPGPIO_PIN_1²ÚPGPIO_PIN_2±ÚPGPIO_PIN_3°ÚPGPIO_PIN_4¯ÚPGPIO_PIN_5®ÚPGPIO_PIN_6­ÚPGPIO_PIN_7¬ÚPGPIO_PIN_8«ÚPGPIO_PIN_9ªÚPGPIO_PIN_10€ÚPGPIO_PIN_11ÚPGPIO_PIN_12~ÚPGPIO_PIN_13}ÚPGPIO_PIN_14|ÚPGPIO_PIN_15{ÚP GPIO_PIN_AllÆÚPGPIO_PIN_MASK±ÚPIS_GPIO_PINEÚPGPIO_MODE_INPUTÚPGPIO_MODE_OUTPUT_PP£ÚPGPIO_MODE_OUTPUT_OD°ÚPGPIO_MODE_AF_PPÚPGPIO_MODE_AF_OD"ÚPGPIO_MODE_ANALOGçÚPGPIO_MODE_IT_RISINGËÚPGPIO_MODE_IT_FALLING˜Ú$PGPIO_MODE_IT_RISING_FALLING_ÚPGPIO_MODE_EVT_RISINGwÚPGPIO_MODE_EVT_FALLINGDÚ%PGPIO_MODE_EVT_RISING_FALLINGÚP IS_GPIO_MODEÚPGPIO_SPEED_FREQ_LOWÈÚPGPIO_SPEED_FREQ_MEDIUMóÚPGPIO_SPEED_FREQ_HIGH˜Ú"PGPIO_SPEED_FREQ_VERY_HIGHéÚPIS_GPIO_SPEED·ÚPGPIO_NOPULLMÚPGPIO_PULLUPEÚPGPIO_PULLDOWN®ÚP IS_GPIO_PULLíÚ!P__HAL_GPIO_EXTI_GET_FLAG)Ú#P__HAL_GPIO_EXTI_CLEAR_FLAGžÚP__HAL_GPIO_EXTI_GET_ITªÚ!P__HAL_GPIO_EXTI_CLEAR_ITÚ&P__HAL_GPIO_EXTI_GENERATE_SWIT‡Ú"P__STM32L0xx_HAL_GPIO_EX_H±ÚPGPIO_AF0_EVENTOUT‹ÚPGPIO_AF0_TIM21¾ÚPGPIO_AF0_SPI1ðÚP GPIO_AF0_MCO0ÚPGPIO_AF0_SWDIO…ÚPGPIO_AF0_SWCLK‡ÚPGPIO_AF0_USART1IÚPGPIO_AF0_SPI2ïÚPGPIO_AF0_LPTIM1RÚPGPIO_AF0_TIM22½ÚPGPIO_AF0_LPUART1þÚPGPIO_AF0_USART2HÚPGPIO_AF0_TIM2ñÚPGPIO_AF1_I2C1ÚPGPIO_AF1_SPI2îÚPGPIO_AF1_TIM21½ÚPGPIO_AF2_TIM2ïÚPGPIO_AF2_TIM3îÚPGPIO_AF2_EVENTOUT‰ÚPGPIO_AF2_LPTIM1PÚPGPIO_AF2_LPUART1üÚP GPIO_AF2_MCO.ÚP GPIO_AF2_RTC$ÚPGPIO_AF2_SPI2íÚPGPIO_AF2_USART5CÚPGPIO_AF2_SPI1îÚPGPIO_AF3_EVENTOUTˆÚPGPIO_AF3_I2C1ÚPGPIO_AF4_USART2DÚPGPIO_AF4_LPUART1úÚPGPIO_AF4_USART1EÚPGPIO_AF4_EVENTOUT‡ÚPGPIO_AF4_TIM22¹ÚPGPIO_AF4_TIM3ìÚPGPIO_AF4_I2C1ÚPGPIO_AF5_TIM2ìÚPGPIO_AF5_TIM21¹ÚPGPIO_AF5_TIM22¸ÚPGPIO_AF5_USART1DÚPGPIO_AF5_SPI2êÚPGPIO_AF5_I2C2ÚPGPIO_AF6_USART4@ÚPGPIO_AF6_LPUART1øÚPGPIO_AF6_EVENTOUT…ÚPGPIO_AF6_I2C1ÚPGPIO_AF6_I2C2ÚPGPIO_AF6_USART5?ÚPGPIO_AF6_TIM21¸ÚPGPIO_AF7_COMP1¤ÚPGPIO_AF7_COMP2£ÚPGPIO_AF7_I2C3ÚPGPIO_AF7_LPUART1÷ÚPIS_GPIO_AF§ÚPGPIOA_PIN_AVAILABLEÚPGPIOB_PIN_AVAILABLEÚPGPIOC_PIN_AVAILABLE ÚPGPIOD_PIN_AVAILABLEÚPGPIOE_PIN_AVAILABLEÚPGPIOH_PIN_AVAILABLEÚPGPIO_GET_INDEXjÚPIS_GPIO_PIN_AVAILABLEQÚ,GPIOx Ú,


GPIO_InitÚHAL_GPIO_InitxÚ,GPIOx Ú,


    GPIO_PinÚHAL_GPIO_DeInitËÚ,GPIOx Ú,    GPIO_PinÚHAL_GPIO_ReadPincÚ,GPIOx Ú,    GPIO_PinÚ,"    PinState’ÚHAL_GPIO_WritePinÒÚ,GPIOx Ú,    GPIO_PinÚHAL_GPIO_TogglePinyÚ,GPIOx Ú,    GPIO_PinÚHAL_GPIO_LockPinVÚ,    GPIO_PinÚ!HAL_GPIO_EXTI_IRQHandler³Ú,    GPIO_PinÚHAL_GPIO_EXTI_CallbackTÚPGPIO_MODE_PosmÚP


GPIO_MODEÚPMODE_INPUT£ÚPMODE_OUTPUT@ÚPMODE_AF²ÚPMODE_ANALOGÚPOUTPUT_TYPE_PosŠÚPOUTPUT_TYPE#ÚP


OUTPUT_PPÉÚP


OUTPUT_ODÖÚPEXTI_MODE_PosbÚP


EXTI_MODEûÚPEXTI_IT‡ÚP    EXTI_EVT3ÚPTRIGGER_MODE_Pos‚ÚP TRIGGER_MODEÚPTRIGGER_RISINGpÚPTRIGGER_FALLING=ÚPSTM32L0xx_HAL_DMA_HÔÚ8


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"…ERequestÚ 


"…E


DirectionLÚ 


"…E


PeriphInckÚ 


"…EMemIncºÚ 


"…EPeriphDataAlignmentXÚ 


"…EMemDataAlignment§Ú 


"…EModerÚ 


"…E    PriorityÚDMA_InitTypeDefmÚHAL_DMA_STATE_RESETÚHAL_DMA_STATE_READYÚHAL_DMA_STATE_BUSYQÚHAL_DMA_STATE_TIMEOUTgÚHAL_DMA_StateTypeDefÂÚHAL_DMA_FULL_TRANSFERwÚHAL_DMA_HALF_TRANSFERÚ%HAL_DMA_LevelCompleteTypeDef‚Ú HAL_DMA_XFER_CPLT_CB_IDÓÚ$HAL_DMA_XFER_HALFCPLT_CB_ID°Ú!HAL_DMA_XFER_ERROR_CB_IDzÚ!HAL_DMA_XFER_ABORT_CB_IDŒÚHAL_DMA_XFER_ALL_CB_ID/Ú"HAL_DMA_CallbackIDTypeDefÚ8__DMA_HandleTypeDef³Ú "E    Instance”Ú " EInitÚ ""ELockAÚ ""EStateÇÚ "EParentcÚ "EXferCpltCallback„Ú "EXferHalfCpltCallbackÚ "EXferErrorCallbackÚ "EXferAbortCallbackÚ 


"E


ErrorCodePÚ "EDmaBaseAddressjÚ 


"E ChannelIndexÚDMA_HandleTypeDef±ÚPHAL_DMA_ERROR_NONE)ÚPHAL_DMA_ERROR_TEÄÚPHAL_DMA_ERROR_NO_XFER"ÚPHAL_DMA_ERROR_TIMEOUT,Ú$PHAL_DMA_ERROR_NOT_SUPPORTED1ÚPDMA_REQUEST_0ÈÚPDMA_REQUEST_1ÇÚPDMA_REQUEST_2ÆÚPDMA_REQUEST_3ÅÚPDMA_REQUEST_4ÄÚPDMA_REQUEST_5ÃÚPDMA_REQUEST_6ÂÚPDMA_REQUEST_7ÁÚPDMA_REQUEST_8ÀÚPDMA_REQUEST_9¿ÚPDMA_REQUEST_10•ÚPDMA_REQUEST_12“ÚPDMA_REQUEST_13’ÚPDMA_REQUEST_14‘ÚPDMA_REQUEST_15ÚPIS_DMA_ALL_REQUESTÚPDMA_PERIPH_TO_MEMORYpÚPDMA_MEMORY_TO_PERIPHpÚPDMA_MEMORY_TO_MEMORY_ÚPDMA_PINC_ENABLELÚPDMA_PINC_DISABLEýÚPDMA_MINC_ENABLEOÚPDMA_MINC_DISABLEÚPDMA_PDATAALIGN_BYTEÚ PDMA_PDATAALIGN_HALFWORDáÚPDMA_PDATAALIGN_WORDÚPDMA_MDATAALIGN_BYTEÚ PDMA_MDATAALIGN_HALFWORDäÚPDMA_MDATAALIGN_WORDÚPDMA_NORMAL½ÚP DMA_CIRCULAR-ÚPDMA_PRIORITY_LOW§ÚPDMA_PRIORITY_MEDIUMÒÚPDMA_PRIORITY_HIGHwÚPDMA_PRIORITY_VERY_HIGHÈÚP


DMA_IT_TCõÚP


DMA_IT_HTðÚP


DMA_IT_TEóÚP DMA_FLAG_GL1EÚP DMA_FLAG_TC1AÚP DMA_FLAG_HT1<ÚP DMA_FLAG_TE1?ÚP DMA_FLAG_GL2DÚP DMA_FLAG_TC2@ÚP DMA_FLAG_HT2;ÚP DMA_FLAG_TE2>ÚP DMA_FLAG_GL3CÚP DMA_FLAG_TC3?ÚP DMA_FLAG_HT3:ÚP DMA_FLAG_TE3=ÚP DMA_FLAG_GL4BÚP DMA_FLAG_TC4>ÚP DMA_FLAG_HT49ÚP DMA_FLAG_TE4<ÚP DMA_FLAG_GL5AÚP DMA_FLAG_TC5=ÚP DMA_FLAG_HT58ÚP DMA_FLAG_TE5;ÚP DMA_FLAG_GL6@ÚP DMA_FLAG_TC6<ÚP DMA_FLAG_HT67ÚP DMA_FLAG_TE6:ÚP DMA_FLAG_GL7?ÚP DMA_FLAG_TC7;ÚP DMA_FLAG_HT76ÚP DMA_FLAG_TE79Ú%P__HAL_DMA_RESET_HANDLE_STATEÚP__HAL_DMA_ENABLEáÚP__HAL_DMA_DISABLE’Ú$P__HAL_DMA_GET_TC_FLAG_INDEXLÚ$P__HAL_DMA_GET_HT_FLAG_INDEXGÚ$P__HAL_DMA_GET_TE_FLAG_INDEXJÚ$P__HAL_DMA_GET_GI_FLAG_INDEXSÚP__HAL_DMA_GET_FLAG+ÚP__HAL_DMA_CLEAR_FLAG ÚP__HAL_DMA_ENABLE_ITßÚP__HAL_DMA_DISABLE_ITÚ P__HAL_DMA_GET_IT_SOURCEnÚP__HAL_DMA_GET_COUNTERÚ ,hdma/Ú HAL_DMA_Init×Ú ,hdma/ÚHAL_DMA_DeInit*Ú ,hdma/Ú,


SrcAddressÝÚ,


DstAddressÚÚ,


DataLengthïÚHAL_DMA_Start[Ú ,hdma/Ú,


SrcAddressÝÚ,


DstAddressÚÚ,


DataLengthïÚHAL_DMA_Start_ITYÚ ,hdma/ÚHAL_DMA_AbortqÚ ,hdma/ÚHAL_DMA_Abort_IToÚ ,hdma/Ú,"CompleteLevelÚ,


TimeoutêÚ HAL_DMA_PollForTransferRÚ ,hdma/ÚHAL_DMA_IRQHandlerµÚ ,hdma/Ú,"CallbackIDÚ,


pCallbackBÚ!HAL_DMA_RegisterCallbackÚ ,hdma/Ú,"CallbackIDÚ#HAL_DMA_UnRegisterCallback:Ú ,hdma/ÚHAL_DMA_GetStateBÚ ,hdma/ÚHAL_DMA_GetError9ÚPIS_DMA_DIRECTIONÞÚPIS_DMA_BUFFER_SIZE'Ú$PIS_DMA_PERIPHERAL_INC_STATEdÚ PIS_DMA_MEMORY_INC_STATEÚ$PIS_DMA_PERIPHERAL_DATA_SIZEjÚ PIS_DMA_MEMORY_DATA_SIZE…ÚPIS_DMA_MODEdÚPIS_DMA_PRIORITYÿÚ!P__STM32L0xx_HAL_CORTEX_H    Ú8


<unnamed>QÚ 


"«FBaseAddressÚ "«FEnableŒÚ "«FNumberjÚ "«FSize<Ú "«FSubRegionDisable}Ú "«F TypeExtFieldÚ "«FAccessPermissionDÚ "«FDisableExecÚ "«FIsShareable†Ú "«FIsCacheable¥Ú "«F IsBufferableÚMPU_Region_InitTypeDef|Ú$PIS_NVIC_PREEMPTION_PRIORITY'ÚPIS_NVIC_DEVICE_IRQ"Ú$PSYSTICK_CLKSOURCE_HCLK_DIV8fÚPSYSTICK_CLKSOURCE_HCLKêÚPIS_SYSTICK_CLK_SOURCEÚPMPU_HFNMI_PRIVDEF_NONEÞÚPMPU_HARDFAULT_NMIzÚPMPU_PRIVILEGED_DEFAULTÿÚPMPU_HFNMI_PRIVDEFwÚPMPU_REGION_ENABLEŽÚPMPU_REGION_DISABLE?Ú&PMPU_INSTRUCTION_ACCESS_ENABLEÇÚ'PMPU_INSTRUCTION_ACCESS_DISABLExÚPMPU_ACCESS_SHAREABLEºÚ!PMPU_ACCESS_NOT_SHAREABLEbÚPMPU_ACCESS_CACHEABLEÙÚ!PMPU_ACCESS_NOT_CACHEABLEÚPMPU_ACCESS_BUFFERABLEqÚ"PMPU_ACCESS_NOT_BUFFERABLEÚPMPU_REGION_SIZE_32BðÚPMPU_REGION_SIZE_64BëÚPMPU_REGION_SIZE_128B¸ÚPMPU_REGION_SIZE_256B¶ÚPMPU_REGION_SIZE_512B»ÚPMPU_REGION_SIZE_1KBÙÚPMPU_REGION_SIZE_2KBØÚPMPU_REGION_SIZE_4KBÖÚPMPU_REGION_SIZE_8KBÒÚPMPU_REGION_SIZE_16KB¡ÚPMPU_REGION_SIZE_32KB£ÚPMPU_REGION_SIZE_64KBžÚPMPU_REGION_SIZE_128KBkÚPMPU_REGION_SIZE_256KBiÚPMPU_REGION_SIZE_512KBnÚPMPU_REGION_SIZE_1MB×ÚPMPU_REGION_SIZE_2MBÖÚPMPU_REGION_SIZE_4MBÔÚPMPU_REGION_SIZE_8MBÐÚPMPU_REGION_SIZE_16MBŸÚPMPU_REGION_SIZE_32MB¡ÚPMPU_REGION_SIZE_64MBœÚPMPU_REGION_SIZE_128MBiÚPMPU_REGION_SIZE_256MBgÚPMPU_REGION_SIZE_512MBlÚPMPU_REGION_SIZE_1GBÝÚPMPU_REGION_SIZE_2GBÜÚPMPU_REGION_SIZE_4GBÚÚPMPU_REGION_NO_ACCESSÚPMPU_REGION_PRIV_RWêÚPMPU_REGION_PRIV_RW_UROÚPMPU_REGION_FULL_ACCESSçÚPMPU_REGION_PRIV_ROòÚPMPU_REGION_PRIV_RO_URO•ÚPMPU_REGION_NUMBER0:ÚPMPU_REGION_NUMBER19ÚPMPU_REGION_NUMBER28ÚPMPU_REGION_NUMBER37ÚPMPU_REGION_NUMBER46ÚPMPU_REGION_NUMBER55ÚPMPU_REGION_NUMBER64ÚPMPU_REGION_NUMBER73Ú ,"IRQnhÚ,


PreemptPriority‚Ú,


SubPriority=ÚHAL_NVIC_SetPriorityoÚ ,"IRQnhÚHAL_NVIC_EnableIRQÎÚ ,"IRQnhÚHAL_NVIC_DisableIRQ_ÚHAL_NVIC_SystemResetuÚ,


 


TicksNumb=ÚHAL_SYSTICK_Config±Ú ,"IRQnhÚHAL_NVIC_GetPriority{Ú ,"IRQnhÚHAL_NVIC_GetPendingIRQ(Ú ,"IRQnhÚHAL_NVIC_SetPendingIRQÚ ,"IRQnhÚ!HAL_NVIC_ClearPendingIRQ]Ú,


 


CLKSource‚Ú$HAL_SYSTICK_CLKSourceConfigTÚHAL_SYSTICK_IRQHandlerUÚHAL_SYSTICK_CallbacköÚ,


MPU_Control—ÚHAL_MPU_EnableÚHAL_MPU_Disable‘Ú,    MPU_InitÜÚHAL_MPU_ConfigRegionÚPIS_MPU_REGION_ENABLEÚ"PIS_MPU_INSTRUCTION_ACCESSÚÚ PIS_MPU_ACCESS_SHAREABLE¹Ú PIS_MPU_ACCESS_CACHEABLEØÚ!PIS_MPU_ACCESS_BUFFERABLEpÚ+P#IS_MPU_REGION_PERMISSION_ATTRIBUTEüÚPIS_MPU_REGION_NUMBERkÚPIS_MPU_REGION_SIZEýÚ"PIS_MPU_SUB_REGION_DISABLEíÚP__STM32L0xx_HAL_ADC_HÚ8


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"›GRatioÞÚ 


"›GRightBitShift²Ú 


"›GTriggeredMode«Ú ADC_OversamplingTypeDefÚ8


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" GClockPrescaler9Ú 


" GResolutionšÚ 


" G


DataAlignkÚ 


" G ScanConvMode*Ú 


" G EOCSelectionMÚ 


" GLowPowerAutoWaitUÚ 


" GLowPowerAutoPowerOffºÚ "" GContinuousConvModeWÚ  "" GDiscontinuousConvModeÚ 


" GExternalTrigConvSÚ 


" GExternalTrigConvEdgeÖÚ  "" GDMAContinuousRequests>Ú 


" GOverrunãÚ  


" GLowPowerFrequencyModeBÚ 


" G SamplingTimeÚ 


" GOversamplingModeFÚ " GOversample–ÚADC_InitTypeDefwÚ8


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"³GChannelÚ 


"³GRank;ÚADC_ChannelConfTypeDef¾Ú8


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"·G WatchdogModeýÚ 


"·GChannelÚ ""·GITModeˆÚ 


"·GHighThreshold„Ú 


"·G LowThresholdÔÚ!ADC_AnalogWDGConfTypeDef?ÚPHAL_ADC_STATE_RESETçÚPHAL_ADC_STATE_READYõÚ$PHAL_ADC_STATE_BUSY_INTERNAL[ÚPHAL_ADC_STATE_TIMEOUT?Ú%PHAL_ADC_STATE_ERROR_INTERNALÚ#PHAL_ADC_STATE_ERROR_CONFIG½Ú PHAL_ADC_STATE_ERROR_DMA§ÚPHAL_ADC_STATE_REG_BUSYäÚPHAL_ADC_STATE_REG_EOCRÚPHAL_ADC_STATE_REG_OVR2Ú PHAL_ADC_STATE_REG_EOSMP¡ÚPHAL_ADC_STATE_INJ_BUSYáÚPHAL_ADC_STATE_INJ_EOCOÚ PHAL_ADC_STATE_INJ_JQOVFœÚPHAL_ADC_STATE_AWD1_ÚPHAL_ADC_STATE_AWD2^ÚPHAL_ADC_STATE_AWD3]Ú&PHAL_ADC_STATE_MULTIMODE_SLAVEÌÚ8__ADC_HandleTypeDef½Ú "ÐG    Instance_Ú "HÐGInitÀÚ "ÐGDMA_HandleÚ ""ÐGLockÚ 


"ÐGState§Ú 


"ÐG


ErrorCodeÚADC_HandleTypeDef»ÚPHAL_ADC_ERROR_NONE3ÚPHAL_ADC_ERROR_INTERNALþÚPHAL_ADC_ERROR_OVRnÚPHAL_ADC_ERROR_DMA“ÚPADC_ENABLE_TIMEOUTSÚPADC_DISABLE_TIMEOUTÚ$PADC_STOP_CONVERSION_TIMEOUT=Ú&PADC_DELAY_10US_MIN_CPU_CYCLESçÚPADC_CLOCK_ASYNC_DIV1ÀÚPADC_CLOCK_ASYNC_DIV2¿ÚPADC_CLOCK_ASYNC_DIV4½ÚPADC_CLOCK_ASYNC_DIV6»ÚPADC_CLOCK_ASYNC_DIV8¹ÚPADC_CLOCK_ASYNC_DIV10ŽÚPADC_CLOCK_ASYNC_DIV12ŒÚPADC_CLOCK_ASYNC_DIV16ˆÚPADC_CLOCK_ASYNC_DIV32ŠÚPADC_CLOCK_ASYNC_DIV64…ÚPADC_CLOCK_ASYNC_DIV128RÚPADC_CLOCK_ASYNC_DIV256PÚ!PADC_CLOCK_SYNC_PCLK_DIV1pÚ!PADC_CLOCK_SYNC_PCLK_DIV2oÚ!PADC_CLOCK_SYNC_PCLK_DIV4mÚPADC_RESOLUTION_12BhÚPADC_RESOLUTION_10BjÚPADC_RESOLUTION_8B•ÚPADC_RESOLUTION_6B—ÚPADC_DATAALIGN_RIGHTÚPADC_DATAALIGN_LEFTqÚ&PADC_EXTERNALTRIGCONVEDGE_NONE÷Ú(P ADC_EXTERNALTRIGCONVEDGE_RISINGWÚ)P!ADC_EXTERNALTRIGCONVEDGE_FALLING$Ú/P'ADC_EXTERNALTRIGCONVEDGE_RISINGFALLINGLÚPADC_EOC_SINGLE_CONVñÚPADC_EOC_SEQ_CONVÐÚPADC_OVR_DATA_PRESERVEDùÚ!PADC_OVR_DATA_OVERWRITTEN<Ú PADC_RANK_CHANNEL_NUMBERÊÚPADC_RANK_NONEÏÚPADC_CHANNEL_0ÚPADC_CHANNEL_1ÚPADC_CHANNEL_2ÚPADC_CHANNEL_3ÿÚPADC_CHANNEL_4þÚPADC_CHANNEL_5ýÚPADC_CHANNEL_6üÚPADC_CHANNEL_7ûÚPADC_CHANNEL_8úÚPADC_CHANNEL_9ùÚPADC_CHANNEL_10ÏÚPADC_CHANNEL_11ÎÚPADC_CHANNEL_12ÍÚPADC_CHANNEL_13ÌÚPADC_CHANNEL_14ËÚPADC_CHANNEL_15ÊÚPADC_CHANNEL_17ÈÚPADC_CHANNEL_18ÇÚPADC_CHANNEL_VREFINTÚPADC_CHANNEL_TEMPSENSORÚPADC_CHANNEL_MASKÚPADC_CHANNEL_AWD_MASK½Ú PADC_SAMPLETIME_1CYCLE_5ñÚ!PADC_SAMPLETIME_3CYCLES_5šÚ!PADC_SAMPLETIME_7CYCLES_5–Ú"PADC_SAMPLETIME_12CYCLES_5hÚ"PADC_SAMPLETIME_19CYCLES_5aÚ"PADC_SAMPLETIME_39CYCLES_5_Ú"PADC_SAMPLETIME_79CYCLES_5[Ú#PADC_SAMPLETIME_160CYCLES_52Ú#PADC_SCAN_DIRECTION_FORWARD×Ú$PADC_SCAN_DIRECTION_BACKWARD«ÚPADC_SCAN_ENABLE[Ú!PADC_OVERSAMPLING_RATIO_2nÚ!PADC_OVERSAMPLING_RATIO_4lÚ!PADC_OVERSAMPLING_RATIO_8hÚ"PADC_OVERSAMPLING_RATIO_167Ú"PADC_OVERSAMPLING_RATIO_329Ú"PADC_OVERSAMPLING_RATIO_644Ú#PADC_OVERSAMPLING_RATIO_128Ú#PADC_OVERSAMPLING_RATIO_256ÿÚPADC_RIGHTBITSHIFT_NONEÚPADC_RIGHTBITSHIFT_1ÚPADC_RIGHTBITSHIFT_2ÚPADC_RIGHTBITSHIFT_3ÚPADC_RIGHTBITSHIFT_4ÚPADC_RIGHTBITSHIFT_5ÚPADC_RIGHTBITSHIFT_6ÚPADC_RIGHTBITSHIFT_7 ÚPADC_RIGHTBITSHIFT_8Ú)P!ADC_TRIGGEREDMODE_SINGLE_TRIGGERÚ(P ADC_TRIGGEREDMODE_MULTI_TRIGGERGÚ PADC_ANALOGWATCHDOG_NONEäÚ&PADC_ANALOGWATCHDOG_SINGLE_REG    Ú#PADC_ANALOGWATCHDOG_ALL_REGøÚPADC_REGULAR_GROUP„ÚPADC_AWD_EVENTÍÚPADC_OVR_EVENT²ÚPADC_IT_RDY¥ÚP ADC_IT_EOSMPÚPADC_IT_EOC½ÚPADC_IT_EOS­ÚPADC_IT_OVRÚPADC_IT_AWD¸ÚP ADC_IT_EOCAL,ÚP ADC_FLAG_RDY$ÚPADC_FLAG_EOSMP‹ÚP ADC_FLAG_EOC<ÚP ADC_FLAG_EOS,ÚP ADC_FLAG_OVRÚP ADC_FLAG_AWD7ÚPADC_FLAG_EOCAL«ÚP ADC_FLAG_ALL:Ú%P__HAL_ADC_RESET_HANDLE_STATEÚP__HAL_ADC_ENABLEëÚ PADC_ENABLING_CONDITIONSÝÚP__HAL_ADC_DISABLEœÚ!PADC_DISABLING_CONDITIONSŽÚPADC_IS_ENABLEèÚPADC_GET_RESOLUTION-Ú&PADC_IS_SOFTWARE_START_REGULAR¦Ú*P"ADC_IS_CONVERSION_ONGOING_REGULAR€ÚPADC_CONTINUOUSqÚPADC_SCANDIRŠÚ*P"__HAL_ADC_CFGR1_DISCONTINUOUS_NUMxÚPADC_DMACONTREQšÚ"P__HAL_ADC_CFGR1_AutoDelayFÚP__HAL_ADC_CFGR1_AUTOFFÚPADC_TRX_HIGHTHRESHOLDPÚ#P__HAL_ADC_CCR_LOWFREQUENCY£Ú$PADC_OFFSET_SHIFT_RESOLUTIONWÚ+P#ADC_AWD1THRESHOLD_SHIFT_RESOLUTIONVÚ#P__HAL_ADC_Value_Shift_leftÚP__HAL_ADC_ENABLE_ITéÚP__HAL_ADC_DISABLE_ITšÚ P__HAL_ADC_GET_IT_SOURCExÚP__HAL_ADC_CLEAR_FLAGªÚP__HAL_ADC_GET_FLAG5ÚPADC_STATE_CLR_SETvÚPADC_CLEAR_ERRORCODEÚ"P__HAL_ADC_CLOCK_PRESCALERÚPIS_ADC_CLOCKPRESCALERrÚPIS_ADC_RESOLUTIONsÚ#PIS_ADC_RESOLUTION_8_6_BITS¤ÚPIS_ADC_DATA_ALIGN£ÚPIS_ADC_EXTTRIG_EDGEèÚPIS_ADC_EOC_SELECTION¥ÚPIS_ADC_OVERRUN\ÚPIS_ADC_RANKgÚPIS_ADC_CHANNEL”ÚPIS_ADC_SAMPLE_TIME5ÚPIS_ADC_SCAN_MODEàÚ"PIS_ADC_OVERSAMPLING_RATIOÚPIS_ADC_RIGHT_BIT_SHIFTäÚ+P#IS_ADC_TRIGGERED_OVERSAMPLING_MODENÚ$PIS_ADC_ANALOG_WATCHDOG_MODEÚ PIS_ADC_CONVERSION_GROUP‰ÚPIS_ADC_EVENT_TYPEdÚP IS_ADC_RANGE$ÚPIS_ADC_REGULAR_NB_CONVçÚ!P__STM32L0xx_HAL_ADC_EX_HÚPADC_SINGLE_ENDEDÚ%PADC_EXTERNALTRIGCONV_T6_TRGOÚ%PADC_EXTERNALTRIGCONV_T21_CC2pÚ%PADC_EXTERNALTRIGCONV_T2_TRGOÚ$PADC_EXTERNALTRIGCONV_T2_CC4¡Ú&PADC_EXTERNALTRIGCONV_T22_TRGOéÚ%PADC_EXTERNALTRIGCONV_T3_TRGOÚ&PADC_EXTERNALTRIGCONV_EXT_IT11íÚPADC_SOFTWARE_START(Ú&PADC_EXTERNALTRIGCONV_T21_TRGOêÚ$PADC_EXTERNALTRIGCONV_T2_CC3¢ÚPADC_FLAG_SENSOR3ÚPADC_FLAG_VREFINTíÚ#PIS_ADC_SINGLE_DIFFERENTIALçÚPIS_ADC_CALFACTŸÚPIS_ADC_EXTTRIGfÚ ,hadc9Ú,


SingleDiffðÚ$HAL_ADCEx_Calibration_StartÅÚ ,hadc9Ú,


SingleDiffðÚ'HAL_ADCEx_Calibration_GetValue°Ú ,hadc9Ú,


SingleDiffðÚ,


CalibrationFactoröÚ'HAL_ADCEx_Calibration_SetValue¤Ú HAL_ADCEx_EnableVREFINT=Ú!HAL_ADCEx_DisableVREFINTÎÚ*"HAL_ADCEx_EnableVREFINTTempSensorÚ+#HAL_ADCEx_DisableVREFINTTempSensorªÚ ,hadc9Ú HAL_ADC_InitáÚ ,hadc9ÚHAL_ADC_DeInit4Ú ,hadc9ÚHAL_ADC_MspInit«Ú ,hadc9ÚHAL_ADC_MspDeInitþÚ ,hadc9ÚHAL_ADC_StarteÚ ,hadc9Ú HAL_ADC_StopÏÚ ,hadc9Ú,


TimeoutêÚ"HAL_ADC_PollForConversionwÚ ,hadc9Ú,


 


EventType)Ú,


TimeoutêÚHAL_ADC_PollForEvent¥Ú ,hadc9ÚHAL_ADC_Start_ITcÚ ,hadc9ÚHAL_ADC_Stop_ITÍÚ ,hadc9Ú,pDataÝÚ,


LengthqÚHAL_ADC_Start_DMA,Ú ,hadc9ÚHAL_ADC_Stop_DMA–Ú ,hadc9ÚHAL_ADC_GetValuePÚ ,hadc9ÚHAL_ADC_IRQHandler¿Ú ,hadc9Ú!HAL_ADC_ConvCpltCallback'Ú ,hadc9Ú%HAL_ADC_ConvHalfCpltCallback¤Ú ,hadc9Ú)!HAL_ADC_LevelOutOfWindowCallbackãÚ ,hadc9ÚHAL_ADC_ErrorCallbackLÚ ,hadc9Ú,sConfigúÚHAL_ADC_ConfigChannelTÚ ,hadc9Ú,AnalogWDGConfig)Ú HAL_ADC_AnalogWDGConfigÕÚ ,hadc9ÚHAL_ADC_GetStateLÚ ,hadc9ÚHAL_ADC_GetErrorCÚ PHAL_COMP_MODULE_ENABLEDÉÚPHAL_CRC_MODULE_ENABLED"Ú PHAL_CRYP_MODULE_ENABLEDºÚPHAL_DAC_MODULE_ENABLED2Ú$PHAL_FIREWALL_MODULE_ENABLEDšÚ P__STM32L0xx_HAL_FLASH_HrÚPFLASH_TIMEOUT_VALUEÕÚ!PFLASH_SIZE_DATA_REGISTERVÚPIS_FLASH_TYPEPROGRAMÚPIS_FLASH_LATENCYÓÚFLASH_PROC_NONEOÚFLASH_PROC_PAGEERASEèÚFLASH_PROC_PROGRAMaÚFLASH_ProcedureTypeDef®Ú8


<unnamed>QÚ ""×IProcedureOnGoingÚ 


"×INbPagesToErase:Ú 


"×IAddressÕÚ 


"×IPage$Ú ""×ILockÚ 


"×I


ErrorCodeÚFLASH_ProcessTypeDef|ÚPHAL_FLASH_ERROR_NONE‰ÚPHAL_FLASH_ERROR_PGAãÚPHAL_FLASH_ERROR_WRPÂÚPHAL_FLASH_ERROR_OPTVpÚPHAL_FLASH_ERROR_SIZE~ÚPHAL_FLASH_ERROR_RD'ÚPHAL_FLASH_ERROR_FWWERRØÚ PHAL_FLASH_ERROR_NOTZERO‚ÚPFLASH_SIZE¯ÚPFLASH_PAGE_SIZE)ÚP


FLASH_ENDÚPFLASH_BANK2_BASEÚPFLASH_BANK1_END]ÚPFLASH_BANK2_END\ÚPFLASH_TYPEPROGRAM_WORDÝÚPFLASH_LATENCY_0AÚPFLASH_LATENCY_1@ÚP FLASH_IT_EOPÚP FLASH_IT_ERRÚPFLASH_FLAG_BSY{ÚPFLASH_FLAG_EOP…ÚPFLASH_FLAG_ENDHVðÚPFLASH_FLAG_READYðÚPFLASH_FLAG_WRPERRÚPFLASH_FLAG_PGAERR¢ÚPFLASH_FLAG_SIZERR„ÚPFLASH_FLAG_OPTVERR/ÚPFLASH_FLAG_RDERRæÚPFLASH_FLAG_FWWERR†ÚPFLASH_FLAG_NOTZEROERRAÚP FLASH_PDKEY18ÚP FLASH_PDKEY27ÚP FLASH_PEKEY17ÚP FLASH_PEKEY26ÚPFLASH_PRGKEY1áÚPFLASH_PRGKEY2àÚPFLASH_OPTKEY1×ÚPFLASH_OPTKEY2ÖÚP__HAL_FLASH_ENABLE_IT?ÚP__HAL_FLASH_DISABLE_ITðÚP__HAL_FLASH_GET_FLAG‹ÚP__HAL_FLASH_CLEAR_FLAGÚ#P__STM32L0xx_HAL_FLASH_EX_HpÚPFLASH_NBPAGES_MAX—ÚP WRP_MASK_LOWÞÚPWRP_MASK_HIGH®ÚPIS_FLASH_TYPEERASE-ÚPIS_OPTIONBYTE©ÚPIS_WRPSTATE@ÚP


IS_OB_WRPÕÚP


IS_OB_RDPèÚPIS_OB_BOR_LEVELÚPIS_OB_IWDG_SOURCEcÚPIS_OB_STOP_SOURCEHÚPIS_OB_STDBY_SOURCEÚPIS_OBEX”ÚPIS_PCROPSTATE±ÚPIS_OB_PCROPFÚPIS_OB_BOOT_BANKÚPIS_OB_BOOT1eÚPIS_TYPEPROGRAMDATA8ÚPIS_FLASH_DATA_ADDRESSZÚ$PIS_FLASH_DATA_BANK1_ADDRESS¢Ú$PIS_FLASH_DATA_BANK2_ADDRESS¡Ú!PIS_FLASH_PROGRAM_ADDRESSVÚ'PIS_FLASH_PROGRAM_BANK1_ADDRESSžÚ'PIS_FLASH_PROGRAM_BANK2_ADDRESSÚPIS_NBPAGES¼Ú,


PageAddress†ÚFLASH_PageEraseÚ8


<unnamed>QÚ 


"¥J


TypeErase6Ú 


"¥JPageAddressÚ 


"¥JNbPages,ÚFLASH_EraseInitTypeDefÓÚ8


<unnamed>QÚ 


"ªJOptionType¦Ú 


"ªJ    WRPStateËÚ 


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WRPSectorZÚ 


"ªJWRPSector2&Ú "ªJ    RDPLevelîÚ "ªJ    BORLevelñÚ "ªJUSERConfig3Ú "ªJBOOTBit1ConfigæÚ#FLASH_OBProgramInitTypeDefRÚ8


<unnamed>QÚ 


"´JOptionTypeœÚ 


"´JPCROPState2Ú 


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PulseÌÚ HAL_LPTIM_SetOnce_StartƒÚ,hlptim7ÚHAL_LPTIM_SetOnce_StopíÚ,hlptim7Ú,


PeriodpÚ,


PulseÌÚ#HAL_LPTIM_SetOnce_Start_ITÚ,hlptim7Ú"HAL_LPTIM_SetOnce_Stop_ITëÚ,hlptim7Ú,


PeriodpÚ HAL_LPTIM_Encoder_StarttÚ,hlptim7ÚHAL_LPTIM_Encoder_StopÞÚ,hlptim7Ú,


PeriodpÚ#HAL_LPTIM_Encoder_Start_ITrÚ,hlptim7Ú"HAL_LPTIM_Encoder_Stop_ITÜÚ,hlptim7Ú,


PeriodpÚ,


TimeoutêÚ HAL_LPTIM_TimeOut_StartmÚ,hlptim7ÚHAL_LPTIM_TimeOut_Stop×Ú,hlptim7Ú,


PeriodpÚ,


TimeoutêÚ#HAL_LPTIM_TimeOut_Start_ITkÚ,hlptim7Ú"HAL_LPTIM_TimeOut_Stop_ITÕÚ,hlptim7Ú,


PeriodpÚ HAL_LPTIM_Counter_StartTÚ,hlptim7ÚHAL_LPTIM_Counter_Stop¾Ú,hlptim7Ú,


PeriodpÚ#HAL_LPTIM_Counter_Start_ITRÚ,hlptim7Ú"HAL_LPTIM_Counter_Stop_IT¼Ú,hlptim7ÚHAL_LPTIM_ReadCounterIÚ,hlptim7Ú!HAL_LPTIM_ReadAutoReload3Ú,hlptim7Ú$HAL_LPTIM_ReadCapturedValueèÚ,hlptim7ÚHAL_LPTIM_IRQHandlerýÚ,hlptim7Ú'HAL_LPTIM_CompareMatchCallbackÒÚ,hlptim7Ú*"HAL_LPTIM_AutoReloadMatchCallback£Ú,hlptim7Ú"HAL_LPTIM_TriggerCallback¼Ú,hlptim7Ú'HAL_LPTIM_CompareWriteCallback´Ú,hlptim7Ú*"HAL_LPTIM_AutoReloadWriteCallback…Ú,hlptim7Ú&HAL_LPTIM_DirectionUpCallback"Ú,hlptim7Ú( HAL_LPTIM_DirectionDownCallbackKÚ,hlptim7ÚHAL_LPTIM_GetStateŠÚPIS_LPTIM_CLOCK_SOURCE%Ú!PIS_LPTIM_CLOCK_PRESCALEROÚ%PIS_LPTIM_CLOCK_PRESCALERDIV13Ú!PIS_LPTIM_OUTPUT_POLARITY÷Ú#PIS_LPTIM_CLOCK_SAMPLE_TIMEœÚ PIS_LPTIM_CLOCK_POLARITY~ÚPIS_LPTIM_TRG_SOURCE¨Ú"PIS_LPTIM_EXT_TRG_POLARITY©Ú"PIS_LPTIM_TRIG_SAMPLE_TIMEÔÚPIS_LPTIM_UPDATE_MODE|Ú PIS_LPTIM_COUNTER_SOURCEmÚPIS_LPTIM_AUTORELOADÕÚPIS_LPTIM_COMPAREÄÚPIS_LPTIM_PERIOD


ÚPIS_LPTIM_PULSEFÚ,hlptim7ÚLPTIM_Disable5ÚP__STM32L0xx_HAL_PWR_HëÚ8


<unnamed>QÚ 


"†Q    PVDLevelÚ 


"†QModeeÚPWR_PVDTypeDefòÚPPWR_EXTI_LINE_PVDGÚPPWR_WAKEUP_PIN1ÚPPWR_WAKEUP_PIN2ÚPPWR_WAKEUP_PIN3ÚPPWR_PVDLEVEL_0fÚPPWR_PVDLEVEL_1eÚPPWR_PVDLEVEL_2dÚPPWR_PVDLEVEL_3cÚPPWR_PVDLEVEL_4bÚPPWR_PVDLEVEL_5aÚPPWR_PVDLEVEL_6`ÚPPWR_PVDLEVEL_7_ÚPPWR_PVD_MODE_NORMAL·ÚPPWR_PVD_MODE_IT_RISING²Ú PPWR_PVD_MODE_IT_FALLINGÚ'PPWR_PVD_MODE_IT_RISING_FALLINGFÚ"PPWR_PVD_MODE_EVENT_RISINGÇÚ#PPWR_PVD_MODE_EVENT_FALLING”Ú*P"PWR_PVD_MODE_EVENT_RISING_FALLING[ÚPPWR_MAINREGULATOR_ONuÚ!PPWR_LOWPOWERREGULATOR_ONÚPPWR_SLEEPENTRY_WFIÿÚPPWR_SLEEPENTRY_WFEÚPPWR_STOPENTRY_WFI4ÚPPWR_STOPENTRY_WFE8Ú%PPWR_REGULATOR_VOLTAGE_SCALE1Ú%PPWR_REGULATOR_VOLTAGE_SCALE2Ú%PPWR_REGULATOR_VOLTAGE_SCALE3Ú%PIS_PWR_VOLTAGE_SCALING_RANGEÚPPWR_FLAG_WU8ÚPPWR_FLAG_SBOÚPPWR_FLAG_PVDO§ÚPPWR_FLAG_VREFINTRDYÇÚP PWR_FLAG_VOSêÚPPWR_FLAG_REGLPdÚ(P __HAL_PWR_VOLTAGESCALING_CONFIGÚP__HAL_PWR_GET_FLAGÚP__HAL_PWR_CLEAR_FLAGyÚ%P__HAL_PWR_PVD_EXTI_ENABLE_ITÄÚ&P__HAL_PWR_PVD_EXTI_DISABLE_ITuÚ(P __HAL_PWR_PVD_EXTI_ENABLE_EVENTÙÚ)P!__HAL_PWR_PVD_EXTI_DISABLE_EVENTŠÚ/P'__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGEÜÚ0P(__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGEÚ.P&__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGEÚ/P'__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGEÀÚ6P.__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE£Ú7P/__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGETÚ$P__HAL_PWR_PVD_EXTI_GET_FLAGÚ&P__HAL_PWR_PVD_EXTI_CLEAR_FLAG…Ú)P!__HAL_PWR_PVD_EXTI_GENERATE_SWITnÚPIS_PWR_PVD_LEVEL—ÚPIS_PWR_PVD_MODEìÚPIS_PWR_WAKEUP_PINCÚPIS_PWR_REGULATOR£ÚPIS_PWR_SLEEP_ENTRYêÚPIS_PWR_STOP_ENTRYÚ!P__STM32L0xx_HAL_PWR_EX_HéÚ%P__HAL_PWR_FLASHWAKEUP_ENABLEÚ&P__HAL_PWR_FLASHWAKEUP_DISABLE¹Ú"HAL_PWREx_GetVoltageRangeŽÚ#HAL_PWREx_EnableFastWakeUpIÚ$HAL_PWREx_DisableFastWakeUpÚÚ&HAL_PWREx_EnableUltraLowPower×Ú'HAL_PWREx_DisableUltraLowPowerhÚ( HAL_PWREx_EnableLowPowerRunMode!Ú)!HAL_PWREx_DisableLowPowerRunMode²ÚHAL_PWR_DeInitÚ!HAL_PWR_EnableBkUpAccess!Ú"HAL_PWR_DisableBkUpAccess²Ú,sConfigPVD


ÚHAL_PWR_ConfigPVDúÚHAL_PWR_EnablePVD    ÚHAL_PWR_DisablePVDšÚHAL_PWR_PVD_IRQHandler=ÚHAL_PWR_PVDCallback?Ú,


WakeUpPinxßÚ HAL_PWR_EnableWakeUpPinsÚ,


WakeUpPinxßÚ!HAL_PWR_DisableWakeUpPinÚ,


 


RegulatorÚ,


STOPEntry|ÚHAL_PWR_EnterSTOPModeiÚ,


 


RegulatorÚ,SLEEPEntryGÚHAL_PWR_EnterSLEEPMode4Ú!HAL_PWR_EnterSTANDBYMode”Ú"HAL_PWR_EnableSleepOnExit“Ú#HAL_PWR_DisableSleepOnExit$Ú HAL_PWR_EnableSEVOnPendµÚ!HAL_PWR_DisableSEVOnPendFÚPHAL_RNG_MODULE_ENABLEDÚPHAL_RTC_MODULE_ENABLEDÚPSTM32L0xx_HAL_SPI_HºÚ8


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"èQModeÚ 


"èQ


DirectionÝÚ 


"èQ    DataSizekÚ 


"èQCLKPolarityLÚ 


"èQ    CLKPhaseµÚ 


"èQNSS–Ú 


"èQBaudRatePrescalerÅÚ 


"èQ    FirstBitYÚ 


"èQTIModebÚ 


"èQCRCCalculation-Ú 


"èQCRCPolynomialzÚSPI_InitTypeDefSÚHAL_SPI_STATE_RESETõÚHAL_SPI_STATE_READYÚHAL_SPI_STATE_BUSY7ÚHAL_SPI_STATE_BUSY_TX&ÚHAL_SPI_STATE_BUSY_RX(Ú!HAL_SPI_STATE_BUSY_TX_RXÚHAL_SPI_STATE_ERRORîÚHAL_SPI_STATE_ABORTÚHAL_SPI_StateTypeDef¨Ú8__SPI_HandleTypeDef™Ú "þQ    Instance'Ú ",þQInit¤Ú "þQpTxBuffPtrcÚ "þQTxXferSizehÚ "þQTxXferCountøÚ "þQpRxBuffPtreÚ "þQRxXferSizejÚ "þQRxXferCountúÚ "þQRxISRªÚ "þQTxISR¨Ú "þQhdmatxÚÚ "þQhdmarxÜÚ ""þQLockÔÚ ""þQStateZÚ 


"þQ


ErrorCodeãÚSPI_HandleTypeDef—ÚPHAL_SPI_ERROR_NONEÚPHAL_SPI_ERROR_MODFÚPHAL_SPI_ERROR_CRCiÚPHAL_SPI_ERROR_OVRJÚPHAL_SPI_ERROR_FREdÚPHAL_SPI_ERROR_DMAoÚPHAL_SPI_ERROR_FLAG%ÚPHAL_SPI_ERROR_ABORTÅÚPSPI_MODE_SLAVEeÚPSPI_MODE_MASTERÚPSPI_DIRECTION_2LINES«Ú$PSPI_DIRECTION_2LINES_RXONLYRÚPSPI_DIRECTION_1LINEÚPSPI_DATASIZE_8BIT“ÚPSPI_DATASIZE_16BITbÚPSPI_POLARITY_LOW›ÚPSPI_POLARITY_HIGHkÚPSPI_PHASE_1EDGELÚPSPI_PHASE_2EDGEKÚP SPI_NSS_SOFTÙÚPSPI_NSS_HARD_INPUTûÚPSPI_NSS_HARD_OUTPUT˜Ú PSPI_BAUDRATEPRESCALER_2ØÚ PSPI_BAUDRATEPRESCALER_4ÖÚ PSPI_BAUDRATEPRESCALER_8ÒÚ!PSPI_BAUDRATEPRESCALER_16¡Ú!PSPI_BAUDRATEPRESCALER_32£Ú!PSPI_BAUDRATEPRESCALER_64žÚ"PSPI_BAUDRATEPRESCALER_128kÚ"PSPI_BAUDRATEPRESCALER_256iÚPSPI_FIRSTBIT_MSB¸ÚPSPI_FIRSTBIT_LSB¹ÚPSPI_TIMODE_DISABLEGÚPSPI_TIMODE_ENABLE–Ú#PSPI_CRCCALCULATION_DISABLEòÚ"PSPI_CRCCALCULATION_ENABLEAÚPSPI_IT_TXEÚPSPI_IT_RXNE1ÚPSPI_IT_ERR‡ÚPSPI_FLAG_RXNE°ÚP SPI_FLAG_TXEþÚP SPI_FLAG_BSYÚPSPI_FLAG_CRCERR(ÚPSPI_FLAG_MODFÇÚP SPI_FLAG_OVRøÚP SPI_FLAG_FREÚPSPI_FLAG_MASKÁÚ%P__HAL_SPI_RESET_HANDLE_STATEèÚP__HAL_SPI_ENABLE_ITÅÚP__HAL_SPI_DISABLE_ITvÚ P__HAL_SPI_GET_IT_SOURCETÚP__HAL_SPI_GET_FLAGÚ#P__HAL_SPI_CLEAR_CRCERRFLAG¹Ú!P__HAL_SPI_CLEAR_MODFFLAGXÚ P__HAL_SPI_CLEAR_OVRFLAG‰Ú P__HAL_SPI_CLEAR_FREFLAG£ÚP__HAL_SPI_ENABLEÇÚP__HAL_SPI_DISABLExÚP SPI_1LINE_TXÚP SPI_1LINE_RXÚPSPI_RESET_CRC¬ÚPSPI_CHECK_FLAGÚPSPI_CHECK_IT_SOURCEÐÚPIS_SPI_MODEJÚPIS_SPI_DIRECTIONÄÚ PIS_SPI_DIRECTION_2LINESªÚ)P!IS_SPI_DIRECTION_2LINES_OR_1LINEàÚPIS_SPI_DATASIZEÚPIS_SPI_CPOLAÚPIS_SPI_CPHASÚPIS_SPI_NSS}Ú"PIS_SPI_BAUDRATE_PRESCALERÚPIS_SPI_FIRST_BITŸÚPIS_SPI_TIMODE©ÚPIS_SPI_CRC_CALCULATIONóÚPIS_SPI_CRC_POLYNOMIAL ÚPIS_SPI_DMA_HANDLE†Ú%PIS_SPI_16BIT_ALIGNED_ADDRESSOÚ ,hspiÚ HAL_SPI_Init½Ú ,hspiÚHAL_SPI_DeInitÚ ,hspiÚHAL_SPI_MspInit‡Ú ,hspiÚHAL_SPI_MspDeInitÚÚ ,hspiÚ,pDataÝÚ ,Size:Ú,


TimeoutêÚHAL_SPI_Transmit÷Ú ,hspiÚ,pDataÝÚ ,Size:Ú,


TimeoutêÚHAL_SPI_ReceiveˆÚ ,hspiÚ,pTxData Ú,pRxDataÚ ,Size:Ú,


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<unnamed>QÚ 


"°S


PrescalerÚ 


"°SCounterModeKÚ 


"°SPeriodWÚ 


"°SClockDivision{Ú 


"°SAutoReloadPreloadíÚTIM_Base_InitTypeDefqÚ8


<unnamed>QÚ 


"·SOCModeœÚ 


"·SPulse¬Ú 


"·SOCPolarityÅÚ 


"·SOCFastModeÚTIM_OC_InitTypeDef^Ú8


<unnamed>QÚ 


"½SOCMode–Ú 


"½SPulse¦Ú 


"½SOCPolarity¿Ú 


"½SICPolarityÅÚ 


"½SICSelectionqÚ 


"½S    ICFilter·Ú!TIM_OnePulse_InitTypeDef¹Ú8


<unnamed>QÚ 


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"ÅS    ICFilter¯ÚTIM_IC_InitTypeDefdÚ8


<unnamed>QÚ 


"ËSEncoderModePÚ 


"ËSIC1Polarity„Ú 


"ËS IC1Selection0Ú 


"ËS IC1Prescaler5Ú 


"ËS


IC1FiltervÚ 


"ËSIC2PolarityƒÚ 


"ËS IC2Selection/Ú 


"ËS IC2Prescaler4Ú 


"ËS


IC2FilteruÚ TIM_Encoder_InitTypeDef&Ú8


<unnamed>QÚ 


"ÖSClockSource-Ú 


"ÖSClockPolarityFÚ 


"ÖSClockPrescaler÷Ú 


"ÖSClockFilter8ÚTIM_ClockConfigTypeDef™Ú8


<unnamed>QÚ 


"ÜSClearInputState„Ú 


"ÜSClearInputSourceÚ 


"ÜSClearInputPolarity+Ú 


"ÜSClearInputPrescalerÜÚ 


"ÜSClearInputFilterÚ$TIM_ClearInputConfigTypeDef„Ú8


<unnamed>QÚ 


"ãSMasterOutputTriggerœÚ 


"ãSMasterSlaveMode‰Ú TIM_MasterConfigTypeDefÚ8


<unnamed>QÚ 


"çS


SlaveModeýÚ 


"çS InputTrigger“Ú 


"çSTriggerPolarityIÚ 


"çSTriggerPrescalerúÚ 


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<unnamed>QÚ "‚T    Instance Ú "‚TInit5Ú ""‚TChannelÚ <"‚ThdmaÚ ""‚TLockMÚ ""‚TStateÓÚ <"‚T ChannelStateïÚ ""‚TDMABurstStateáÚTIM_HandleTypeDef™Ú"PTIM_CLEARINPUTSOURCE_NONEùÚ!PTIM_CLEARINPUTSOURCE_ETR@ÚPTIM_DMABASE_CR1RÚPTIM_DMABASE_CR2QÚPTIM_DMABASE_SMCRáÚPTIM_DMABASE_DIERòÚPTIM_DMABASE_SRuÚPTIM_DMABASE_EGR:ÚPTIM_DMABASE_CCMR1¾ÚPTIM_DMABASE_CCMR2½ÚPTIM_DMABASE_CCERùÚPTIM_DMABASE_CNT3ÚPTIM_DMABASE_PSC2ÚPTIM_DMABASE_ARR3ÚPTIM_DMABASE_CCR1 ÚPTIM_DMABASE_CCR2ÚPTIM_DMABASE_CCR3ÚPTIM_DMABASE_CCR4


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ÚPTIM_ENCODERMODE_TI2    ÚPTIM_ENCODERMODE_TI12ÖÚPTIM_IT_UPDATE©ÚPTIM_IT_CC1»ÚPTIM_IT_CC2ºÚPTIM_IT_CC3¹ÚPTIM_IT_CC4¸ÚPTIM_IT_TRIGGERVÚPTIM_DMA_UPDATErÚPTIM_DMA_CC1„ÚPTIM_DMA_CC2ƒÚPTIM_DMA_CC3‚ÚPTIM_DMA_CC4ÚPTIM_DMA_TRIGGERÚPTIM_CCDMAREQUEST_CCöÚ PTIM_CCDMAREQUEST_UPDATE±ÚPTIM_FLAG_UPDATE(ÚP TIM_FLAG_CC1:ÚP TIM_FLAG_CC29ÚP TIM_FLAG_CC38ÚP TIM_FLAG_CC47ÚPTIM_FLAG_TRIGGERÕÚPTIM_FLAG_CC1OF¡ÚPTIM_FLAG_CC2OF ÚPTIM_FLAG_CC3OFŸÚPTIM_FLAG_CC4OFžÚPTIM_CHANNEL_1ßÚPTIM_CHANNEL_2ÞÚPTIM_CHANNEL_3ÝÚPTIM_CHANNEL_4ÜÚPTIM_CHANNEL_ALL3Ú!PTIM_CLOCKSOURCE_INTERNALYÚ!PTIM_CLOCKSOURCE_ETRMODE1uÚ!PTIM_CLOCKSOURCE_ETRMODE2tÚPTIM_CLOCKSOURCE_TI1EDeÚPTIM_CLOCKSOURCE_TI1òÚPTIM_CLOCKSOURCE_TI2ñÚPTIM_CLOCKSOURCE_ITR0ŸÚPTIM_CLOCKSOURCE_ITR1žÚPTIM_CLOCKSOURCE_ITR2ÚPTIM_CLOCKSOURCE_ITR3œÚ#PTIM_CLOCKPOLARITY_INVERTED®Ú&PTIM_CLOCKPOLARITY_NONINVERTED½Ú!PTIM_CLOCKPOLARITY_RISINGGÚ"PTIM_CLOCKPOLARITY_FALLINGÚ#PTIM_CLOCKPOLARITY_BOTHEDGEÍÚ PTIM_CLOCKPRESCALER_DIV1ÔÚ PTIM_CLOCKPRESCALER_DIV2ÓÚ PTIM_CLOCKPRESCALER_DIV4ÑÚ PTIM_CLOCKPRESCALER_DIV8ÍÚ(P TIM_CLEARINPUTPOLARITY_INVERTEDÚ+P#TIM_CLEARINPUTPOLARITY_NONINVERTED(Ú%PTIM_CLEARINPUTPRESCALER_DIV1?Ú%PTIM_CLEARINPUTPRESCALER_DIV2>Ú%PTIM_CLEARINPUTPRESCALER_DIV4<Ú%PTIM_CLEARINPUTPRESCALER_DIV88ÚPTIM_TRGO_RESETHÚPTIM_TRGO_ENABLE"ÚPTIM_TRGO_UPDATEÚP TIM_TRGO_OC1ÚPTIM_TRGO_OC1REF)ÚPTIM_TRGO_OC2REF(ÚPTIM_TRGO_OC3REF'ÚPTIM_TRGO_OC4REF&Ú#PTIM_MASTERSLAVEMODE_ENABLEÜÚ$PTIM_MASTERSLAVEMODE_DISABLEÚPTIM_SLAVEMODE_DISABLEeÚPTIM_SLAVEMODE_RESETÚÚPTIM_SLAVEMODE_GATEDøÚPTIM_SLAVEMODE_TRIGGEREÚ PTIM_SLAVEMODE_EXTERNAL1ÁÚPTIM_OCMODE_TIMING‚ÚPTIM_OCMODE_ACTIVEŽÚPTIM_OCMODE_INACTIVEóÚPTIM_OCMODE_TOGGLEˆÚPTIM_OCMODE_PWM1)ÚPTIM_OCMODE_PWM2(Ú!PTIM_OCMODE_FORCED_ACTIVEnÚ#PTIM_OCMODE_FORCED_INACTIVEÓÚPTIM_TS_ITR0GÚPTIM_TS_ITR1FÚPTIM_TS_ITR2EÚPTIM_TS_ITR3DÚPTIM_TS_TI1F_EDdÚPTIM_TS_TI1FP1ÍÚPTIM_TS_TI2FP2ËÚPTIM_TS_ETRF5ÚPTIM_TS_NONE6Ú%PTIM_TRIGGERPOLARITY_INVERTEDÚ(P TIM_TRIGGERPOLARITY_NONINVERTEDÚ#PTIM_TRIGGERPOLARITY_RISING›Ú$PTIM_TRIGGERPOLARITY_FALLINGhÚ%PTIM_TRIGGERPOLARITY_BOTHEDGE!Ú"PTIM_TRIGGERPRESCALER_DIV1(Ú"PTIM_TRIGGERPRESCALER_DIV2'Ú"PTIM_TRIGGERPRESCALER_DIV4%Ú"PTIM_TRIGGERPRESCALER_DIV8!ÚPTIM_TI1SELECTION_CH1ËÚ(P TIM_TI1SELECTION_XORCOMBINATIONEÚ%PTIM_DMABURSTLENGTH_1TRANSFER1Ú&PTIM_DMABURSTLENGTH_2TRANSFERSÛÚ&PTIM_DMABURSTLENGTH_3TRANSFERSÚÚ&PTIM_DMABURSTLENGTH_4TRANSFERSÙÚ&PTIM_DMABURSTLENGTH_5TRANSFERSØÚ&PTIM_DMABURSTLENGTH_6TRANSFERS×Ú&PTIM_DMABURSTLENGTH_7TRANSFERSÖÚ&PTIM_DMABURSTLENGTH_8TRANSFERSÕÚ&PTIM_DMABURSTLENGTH_9TRANSFERSÔÚ'PTIM_DMABURSTLENGTH_10TRANSFERSªÚ'PTIM_DMABURSTLENGTH_11TRANSFERS©Ú'PTIM_DMABURSTLENGTH_12TRANSFERS¨Ú'PTIM_DMABURSTLENGTH_13TRANSFERS§Ú'PTIM_DMABURSTLENGTH_14TRANSFERS¦Ú'PTIM_DMABURSTLENGTH_15TRANSFERS¥Ú'PTIM_DMABURSTLENGTH_16TRANSFERS¤Ú'PTIM_DMABURSTLENGTH_17TRANSFERS£Ú'PTIM_DMABURSTLENGTH_18TRANSFERS¢ÚPTIM_DMA_ID_UPDATE€ÚPTIM_DMA_ID_CC1’ÚPTIM_DMA_ID_CC2‘ÚPTIM_DMA_ID_CC3ÚPTIM_DMA_ID_CC4ÚPTIM_DMA_ID_TRIGGER-ÚPTIM_CCx_ENABLEbÚPTIM_CCx_DISABLEÚ%P__HAL_TIM_RESET_HANDLE_STATEêÚP__HAL_TIM_ENABLEÉÚP__HAL_TIM_DISABLEzÚP__HAL_TIM_ENABLE_ITÇÚP__HAL_TIM_DISABLE_ITxÚP__HAL_TIM_ENABLE_DMAÚP__HAL_TIM_DISABLE_DMAAÚP__HAL_TIM_GET_FLAGÚP__HAL_TIM_CLEAR_FLAGˆÚ P__HAL_TIM_GET_IT_SOURCEVÚP__HAL_TIM_CLEAR_IT    Ú'P__HAL_TIM_IS_TIM_COUNTING_DOWNÚ P__HAL_TIM_SET_PRESCALERvÚP__HAL_TIM_SET_COUNTERûÚP__HAL_TIM_GET_COUNTERÚ!P__HAL_TIM_SET_AUTORELOAD%Ú!P__HAL_TIM_GET_AUTORELOAD1Ú$P__HAL_TIM_SET_CLOCKDIVISION>Ú$P__HAL_TIM_GET_CLOCKDIVISIONJÚ"P__HAL_TIM_SET_ICPRESCALERæÚ"P__HAL_TIM_GET_ICPRESCALERòÚP__HAL_TIM_SET_COMPAREÚP__HAL_TIM_GET_COMPARE Ú$P__HAL_TIM_ENABLE_OCxPRELOADCÚ%P__HAL_TIM_DISABLE_OCxPRELOADôÚ!P__HAL_TIM_ENABLE_OCxFAST"Ú"P__HAL_TIM_DISABLE_OCxFASTÓÚP__HAL_TIM_URS_ENABLEhÚP__HAL_TIM_URS_DISABLEÚ&P__HAL_TIM_SET_CAPTUREPOLARITYƒÚ&P__HAL_TIM_SELECT_CCDMAREQUEST¶ÚPTIM_CCER_CCxE_MASKÚ!PIS_TIM_CLEARINPUT_SOURCE0ÚPIS_TIM_DMA_BASEÚPIS_TIM_EVENT_SOURCE¯ÚPIS_TIM_COUNTER_MODE½Ú!PIS_TIM_CLOCKDIVISION_DIVDÚ"PIS_TIM_AUTORELOAD_PRELOADÿÚPIS_TIM_FAST_STATEWÚPIS_TIM_OC_POLARITYþÚ%PIS_TIM_ENCODERINPUT_POLARITYìÚPIS_TIM_IC_POLARITYÚPIS_TIM_IC_SELECTIONÐÚPIS_TIM_IC_PRESCALERÕÚPIS_TIM_OPM_MODEùÚPIS_TIM_ENCODER_MODEÝÚPIS_TIM_DMA_SOURCEcÚPIS_TIM_CHANNELSÚPIS_TIM_OPM_CHANNELSÊÚPIS_TIM_PERIODªÚPIS_TIM_PRESCALERÆÚPIS_TIM_CLOCKSOURCE&ÚPIS_TIM_CLOCKPOLARITYÚPIS_TIM_CLOCKPRESCALERPÚPIS_TIM_CLOCKFILTER1Ú#PIS_TIM_CLEARINPUT_POLARITY‰Ú$PIS_TIM_CLEARINPUT_PRESCALERZÚ!PIS_TIM_CLEARINPUT_FILTER;ÚPIS_TIM_TRGO_SOURCE÷ÚPIS_TIM_MSM_STATEšÚPIS_TIM_SLAVE_MODEfÚPIS_TIM_PWM_MODEñÚPIS_TIM_OC_MODEUÚ!PIS_TIM_TRIGGER_SELECTION>Ú/P'IS_TIM_INTERNAL_TRIGGEREVENT_SELECTIONäÚPIS_TIM_TRIGGERPOLARITYÓÚ PIS_TIM_TRIGGERPRESCALER¤ÚPIS_TIM_TRIGGERFILTER…ÚPIS_TIM_TI1SELECTIONíÚPIS_TIM_DMA_LENGTHrÚPIS_TIM_DMA_DATA_LENGTHïÚPIS_TIM_IC_FILTER¶Ú)P!IS_TIM_SLAVEMODE_TRIGGER_ENABLEDêÚ!PTIM_SET_ICPRESCALERVALUE]Ú#PTIM_RESET_ICPRESCALERVALUEÂÚ PTIM_SET_CAPTUREPOLARITYÚ"PTIM_RESET_CAPTUREPOLARITYæÚPTIM_CHANNEL_STATE_GET@ÚPTIM_CHANNEL_STATE_SET4Ú"PTIM_CHANNEL_STATE_SET_ALLôÚPSTM32L0xx_HAL_TIM_EX_HºÚPTIM2_ETR_GPIO½ÚPTIM2_ETR_HSI16ŸÚP TIM2_ETR_LSE


ÚPTIM2_ETR_COMP2_OUT*ÚPTIM2_ETR_COMP1_OUT+ÚPTIM2_TI4_GPIO×ÚPTIM2_TI4_COMP2£ÚPTIM2_TI4_COMP1¤ÚPTIM3_TI4_GPIOC9_AF26ÚPTIM3_TI2_GPIO_DEF¢ÚPTIM3_TI2_GPIOB5_AF4;ÚPTIM3_TI1_GPIOÙÚPTIM3_ETR_GPIO¼ÚP TIM3_ETR_HSI    ÚPTIM21_ETR_GPIOŠÚPTIM21_ETR_COMP2_OUT÷ÚPTIM21_ETR_COMP1_OUTøÚPTIM21_ETR_LSE×ÚPTIM21_TI1_GPIO§ÚPTIM21_TI1_MCOùÚPTIM21_TI1_RTC_WKUT_IT9ÚPTIM21_TI1_HSE_RTC¨ÚPTIM21_TI1_MSIïÚPTIM21_TI1_LSEôÚPTIM21_TI1_LSIðÚPTIM21_TI1_COMP1_OUTÚPTIM21_TI2_GPIO¦ÚPTIM21_TI2_COMP2_OUTÚPTIM22_ETR_GPIO‰ÚPTIM22_ETR_COMP2_OUTöÚPTIM22_ETR_COMP1_OUT÷ÚPTIM22_ETR_LSEÖÚPTIM22_TI1_GPIO¦ÚPTIM22_TI1_COMP2_OUTÚPTIM22_TI1_COMP1_OUTÚP IS_TIM_REMAPúÚPIS_CHANNEL_AVAILABLEÏÚ ,htimÚ,sMasterConfig‚Ú.&HAL_TIMEx_MasterConfigSynchronizationPÚ ,htimÚ,


RemapàÚHAL_TIMEx_RemapConfig9Ú ,htimÚHAL_TIM_Base_InitÛÚ ,htimÚHAL_TIM_Base_DeInit.Ú ,htimÚHAL_TIM_Base_MspInit¥Ú ,htimÚHAL_TIM_Base_MspDeInitøÚ ,htimÚHAL_TIM_Base_Start_Ú ,htimÚHAL_TIM_Base_StopÉÚ ,htimÚHAL_TIM_Base_Start_IT]Ú ,htimÚHAL_TIM_Base_Stop_ITÇÚ ,htimÚ,pDataÝÚ,LengthoÚHAL_TIM_Base_Start_DMA&Ú ,htimÚHAL_TIM_Base_Stop_DMAÚ ,htimÚHAL_TIM_OC_InitÈÚ ,htimÚHAL_TIM_OC_DeInitÚ ,htimÚHAL_TIM_OC_MspInit’Ú ,htimÚHAL_TIM_OC_MspDeInitåÚ ,htimÚ,


ChannelÚHAL_TIM_OC_StartLÚ ,htimÚ,


ChannelÚHAL_TIM_OC_Stop¶Ú ,htimÚ,


ChannelÚHAL_TIM_OC_Start_ITJÚ ,htimÚ,


ChannelÚHAL_TIM_OC_Stop_IT´Ú ,htimÚ,


ChannelÚ,pDataÝÚ,LengthoÚHAL_TIM_OC_Start_DMAÚ ,htimÚ,


ChannelÚHAL_TIM_OC_Stop_DMA}Ú ,htimÚHAL_TIM_PWM_InitdÚ ,htimÚHAL_TIM_PWM_DeInit·Ú ,htimÚHAL_TIM_PWM_MspInit.Ú ,htimÚHAL_TIM_PWM_MspDeInitÚ ,htimÚ,


ChannelÚHAL_TIM_PWM_StartèÚ ,htimÚ,


ChannelÚHAL_TIM_PWM_StopRÚ ,htimÚ,


ChannelÚHAL_TIM_PWM_Start_ITæÚ ,htimÚ,


ChannelÚHAL_TIM_PWM_Stop_ITPÚ ,htimÚ,


ChannelÚ,pDataÝÚ,LengthoÚHAL_TIM_PWM_Start_DMA¯Ú ,htimÚ,


ChannelÚHAL_TIM_PWM_Stop_DMAÚ ,htimÚHAL_TIM_IC_InitÎÚ ,htimÚHAL_TIM_IC_DeInit!Ú ,htimÚHAL_TIM_IC_MspInit˜Ú ,htimÚHAL_TIM_IC_MspDeInitëÚ ,htimÚ,


ChannelÚHAL_TIM_IC_StartRÚ ,htimÚ,


ChannelÚHAL_TIM_IC_Stop¼Ú ,htimÚ,


ChannelÚHAL_TIM_IC_Start_ITPÚ ,htimÚ,


ChannelÚHAL_TIM_IC_Stop_ITºÚ ,htimÚ,


ChannelÚ,pDataÝÚ,LengthoÚHAL_TIM_IC_Start_DMAÚ ,htimÚ,


ChannelÚHAL_TIM_IC_Stop_DMAƒÚ ,htimÚ,


 OnePulseModeÚHAL_TIM_OnePulse_Init#Ú ,htimÚ HAL_TIM_OnePulse_DeInitvÚ ,htimÚ!HAL_TIM_OnePulse_MspInitíÚ ,htimÚ#HAL_TIM_OnePulse_MspDeInit@Ú ,htimÚ,


OutputChannel{ÚHAL_TIM_OnePulse_Start§Ú ,htimÚ,


OutputChannel{ÚHAL_TIM_OnePulse_StopÚ ,htimÚ,


OutputChannel{Ú"HAL_TIM_OnePulse_Start_IT¥Ú ,htimÚ,


OutputChannel{Ú!HAL_TIM_OnePulse_Stop_ITÚ ,htimÚ,sConfigúÚHAL_TIM_Encoder_InitÚ ,htimÚHAL_TIM_Encoder_DeInitãÚ ,htimÚ HAL_TIM_Encoder_MspInitZÚ ,htimÚ"HAL_TIM_Encoder_MspDeInit­Ú ,htimÚ,


ChannelÚHAL_TIM_Encoder_StartÚ ,htimÚ,


ChannelÚHAL_TIM_Encoder_Stop~Ú ,htimÚ,


ChannelÚ!HAL_TIM_Encoder_Start_ITÚ ,htimÚ,


ChannelÚ HAL_TIM_Encoder_Stop_IT|Ú ,htimÚ,


ChannelÚ,pData1ªÚ,pData2©Ú,LengthoÚ"HAL_TIM_Encoder_Start_DMAÛÚ ,htimÚ,


ChannelÚ!HAL_TIM_Encoder_Stop_DMAEÚ ,htimÚHAL_TIM_IRQHandlerÚ ,htimÚ,sConfigúÚ,


ChannelÚ!HAL_TIM_OC_ConfigChannel;Ú ,htimÚ,sConfigúÚ,


ChannelÚ"HAL_TIM_PWM_ConfigChannel×Ú ,htimÚ,sConfigúÚ,


ChannelÚ!HAL_TIM_IC_ConfigChannelAÚ ,htimÚ,sConfigúÚ,


OutputChannel{Ú,


 InputChannelþÚ'HAL_TIM_OnePulse_ConfigChannel–Ú ,htimÚ,sClearInputConfigïÚ,


ChannelÚ!HAL_TIM_ConfigOCrefClear/Ú ,htimÚ,sClockSourceConfig‡Ú"HAL_TIM_ConfigClockSource†Ú ,htimÚ,


TI1_SelectionòÚHAL_TIM_ConfigTI1InputÚ ,htimÚ, sSlaveConfigõÚ#HAL_TIM_SlaveConfigSynchroÚ ,htimÚ, sSlaveConfigõÚ&HAL_TIM_SlaveConfigSynchro_ITþÚ ,htimÚ,


BurstBaseAddressnÚ,


BurstRequestSrc Ú,BurstBufferQÚ,


BurstLengthWÚ$HAL_TIM_DMABurst_WriteStartÛÚ ,htimÚ,


BurstBaseAddressnÚ,


BurstRequestSrc Ú,BurstBufferQÚ,


BurstLengthWÚ,


DataLengthïÚ)!HAL_TIM_DMABurst_MultiWriteStartÆÚ ,htimÚ,


BurstRequestSrc Ú#HAL_TIM_DMABurst_WriteStopEÚ ,htimÚ,


BurstBaseAddressnÚ,


BurstRequestSrc Ú,BurstBufferQÚ,


BurstLengthWÚ#HAL_TIM_DMABurst_ReadStartlÚ ,htimÚ,


BurstBaseAddressnÚ,


BurstRequestSrc Ú,BurstBufferQÚ,


BurstLengthWÚ,


DataLengthïÚ( HAL_TIM_DMABurst_MultiReadStartWÚ ,htimÚ,


BurstRequestSrc Ú"HAL_TIM_DMABurst_ReadStopÖÚ ,htimÚ,


EventSourceVÚHAL_TIM_GenerateEventÚ ,htimÚ,


ChannelÚ"HAL_TIM_ReadCapturedValueˆÚ ,htimÚ&HAL_TIM_PeriodElapsedCallbackÚ ,htimÚ.&HAL_TIM_PeriodElapsedHalfCpltCallbackåÚ ,htimÚ( HAL_TIM_OC_DelayElapsedCallback‚Ú ,htimÚ#HAL_TIM_IC_CaptureCallbackkÚ ,htimÚ+#HAL_TIM_IC_CaptureHalfCpltCallbackMÚ ,htimÚ*"HAL_TIM_PWM_PulseFinishedCallback–Ú ,htimÚ2*HAL_TIM_PWM_PulseFinishedHalfCpltCallbackxÚ ,htimÚ HAL_TIM_TriggerCallback\Ú ,htimÚ( HAL_TIM_TriggerHalfCpltCallback>Ú ,htimÚHAL_TIM_ErrorCallback*Ú ,htimÚHAL_TIM_Base_GetStateFÚ ,htimÚHAL_TIM_OC_GetState3Ú ,htimÚHAL_TIM_PWM_GetStateÏÚ ,htimÚHAL_TIM_IC_GetState9Ú ,htimÚ"HAL_TIM_OnePulse_GetStateŽÚ ,htimÚ!HAL_TIM_Encoder_GetStateûÚ ,htimÚ!HAL_TIM_GetActiveChannelÚ ,htimÚ,


ChannelÚ HAL_TIM_GetChannelStatecÚ ,htimÚHAL_TIM_DMABurstState^Ú ,hdma/Ú TIM_DMAError«Ú ,hdma/ÚTIM_DMACaptureCpltBÚ ,hdma/ÚTIM_DMACaptureHalfCplt¿ÚPHAL_TSC_MODULE_ENABLEDÚPSTM32L0xx_HAL_UART_HhÚ8


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"éXOverrunDisableÇÚ 


"éXDMADisableonRxError+Ú 


"éXAutoBaudRateEnable|Ú 


"éXAutoBaudRateModeBÚ 


"éX    MSBFirstŽÚ#UART_AdvFeatureInitTypeDefÚHAL_UART_StateTypeDefVÚUART_CLOCKSOURCE_PCLK1?ÚUART_CLOCKSOURCE_PCLK2>ÚUART_CLOCKSOURCE_HSIºÚ UART_CLOCKSOURCE_SYSCLK¿ÚUART_CLOCKSOURCE_LSEºÚ#UART_CLOCKSOURCE_UNDEFINEDÚ UART_ClockSourceTypeDef*ÚHAL_UART_RxTypeTypeDeféÚ$HAL_UART_RxEventTypeTypeDefÝÚ8__UART_HandleTypeDefGÚ "ÿX    InstanceÚ " ÿXInit¨Ú "(ÿX AdvancedInitzÚ "ÿXpTxBuffPtr[Ú "ÿXTxXferSize`Ú "ÿXTxXferCountðÚ "ÿXpRxBuffPtr]Ú "ÿXRxXferSizebÚ "ÿXRxXferCountòÚ "ÿXMaskÜÚ 


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