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2024-04-03 c8cd9a085e6a250941fb463b3cba5f31f592f7ba

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..\Drivers\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_tim.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM__asm___19_stm32l0xx_hal_tim_c_a9d95b52____REV16X>

 




..\Drivers\CMSIS\Include\cmsis_armcc.h
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..\Drivers\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_tim.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM__asm___19_stm32l0xx_hal_tim_c_a9d95b52____REVSHX>

 




..\Drivers\CMSIS\Include\cmsis_armcc.h
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__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
__SOFTFP__ 1
'
ØHAL_TIM_Base_MspInit$,
ØHAL_TIM_Base_Init)
ØHAL_TIM_Base_MspDeInit&,
ØHAL_TIM_Base_DeInit%<
ØHAL_TIM_Base_Start$(
ØHAL_TIM_Base_Stop(<
ØHAL_TIM_Base_Start_IT',
ØHAL_TIM_Base_Stop_IT(
ØHAL_TIM_ErrorCallback
ØTIM_DMAError8 
ØHAL_TIM_PeriodElapsedHalfCpltCallback0
ØHAL_TIM_PeriodElapsedCallback)`
ØHAL_TIM_Base_Start_DMA(,
ØHAL_TIM_Base_Stop_DMA%
ØHAL_TIM_OC_MspInit"(
ØHAL_TIM_OC_Init'
ØHAL_TIM_OC_MspDeInit$(
ØHAL_TIM_OC_DeInit#L
ØHAL_TIM_OC_Start"<
ØHAL_TIM_OC_Stop&`
ØHAL_TIM_OC_Start_IT%L
ØHAL_TIM_OC_Stop_IT<$
ØHAL_TIM_PWM_PulseFinishedHalfCpltCallback4
ØHAL_TIM_PWM_PulseFinishedCallback'€
ØHAL_TIM_OC_Start_DMA&P
ØHAL_TIM_OC_Stop_DMA&
ØHAL_TIM_PWM_MspInit#(
ØHAL_TIM_PWM_Init(
ØHAL_TIM_PWM_MspDeInit%,
ØHAL_TIM_PWM_DeInit$L
ØHAL_TIM_PWM_Start#<
ØHAL_TIM_PWM_Stop'`
ØHAL_TIM_PWM_Start_IT&P
ØHAL_TIM_PWM_Stop_IT(€
ØHAL_TIM_PWM_Start_DMA'P
ØHAL_TIM_PWM_Stop_DMA%
ØHAL_TIM_IC_MspInit"(
ØHAL_TIM_IC_Init'
ØHAL_TIM_IC_MspDeInit$(
ØHAL_TIM_IC_DeInit#`
ØHAL_TIM_IC_Start"<
ØHAL_TIM_IC_Stop&t
ØHAL_TIM_IC_Start_IT%L
ØHAL_TIM_IC_Stop_IT5 
ØHAL_TIM_IC_CaptureHalfCpltCallback)$
ØTIM_DMACaptureHalfCplt-
ØHAL_TIM_IC_CaptureCallback% 
ØTIM_DMACaptureCplt'˜
ØHAL_TIM_IC_Start_DMA&P
ØHAL_TIM_IC_Stop_DMA+
ØHAL_TIM_OnePulse_MspInit(D
ØHAL_TIM_OnePulse_Init-
ØHAL_TIM_OnePulse_MspDeInit*0
ØHAL_TIM_OnePulse_DeInit)x
ØHAL_TIM_OnePulse_Start(@
ØHAL_TIM_OnePulse_Stop,|
ØHAL_TIM_OnePulse_Start_IT+D
ØHAL_TIM_OnePulse_Stop_IT*
ØHAL_TIM_Encoder_MspInit'l
ØHAL_TIM_Encoder_Init,
ØHAL_TIM_Encoder_MspDeInit)0
ØHAL_TIM_Encoder_DeInit(t
ØHAL_TIM_Encoder_Start'@
ØHAL_TIM_Encoder_Stop+x
ØHAL_TIM_Encoder_Start_IT*@
ØHAL_TIM_Encoder_Stop_IT,¬
ØHAL_TIM_Encoder_Start_DMA+D
ØHAL_TIM_Encoder_Stop_DMA*
ØHAL_TIM_TriggerCallback2
ØHAL_TIM_OC_DelayElapsedCallback%
ØHAL_TIM_IRQHandler+d
ØHAL_TIM_OC_ConfigChannel+Ü
ØHAL_TIM_IC_ConfigChannel,h
ØHAL_TIM_PWM_ConfigChannel1˜
ØHAL_TIM_OnePulse_ConfigChannel2
ØHAL_TIM_TriggerHalfCpltCallback3À
ØHAL_TIM_DMABurst_MultiWriteStart. 
ØHAL_TIM_DMABurst_WriteStart-\
ØHAL_TIM_DMABurst_WriteStop2À
ØHAL_TIM_DMABurst_MultiReadStart- 
ØHAL_TIM_DMABurst_ReadStart,\
ØHAL_TIM_DMABurst_ReadStop(D
ØHAL_TIM_GenerateEvent+p
ØHAL_TIM_ConfigOCrefClear,p
ØHAL_TIM_ConfigClockSource)T
ØHAL_TIM_ConfigTI1Input-L
ØHAL_TIM_SlaveConfigSynchro0L
ØHAL_TIM_SlaveConfigSynchro_IT,T
ØHAL_TIM_ReadCapturedValue(,
ØHAL_TIM_Base_GetState&,
ØHAL_TIM_OC_GetState',
ØHAL_TIM_PWM_GetState&,
ØHAL_TIM_IC_GetState,0
ØHAL_TIM_OnePulse_GetState+0
ØHAL_TIM_Encoder_GetState+0
ØHAL_TIM_GetActiveChannel*X
ØHAL_TIM_GetChannelState(,
ØHAL_TIM_DMABurstState
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__stdint_h 
__ARMCLIB_VERSION 5060037
__INT64 __int64
__INT64_C_SUFFIX__ ll
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__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
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__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
,__CLIBNS 
sINT8_MIN -128
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yINT8_MAX 127
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SIG_ATOMIC_MAX 2147483647
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SIZE_MAX UINT32_MAXç
WCHAR_MINè
WCHAR_MAX
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WCHAR_MIN 0
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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h


C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
signed charshortintlong long
unsigned charunsigned shortunsigned intunsigned long longPint8_tŠ
8 Pint16_t™
9 Pint32_t¢
: Pint64_t©
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@ Puint64_té
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I Pint_least64_t©
J Puint_least8_t¶
M Puint_least16_tÇ
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P Pint_fast8_t¢
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#__CM_CMSIS_VERSION_MAIN ( 5U)
$__CM_CMSIS_VERSION_SUB ( 1U)
%__CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB )L@
 




../Drivers/CMSIS/Include/cmsis_version.h


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../Drivers/CMSIS/Include/cmsis_version.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
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__CMSIS_ARMCC_H 
$__ARM_ARCH_6M__ 1
5__ASM __asm
8__INLINE __inline
;__STATIC_INLINE static __inline
>__STATIC_FORCEINLINE static __forceinline
A__NO_RETURN __declspec(noreturn)
D__USED __attribute__((used))
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M__PACKED_STRUCT __packed struct
P__PACKED_UNION __packed union
S__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
V__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val))
Y__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
\__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val))
___UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
b__ALIGNED(x) __attribute__((aligned(x)))
e__RESTRICT __restrict
ƒ__NOP __nop
Š__WFI __wfi
’__WFE __wfe
™__SEV __sev
¢__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U)
­__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U)
¸__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U)
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œ__CLZ __clzH>
 




../Drivers/CMSIS/Include/cmsis_armcc.h


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../Drivers/CMSIS/Include/cmsis_armcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM;„
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../Drivers/CMSIS/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.h
stdint.hcmsis_armcc.h


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../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
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 ARM_MPU_ARMV7_H 
"ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
$ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
%ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
&ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
'ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
(ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
)ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
*ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
,ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
-ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
.ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
/ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
0ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
1ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
2ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
3ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
4ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
5ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
6ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
7ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
8ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
9ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
:ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
;ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
<ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
=ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
?ARM_MPU_AP_NONE 0U
@ARM_MPU_AP_PRIV 1U
AARM_MPU_AP_URO 2U
BARM_MPU_AP_FULL 3U
CARM_MPU_AP_PRO 5U
DARM_MPU_AP_RO 6U
KARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk))
XARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
gARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
xARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
‚
ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
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ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
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ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
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ARM_MPU_CACHEP_NOCACHE 0U
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../Drivers/CMSIS/Include/mpu_armv7.h


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../Drivers/CMSIS/Include/mpu_armv7.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*â
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B__CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
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D__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
G__CORTEX_M (0U)
L__FPU_USED 0Us
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__I volatile const
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²
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APSR_N_Pos 31U
á
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APSR_Z_Pos 30U
ä
APSR_Z_Msk (1UL << APSR_Z_Pos)
æ
APSR_C_Pos 29U
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APSR_C_Msk (1UL << APSR_C_Pos)
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APSR_V_Pos 28U
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APSR_V_Msk (1UL << APSR_V_Pos)
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IPSR_ISR_Pos 0U
ü
IPSR_ISR_Msk (0x1FFUL )
“xPSR_N_Pos 31U
”xPSR_N_Msk (1UL << xPSR_N_Pos)
–xPSR_Z_Pos 30U
—xPSR_Z_Msk (1UL << xPSR_Z_Pos)
™xPSR_C_Pos 29U
šxPSR_C_Msk (1UL << xPSR_C_Pos)
œxPSR_V_Pos 28U
xPSR_V_Msk (1UL << xPSR_V_Pos)
ŸxPSR_T_Pos 24U
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¢xPSR_ISR_Pos 0U
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µCONTROL_SPSEL_Pos 1U
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¸CONTROL_nPRIV_Pos 0U
¹CONTROL_nPRIV_Msk (1UL )
õSCB_CPUID_IMPLEMENTER_Pos 24U
öSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
øSCB_CPUID_VARIANT_Pos 20U
ùSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ûSCB_CPUID_ARCHITECTURE_Pos 16U
üSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
þSCB_CPUID_PARTNO_Pos 4U
ÿSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
SCB_CPUID_REVISION_Pos 0U
‚SCB_CPUID_REVISION_Msk (0xFUL )
…SCB_ICSR_NMIPENDSET_Pos 31U
†SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ˆSCB_ICSR_PENDSVSET_Pos 28U
‰SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
‹SCB_ICSR_PENDSVCLR_Pos 27U
ŒSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
ŽSCB_ICSR_PENDSTSET_Pos 26U
SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
‘SCB_ICSR_PENDSTCLR_Pos 25U
’SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
”SCB_ICSR_ISRPREEMPT_Pos 23U
•SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
—SCB_ICSR_ISRPENDING_Pos 22U
˜SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
šSCB_ICSR_VECTPENDING_Pos 12U
›SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
SCB_ICSR_VECTACTIVE_Pos 0U
žSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
¢SCB_VTOR_TBLOFF_Pos 8U
£SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
§SCB_AIRCR_VECTKEY_Pos 16U
¨SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ªSCB_AIRCR_VECTKEYSTAT_Pos 16U
«SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
­SCB_AIRCR_ENDIANESS_Pos 15U
®SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
°SCB_AIRCR_SYSRESETREQ_Pos 2U
±SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
³SCB_AIRCR_VECTCLRACTIVE_Pos 1U
´SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
·SCB_SCR_SEVONPEND_Pos 4U
¸SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
ºSCB_SCR_SLEEPDEEP_Pos 2U
»SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
½SCB_SCR_SLEEPONEXIT_Pos 1U
¾SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
ÁSCB_CCR_STKALIGN_Pos 9U
ÂSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
ÄSCB_CCR_UNALIGN_TRP_Pos 3U
ÅSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
ÈSCB_SHCSR_SVCALLPENDED_Pos 15U
ÉSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
áSysTick_CTRL_COUNTFLAG_Pos 16U
âSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
äSysTick_CTRL_CLKSOURCE_Pos 2U
åSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
çSysTick_CTRL_TICKINT_Pos 1U
èSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
êSysTick_CTRL_ENABLE_Pos 0U
ëSysTick_CTRL_ENABLE_Msk (1UL )
îSysTick_LOAD_RELOAD_Pos 0U
ïSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
òSysTick_VAL_CURRENT_Pos 0U
óSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
öSysTick_CALIB_NOREF_Pos 31U
÷SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ùSysTick_CALIB_SKEW_Pos 30U
úSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
üSysTick_CALIB_TENMS_Pos 0U
ýSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
•MPU_TYPE_RALIASES 1U
˜MPU_TYPE_IREGION_Pos 16U
™MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
›MPU_TYPE_DREGION_Pos 8U
œMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
žMPU_TYPE_SEPARATE_Pos 0U
ŸMPU_TYPE_SEPARATE_Msk (1UL )
¢MPU_CTRL_PRIVDEFENA_Pos 2U
£MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
¥MPU_CTRL_HFNMIENA_Pos 1U
¦MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
¨MPU_CTRL_ENABLE_Pos 0U
©MPU_CTRL_ENABLE_Msk (1UL )
¬MPU_RNR_REGION_Pos 0U
­MPU_RNR_REGION_Msk (0xFFUL )
°MPU_RBAR_ADDR_Pos 8U
±MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
³MPU_RBAR_VALID_Pos 4U
´MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
¶MPU_RBAR_REGION_Pos 0U
·MPU_RBAR_REGION_Msk (0xFUL )
ºMPU_RASR_ATTRS_Pos 16U
»MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
½MPU_RASR_XN_Pos 28U
¾MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
ÀMPU_RASR_AP_Pos 24U
ÁMPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
ÃMPU_RASR_TEX_Pos 19U
ÄMPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
ÆMPU_RASR_S_Pos 18U
ÇMPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
ÉMPU_RASR_C_Pos 17U
ÊMPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
ÌMPU_RASR_B_Pos 16U
ÍMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
ÏMPU_RASR_SRD_Pos 8U
ÐMPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
ÒMPU_RASR_SIZE_Pos 1U
ÓMPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
ÕMPU_RASR_ENABLE_Pos 0U
ÖMPU_RASR_ENABLE_Msk (1UL )
ó_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
û_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ˆSCS_BASE (0xE000E000UL)
‰SysTick_BASE (SCS_BASE + 0x0010UL)
ŠNVIC_BASE (SCS_BASE + 0x0100UL)
‹SCB_BASE (SCS_BASE + 0x0D00UL)
SCB ((SCB_Type *) SCB_BASE )
ŽSysTick ((SysTick_Type *) SysTick_BASE )
NVIC ((NVIC_Type *) NVIC_BASE )
’MPU_BASE (SCS_BASE + 0x0D90UL)
“MPU ((MPU_Type *) MPU_BASE )
µNVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
¶NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
·NVIC_EnableIRQ __NVIC_EnableIRQ
¸NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
¹NVIC_DisableIRQ __NVIC_DisableIRQ
ºNVIC_GetPendingIRQ __NVIC_GetPendingIRQ
»NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
¼NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
¾NVIC_SetPriority __NVIC_SetPriority
¿NVIC_GetPriority __NVIC_GetPriority
ÀNVIC_SystemReset __NVIC_SystemReset
ÉNVIC_SetVector __NVIC_SetVector
ÊNVIC_GetVector __NVIC_GetVector
ÍNVIC_USER_IRQ_OFFSET 16
ÑEXC_RETURN_HANDLER (0xFFFFFFF1UL)
ÒEXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
ÓEXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
Ø_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Ù_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Ú_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Ü__NVIC_SetPriorityGrouping(X) (void)(X)
Ý__NVIC_GetPriorityGrouping() (0U)ë°¦
 




../Drivers/CMSIS/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcmsis_version.h
cmsis_compiler.h
mpu_armv7.h


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../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h


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$__STM32L071xx_H 
1__CM0PLUS_REV 0U
2__MPU_PRESENT 1U
3__VTOR_PRESENT 1U
4__NVIC_PRIO_BITS 2U
5__Vendor_SysTickConfig 0Uqrs
ýFLASH_BASE (0x08000000UL)
ÿDATA_EEPROM_BASE (0x08080000UL)
€DATA_EEPROM_BANK2_BASE (0x08080C00UL)
DATA_EEPROM_BANK1_END (0x08080BFFUL)
‚DATA_EEPROM_BANK2_END (0x080817FFUL)
ƒSRAM_BASE (0x20000000UL)
„SRAM_SIZE_MAX (0x00005000UL)
†PERIPH_BASE (0x40000000UL)
‰APBPERIPH_BASE PERIPH_BASE
ŠAHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
‹IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
ŽTIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
‘RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
’WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
“IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
”SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
•USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
–LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
—USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
˜USART5_BASE (APBPERIPH_BASE + 0x00005000UL)
™I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
šI2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
›PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
œLPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
I2C3_BASE (APBPERIPH_BASE + 0x00007800UL)
ŸSYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
 COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
¡COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
¢COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
£EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
¤TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
¥TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
¦FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
§ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
¨ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
©SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
ªUSART1_BASE (APBPERIPH_BASE + 0x00013800UL)
«DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
­DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
®DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
¯DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
°DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
±DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
²DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
³DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
´DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
µDMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
¸RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
¹FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
ºOB_BASE (0x1FF80000UL)
»FLASHSIZE_BASE (0x1FF8007CUL)
¼UID_BASE (0x1FF80050UL)
½CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
¿GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
ÀGPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
ÁGPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
ÂGPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
ÃGPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)
ÄGPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
ÎTIM2 ((TIM_TypeDef *) TIM2_BASE)
ÏTIM3 ((TIM_TypeDef *) TIM3_BASE)
ÐTIM6 ((TIM_TypeDef *) TIM6_BASE)
ÑTIM7 ((TIM_TypeDef *) TIM7_BASE)
ÒRTC ((RTC_TypeDef *) RTC_BASE)
ÓWWDG ((WWDG_TypeDef *) WWDG_BASE)
ÔIWDG ((IWDG_TypeDef *) IWDG_BASE)
ÕSPI2 ((SPI_TypeDef *) SPI2_BASE)
ÖUSART2 ((USART_TypeDef *) USART2_BASE)
×LPUART1 ((USART_TypeDef *) LPUART1_BASE)
ØI2C1 ((I2C_TypeDef *) I2C1_BASE)
ÙI2C2 ((I2C_TypeDef *) I2C2_BASE)
ÚI2C3 ((I2C_TypeDef *) I2C3_BASE)
ÛPWR ((PWR_TypeDef *) PWR_BASE)
ÜLPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
ÝUSART4 ((USART_TypeDef *) USART4_BASE)
ÞUSART5 ((USART_TypeDef *) USART5_BASE)
àSYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
áCOMP1 ((COMP_TypeDef *) COMP1_BASE)
âCOMP2 ((COMP_TypeDef *) COMP2_BASE)
ãEXTI ((EXTI_TypeDef *) EXTI_BASE)
äTIM21 ((TIM_TypeDef *) TIM21_BASE)
åTIM22 ((TIM_TypeDef *) TIM22_BASE)
æFIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
çADC1 ((ADC_TypeDef *) ADC1_BASE)
èADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
êADC ADC1_COMMON
ëSPI1 ((SPI_TypeDef *) SPI1_BASE)
ìUSART1 ((USART_TypeDef *) USART1_BASE)
íDBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
ïDMA1 ((DMA_TypeDef *) DMA1_BASE)
ðDMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
ñDMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
òDMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
óDMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
ôDMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
õDMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
öDMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
÷DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
úFLASH ((FLASH_TypeDef *) FLASH_R_BASE)
ûOB ((OB_TypeDef *) OB_BASE)
üRCC ((RCC_TypeDef *) RCC_BASE)
ýCRC ((CRC_TypeDef *) CRC_BASE)
ÿGPIOA ((GPIO_TypeDef *) GPIOA_BASE)
€GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
‚GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
ƒGPIOE ((GPIO_TypeDef *) GPIOE_BASE)
„GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
‘LSI_STARTUP_TIME 200U
¤ADC_ISR_EOCAL_Pos (11U)
¥ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos)
¦ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk
§ADC_ISR_AWD_Pos (7U)
¨ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos)
©ADC_ISR_AWD ADC_ISR_AWD_Msk
ªADC_ISR_OVR_Pos (4U)
«ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
¬ADC_ISR_OVR ADC_ISR_OVR_Msk
­ADC_ISR_EOSEQ_Pos (3U)
®ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos)
¯ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk
°ADC_ISR_EOC_Pos (2U)
±ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
²ADC_ISR_EOC ADC_ISR_EOC_Msk
³ADC_ISR_EOSMP_Pos (1U)
´ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
µADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
¶ADC_ISR_ADRDY_Pos (0U)
·ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
¸ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
»ADC_ISR_EOS ADC_ISR_EOSEQ
¾ADC_IER_EOCALIE_Pos (11U)
¿ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos)
ÀADC_IER_EOCALIE ADC_IER_EOCALIE_Msk
ÁADC_IER_AWDIE_Pos (7U)
ÂADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos)
ÃADC_IER_AWDIE ADC_IER_AWDIE_Msk
ÄADC_IER_OVRIE_Pos (4U)
ÅADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
ÆADC_IER_OVRIE ADC_IER_OVRIE_Msk
ÇADC_IER_EOSEQIE_Pos (3U)
ÈADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos)
ÉADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk
ÊADC_IER_EOCIE_Pos (2U)
ËADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
ÌADC_IER_EOCIE ADC_IER_EOCIE_Msk
ÍADC_IER_EOSMPIE_Pos (1U)
ÎADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
ÏADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
ÐADC_IER_ADRDYIE_Pos (0U)
ÑADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
ÒADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
ÕADC_IER_EOSIE ADC_IER_EOSEQIE
ØADC_CR_ADCAL_Pos (31U)
ÙADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
ÚADC_CR_ADCAL ADC_CR_ADCAL_Msk
ÛADC_CR_ADVREGEN_Pos (28U)
ÜADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
ÝADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
ÞADC_CR_ADSTP_Pos (4U)
ßADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
àADC_CR_ADSTP ADC_CR_ADSTP_Msk
áADC_CR_ADSTART_Pos (2U)
âADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
ãADC_CR_ADSTART ADC_CR_ADSTART_Msk
äADC_CR_ADDIS_Pos (1U)
åADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
æADC_CR_ADDIS ADC_CR_ADDIS_Msk
çADC_CR_ADEN_Pos (0U)
èADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
éADC_CR_ADEN ADC_CR_ADEN_Msk
ìADC_CFGR1_AWDCH_Pos (26U)
íADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos)
îADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk
ïADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos)
ðADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos)
ñADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos)
òADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos)
óADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos)
ôADC_CFGR1_AWDEN_Pos (23U)
õADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos)
öADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk
÷ADC_CFGR1_AWDSGL_Pos (22U)
øADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos)
ùADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk
úADC_CFGR1_DISCEN_Pos (16U)
ûADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos)
üADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk
ýADC_CFGR1_AUTOFF_Pos (15U)
þADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos)
ÿADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk
€ADC_CFGR1_WAIT_Pos (14U)
ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos)
‚ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk
ƒADC_CFGR1_CONT_Pos (13U)
„ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos)
…ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk
†ADC_CFGR1_OVRMOD_Pos (12U)
‡ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos)
ˆADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk
‰ADC_CFGR1_EXTEN_Pos (10U)
ŠADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos)
‹ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk
ŒADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos)
ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos)
ŽADC_CFGR1_EXTSEL_Pos (6U)
ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos)
ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk
‘ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos)
’ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos)
“ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos)
”ADC_CFGR1_ALIGN_Pos (5U)
•ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos)
–ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk
—ADC_CFGR1_RES_Pos (3U)
˜ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)
™ADC_CFGR1_RES ADC_CFGR1_RES_Msk
šADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos)
›ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos)
œADC_CFGR1_SCANDIR_Pos (2U)
ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos)
žADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk
ŸADC_CFGR1_DMACFG_Pos (1U)
 ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)
¡ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk
¢ADC_CFGR1_DMAEN_Pos (0U)
£ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)
¤ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk
§ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
ªADC_CFGR2_TOVS_Pos (9U)
«ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos)
¬ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk
­ADC_CFGR2_OVSS_Pos (5U)
®ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
¯ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
°ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
±ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
²ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
³ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
´ADC_CFGR2_OVSR_Pos (2U)
µADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)
¶ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
·ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)
¸ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)
¹ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)
ºADC_CFGR2_OVSE_Pos (0U)
»ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos)
¼ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk
½ADC_CFGR2_CKMODE_Pos (30U)
¾ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos)
¿ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk
ÀADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos)
ÁADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos)
ÅADC_SMPR_SMP_Pos (0U)
ÆADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos)
ÇADC_SMPR_SMP ADC_SMPR_SMP_Msk
ÈADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos)
ÉADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos)
ÊADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos)
ÍADC_SMPR_SMPR ADC_SMPR_SMP
ÎADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
ÏADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
ÐADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
ÓADC_TR_HT_Pos (16U)
ÔADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos)
ÕADC_TR_HT ADC_TR_HT_Msk
ÖADC_TR_LT_Pos (0U)
×ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos)
ØADC_TR_LT ADC_TR_LT_Msk
ÛADC_CHSELR_CHSEL_Pos (0U)
ÜADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)
ÝADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk
ÞADC_CHSELR_CHSEL18_Pos (18U)
ßADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos)
àADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk
áADC_CHSELR_CHSEL17_Pos (17U)
âADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos)
ãADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk
äADC_CHSELR_CHSEL15_Pos (15U)
åADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos)
æADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk
çADC_CHSELR_CHSEL14_Pos (14U)
èADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos)
éADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk
êADC_CHSELR_CHSEL13_Pos (13U)
ëADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos)
ìADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk
íADC_CHSELR_CHSEL12_Pos (12U)
îADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos)
ïADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk
ðADC_CHSELR_CHSEL11_Pos (11U)
ñADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos)
òADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk
óADC_CHSELR_CHSEL10_Pos (10U)
ôADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos)
õADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk
öADC_CHSELR_CHSEL9_Pos (9U)
÷ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos)
øADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk
ùADC_CHSELR_CHSEL8_Pos (8U)
úADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos)
ûADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk
üADC_CHSELR_CHSEL7_Pos (7U)
ýADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos)
þADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk
ÿADC_CHSELR_CHSEL6_Pos (6U)
€ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos)
ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk
‚ADC_CHSELR_CHSEL5_Pos (5U)
ƒADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos)
„ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk
…ADC_CHSELR_CHSEL4_Pos (4U)
†ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos)
‡ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk
ˆADC_CHSELR_CHSEL3_Pos (3U)
‰ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos)
ŠADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk
‹ADC_CHSELR_CHSEL2_Pos (2U)
ŒADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos)
ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk
ŽADC_CHSELR_CHSEL1_Pos (1U)
ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos)
ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk
‘ADC_CHSELR_CHSEL0_Pos (0U)
’ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos)
“ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk
–ADC_DR_DATA_Pos (0U)
—ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
˜ADC_DR_DATA ADC_DR_DATA_Msk
›ADC_CALFACT_CALFACT_Pos (0U)
œADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos)
ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk
 ADC_CCR_LFMEN_Pos (25U)
¡ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos)
¢ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk
£ADC_CCR_TSEN_Pos (23U)
¤ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
¥ADC_CCR_TSEN ADC_CCR_TSEN_Msk
¦ADC_CCR_VREFEN_Pos (22U)
§ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
¨ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
©ADC_CCR_PRESC_Pos (18U)
ªADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
«ADC_CCR_PRESC ADC_CCR_PRESC_Msk
¬ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
­ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
®ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
¯ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
¸COMP_CSR_COMP1EN_Pos (0U)
¹COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos)
ºCOMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk
»COMP_CSR_COMP1INNSEL_Pos (4U)
¼COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos)
½COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk
¾COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos)
¿COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos)
ÀCOMP_CSR_COMP1WM_Pos (8U)
ÁCOMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos)
ÂCOMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk
ÃCOMP_CSR_COMP1LPTIM1IN1_Pos (12U)
ÄCOMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)
ÅCOMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk
ÆCOMP_CSR_COMP1POLARITY_Pos (15U)
ÇCOMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos)
ÈCOMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk
ÉCOMP_CSR_COMP1VALUE_Pos (30U)
ÊCOMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos)
ËCOMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk
ÌCOMP_CSR_COMP1LOCK_Pos (31U)
ÍCOMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos)
ÎCOMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk
ÐCOMP_CSR_COMP2EN_Pos (0U)
ÑCOMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos)
ÒCOMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk
ÓCOMP_CSR_COMP2SPEED_Pos (3U)
ÔCOMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos)
ÕCOMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk
ÖCOMP_CSR_COMP2INNSEL_Pos (4U)
×COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos)
ØCOMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk
ÙCOMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos)
ÚCOMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos)
ÛCOMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos)
ÜCOMP_CSR_COMP2INPSEL_Pos (8U)
ÝCOMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos)
ÞCOMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk
ßCOMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos)
àCOMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos)
áCOMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos)
âCOMP_CSR_COMP2LPTIM1IN2_Pos (12U)
ãCOMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)
äCOMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk
åCOMP_CSR_COMP2LPTIM1IN1_Pos (13U)
æCOMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)
çCOMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk
èCOMP_CSR_COMP2POLARITY_Pos (15U)
éCOMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos)
êCOMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk
ëCOMP_CSR_COMP2VALUE_Pos (30U)
ìCOMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos)
íCOMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk
îCOMP_CSR_COMP2LOCK_Pos (31U)
ïCOMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos)
ðCOMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk
óCOMP_CSR_COMPxEN_Pos (0U)
ôCOMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos)
õCOMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk
öCOMP_CSR_COMPxPOLARITY_Pos (15U)
÷COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)
øCOMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk
ùCOMP_CSR_COMPxOUTVALUE_Pos (30U)
úCOMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)
ûCOMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk
üCOMP_CSR_COMPxLOCK_Pos (31U)
ýCOMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos)
þCOMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk
COMP_CSR_WINMODE COMP_CSR_COMP1WM
‰CRC_DR_DR_Pos (0U)
ŠCRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
‹CRC_DR_DR CRC_DR_DR_Msk
ŽCRC_IDR_IDR (0xFFU)
‘CRC_CR_RESET_Pos (0U)
’CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
“CRC_CR_RESET CRC_CR_RESET_Msk
”CRC_CR_POLYSIZE_Pos (3U)
•CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
–CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
—CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
˜CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
™CRC_CR_REV_IN_Pos (5U)
šCRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
›CRC_CR_REV_IN CRC_CR_REV_IN_Msk
œCRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
žCRC_CR_REV_OUT_Pos (7U)
ŸCRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
 CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
£CRC_INIT_INIT_Pos (0U)
¤CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
¥CRC_INIT_INIT CRC_INIT_INIT_Msk
¨CRC_POL_POL_Pos (0U)
©CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
ªCRC_POL_POL CRC_POL_POL_Msk
³DBGMCU_IDCODE_DEV_ID_Pos (0U)
´DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
µDBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
·DBGMCU_IDCODE_REV_ID_Pos (16U)
¸DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
¹DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
ºDBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)
»DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)
¼DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)
½DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)
¾DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)
¿DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)
ÀDBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)
ÁDBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)
ÂDBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)
ÃDBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)
ÄDBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)
ÅDBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)
ÆDBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)
ÇDBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)
ÈDBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)
ÉDBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)
ÌDBGMCU_CR_DBG_Pos (0U)
ÍDBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos)
ÎDBGMCU_CR_DBG DBGMCU_CR_DBG_Msk
ÏDBGMCU_CR_DBG_SLEEP_Pos (0U)
ÐDBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
ÑDBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
ÒDBGMCU_CR_DBG_STOP_Pos (1U)
ÓDBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
ÔDBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
ÕDBGMCU_CR_DBG_STANDBY_Pos (2U)
ÖDBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
×DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
ÚDBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
ÛDBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
ÜDBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
ÝDBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
ÞDBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
ßDBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
àDBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
áDBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
âDBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
ãDBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
äDBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
åDBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
æDBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
çDBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
èDBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
éDBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
êDBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
ëDBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
ìDBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
íDBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
îDBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
ïDBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
ðDBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos)
ñDBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk
òDBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
óDBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos)
ôDBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk
õDBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
öDBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos)
÷DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk
øDBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
ùDBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos)
úDBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk
üDBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
ýDBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos)
þDBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk
ÿDBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
€    DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos)
    DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk
Š    DMA_ISR_GIF1_Pos (0U)
‹    DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
Œ    DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
    DMA_ISR_TCIF1_Pos (1U)
Ž    DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
    DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
    DMA_ISR_HTIF1_Pos (2U)
‘    DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
’    DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
“    DMA_ISR_TEIF1_Pos (3U)
”    DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
•    DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
–    DMA_ISR_GIF2_Pos (4U)
—    DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
˜    DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
™    DMA_ISR_TCIF2_Pos (5U)
š    DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
›    DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
œ    DMA_ISR_HTIF2_Pos (6U)
    DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
ž    DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
Ÿ    DMA_ISR_TEIF2_Pos (7U)
     DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
¡    DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
¢    DMA_ISR_GIF3_Pos (8U)
£    DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
¤    DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
¥    DMA_ISR_TCIF3_Pos (9U)
¦    DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
§    DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
¨    DMA_ISR_HTIF3_Pos (10U)
©    DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
ª    DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
«    DMA_ISR_TEIF3_Pos (11U)
¬    DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
­    DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
®    DMA_ISR_GIF4_Pos (12U)
¯    DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
°    DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
±    DMA_ISR_TCIF4_Pos (13U)
²    DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
³    DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
´    DMA_ISR_HTIF4_Pos (14U)
µ    DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
¶    DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
·    DMA_ISR_TEIF4_Pos (15U)
¸    DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
¹    DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
º    DMA_ISR_GIF5_Pos (16U)
»    DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
¼    DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
½    DMA_ISR_TCIF5_Pos (17U)
¾    DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
¿    DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
À    DMA_ISR_HTIF5_Pos (18U)
Á    DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
    DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
à   DMA_ISR_TEIF5_Pos (19U)
Ä    DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
Å    DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
Æ    DMA_ISR_GIF6_Pos (20U)
Ç    DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
È    DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
É    DMA_ISR_TCIF6_Pos (21U)
Ê    DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
Ë    DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
Ì    DMA_ISR_HTIF6_Pos (22U)
Í    DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
Π   DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
Ï    DMA_ISR_TEIF6_Pos (23U)
Р   DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
Ñ    DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
Ò    DMA_ISR_GIF7_Pos (24U)
Ó    DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
Ô    DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
Õ    DMA_ISR_TCIF7_Pos (25U)
Ö    DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
×    DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
Ø    DMA_ISR_HTIF7_Pos (26U)
Ù    DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
Ú    DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
Û    DMA_ISR_TEIF7_Pos (27U)
Ü    DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
Ý    DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
à    DMA_IFCR_CGIF1_Pos (0U)
á    DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
â    DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
ã    DMA_IFCR_CTCIF1_Pos (1U)
ä    DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
å    DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
æ    DMA_IFCR_CHTIF1_Pos (2U)
ç    DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
è    DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
é    DMA_IFCR_CTEIF1_Pos (3U)
ê    DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
ë    DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
ì    DMA_IFCR_CGIF2_Pos (4U)
í    DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
î    DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
ï    DMA_IFCR_CTCIF2_Pos (5U)
ð    DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
ñ    DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
ò    DMA_IFCR_CHTIF2_Pos (6U)
ó    DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
ô    DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
õ    DMA_IFCR_CTEIF2_Pos (7U)
ö    DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
÷    DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
ø    DMA_IFCR_CGIF3_Pos (8U)
ù    DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
ú    DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
û    DMA_IFCR_CTCIF3_Pos (9U)
ü    DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
ý    DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
þ    DMA_IFCR_CHTIF3_Pos (10U)
ÿ    DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
€
DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

DMA_IFCR_CTEIF3_Pos (11U)
‚
DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
ƒ
DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
„
DMA_IFCR_CGIF4_Pos (12U)
…
DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
†
DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
‡
DMA_IFCR_CTCIF4_Pos (13U)
ˆ
DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
‰
DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
Š
DMA_IFCR_CHTIF4_Pos (14U)
‹
DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
Œ
DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

DMA_IFCR_CTEIF4_Pos (15U)
Ž
DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

DMA_IFCR_CGIF5_Pos (16U)
‘
DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
’
DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
“
DMA_IFCR_CTCIF5_Pos (17U)
”
DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
•
DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
–
DMA_IFCR_CHTIF5_Pos (18U)
—
DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
˜
DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
™
DMA_IFCR_CTEIF5_Pos (19U)
š
DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
›
DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
œ
DMA_IFCR_CGIF6_Pos (20U)

DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
ž
DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
Ÿ
DMA_IFCR_CTCIF6_Pos (21U)
 
DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
¡
DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
¢
DMA_IFCR_CHTIF6_Pos (22U)
£
DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
¤
DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
¥
DMA_IFCR_CTEIF6_Pos (23U)
¦
DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
§
DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
¨
DMA_IFCR_CGIF7_Pos (24U)
©
DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
ª
DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
«
DMA_IFCR_CTCIF7_Pos (25U)
¬
DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
­
DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
®
DMA_IFCR_CHTIF7_Pos (26U)
¯
DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
°
DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
±
DMA_IFCR_CTEIF7_Pos (27U)
²
DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
³
DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
¶
DMA_CCR_EN_Pos (0U)
·
DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
¸
DMA_CCR_EN DMA_CCR_EN_Msk
¹
DMA_CCR_TCIE_Pos (1U)
º
DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
»
DMA_CCR_TCIE DMA_CCR_TCIE_Msk
¼
DMA_CCR_HTIE_Pos (2U)
½
DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
¾
DMA_CCR_HTIE DMA_CCR_HTIE_Msk
¿
DMA_CCR_TEIE_Pos (3U)
À
DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
Á
DMA_CCR_TEIE DMA_CCR_TEIE_Msk
Â
DMA_CCR_DIR_Pos (4U)
Ã
DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
Ä
DMA_CCR_DIR DMA_CCR_DIR_Msk
Å
DMA_CCR_CIRC_Pos (5U)
Æ
DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
Ç
DMA_CCR_CIRC DMA_CCR_CIRC_Msk
È
DMA_CCR_PINC_Pos (6U)
É
DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
Ê
DMA_CCR_PINC DMA_CCR_PINC_Msk
Ë
DMA_CCR_MINC_Pos (7U)
Ì
DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
Í
DMA_CCR_MINC DMA_CCR_MINC_Msk
Ï
DMA_CCR_PSIZE_Pos (8U)
Ð
DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
Ñ
DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
Ò
DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
Ó
DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
Õ
DMA_CCR_MSIZE_Pos (10U)
Ö
DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
×
DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
Ø
DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
Ù
DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
Û
DMA_CCR_PL_Pos (12U)
Ü
DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
Ý
DMA_CCR_PL DMA_CCR_PL_Msk
Þ
DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
ß
DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
á
DMA_CCR_MEM2MEM_Pos (14U)
â
DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
ã
DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
æ
DMA_CNDTR_NDT_Pos (0U)
ç
DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
è
DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
ë
DMA_CPAR_PA_Pos (0U)
ì
DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
í
DMA_CPAR_PA DMA_CPAR_PA_Msk
ð
DMA_CMAR_MA_Pos (0U)
ñ
DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
ò
DMA_CMAR_MA DMA_CMAR_MA_Msk
ö
DMA_CSELR_C1S_Pos (0U)
÷
DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos)
ø
DMA_CSELR_C1S DMA_CSELR_C1S_Msk
ù
DMA_CSELR_C2S_Pos (4U)
ú
DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos)
û
DMA_CSELR_C2S DMA_CSELR_C2S_Msk
ü
DMA_CSELR_C3S_Pos (8U)
ý
DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos)
þ
DMA_CSELR_C3S DMA_CSELR_C3S_Msk
ÿ
DMA_CSELR_C4S_Pos (12U)
€DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos)
DMA_CSELR_C4S DMA_CSELR_C4S_Msk
‚DMA_CSELR_C5S_Pos (16U)
ƒDMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos)
„DMA_CSELR_C5S DMA_CSELR_C5S_Msk
…DMA_CSELR_C6S_Pos (20U)
†DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos)
‡DMA_CSELR_C6S DMA_CSELR_C6S_Msk
ˆDMA_CSELR_C7S_Pos (24U)
‰DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos)
ŠDMA_CSELR_C7S DMA_CSELR_C7S_Msk
“EXTI_IMR_IM0_Pos (0U)
”EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos)
•EXTI_IMR_IM0 EXTI_IMR_IM0_Msk
–EXTI_IMR_IM1_Pos (1U)
—EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos)
˜EXTI_IMR_IM1 EXTI_IMR_IM1_Msk
™EXTI_IMR_IM2_Pos (2U)
šEXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos)
›EXTI_IMR_IM2 EXTI_IMR_IM2_Msk
œEXTI_IMR_IM3_Pos (3U)
EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos)
žEXTI_IMR_IM3 EXTI_IMR_IM3_Msk
ŸEXTI_IMR_IM4_Pos (4U)
 EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos)
¡EXTI_IMR_IM4 EXTI_IMR_IM4_Msk
¢EXTI_IMR_IM5_Pos (5U)
£EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos)
¤EXTI_IMR_IM5 EXTI_IMR_IM5_Msk
¥EXTI_IMR_IM6_Pos (6U)
¦EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos)
§EXTI_IMR_IM6 EXTI_IMR_IM6_Msk
¨EXTI_IMR_IM7_Pos (7U)
©EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos)
ªEXTI_IMR_IM7 EXTI_IMR_IM7_Msk
«EXTI_IMR_IM8_Pos (8U)
¬EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos)
­EXTI_IMR_IM8 EXTI_IMR_IM8_Msk
®EXTI_IMR_IM9_Pos (9U)
¯EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos)
°EXTI_IMR_IM9 EXTI_IMR_IM9_Msk
±EXTI_IMR_IM10_Pos (10U)
²EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos)
³EXTI_IMR_IM10 EXTI_IMR_IM10_Msk
´EXTI_IMR_IM11_Pos (11U)
µEXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos)
¶EXTI_IMR_IM11 EXTI_IMR_IM11_Msk
·EXTI_IMR_IM12_Pos (12U)
¸EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos)
¹EXTI_IMR_IM12 EXTI_IMR_IM12_Msk
ºEXTI_IMR_IM13_Pos (13U)
»EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos)
¼EXTI_IMR_IM13 EXTI_IMR_IM13_Msk
½EXTI_IMR_IM14_Pos (14U)
¾EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos)
¿EXTI_IMR_IM14 EXTI_IMR_IM14_Msk
ÀEXTI_IMR_IM15_Pos (15U)
ÁEXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos)
ÂEXTI_IMR_IM15 EXTI_IMR_IM15_Msk
ÃEXTI_IMR_IM16_Pos (16U)
ÄEXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos)
ÅEXTI_IMR_IM16 EXTI_IMR_IM16_Msk
ÆEXTI_IMR_IM17_Pos (17U)
ÇEXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos)
ÈEXTI_IMR_IM17 EXTI_IMR_IM17_Msk
ÉEXTI_IMR_IM18_Pos (18U)
ÊEXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos)
ËEXTI_IMR_IM18 EXTI_IMR_IM18_Msk
ÌEXTI_IMR_IM19_Pos (19U)
ÍEXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos)
ÎEXTI_IMR_IM19 EXTI_IMR_IM19_Msk
ÏEXTI_IMR_IM20_Pos (20U)
ÐEXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos)
ÑEXTI_IMR_IM20 EXTI_IMR_IM20_Msk
ÒEXTI_IMR_IM21_Pos (21U)
ÓEXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos)
ÔEXTI_IMR_IM21 EXTI_IMR_IM21_Msk
ÕEXTI_IMR_IM22_Pos (22U)
ÖEXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos)
×EXTI_IMR_IM22 EXTI_IMR_IM22_Msk
ØEXTI_IMR_IM23_Pos (23U)
ÙEXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos)
ÚEXTI_IMR_IM23 EXTI_IMR_IM23_Msk
ÛEXTI_IMR_IM24_Pos (24U)
ÜEXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos)
ÝEXTI_IMR_IM24 EXTI_IMR_IM24_Msk
ÞEXTI_IMR_IM25_Pos (25U)
ßEXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos)
àEXTI_IMR_IM25 EXTI_IMR_IM25_Msk
áEXTI_IMR_IM26_Pos (26U)
âEXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos)
ãEXTI_IMR_IM26 EXTI_IMR_IM26_Msk
äEXTI_IMR_IM28_Pos (28U)
åEXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos)
æEXTI_IMR_IM28 EXTI_IMR_IM28_Msk
çEXTI_IMR_IM29_Pos (29U)
èEXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos)
éEXTI_IMR_IM29 EXTI_IMR_IM29_Msk
ëEXTI_IMR_IM_Pos (0U)
ìEXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos)
íEXTI_IMR_IM EXTI_IMR_IM_Msk
ðEXTI_EMR_EM0_Pos (0U)
ñEXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos)
òEXTI_EMR_EM0 EXTI_EMR_EM0_Msk
óEXTI_EMR_EM1_Pos (1U)
ôEXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos)
õEXTI_EMR_EM1 EXTI_EMR_EM1_Msk
öEXTI_EMR_EM2_Pos (2U)
÷EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos)
øEXTI_EMR_EM2 EXTI_EMR_EM2_Msk
ùEXTI_EMR_EM3_Pos (3U)
úEXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos)
ûEXTI_EMR_EM3 EXTI_EMR_EM3_Msk
üEXTI_EMR_EM4_Pos (4U)
ýEXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos)
þEXTI_EMR_EM4 EXTI_EMR_EM4_Msk
ÿEXTI_EMR_EM5_Pos (5U)
€EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos)
EXTI_EMR_EM5 EXTI_EMR_EM5_Msk
‚EXTI_EMR_EM6_Pos (6U)
ƒEXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos)
„EXTI_EMR_EM6 EXTI_EMR_EM6_Msk
…EXTI_EMR_EM7_Pos (7U)
†EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos)
‡EXTI_EMR_EM7 EXTI_EMR_EM7_Msk
ˆEXTI_EMR_EM8_Pos (8U)
‰EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos)
ŠEXTI_EMR_EM8 EXTI_EMR_EM8_Msk
‹EXTI_EMR_EM9_Pos (9U)
ŒEXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos)
EXTI_EMR_EM9 EXTI_EMR_EM9_Msk
ŽEXTI_EMR_EM10_Pos (10U)
EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos)
EXTI_EMR_EM10 EXTI_EMR_EM10_Msk
‘EXTI_EMR_EM11_Pos (11U)
’EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos)
“EXTI_EMR_EM11 EXTI_EMR_EM11_Msk
”EXTI_EMR_EM12_Pos (12U)
•EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos)
–EXTI_EMR_EM12 EXTI_EMR_EM12_Msk
—EXTI_EMR_EM13_Pos (13U)
˜EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos)
™EXTI_EMR_EM13 EXTI_EMR_EM13_Msk
šEXTI_EMR_EM14_Pos (14U)
›EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos)
œEXTI_EMR_EM14 EXTI_EMR_EM14_Msk
EXTI_EMR_EM15_Pos (15U)
žEXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos)
ŸEXTI_EMR_EM15 EXTI_EMR_EM15_Msk
 EXTI_EMR_EM16_Pos (16U)
¡EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos)
¢EXTI_EMR_EM16 EXTI_EMR_EM16_Msk
£EXTI_EMR_EM17_Pos (17U)
¤EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos)
¥EXTI_EMR_EM17 EXTI_EMR_EM17_Msk
¦EXTI_EMR_EM18_Pos (18U)
§EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos)
¨EXTI_EMR_EM18 EXTI_EMR_EM18_Msk
©EXTI_EMR_EM19_Pos (19U)
ªEXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos)
«EXTI_EMR_EM19 EXTI_EMR_EM19_Msk
¬EXTI_EMR_EM20_Pos (20U)
­EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos)
®EXTI_EMR_EM20 EXTI_EMR_EM20_Msk
¯EXTI_EMR_EM21_Pos (21U)
°EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos)
±EXTI_EMR_EM21 EXTI_EMR_EM21_Msk
²EXTI_EMR_EM22_Pos (22U)
³EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos)
´EXTI_EMR_EM22 EXTI_EMR_EM22_Msk
µEXTI_EMR_EM23_Pos (23U)
¶EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos)
·EXTI_EMR_EM23 EXTI_EMR_EM23_Msk
¸EXTI_EMR_EM24_Pos (24U)
¹EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos)
ºEXTI_EMR_EM24 EXTI_EMR_EM24_Msk
»EXTI_EMR_EM25_Pos (25U)
¼EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos)
½EXTI_EMR_EM25 EXTI_EMR_EM25_Msk
¾EXTI_EMR_EM26_Pos (26U)
¿EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos)
ÀEXTI_EMR_EM26 EXTI_EMR_EM26_Msk
ÁEXTI_EMR_EM28_Pos (28U)
ÂEXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos)
ÃEXTI_EMR_EM28 EXTI_EMR_EM28_Msk
ÄEXTI_EMR_EM29_Pos (29U)
ÅEXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos)
ÆEXTI_EMR_EM29 EXTI_EMR_EM29_Msk
ÉEXTI_RTSR_RT0_Pos (0U)
ÊEXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos)
ËEXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk
ÌEXTI_RTSR_RT1_Pos (1U)
ÍEXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos)
ÎEXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk
ÏEXTI_RTSR_RT2_Pos (2U)
ÐEXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos)
ÑEXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk
ÒEXTI_RTSR_RT3_Pos (3U)
ÓEXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos)
ÔEXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk
ÕEXTI_RTSR_RT4_Pos (4U)
ÖEXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos)
×EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk
ØEXTI_RTSR_RT5_Pos (5U)
ÙEXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos)
ÚEXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk
ÛEXTI_RTSR_RT6_Pos (6U)
ÜEXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos)
ÝEXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk
ÞEXTI_RTSR_RT7_Pos (7U)
ßEXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos)
àEXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk
áEXTI_RTSR_RT8_Pos (8U)
âEXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos)
ãEXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk
äEXTI_RTSR_RT9_Pos (9U)
åEXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos)
æEXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk
çEXTI_RTSR_RT10_Pos (10U)
èEXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos)
éEXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk
êEXTI_RTSR_RT11_Pos (11U)
ëEXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos)
ìEXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk
íEXTI_RTSR_RT12_Pos (12U)
îEXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos)
ïEXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk
ðEXTI_RTSR_RT13_Pos (13U)
ñEXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos)
òEXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk
óEXTI_RTSR_RT14_Pos (14U)
ôEXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos)
õEXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk
öEXTI_RTSR_RT15_Pos (15U)
÷EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos)
øEXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk
ùEXTI_RTSR_RT16_Pos (16U)
úEXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos)
ûEXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk
üEXTI_RTSR_RT17_Pos (17U)
ýEXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos)
þEXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk
ÿEXTI_RTSR_RT19_Pos (19U)
€ EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos)
 EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk
‚ EXTI_RTSR_RT20_Pos (20U)
ƒ EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos)
„ EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk
… EXTI_RTSR_RT21_Pos (21U)
† EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos)
‡ EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk
ˆ EXTI_RTSR_RT22_Pos (22U)
‰ EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos)
Š EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk
 EXTI_RTSR_TR0 EXTI_RTSR_RT0
Ž EXTI_RTSR_TR1 EXTI_RTSR_RT1
 EXTI_RTSR_TR2 EXTI_RTSR_RT2
 EXTI_RTSR_TR3 EXTI_RTSR_RT3
‘ EXTI_RTSR_TR4 EXTI_RTSR_RT4
’ EXTI_RTSR_TR5 EXTI_RTSR_RT5
“ EXTI_RTSR_TR6 EXTI_RTSR_RT6
” EXTI_RTSR_TR7 EXTI_RTSR_RT7
• EXTI_RTSR_TR8 EXTI_RTSR_RT8
– EXTI_RTSR_TR9 EXTI_RTSR_RT9
— EXTI_RTSR_TR10 EXTI_RTSR_RT10
˜ EXTI_RTSR_TR11 EXTI_RTSR_RT11
™ EXTI_RTSR_TR12 EXTI_RTSR_RT12
š EXTI_RTSR_TR13 EXTI_RTSR_RT13
› EXTI_RTSR_TR14 EXTI_RTSR_RT14
œ EXTI_RTSR_TR15 EXTI_RTSR_RT15
 EXTI_RTSR_TR16 EXTI_RTSR_RT16
ž EXTI_RTSR_TR17 EXTI_RTSR_RT17
Ÿ EXTI_RTSR_TR19 EXTI_RTSR_RT19
  EXTI_RTSR_TR20 EXTI_RTSR_RT20
¡ EXTI_RTSR_TR21 EXTI_RTSR_RT21
¢ EXTI_RTSR_TR22 EXTI_RTSR_RT22
¥ EXTI_FTSR_FT0_Pos (0U)
¦ EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos)
§ EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk
¨ EXTI_FTSR_FT1_Pos (1U)
© EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos)
ª EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk
« EXTI_FTSR_FT2_Pos (2U)
¬ EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos)
­ EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk
® EXTI_FTSR_FT3_Pos (3U)
¯ EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos)
° EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk
± EXTI_FTSR_FT4_Pos (4U)
² EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos)
³ EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk
´ EXTI_FTSR_FT5_Pos (5U)
µ EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos)
¶ EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk
· EXTI_FTSR_FT6_Pos (6U)
¸ EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos)
¹ EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk
º EXTI_FTSR_FT7_Pos (7U)
» EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos)
¼ EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk
½ EXTI_FTSR_FT8_Pos (8U)
¾ EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos)
¿ EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk
À EXTI_FTSR_FT9_Pos (9U)
Á EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos)
 EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk
à EXTI_FTSR_FT10_Pos (10U)
Ä EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos)
Å EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk
Æ EXTI_FTSR_FT11_Pos (11U)
Ç EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos)
È EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk
É EXTI_FTSR_FT12_Pos (12U)
Ê EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos)
Ë EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk
Ì EXTI_FTSR_FT13_Pos (13U)
Í EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos)
Î EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk
Ï EXTI_FTSR_FT14_Pos (14U)
Ð EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos)
Ñ EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk
Ò EXTI_FTSR_FT15_Pos (15U)
Ó EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos)
Ô EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk
Õ EXTI_FTSR_FT16_Pos (16U)
Ö EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos)
× EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk
Ø EXTI_FTSR_FT17_Pos (17U)
Ù EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos)
Ú EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk
Û EXTI_FTSR_FT19_Pos (19U)
Ü EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos)
Ý EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk
Þ EXTI_FTSR_FT20_Pos (20U)
ß EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos)
à EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk
á EXTI_FTSR_FT21_Pos (21U)
â EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos)
ã EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk
ä EXTI_FTSR_FT22_Pos (22U)
å EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos)
æ EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk
é EXTI_FTSR_TR0 EXTI_FTSR_FT0
ê EXTI_FTSR_TR1 EXTI_FTSR_FT1
ë EXTI_FTSR_TR2 EXTI_FTSR_FT2
ì EXTI_FTSR_TR3 EXTI_FTSR_FT3
í EXTI_FTSR_TR4 EXTI_FTSR_FT4
î EXTI_FTSR_TR5 EXTI_FTSR_FT5
ï EXTI_FTSR_TR6 EXTI_FTSR_FT6
ð EXTI_FTSR_TR7 EXTI_FTSR_FT7
ñ EXTI_FTSR_TR8 EXTI_FTSR_FT8
ò EXTI_FTSR_TR9 EXTI_FTSR_FT9
ó EXTI_FTSR_TR10 EXTI_FTSR_FT10
ô EXTI_FTSR_TR11 EXTI_FTSR_FT11
õ EXTI_FTSR_TR12 EXTI_FTSR_FT12
ö EXTI_FTSR_TR13 EXTI_FTSR_FT13
÷ EXTI_FTSR_TR14 EXTI_FTSR_FT14
ø EXTI_FTSR_TR15 EXTI_FTSR_FT15
ù EXTI_FTSR_TR16 EXTI_FTSR_FT16
ú EXTI_FTSR_TR17 EXTI_FTSR_FT17
û EXTI_FTSR_TR19 EXTI_FTSR_FT19
ü EXTI_FTSR_TR20 EXTI_FTSR_FT20
ý EXTI_FTSR_TR21 EXTI_FTSR_FT21
þ EXTI_FTSR_TR22 EXTI_FTSR_FT22
EXTI_SWIER_SWI0_Pos (0U)
‚EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos)
ƒEXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk
„EXTI_SWIER_SWI1_Pos (1U)
…EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos)
†EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk
‡EXTI_SWIER_SWI2_Pos (2U)
ˆEXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos)
‰EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk
ŠEXTI_SWIER_SWI3_Pos (3U)
‹EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos)
ŒEXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk
EXTI_SWIER_SWI4_Pos (4U)
ŽEXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos)
EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk
EXTI_SWIER_SWI5_Pos (5U)
‘EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos)
’EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk
“EXTI_SWIER_SWI6_Pos (6U)
”EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos)
•EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk
–EXTI_SWIER_SWI7_Pos (7U)
—EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos)
˜EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk
™EXTI_SWIER_SWI8_Pos (8U)
šEXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos)
›EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk
œEXTI_SWIER_SWI9_Pos (9U)
EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos)
žEXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk
ŸEXTI_SWIER_SWI10_Pos (10U)
 EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos)
¡EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk
¢EXTI_SWIER_SWI11_Pos (11U)
£EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos)
¤EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk
¥EXTI_SWIER_SWI12_Pos (12U)
¦EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos)
§EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk
¨EXTI_SWIER_SWI13_Pos (13U)
©EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos)
ªEXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk
«EXTI_SWIER_SWI14_Pos (14U)
¬EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos)
­EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk
®EXTI_SWIER_SWI15_Pos (15U)
¯EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos)
°EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk
±EXTI_SWIER_SWI16_Pos (16U)
²EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos)
³EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk
´EXTI_SWIER_SWI17_Pos (17U)
µEXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos)
¶EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk
·EXTI_SWIER_SWI19_Pos (19U)
¸EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos)
¹EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk
ºEXTI_SWIER_SWI20_Pos (20U)
»EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos)
¼EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk
½EXTI_SWIER_SWI21_Pos (21U)
¾EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos)
¿EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk
ÀEXTI_SWIER_SWI22_Pos (22U)
ÁEXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos)
ÂEXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk
ÅEXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
ÆEXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
ÇEXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
ÈEXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
ÉEXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
ÊEXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
ËEXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
ÌEXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
ÍEXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
ÎEXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
ÏEXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
ÐEXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
ÑEXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
ÒEXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
ÓEXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
ÔEXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
ÕEXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
ÖEXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
×EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
ØEXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
ÙEXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
ÚEXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
ÝEXTI_PR_PIF0_Pos (0U)
ÞEXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos)
ßEXTI_PR_PIF0 EXTI_PR_PIF0_Msk
àEXTI_PR_PIF1_Pos (1U)
áEXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos)
âEXTI_PR_PIF1 EXTI_PR_PIF1_Msk
ãEXTI_PR_PIF2_Pos (2U)
äEXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos)
åEXTI_PR_PIF2 EXTI_PR_PIF2_Msk
æEXTI_PR_PIF3_Pos (3U)
çEXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos)
èEXTI_PR_PIF3 EXTI_PR_PIF3_Msk
éEXTI_PR_PIF4_Pos (4U)
êEXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos)
ëEXTI_PR_PIF4 EXTI_PR_PIF4_Msk
ìEXTI_PR_PIF5_Pos (5U)
íEXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos)
îEXTI_PR_PIF5 EXTI_PR_PIF5_Msk
ïEXTI_PR_PIF6_Pos (6U)
ðEXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos)
ñEXTI_PR_PIF6 EXTI_PR_PIF6_Msk
òEXTI_PR_PIF7_Pos (7U)
óEXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos)
ôEXTI_PR_PIF7 EXTI_PR_PIF7_Msk
õEXTI_PR_PIF8_Pos (8U)
öEXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos)
÷EXTI_PR_PIF8 EXTI_PR_PIF8_Msk
øEXTI_PR_PIF9_Pos (9U)
ùEXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos)
úEXTI_PR_PIF9 EXTI_PR_PIF9_Msk
ûEXTI_PR_PIF10_Pos (10U)
üEXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos)
ýEXTI_PR_PIF10 EXTI_PR_PIF10_Msk
þEXTI_PR_PIF11_Pos (11U)
ÿEXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos)
€EXTI_PR_PIF11 EXTI_PR_PIF11_Msk
EXTI_PR_PIF12_Pos (12U)
‚EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos)
ƒEXTI_PR_PIF12 EXTI_PR_PIF12_Msk
„EXTI_PR_PIF13_Pos (13U)
…EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos)
†EXTI_PR_PIF13 EXTI_PR_PIF13_Msk
‡EXTI_PR_PIF14_Pos (14U)
ˆEXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos)
‰EXTI_PR_PIF14 EXTI_PR_PIF14_Msk
ŠEXTI_PR_PIF15_Pos (15U)
‹EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos)
ŒEXTI_PR_PIF15 EXTI_PR_PIF15_Msk
EXTI_PR_PIF16_Pos (16U)
ŽEXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos)
EXTI_PR_PIF16 EXTI_PR_PIF16_Msk
EXTI_PR_PIF17_Pos (17U)
‘EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos)
’EXTI_PR_PIF17 EXTI_PR_PIF17_Msk
“EXTI_PR_PIF19_Pos (19U)
”EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos)
•EXTI_PR_PIF19 EXTI_PR_PIF19_Msk
–EXTI_PR_PIF20_Pos (20U)
—EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos)
˜EXTI_PR_PIF20 EXTI_PR_PIF20_Msk
™EXTI_PR_PIF21_Pos (21U)
šEXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos)
›EXTI_PR_PIF21 EXTI_PR_PIF21_Msk
œEXTI_PR_PIF22_Pos (22U)
EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos)
žEXTI_PR_PIF22 EXTI_PR_PIF22_Msk
¡EXTI_PR_PR0 EXTI_PR_PIF0
¢EXTI_PR_PR1 EXTI_PR_PIF1
£EXTI_PR_PR2 EXTI_PR_PIF2
¤EXTI_PR_PR3 EXTI_PR_PIF3
¥EXTI_PR_PR4 EXTI_PR_PIF4
¦EXTI_PR_PR5 EXTI_PR_PIF5
§EXTI_PR_PR6 EXTI_PR_PIF6
¨EXTI_PR_PR7 EXTI_PR_PIF7
©EXTI_PR_PR8 EXTI_PR_PIF8
ªEXTI_PR_PR9 EXTI_PR_PIF9
«EXTI_PR_PR10 EXTI_PR_PIF10
¬EXTI_PR_PR11 EXTI_PR_PIF11
­EXTI_PR_PR12 EXTI_PR_PIF12
®EXTI_PR_PR13 EXTI_PR_PIF13
¯EXTI_PR_PR14 EXTI_PR_PIF14
°EXTI_PR_PR15 EXTI_PR_PIF15
±EXTI_PR_PR16 EXTI_PR_PIF16
²EXTI_PR_PR17 EXTI_PR_PIF17
³EXTI_PR_PR19 EXTI_PR_PIF19
´EXTI_PR_PR20 EXTI_PR_PIF20
µEXTI_PR_PR21 EXTI_PR_PIF21
¶EXTI_PR_PR22 EXTI_PR_PIF22
¿FLASH_ACR_LATENCY_Pos (0U)
ÀFLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos)
ÁFLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
ÂFLASH_ACR_PRFTEN_Pos (1U)
ÃFLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
ÄFLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
ÅFLASH_ACR_SLEEP_PD_Pos (3U)
ÆFLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)
ÇFLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk
ÈFLASH_ACR_RUN_PD_Pos (4U)
ÉFLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)
ÊFLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk
ËFLASH_ACR_DISAB_BUF_Pos (5U)
ÌFLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos)
ÍFLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk
ÎFLASH_ACR_PRE_READ_Pos (6U)
ÏFLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos)
ÐFLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk
ÓFLASH_PECR_PELOCK_Pos (0U)
ÔFLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos)
ÕFLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk
ÖFLASH_PECR_PRGLOCK_Pos (1U)
×FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos)
ØFLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk
ÙFLASH_PECR_OPTLOCK_Pos (2U)
ÚFLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos)
ÛFLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk
ÜFLASH_PECR_PROG_Pos (3U)
ÝFLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos)
ÞFLASH_PECR_PROG FLASH_PECR_PROG_Msk
ßFLASH_PECR_DATA_Pos (4U)
àFLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos)
áFLASH_PECR_DATA FLASH_PECR_DATA_Msk
âFLASH_PECR_FIX_Pos (8U)
ãFLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos)
äFLASH_PECR_FIX FLASH_PECR_FIX_Msk
åFLASH_PECR_ERASE_Pos (9U)
æFLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos)
çFLASH_PECR_ERASE FLASH_PECR_ERASE_Msk
èFLASH_PECR_FPRG_Pos (10U)
éFLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos)
êFLASH_PECR_FPRG FLASH_PECR_FPRG_Msk
ëFLASH_PECR_PARALLBANK_Pos (15U)
ìFLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos)
íFLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk
îFLASH_PECR_EOPIE_Pos (16U)
ïFLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos)
ðFLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk
ñFLASH_PECR_ERRIE_Pos (17U)
òFLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos)
óFLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk
ôFLASH_PECR_OBL_LAUNCH_Pos (18U)
õFLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)
öFLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk
÷FLASH_PECR_HALF_ARRAY_Pos (19U)
øFLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)
ùFLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk
úFLASH_PECR_NZDISABLE_Pos (22U)
ûFLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos)
üFLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk
ÿFLASH_PDKEYR_PDKEYR_Pos (0U)
€FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)
FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk
„FLASH_PEKEYR_PEKEYR_Pos (0U)
…FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)
†FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk
‰FLASH_PRGKEYR_PRGKEYR_Pos (0U)
ŠFLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos)
‹FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk
ŽFLASH_OPTKEYR_OPTKEYR_Pos (0U)
FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)
FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk
“FLASH_SR_BSY_Pos (0U)
”FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
•FLASH_SR_BSY FLASH_SR_BSY_Msk
–FLASH_SR_EOP_Pos (1U)
—FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
˜FLASH_SR_EOP FLASH_SR_EOP_Msk
™FLASH_SR_HVOFF_Pos (2U)
šFLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos)
›FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk
œFLASH_SR_READY_Pos (3U)
FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos)
žFLASH_SR_READY FLASH_SR_READY_Msk
 FLASH_SR_WRPERR_Pos (8U)
¡FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
¢FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
£FLASH_SR_PGAERR_Pos (9U)
¤FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
¥FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
¦FLASH_SR_SIZERR_Pos (10U)
§FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)
¨FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
©FLASH_SR_OPTVERR_Pos (11U)
ªFLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)
«FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
¬FLASH_SR_RDERR_Pos (13U)
­FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
®FLASH_SR_RDERR FLASH_SR_RDERR_Msk
¯FLASH_SR_NOTZEROERR_Pos (16U)
°FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos)
±FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk
²FLASH_SR_FWWERR_Pos (17U)
³FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos)
´FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk
·FLASH_SR_FWWER FLASH_SR_FWWERR
¸FLASH_SR_ENHV FLASH_SR_HVOFF
¹FLASH_SR_ENDHV FLASH_SR_HVOFF
¼FLASH_OPTR_RDPROT_Pos (0U)
½FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos)
¾FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk
¿FLASH_OPTR_WPRMOD_Pos (8U)
ÀFLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos)
ÁFLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk
ÂFLASH_OPTR_BOR_LEV_Pos (16U)
ÃFLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos)
ÄFLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
ÅFLASH_OPTR_IWDG_SW_Pos (20U)
ÆFLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)
ÇFLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
ÈFLASH_OPTR_nRST_STOP_Pos (21U)
ÉFLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)
ÊFLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
ËFLASH_OPTR_nRST_STDBY_Pos (22U)
ÌFLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)
ÍFLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
ÎFLASH_OPTR_BFB2_Pos (23U)
ÏFLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos)
ÐFLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
ÑFLASH_OPTR_USER_Pos (20U)
ÒFLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos)
ÓFLASH_OPTR_USER FLASH_OPTR_USER_Msk
ÔFLASH_OPTR_BOOT1_Pos (31U)
ÕFLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos)
ÖFLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk
ÙFLASH_WRPR_WRP_Pos (0U)
ÚFLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos)
ÛFLASH_WRPR_WRP FLASH_WRPR_WRP_Msk
ãGPIO_MODER_MODE0_Pos (0U)
äGPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
åGPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
æGPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
çGPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
èGPIO_MODER_MODE1_Pos (2U)
éGPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
êGPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
ëGPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
ìGPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
íGPIO_MODER_MODE2_Pos (4U)
îGPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
ïGPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
ðGPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
ñGPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
òGPIO_MODER_MODE3_Pos (6U)
óGPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
ôGPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
õGPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
öGPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
÷GPIO_MODER_MODE4_Pos (8U)
øGPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
ùGPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
úGPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
ûGPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
üGPIO_MODER_MODE5_Pos (10U)
ýGPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
þGPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
ÿGPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
€GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
GPIO_MODER_MODE6_Pos (12U)
‚GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
ƒGPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
„GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
…GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
†GPIO_MODER_MODE7_Pos (14U)
‡GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
ˆGPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
‰GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
ŠGPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
‹GPIO_MODER_MODE8_Pos (16U)
ŒGPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
ŽGPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
GPIO_MODER_MODE9_Pos (18U)
‘GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
’GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
“GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
”GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
•GPIO_MODER_MODE10_Pos (20U)
–GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
—GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
˜GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
™GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
šGPIO_MODER_MODE11_Pos (22U)
›GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
œGPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
žGPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
ŸGPIO_MODER_MODE12_Pos (24U)
 GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
¡GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
¢GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
£GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
¤GPIO_MODER_MODE13_Pos (26U)
¥GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
¦GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
§GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
¨GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
©GPIO_MODER_MODE14_Pos (28U)
ªGPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
«GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
¬GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
­GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
®GPIO_MODER_MODE15_Pos (30U)
¯GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
°GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
±GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
²GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
µGPIO_OTYPER_OT_0 (0x00000001U)
¶GPIO_OTYPER_OT_1 (0x00000002U)
·GPIO_OTYPER_OT_2 (0x00000004U)
¸GPIO_OTYPER_OT_3 (0x00000008U)
¹GPIO_OTYPER_OT_4 (0x00000010U)
ºGPIO_OTYPER_OT_5 (0x00000020U)
»GPIO_OTYPER_OT_6 (0x00000040U)
¼GPIO_OTYPER_OT_7 (0x00000080U)
½GPIO_OTYPER_OT_8 (0x00000100U)
¾GPIO_OTYPER_OT_9 (0x00000200U)
¿GPIO_OTYPER_OT_10 (0x00000400U)
ÀGPIO_OTYPER_OT_11 (0x00000800U)
ÁGPIO_OTYPER_OT_12 (0x00001000U)
ÂGPIO_OTYPER_OT_13 (0x00002000U)
ÃGPIO_OTYPER_OT_14 (0x00004000U)
ÄGPIO_OTYPER_OT_15 (0x00008000U)
ÇGPIO_OSPEEDER_OSPEED0_Pos (0U)
ÈGPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)
ÉGPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
ÊGPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)
ËGPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)
ÌGPIO_OSPEEDER_OSPEED1_Pos (2U)
ÍGPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)
ÎGPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
ÏGPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)
ÐGPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)
ÑGPIO_OSPEEDER_OSPEED2_Pos (4U)
ÒGPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)
ÓGPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
ÔGPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)
ÕGPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)
ÖGPIO_OSPEEDER_OSPEED3_Pos (6U)
×GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)
ØGPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
ÙGPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)
ÚGPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)
ÛGPIO_OSPEEDER_OSPEED4_Pos (8U)
ÜGPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)
ÝGPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
ÞGPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)
ßGPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)
àGPIO_OSPEEDER_OSPEED5_Pos (10U)
áGPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)
âGPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
ãGPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)
äGPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)
åGPIO_OSPEEDER_OSPEED6_Pos (12U)
æGPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)
çGPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
èGPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)
éGPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)
êGPIO_OSPEEDER_OSPEED7_Pos (14U)
ëGPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)
ìGPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
íGPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)
îGPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)
ïGPIO_OSPEEDER_OSPEED8_Pos (16U)
ðGPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)
ñGPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
òGPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)
óGPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)
ôGPIO_OSPEEDER_OSPEED9_Pos (18U)
õGPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)
öGPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
÷GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)
øGPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)
ùGPIO_OSPEEDER_OSPEED10_Pos (20U)
úGPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)
ûGPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
üGPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)
ýGPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)
þGPIO_OSPEEDER_OSPEED11_Pos (22U)
ÿGPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)
€GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)
‚GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)
ƒGPIO_OSPEEDER_OSPEED12_Pos (24U)
„GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)
…GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
†GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)
‡GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)
ˆGPIO_OSPEEDER_OSPEED13_Pos (26U)
‰GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)
ŠGPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
‹GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)
ŒGPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)
GPIO_OSPEEDER_OSPEED14_Pos (28U)
ŽGPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)
GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)
‘GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)
’GPIO_OSPEEDER_OSPEED15_Pos (30U)
“GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)
”GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
•GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)
–GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)
™GPIO_PUPDR_PUPD0_Pos (0U)
šGPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
›GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
œGPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
žGPIO_PUPDR_PUPD1_Pos (2U)
ŸGPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
 GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
¡GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
¢GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
£GPIO_PUPDR_PUPD2_Pos (4U)
¤GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
¥GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
¦GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
§GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
¨GPIO_PUPDR_PUPD3_Pos (6U)
©GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
ªGPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
«GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
¬GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
­GPIO_PUPDR_PUPD4_Pos (8U)
®GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
¯GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
°GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
±GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
²GPIO_PUPDR_PUPD5_Pos (10U)
³GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
´GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
µGPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
¶GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
·GPIO_PUPDR_PUPD6_Pos (12U)
¸GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
¹GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
ºGPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
»GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
¼GPIO_PUPDR_PUPD7_Pos (14U)
½GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
¾GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
¿GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
ÀGPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
ÁGPIO_PUPDR_PUPD8_Pos (16U)
ÂGPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
ÃGPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
ÄGPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
ÅGPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
ÆGPIO_PUPDR_PUPD9_Pos (18U)
ÇGPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
ÈGPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
ÉGPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
ÊGPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
ËGPIO_PUPDR_PUPD10_Pos (20U)
ÌGPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
ÍGPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
ÎGPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
ÏGPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
ÐGPIO_PUPDR_PUPD11_Pos (22U)
ÑGPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
ÒGPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
ÓGPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
ÔGPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
ÕGPIO_PUPDR_PUPD12_Pos (24U)
ÖGPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
×GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
ØGPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
ÙGPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
ÚGPIO_PUPDR_PUPD13_Pos (26U)
ÛGPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
ÜGPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
ÝGPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
ÞGPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
ßGPIO_PUPDR_PUPD14_Pos (28U)
àGPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
áGPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
âGPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
ãGPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
äGPIO_PUPDR_PUPD15_Pos (30U)
åGPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
æGPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
çGPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
èGPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
ëGPIO_IDR_ID0_Pos (0U)
ìGPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
íGPIO_IDR_ID0 GPIO_IDR_ID0_Msk
îGPIO_IDR_ID1_Pos (1U)
ïGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
ðGPIO_IDR_ID1 GPIO_IDR_ID1_Msk
ñGPIO_IDR_ID2_Pos (2U)
òGPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
óGPIO_IDR_ID2 GPIO_IDR_ID2_Msk
ôGPIO_IDR_ID3_Pos (3U)
õGPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
öGPIO_IDR_ID3 GPIO_IDR_ID3_Msk
÷GPIO_IDR_ID4_Pos (4U)
øGPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
ùGPIO_IDR_ID4 GPIO_IDR_ID4_Msk
úGPIO_IDR_ID5_Pos (5U)
ûGPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
üGPIO_IDR_ID5 GPIO_IDR_ID5_Msk
ýGPIO_IDR_ID6_Pos (6U)
þGPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
ÿGPIO_IDR_ID6 GPIO_IDR_ID6_Msk
€GPIO_IDR_ID7_Pos (7U)
GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
‚GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
ƒGPIO_IDR_ID8_Pos (8U)
„GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
…GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
†GPIO_IDR_ID9_Pos (9U)
‡GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
ˆGPIO_IDR_ID9 GPIO_IDR_ID9_Msk
‰GPIO_IDR_ID10_Pos (10U)
ŠGPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
‹GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
ŒGPIO_IDR_ID11_Pos (11U)
GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
ŽGPIO_IDR_ID11 GPIO_IDR_ID11_Msk
GPIO_IDR_ID12_Pos (12U)
GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
‘GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
’GPIO_IDR_ID13_Pos (13U)
“GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
”GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
•GPIO_IDR_ID14_Pos (14U)
–GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
—GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
˜GPIO_IDR_ID15_Pos (15U)
™GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
šGPIO_IDR_ID15 GPIO_IDR_ID15_Msk
GPIO_ODR_OD0_Pos (0U)
žGPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
ŸGPIO_ODR_OD0 GPIO_ODR_OD0_Msk
 GPIO_ODR_OD1_Pos (1U)
¡GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
¢GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
£GPIO_ODR_OD2_Pos (2U)
¤GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
¥GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
¦GPIO_ODR_OD3_Pos (3U)
§GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
¨GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
©GPIO_ODR_OD4_Pos (4U)
ªGPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
«GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
¬GPIO_ODR_OD5_Pos (5U)
­GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
®GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
¯GPIO_ODR_OD6_Pos (6U)
°GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
±GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
²GPIO_ODR_OD7_Pos (7U)
³GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
´GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
µGPIO_ODR_OD8_Pos (8U)
¶GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
·GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
¸GPIO_ODR_OD9_Pos (9U)
¹GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
ºGPIO_ODR_OD9 GPIO_ODR_OD9_Msk
»GPIO_ODR_OD10_Pos (10U)
¼GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
½GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
¾GPIO_ODR_OD11_Pos (11U)
¿GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
ÀGPIO_ODR_OD11 GPIO_ODR_OD11_Msk
ÁGPIO_ODR_OD12_Pos (12U)
ÂGPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
ÃGPIO_ODR_OD12 GPIO_ODR_OD12_Msk
ÄGPIO_ODR_OD13_Pos (13U)
ÅGPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
ÆGPIO_ODR_OD13 GPIO_ODR_OD13_Msk
ÇGPIO_ODR_OD14_Pos (14U)
ÈGPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
ÉGPIO_ODR_OD14 GPIO_ODR_OD14_Msk
ÊGPIO_ODR_OD15_Pos (15U)
ËGPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
ÌGPIO_ODR_OD15 GPIO_ODR_OD15_Msk
ÏGPIO_BSRR_BS_0 (0x00000001U)
ÐGPIO_BSRR_BS_1 (0x00000002U)
ÑGPIO_BSRR_BS_2 (0x00000004U)
ÒGPIO_BSRR_BS_3 (0x00000008U)
ÓGPIO_BSRR_BS_4 (0x00000010U)
ÔGPIO_BSRR_BS_5 (0x00000020U)
ÕGPIO_BSRR_BS_6 (0x00000040U)
ÖGPIO_BSRR_BS_7 (0x00000080U)
×GPIO_BSRR_BS_8 (0x00000100U)
ØGPIO_BSRR_BS_9 (0x00000200U)
ÙGPIO_BSRR_BS_10 (0x00000400U)
ÚGPIO_BSRR_BS_11 (0x00000800U)
ÛGPIO_BSRR_BS_12 (0x00001000U)
ÜGPIO_BSRR_BS_13 (0x00002000U)
ÝGPIO_BSRR_BS_14 (0x00004000U)
ÞGPIO_BSRR_BS_15 (0x00008000U)
ßGPIO_BSRR_BR_0 (0x00010000U)
àGPIO_BSRR_BR_1 (0x00020000U)
áGPIO_BSRR_BR_2 (0x00040000U)
âGPIO_BSRR_BR_3 (0x00080000U)
ãGPIO_BSRR_BR_4 (0x00100000U)
äGPIO_BSRR_BR_5 (0x00200000U)
åGPIO_BSRR_BR_6 (0x00400000U)
æGPIO_BSRR_BR_7 (0x00800000U)
çGPIO_BSRR_BR_8 (0x01000000U)
èGPIO_BSRR_BR_9 (0x02000000U)
éGPIO_BSRR_BR_10 (0x04000000U)
êGPIO_BSRR_BR_11 (0x08000000U)
ëGPIO_BSRR_BR_12 (0x10000000U)
ìGPIO_BSRR_BR_13 (0x20000000U)
íGPIO_BSRR_BR_14 (0x40000000U)
îGPIO_BSRR_BR_15 (0x80000000U)
ñGPIO_LCKR_LCK0_Pos (0U)
òGPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
óGPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
ôGPIO_LCKR_LCK1_Pos (1U)
õGPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
öGPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
÷GPIO_LCKR_LCK2_Pos (2U)
øGPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
ùGPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
úGPIO_LCKR_LCK3_Pos (3U)
ûGPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
üGPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
ýGPIO_LCKR_LCK4_Pos (4U)
þGPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
ÿGPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
€GPIO_LCKR_LCK5_Pos (5U)
GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
‚GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
ƒGPIO_LCKR_LCK6_Pos (6U)
„GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
…GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
†GPIO_LCKR_LCK7_Pos (7U)
‡GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
ˆGPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
‰GPIO_LCKR_LCK8_Pos (8U)
ŠGPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
‹GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
ŒGPIO_LCKR_LCK9_Pos (9U)
GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
ŽGPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
GPIO_LCKR_LCK10_Pos (10U)
GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
‘GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
’GPIO_LCKR_LCK11_Pos (11U)
“GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
”GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
•GPIO_LCKR_LCK12_Pos (12U)
–GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
—GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
˜GPIO_LCKR_LCK13_Pos (13U)
™GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
šGPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
›GPIO_LCKR_LCK14_Pos (14U)
œGPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
žGPIO_LCKR_LCK15_Pos (15U)
ŸGPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
 GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
¡GPIO_LCKR_LCKK_Pos (16U)
¢GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
£GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
¦GPIO_AFRL_AFSEL0_Pos (0U)
§GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
¨GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
©GPIO_AFRL_AFSEL1_Pos (4U)
ªGPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
«GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
¬GPIO_AFRL_AFSEL2_Pos (8U)
­GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
®GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
¯GPIO_AFRL_AFSEL3_Pos (12U)
°GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
±GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
²GPIO_AFRL_AFSEL4_Pos (16U)
³GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
´GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
µGPIO_AFRL_AFSEL5_Pos (20U)
¶GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
·GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
¸GPIO_AFRL_AFSEL6_Pos (24U)
¹GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
ºGPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
»GPIO_AFRL_AFSEL7_Pos (28U)
¼GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
½GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
ÀGPIO_AFRH_AFSEL8_Pos (0U)
ÁGPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
ÂGPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
ÃGPIO_AFRH_AFSEL9_Pos (4U)
ÄGPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
ÅGPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
ÆGPIO_AFRH_AFSEL10_Pos (8U)
ÇGPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
ÈGPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
ÉGPIO_AFRH_AFSEL11_Pos (12U)
ÊGPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
ËGPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
ÌGPIO_AFRH_AFSEL12_Pos (16U)
ÍGPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
ÎGPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
ÏGPIO_AFRH_AFSEL13_Pos (20U)
ÐGPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
ÑGPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
ÒGPIO_AFRH_AFSEL14_Pos (24U)
ÓGPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
ÔGPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
ÕGPIO_AFRH_AFSEL15_Pos (28U)
ÖGPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
×GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
ÚGPIO_BRR_BR_0 (0x00000001U)
ÛGPIO_BRR_BR_1 (0x00000002U)
ÜGPIO_BRR_BR_2 (0x00000004U)
ÝGPIO_BRR_BR_3 (0x00000008U)
ÞGPIO_BRR_BR_4 (0x00000010U)
ßGPIO_BRR_BR_5 (0x00000020U)
àGPIO_BRR_BR_6 (0x00000040U)
áGPIO_BRR_BR_7 (0x00000080U)
âGPIO_BRR_BR_8 (0x00000100U)
ãGPIO_BRR_BR_9 (0x00000200U)
äGPIO_BRR_BR_10 (0x00000400U)
åGPIO_BRR_BR_11 (0x00000800U)
æGPIO_BRR_BR_12 (0x00001000U)
çGPIO_BRR_BR_13 (0x00002000U)
èGPIO_BRR_BR_14 (0x00004000U)
éGPIO_BRR_BR_15 (0x00008000U)
òI2C_CR1_PE_Pos (0U)
óI2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
ôI2C_CR1_PE I2C_CR1_PE_Msk
õI2C_CR1_TXIE_Pos (1U)
öI2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
÷I2C_CR1_TXIE I2C_CR1_TXIE_Msk
øI2C_CR1_RXIE_Pos (2U)
ùI2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
úI2C_CR1_RXIE I2C_CR1_RXIE_Msk
ûI2C_CR1_ADDRIE_Pos (3U)
üI2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
ýI2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
þI2C_CR1_NACKIE_Pos (4U)
ÿI2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
€I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
I2C_CR1_STOPIE_Pos (5U)
‚I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
ƒI2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
„I2C_CR1_TCIE_Pos (6U)
…I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
†I2C_CR1_TCIE I2C_CR1_TCIE_Msk
‡I2C_CR1_ERRIE_Pos (7U)
ˆI2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
‰I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
ŠI2C_CR1_DNF_Pos (8U)
‹I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
ŒI2C_CR1_DNF I2C_CR1_DNF_Msk
I2C_CR1_ANFOFF_Pos (12U)
ŽI2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
I2C_CR1_TXDMAEN_Pos (14U)
‘I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
’I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
“I2C_CR1_RXDMAEN_Pos (15U)
”I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
•I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
–I2C_CR1_SBC_Pos (16U)
—I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
˜I2C_CR1_SBC I2C_CR1_SBC_Msk
™I2C_CR1_NOSTRETCH_Pos (17U)
šI2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
›I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
œI2C_CR1_WUPEN_Pos (18U)
I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
žI2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
ŸI2C_CR1_GCEN_Pos (19U)
 I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
¡I2C_CR1_GCEN I2C_CR1_GCEN_Msk
¢I2C_CR1_SMBHEN_Pos (20U)
£I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
¤I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
¥I2C_CR1_SMBDEN_Pos (21U)
¦I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
§I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
¨I2C_CR1_ALERTEN_Pos (22U)
©I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
ªI2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
«I2C_CR1_PECEN_Pos (23U)
¬I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
­I2C_CR1_PECEN I2C_CR1_PECEN_Msk
°I2C_CR2_SADD_Pos (0U)
±I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
²I2C_CR2_SADD I2C_CR2_SADD_Msk
³I2C_CR2_RD_WRN_Pos (10U)
´I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
µI2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
¶I2C_CR2_ADD10_Pos (11U)
·I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
¸I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
¹I2C_CR2_HEAD10R_Pos (12U)
ºI2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
»I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
¼I2C_CR2_START_Pos (13U)
½I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
¾I2C_CR2_START I2C_CR2_START_Msk
¿I2C_CR2_STOP_Pos (14U)
ÀI2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
ÁI2C_CR2_STOP I2C_CR2_STOP_Msk
ÂI2C_CR2_NACK_Pos (15U)
ÃI2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
ÄI2C_CR2_NACK I2C_CR2_NACK_Msk
ÅI2C_CR2_NBYTES_Pos (16U)
ÆI2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
ÇI2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
ÈI2C_CR2_RELOAD_Pos (24U)
ÉI2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
ÊI2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
ËI2C_CR2_AUTOEND_Pos (25U)
ÌI2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
ÍI2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
ÎI2C_CR2_PECBYTE_Pos (26U)
ÏI2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
ÐI2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
ÓI2C_OAR1_OA1_Pos (0U)
ÔI2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
ÕI2C_OAR1_OA1 I2C_OAR1_OA1_Msk
ÖI2C_OAR1_OA1MODE_Pos (10U)
×I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
ØI2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
ÙI2C_OAR1_OA1EN_Pos (15U)
ÚI2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
ÛI2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
ÞI2C_OAR2_OA2_Pos (1U)
ßI2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
àI2C_OAR2_OA2 I2C_OAR2_OA2_Msk
áI2C_OAR2_OA2MSK_Pos (8U)
âI2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
ãI2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
äI2C_OAR2_OA2NOMASK (0x00000000U)
åI2C_OAR2_OA2MASK01_Pos (8U)
æI2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
çI2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
èI2C_OAR2_OA2MASK02_Pos (9U)
éI2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
êI2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
ëI2C_OAR2_OA2MASK03_Pos (8U)
ìI2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
íI2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
îI2C_OAR2_OA2MASK04_Pos (10U)
ïI2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
ðI2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
ñI2C_OAR2_OA2MASK05_Pos (8U)
òI2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
óI2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
ôI2C_OAR2_OA2MASK06_Pos (9U)
õI2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
öI2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
÷I2C_OAR2_OA2MASK07_Pos (8U)
øI2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
ùI2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
úI2C_OAR2_OA2EN_Pos (15U)
ûI2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
üI2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
ÿI2C_TIMINGR_SCLL_Pos (0U)
€I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
‚I2C_TIMINGR_SCLH_Pos (8U)
ƒI2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
„I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
…I2C_TIMINGR_SDADEL_Pos (16U)
†I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
‡I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
ˆI2C_TIMINGR_SCLDEL_Pos (20U)
‰I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
ŠI2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
‹I2C_TIMINGR_PRESC_Pos (28U)
ŒI2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
‘I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
’I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
“I2C_TIMEOUTR_TIDLE_Pos (12U)
”I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
•I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
–I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
—I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
˜I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
™I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
šI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
›I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
œI2C_TIMEOUTR_TEXTEN_Pos (31U)
I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
žI2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
¡I2C_ISR_TXE_Pos (0U)
¢I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
£I2C_ISR_TXE I2C_ISR_TXE_Msk
¤I2C_ISR_TXIS_Pos (1U)
¥I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
¦I2C_ISR_TXIS I2C_ISR_TXIS_Msk
§I2C_ISR_RXNE_Pos (2U)
¨I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
©I2C_ISR_RXNE I2C_ISR_RXNE_Msk
ªI2C_ISR_ADDR_Pos (3U)
«I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
¬I2C_ISR_ADDR I2C_ISR_ADDR_Msk
­I2C_ISR_NACKF_Pos (4U)
®I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
¯I2C_ISR_NACKF I2C_ISR_NACKF_Msk
°I2C_ISR_STOPF_Pos (5U)
±I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
²I2C_ISR_STOPF I2C_ISR_STOPF_Msk
³I2C_ISR_TC_Pos (6U)
´I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
µI2C_ISR_TC I2C_ISR_TC_Msk
¶I2C_ISR_TCR_Pos (7U)
·I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
¸I2C_ISR_TCR I2C_ISR_TCR_Msk
¹I2C_ISR_BERR_Pos (8U)
ºI2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
»I2C_ISR_BERR I2C_ISR_BERR_Msk
¼I2C_ISR_ARLO_Pos (9U)
½I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
¾I2C_ISR_ARLO I2C_ISR_ARLO_Msk
¿I2C_ISR_OVR_Pos (10U)
ÀI2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
ÁI2C_ISR_OVR I2C_ISR_OVR_Msk
ÂI2C_ISR_PECERR_Pos (11U)
ÃI2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
ÄI2C_ISR_PECERR I2C_ISR_PECERR_Msk
ÅI2C_ISR_TIMEOUT_Pos (12U)
ÆI2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
ÇI2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
ÈI2C_ISR_ALERT_Pos (13U)
ÉI2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
ÊI2C_ISR_ALERT I2C_ISR_ALERT_Msk
ËI2C_ISR_BUSY_Pos (15U)
ÌI2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
ÍI2C_ISR_BUSY I2C_ISR_BUSY_Msk
ÎI2C_ISR_DIR_Pos (16U)
ÏI2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
ÐI2C_ISR_DIR I2C_ISR_DIR_Msk
ÑI2C_ISR_ADDCODE_Pos (17U)
ÒI2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
ÓI2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
ÖI2C_ICR_ADDRCF_Pos (3U)
×I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
ØI2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
ÙI2C_ICR_NACKCF_Pos (4U)
ÚI2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
ÛI2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
ÜI2C_ICR_STOPCF_Pos (5U)
ÝI2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
ÞI2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
ßI2C_ICR_BERRCF_Pos (8U)
àI2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
áI2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
âI2C_ICR_ARLOCF_Pos (9U)
ãI2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
äI2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
åI2C_ICR_OVRCF_Pos (10U)
æI2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
çI2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
èI2C_ICR_PECCF_Pos (11U)
éI2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
êI2C_ICR_PECCF I2C_ICR_PECCF_Msk
ëI2C_ICR_TIMOUTCF_Pos (12U)
ìI2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
íI2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
îI2C_ICR_ALERTCF_Pos (13U)
ïI2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
ðI2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
óI2C_PECR_PEC_Pos (0U)
ôI2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
õI2C_PECR_PEC I2C_PECR_PEC_Msk
øI2C_RXDR_RXDATA_Pos (0U)
ùI2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
úI2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
ýI2C_TXDR_TXDATA_Pos (0U)
þI2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
ÿI2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
‡IWDG_KR_KEY_Pos (0U)
ˆIWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
‰IWDG_KR_KEY IWDG_KR_KEY_Msk
ŒIWDG_PR_PR_Pos (0U)
IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
ŽIWDG_PR_PR IWDG_PR_PR_Msk
IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
‘IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
”IWDG_RLR_RL_Pos (0U)
•IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
–IWDG_RLR_RL IWDG_RLR_RL_Msk
™IWDG_SR_PVU_Pos (0U)
šIWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
›IWDG_SR_PVU IWDG_SR_PVU_Msk
œIWDG_SR_RVU_Pos (1U)
IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
žIWDG_SR_RVU IWDG_SR_RVU_Msk
ŸIWDG_SR_WVU_Pos (2U)
 IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
¡IWDG_SR_WVU IWDG_SR_WVU_Msk
¤IWDG_WINR_WIN_Pos (0U)
¥IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
¦IWDG_WINR_WIN IWDG_WINR_WIN_Msk
®LPTIM_ISR_CMPM_Pos (0U)
¯LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
°LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
±LPTIM_ISR_ARRM_Pos (1U)
²LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
³LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
´LPTIM_ISR_EXTTRIG_Pos (2U)
µLPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
¶LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
·LPTIM_ISR_CMPOK_Pos (3U)
¸LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
¹LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
ºLPTIM_ISR_ARROK_Pos (4U)
»LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
¼LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
½LPTIM_ISR_UP_Pos (5U)
¾LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
¿LPTIM_ISR_UP LPTIM_ISR_UP_Msk
ÀLPTIM_ISR_DOWN_Pos (6U)
ÁLPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
ÂLPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
ÅLPTIM_ICR_CMPMCF_Pos (0U)
ÆLPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
ÇLPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
ÈLPTIM_ICR_ARRMCF_Pos (1U)
ÉLPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
ÊLPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
ËLPTIM_ICR_EXTTRIGCF_Pos (2U)
ÌLPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
ÍLPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
ÎLPTIM_ICR_CMPOKCF_Pos (3U)
ÏLPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
ÐLPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
ÑLPTIM_ICR_ARROKCF_Pos (4U)
ÒLPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
ÓLPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
ÔLPTIM_ICR_UPCF_Pos (5U)
ÕLPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
ÖLPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
×LPTIM_ICR_DOWNCF_Pos (6U)
ØLPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
ÙLPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
ÜLPTIM_IER_CMPMIE_Pos (0U)
ÝLPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
ÞLPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
ßLPTIM_IER_ARRMIE_Pos (1U)
àLPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
áLPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
âLPTIM_IER_EXTTRIGIE_Pos (2U)
ãLPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
äLPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
åLPTIM_IER_CMPOKIE_Pos (3U)
æLPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
çLPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
èLPTIM_IER_ARROKIE_Pos (4U)
éLPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
êLPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
ëLPTIM_IER_UPIE_Pos (5U)
ìLPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
íLPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
îLPTIM_IER_DOWNIE_Pos (6U)
ïLPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
ðLPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
óLPTIM_CFGR_CKSEL_Pos (0U)
ôLPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
õLPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
÷LPTIM_CFGR_CKPOL_Pos (1U)
øLPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
ùLPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
úLPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
ûLPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
ýLPTIM_CFGR_CKFLT_Pos (3U)
þLPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
ÿLPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
€LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
ƒLPTIM_CFGR_TRGFLT_Pos (6U)
„LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
…LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
†LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
‡LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
‰LPTIM_CFGR_PRESC_Pos (9U)
ŠLPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
‹LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
ŒLPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
ŽLPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
LPTIM_CFGR_TRIGSEL_Pos (13U)
‘LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
’LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
“LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
”LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
•LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
—LPTIM_CFGR_TRIGEN_Pos (17U)
˜LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
™LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
šLPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
›LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
LPTIM_CFGR_TIMOUT_Pos (19U)
žLPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
ŸLPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
 LPTIM_CFGR_WAVE_Pos (20U)
¡LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
¢LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
£LPTIM_CFGR_WAVPOL_Pos (21U)
¤LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
¥LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
¦LPTIM_CFGR_PRELOAD_Pos (22U)
§LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
¨LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
©LPTIM_CFGR_COUNTMODE_Pos (23U)
ªLPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
«LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
¬LPTIM_CFGR_ENC_Pos (24U)
­LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
®LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
±LPTIM_CR_ENABLE_Pos (0U)
²LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
³LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
´LPTIM_CR_SNGSTRT_Pos (1U)
µLPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
¶LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
·LPTIM_CR_CNTSTRT_Pos (2U)
¸LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
¹LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
¼LPTIM_CMP_CMP_Pos (0U)
½LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
¾LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
ÁLPTIM_ARR_ARR_Pos (0U)
ÂLPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
ÃLPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
ÆLPTIM_CNT_CNT_Pos (0U)
ÇLPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
ÈLPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
ÑFW_CSSA_ADD_Pos (8U)
ÒFW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos)
ÓFW_CSSA_ADD FW_CSSA_ADD_Msk
ÔFW_CSL_LENG_Pos (8U)
ÕFW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos)
ÖFW_CSL_LENG FW_CSL_LENG_Msk
×FW_NVDSSA_ADD_Pos (8U)
ØFW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos)
ÙFW_NVDSSA_ADD FW_NVDSSA_ADD_Msk
ÚFW_NVDSL_LENG_Pos (8U)
ÛFW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos)
ÜFW_NVDSL_LENG FW_NVDSL_LENG_Msk
ÝFW_VDSSA_ADD_Pos (6U)
ÞFW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos)
ßFW_VDSSA_ADD FW_VDSSA_ADD_Msk
àFW_VDSL_LENG_Pos (6U)
áFW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos)
âFW_VDSL_LENG FW_VDSL_LENG_Msk
åFW_CR_FPA_Pos (0U)
æFW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos)
çFW_CR_FPA FW_CR_FPA_Msk
èFW_CR_VDS_Pos (1U)
éFW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos)
êFW_CR_VDS FW_CR_VDS_Msk
ëFW_CR_VDE_Pos (2U)
ìFW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos)
íFW_CR_VDE FW_CR_VDE_Msk
õPWR_PVD_SUPPORT 
øPWR_CR_LPSDSR_Pos (0U)
ùPWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos)
úPWR_CR_LPSDSR PWR_CR_LPSDSR_Msk
ûPWR_CR_PDDS_Pos (1U)
üPWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
ýPWR_CR_PDDS PWR_CR_PDDS_Msk
þPWR_CR_CWUF_Pos (2U)
ÿPWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
€PWR_CR_CWUF PWR_CR_CWUF_Msk
PWR_CR_CSBF_Pos (3U)
‚PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
ƒPWR_CR_CSBF PWR_CR_CSBF_Msk
„PWR_CR_PVDE_Pos (4U)
…PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
†PWR_CR_PVDE PWR_CR_PVDE_Msk
ˆPWR_CR_PLS_Pos (5U)
‰PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
ŠPWR_CR_PLS PWR_CR_PLS_Msk
‹PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
ŒPWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
PWR_CR_PLS_LEV0 (0x00000000U)
‘PWR_CR_PLS_LEV1 (0x00000020U)
’PWR_CR_PLS_LEV2 (0x00000040U)
“PWR_CR_PLS_LEV3 (0x00000060U)
”PWR_CR_PLS_LEV4 (0x00000080U)
•PWR_CR_PLS_LEV5 (0x000000A0U)
–PWR_CR_PLS_LEV6 (0x000000C0U)
—PWR_CR_PLS_LEV7 (0x000000E0U)
™PWR_CR_DBP_Pos (8U)
šPWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
›PWR_CR_DBP PWR_CR_DBP_Msk
œPWR_CR_ULP_Pos (9U)
PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos)
žPWR_CR_ULP PWR_CR_ULP_Msk
ŸPWR_CR_FWU_Pos (10U)
 PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos)
¡PWR_CR_FWU PWR_CR_FWU_Msk
£PWR_CR_VOS_Pos (11U)
¤PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
¥PWR_CR_VOS PWR_CR_VOS_Msk
¦PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos)
§PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos)
¨PWR_CR_DSEEKOFF_Pos (13U)
©PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos)
ªPWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk
«PWR_CR_LPRUN_Pos (14U)
¬PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos)
­PWR_CR_LPRUN PWR_CR_LPRUN_Msk
°PWR_CSR_WUF_Pos (0U)
±PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
²PWR_CSR_WUF PWR_CSR_WUF_Msk
³PWR_CSR_SBF_Pos (1U)
´PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
µPWR_CSR_SBF PWR_CSR_SBF_Msk
¶PWR_CSR_PVDO_Pos (2U)
·PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
¸PWR_CSR_PVDO PWR_CSR_PVDO_Msk
¹PWR_CSR_VREFINTRDYF_Pos (3U)
ºPWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos)
»PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk
¼PWR_CSR_VOSF_Pos (4U)
½PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos)
¾PWR_CSR_VOSF PWR_CSR_VOSF_Msk
¿PWR_CSR_REGLPF_Pos (5U)
ÀPWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos)
ÁPWR_CSR_REGLPF PWR_CSR_REGLPF_Msk
ÃPWR_CSR_EWUP1_Pos (8U)
ÄPWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
ÅPWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
ÆPWR_CSR_EWUP2_Pos (9U)
ÇPWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
ÈPWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
ÉPWR_CSR_EWUP3_Pos (10U)
ÊPWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)
ËPWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk
ÕRCC_HSECSS_SUPPORT 
ÖRCC_MCO3_SUPPORT 
×RCC_MCO3_AF2_SUPPORT 
ÚRCC_CR_HSION_Pos (0U)
ÛRCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
ÜRCC_CR_HSION RCC_CR_HSION_Msk
ÝRCC_CR_HSIKERON_Pos (1U)
ÞRCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
ßRCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
àRCC_CR_HSIRDY_Pos (2U)
áRCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
âRCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
ãRCC_CR_HSIDIVEN_Pos (3U)
äRCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos)
åRCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk
æRCC_CR_HSIDIVF_Pos (4U)
çRCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
èRCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
éRCC_CR_HSIOUTEN_Pos (5U)
êRCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos)
ëRCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk
ìRCC_CR_MSION_Pos (8U)
íRCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)
îRCC_CR_MSION RCC_CR_MSION_Msk
ïRCC_CR_MSIRDY_Pos (9U)
ðRCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)
ñRCC_CR_MSIRDY RCC_CR_MSIRDY_Msk
òRCC_CR_HSEON_Pos (16U)
óRCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
ôRCC_CR_HSEON RCC_CR_HSEON_Msk
õRCC_CR_HSERDY_Pos (17U)
öRCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
÷RCC_CR_HSERDY RCC_CR_HSERDY_Msk
øRCC_CR_HSEBYP_Pos (18U)
ùRCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
úRCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
ûRCC_CR_CSSHSEON_Pos (19U)
üRCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
ýRCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
þRCC_CR_RTCPRE_Pos (20U)
ÿRCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos)
€RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk
RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos)
‚RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos)
ƒRCC_CR_PLLON_Pos (24U)
„RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
…RCC_CR_PLLON RCC_CR_PLLON_Msk
†RCC_CR_PLLRDY_Pos (25U)
‡RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
ˆRCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
‹RCC_CR_CSSON RCC_CR_CSSHSEON
ŽRCC_ICSCR_HSICAL_Pos (0U)
RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)
RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk
‘RCC_ICSCR_HSITRIM_Pos (8U)
’RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos)
“RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk
•RCC_ICSCR_MSIRANGE_Pos (13U)
–RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos)
—RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk
˜RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos)
™RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos)
šRCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos)
›RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos)
œRCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos)
RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos)
žRCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos)
ŸRCC_ICSCR_MSICAL_Pos (16U)
 RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)
¡RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk
¢RCC_ICSCR_MSITRIM_Pos (24U)
£RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)
¤RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk
©RCC_CFGR_SW_Pos (0U)
ªRCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
«RCC_CFGR_SW RCC_CFGR_SW_Msk
¬RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
­RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
¯RCC_CFGR_SW_MSI (0x00000000U)
°RCC_CFGR_SW_HSI (0x00000001U)
±RCC_CFGR_SW_HSE (0x00000002U)
²RCC_CFGR_SW_PLL (0x00000003U)
µRCC_CFGR_SWS_Pos (2U)
¶RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
·RCC_CFGR_SWS RCC_CFGR_SWS_Msk
¸RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
¹RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
»RCC_CFGR_SWS_MSI (0x00000000U)
¼RCC_CFGR_SWS_HSI (0x00000004U)
½RCC_CFGR_SWS_HSE (0x00000008U)
¾RCC_CFGR_SWS_PLL (0x0000000CU)
ÁRCC_CFGR_HPRE_Pos (4U)
ÂRCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
ÃRCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
ÄRCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
ÅRCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
ÆRCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
ÇRCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
ÉRCC_CFGR_HPRE_DIV1 (0x00000000U)
ÊRCC_CFGR_HPRE_DIV2 (0x00000080U)
ËRCC_CFGR_HPRE_DIV4 (0x00000090U)
ÌRCC_CFGR_HPRE_DIV8 (0x000000A0U)
ÍRCC_CFGR_HPRE_DIV16 (0x000000B0U)
ÎRCC_CFGR_HPRE_DIV64 (0x000000C0U)
ÏRCC_CFGR_HPRE_DIV128 (0x000000D0U)
ÐRCC_CFGR_HPRE_DIV256 (0x000000E0U)
ÑRCC_CFGR_HPRE_DIV512 (0x000000F0U)
ÔRCC_CFGR_PPRE1_Pos (8U)
ÕRCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
ÖRCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
×RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
ØRCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
ÙRCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
ÛRCC_CFGR_PPRE1_DIV1 (0x00000000U)
ÜRCC_CFGR_PPRE1_DIV2 (0x00000400U)
ÝRCC_CFGR_PPRE1_DIV4 (0x00000500U)
ÞRCC_CFGR_PPRE1_DIV8 (0x00000600U)
ßRCC_CFGR_PPRE1_DIV16 (0x00000700U)
âRCC_CFGR_PPRE2_Pos (11U)
ãRCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
äRCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
åRCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
æRCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
çRCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
éRCC_CFGR_PPRE2_DIV1 (0x00000000U)
êRCC_CFGR_PPRE2_DIV2 (0x00002000U)
ëRCC_CFGR_PPRE2_DIV4 (0x00002800U)
ìRCC_CFGR_PPRE2_DIV8 (0x00003000U)
íRCC_CFGR_PPRE2_DIV16 (0x00003800U)
ïRCC_CFGR_STOPWUCK_Pos (15U)
ðRCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
ñRCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
ôRCC_CFGR_PLLSRC_Pos (16U)
õRCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
öRCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
øRCC_CFGR_PLLSRC_HSI (0x00000000U)
ùRCC_CFGR_PLLSRC_HSE (0x00010000U)
ýRCC_CFGR_PLLMUL_Pos (18U)
þRCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)
ÿRCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk
€RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)
RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)
‚RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)
ƒRCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)
…RCC_CFGR_PLLMUL3 (0x00000000U)
†RCC_CFGR_PLLMUL4 (0x00040000U)
‡RCC_CFGR_PLLMUL6 (0x00080000U)
ˆRCC_CFGR_PLLMUL8 (0x000C0000U)
‰RCC_CFGR_PLLMUL12 (0x00100000U)
ŠRCC_CFGR_PLLMUL16 (0x00140000U)
‹RCC_CFGR_PLLMUL24 (0x00180000U)
ŒRCC_CFGR_PLLMUL32 (0x001C0000U)
RCC_CFGR_PLLMUL48 (0x00200000U)
RCC_CFGR_PLLDIV_Pos (22U)
‘RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos)
’RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk
“RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos)
”RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos)
–RCC_CFGR_PLLDIV2_Pos (22U)
—RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos)
˜RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk
™RCC_CFGR_PLLDIV3_Pos (23U)
šRCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos)
›RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk
œRCC_CFGR_PLLDIV4_Pos (22U)
RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos)
žRCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk
¡RCC_CFGR_MCOSEL_Pos (24U)
¢RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)
£RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk
¤RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)
¥RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)
¦RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)
§RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)
©RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U)
ªRCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
«RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos)
¬RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk
­RCC_CFGR_MCOSEL_HSI_Pos (25U)
®RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)
¯RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk
°RCC_CFGR_MCOSEL_MSI_Pos (24U)
±RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)
²RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk
³RCC_CFGR_MCOSEL_HSE_Pos (26U)
´RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)
µRCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk
¶RCC_CFGR_MCOSEL_PLL_Pos (24U)
·RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)
¸RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk
¹RCC_CFGR_MCOSEL_LSI_Pos (25U)
ºRCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)
»RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk
¼RCC_CFGR_MCOSEL_LSE_Pos (24U)
½RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)
¾RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk
ÀRCC_CFGR_MCOPRE_Pos (28U)
ÁRCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
ÂRCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
ÃRCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
ÄRCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
ÅRCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
ÇRCC_CFGR_MCOPRE_DIV1 (0x00000000U)
ÈRCC_CFGR_MCOPRE_DIV2 (0x10000000U)
ÉRCC_CFGR_MCOPRE_DIV4 (0x20000000U)
ÊRCC_CFGR_MCOPRE_DIV8 (0x30000000U)
ËRCC_CFGR_MCOPRE_DIV16 (0x40000000U)
ÎRCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
ÏRCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
ÐRCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
ÑRCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
ÒRCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
ÓRCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
ÔRCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
ÕRCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
ÚRCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
ÛRCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
ÜRCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
ÝRCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
ÞRCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
ßRCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
âRCC_CIER_LSIRDYIE_Pos (0U)
ãRCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
äRCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
åRCC_CIER_LSERDYIE_Pos (1U)
æRCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
çRCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
èRCC_CIER_HSIRDYIE_Pos (2U)
éRCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
êRCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
ëRCC_CIER_HSERDYIE_Pos (3U)
ìRCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
íRCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
îRCC_CIER_PLLRDYIE_Pos (4U)
ïRCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)
ðRCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
ñRCC_CIER_MSIRDYIE_Pos (5U)
òRCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)
óRCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
ôRCC_CIER_CSSLSE_Pos (7U)
õRCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos)
öRCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk
ùRCC_CIER_LSECSSIE RCC_CIER_CSSLSE
üRCC_CIFR_LSIRDYF_Pos (0U)
ýRCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
þRCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
ÿRCC_CIFR_LSERDYF_Pos (1U)
€RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
‚RCC_CIFR_HSIRDYF_Pos (2U)
ƒRCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
„RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
…RCC_CIFR_HSERDYF_Pos (3U)
†RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
‡RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
ˆRCC_CIFR_PLLRDYF_Pos (4U)
‰RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
ŠRCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
‹RCC_CIFR_MSIRDYF_Pos (5U)
ŒRCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)
RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
ŽRCC_CIFR_CSSLSEF_Pos (7U)
RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos)
RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk
‘RCC_CIFR_CSSHSEF_Pos (8U)
’RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos)
“RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk
–RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
—RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
šRCC_CICR_LSIRDYC_Pos (0U)
›RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
œRCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
RCC_CICR_LSERDYC_Pos (1U)
žRCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
ŸRCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
 RCC_CICR_HSIRDYC_Pos (2U)
¡RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
¢RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
£RCC_CICR_HSERDYC_Pos (3U)
¤RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
¥RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
¦RCC_CICR_PLLRDYC_Pos (4U)
§RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
¨RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
©RCC_CICR_MSIRDYC_Pos (5U)
ªRCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)
«RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
¬RCC_CICR_CSSLSEC_Pos (7U)
­RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos)
®RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk
¯RCC_CICR_CSSHSEC_Pos (8U)
°RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos)
±RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk
´RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
µRCC_CICR_CSSC RCC_CICR_CSSHSEC
·RCC_IOPRSTR_IOPARST_Pos (0U)
¸RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos)
¹RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk
ºRCC_IOPRSTR_IOPBRST_Pos (1U)
»RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)
¼RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk
½RCC_IOPRSTR_IOPCRST_Pos (2U)
¾RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)
¿RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk
ÀRCC_IOPRSTR_IOPDRST_Pos (3U)
ÁRCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)
ÂRCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk
ÃRCC_IOPRSTR_IOPERST_Pos (4U)
ÄRCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos)
ÅRCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk
ÆRCC_IOPRSTR_IOPHRST_Pos (7U)
ÇRCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)
ÈRCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk
ËRCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST
ÌRCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST
ÍRCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST
ÎRCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST
ÏRCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST
ÐRCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST
ÔRCC_AHBRSTR_DMARST_Pos (0U)
ÕRCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos)
ÖRCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk
×RCC_AHBRSTR_MIFRST_Pos (8U)
ØRCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos)
ÙRCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk
ÚRCC_AHBRSTR_CRCRST_Pos (12U)
ÛRCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos)
ÜRCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk
ßRCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST
âRCC_APB2RSTR_SYSCFGRST_Pos (0U)
ãRCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
äRCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
åRCC_APB2RSTR_TIM21RST_Pos (2U)
æRCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)
çRCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk
èRCC_APB2RSTR_TIM22RST_Pos (5U)
éRCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)
êRCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk
ëRCC_APB2RSTR_ADCRST_Pos (9U)
ìRCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
íRCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
îRCC_APB2RSTR_SPI1RST_Pos (12U)
ïRCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
ðRCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
ñRCC_APB2RSTR_USART1RST_Pos (14U)
òRCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
óRCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
ôRCC_APB2RSTR_DBGRST_Pos (22U)
õRCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos)
öRCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk
ùRCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
úRCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST
ýRCC_APB1RSTR_TIM2RST_Pos (0U)
þRCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
ÿRCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
€RCC_APB1RSTR_TIM3RST_Pos (1U)
RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
‚RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
ƒRCC_APB1RSTR_TIM6RST_Pos (4U)
„RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
…RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
†RCC_APB1RSTR_TIM7RST_Pos (5U)
‡RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
ˆRCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
‰RCC_APB1RSTR_WWDGRST_Pos (11U)
ŠRCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
‹RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
ŒRCC_APB1RSTR_SPI2RST_Pos (14U)
RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
ŽRCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
RCC_APB1RSTR_USART2RST_Pos (17U)
RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
‘RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
’RCC_APB1RSTR_LPUART1RST_Pos (18U)
“RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos)
”RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk
•RCC_APB1RSTR_USART4RST_Pos (19U)
–RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos)
—RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk
˜RCC_APB1RSTR_USART5RST_Pos (20U)
™RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos)
šRCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk
›RCC_APB1RSTR_I2C1RST_Pos (21U)
œRCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
žRCC_APB1RSTR_I2C2RST_Pos (22U)
ŸRCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
 RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
¡RCC_APB1RSTR_PWRRST_Pos (28U)
¢RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
£RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
¤RCC_APB1RSTR_I2C3RST_Pos (30U)
¥RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
¦RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
§RCC_APB1RSTR_LPTIM1RST_Pos (31U)
¨RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
©RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
¬RCC_IOPENR_IOPAEN_Pos (0U)
­RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos)
®RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk
¯RCC_IOPENR_IOPBEN_Pos (1U)
°RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos)
±RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk
²RCC_IOPENR_IOPCEN_Pos (2U)
³RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos)
´RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk
µRCC_IOPENR_IOPDEN_Pos (3U)
¶RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos)
·RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk
¸RCC_IOPENR_IOPEEN_Pos (4U)
¹RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos)
ºRCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk
»RCC_IOPENR_IOPHEN_Pos (7U)
¼RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos)
½RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk
ÀRCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN
ÁRCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN
ÂRCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN
ÃRCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN
ÄRCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN
ÅRCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN
ÈRCC_AHBENR_DMAEN_Pos (0U)
ÉRCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos)
ÊRCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk
ËRCC_AHBENR_MIFEN_Pos (8U)
ÌRCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos)
ÍRCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk
ÎRCC_AHBENR_CRCEN_Pos (12U)
ÏRCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)
ÐRCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
ÓRCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN
ÖRCC_APB2ENR_SYSCFGEN_Pos (0U)
×RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
ØRCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
ÙRCC_APB2ENR_TIM21EN_Pos (2U)
ÚRCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos)
ÛRCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk
ÜRCC_APB2ENR_TIM22EN_Pos (5U)
ÝRCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos)
ÞRCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk
ßRCC_APB2ENR_FWEN_Pos (7U)
àRCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos)
áRCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
âRCC_APB2ENR_ADCEN_Pos (9U)
ãRCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos)
äRCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk
åRCC_APB2ENR_SPI1EN_Pos (12U)
æRCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
çRCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
èRCC_APB2ENR_USART1EN_Pos (14U)
éRCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
êRCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
ëRCC_APB2ENR_DBGEN_Pos (22U)
ìRCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos)
íRCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk
ñRCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN
òRCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN
óRCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN
öRCC_APB1ENR_TIM2EN_Pos (0U)
÷RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
øRCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
ùRCC_APB1ENR_TIM3EN_Pos (1U)
úRCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
ûRCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
üRCC_APB1ENR_TIM6EN_Pos (4U)
ýRCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
þRCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
ÿRCC_APB1ENR_TIM7EN_Pos (5U)
€RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
‚RCC_APB1ENR_WWDGEN_Pos (11U)
ƒRCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
„RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
…RCC_APB1ENR_SPI2EN_Pos (14U)
†RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
‡RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
ˆRCC_APB1ENR_USART2EN_Pos (17U)
‰RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
ŠRCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
‹RCC_APB1ENR_LPUART1EN_Pos (18U)
ŒRCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)
RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk
ŽRCC_APB1ENR_USART4EN_Pos (19U)
RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos)
RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk
‘RCC_APB1ENR_USART5EN_Pos (20U)
’RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos)
“RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk
”RCC_APB1ENR_I2C1EN_Pos (21U)
•RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
–RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
—RCC_APB1ENR_I2C2EN_Pos (22U)
˜RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
™RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
šRCC_APB1ENR_PWREN_Pos (28U)
›RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
œRCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
RCC_APB1ENR_I2C3EN_Pos (30U)
žRCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
ŸRCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
 RCC_APB1ENR_LPTIM1EN_Pos (31U)
¡RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
¢RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
¥RCC_IOPSMENR_IOPASMEN_Pos (0U)
¦RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)
§RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk
¨RCC_IOPSMENR_IOPBSMEN_Pos (1U)
©RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)
ªRCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk
«RCC_IOPSMENR_IOPCSMEN_Pos (2U)
¬RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)
­RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk
®RCC_IOPSMENR_IOPDSMEN_Pos (3U)
¯RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)
°RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk
±RCC_IOPSMENR_IOPESMEN_Pos (4U)
²RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos)
³RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk
´RCC_IOPSMENR_IOPHSMEN_Pos (7U)
µRCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)
¶RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk
¹RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN
ºRCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN
»RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN
¼RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN
½RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN
¾RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN
ÁRCC_AHBSMENR_DMASMEN_Pos (0U)
ÂRCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)
ÃRCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk
ÄRCC_AHBSMENR_MIFSMEN_Pos (8U)
ÅRCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)
ÆRCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk
ÇRCC_AHBSMENR_SRAMSMEN_Pos (9U)
ÈRCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)
ÉRCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk
ÊRCC_AHBSMENR_CRCSMEN_Pos (12U)
ËRCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)
ÌRCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk
ÏRCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN
ÒRCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
ÓRCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)
ÔRCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
ÕRCC_APB2SMENR_TIM21SMEN_Pos (2U)
ÖRCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos)
×RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk
ØRCC_APB2SMENR_TIM22SMEN_Pos (5U)
ÙRCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos)
ÚRCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk
ÛRCC_APB2SMENR_ADCSMEN_Pos (9U)
ÜRCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)
ÝRCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk
ÞRCC_APB2SMENR_SPI1SMEN_Pos (12U)
ßRCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)
àRCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
áRCC_APB2SMENR_USART1SMEN_Pos (14U)
âRCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)
ãRCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
äRCC_APB2SMENR_DBGSMEN_Pos (22U)
åRCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)
æRCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk
éRCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN
êRCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN
íRCC_APB1SMENR_TIM2SMEN_Pos (0U)
îRCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)
ïRCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk
ðRCC_APB1SMENR_TIM3SMEN_Pos (1U)
ñRCC_APB1SMENR_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos)
òRCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk
óRCC_APB1SMENR_TIM6SMEN_Pos (4U)
ôRCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)
õRCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk
öRCC_APB1SMENR_TIM7SMEN_Pos (5U)
÷RCC_APB1SMENR_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos)
øRCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk
ùRCC_APB1SMENR_WWDGSMEN_Pos (11U)
úRCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)
ûRCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk
üRCC_APB1SMENR_SPI2SMEN_Pos (14U)
ýRCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)
þRCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk
ÿRCC_APB1SMENR_USART2SMEN_Pos (17U)
€RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos)
RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk
‚RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
ƒRCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos)
„RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk
…RCC_APB1SMENR_USART4SMEN_Pos (19U)
†RCC_APB1SMENR_USART4SMEN_Msk (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos)
‡RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk
ˆRCC_APB1SMENR_USART5SMEN_Pos (20U)
‰RCC_APB1SMENR_USART5SMEN_Msk (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos)
ŠRCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk
‹RCC_APB1SMENR_I2C1SMEN_Pos (21U)
ŒRCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)
RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk
ŽRCC_APB1SMENR_I2C2SMEN_Pos (22U)
RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)
RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk
‘RCC_APB1SMENR_PWRSMEN_Pos (28U)
’RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)
“RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk
”RCC_APB1SMENR_I2C3SMEN_Pos (30U)
•RCC_APB1SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos)
–RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk
—RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
˜RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos)
™RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk
RCC_CCIPR_USART1SEL_Pos (0U)
žRCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)
ŸRCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
 RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)
¡RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)
¤RCC_CCIPR_USART2SEL_Pos (2U)
¥RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)
¦RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
§RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)
¨RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)
«RCC_CCIPR_LPUART1SEL_Pos (10U)
¬RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)
­RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
®RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)
¯RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)
²RCC_CCIPR_I2C1SEL_Pos (12U)
³RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)
´RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
µRCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)
¶RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)
¹RCC_CCIPR_I2C3SEL_Pos (16U)
ºRCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)
»RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
¼RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)
½RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)
ÀRCC_CCIPR_LPTIM1SEL_Pos (18U)
ÁRCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)
ÂRCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
ÃRCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)
ÄRCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)
ÇRCC_CSR_LSION_Pos (0U)
ÈRCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
ÉRCC_CSR_LSION RCC_CSR_LSION_Msk
ÊRCC_CSR_LSIRDY_Pos (1U)
ËRCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
ÌRCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
ÎRCC_CSR_LSEON_Pos (8U)
ÏRCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos)
ÐRCC_CSR_LSEON RCC_CSR_LSEON_Msk
ÑRCC_CSR_LSERDY_Pos (9U)
ÒRCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos)
ÓRCC_CSR_LSERDY RCC_CSR_LSERDY_Msk
ÔRCC_CSR_LSEBYP_Pos (10U)
ÕRCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos)
ÖRCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk
ØRCC_CSR_LSEDRV_Pos (11U)
ÙRCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos)
ÚRCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk
ÛRCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos)
ÜRCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos)
ÞRCC_CSR_LSECSSON_Pos (13U)
ßRCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos)
àRCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk
áRCC_CSR_LSECSSD_Pos (14U)
âRCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos)
ãRCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk
æRCC_CSR_RTCSEL_Pos (16U)
çRCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos)
èRCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk
éRCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos)
êRCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos)
ìRCC_CSR_RTCSEL_NOCLOCK (0x00000000U)
íRCC_CSR_RTCSEL_LSE_Pos (16U)
îRCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)
ïRCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk
ðRCC_CSR_RTCSEL_LSI_Pos (17U)
ñRCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)
òRCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk
óRCC_CSR_RTCSEL_HSE_Pos (16U)
ôRCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)
õRCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk
÷RCC_CSR_RTCEN_Pos (18U)
øRCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos)
ùRCC_CSR_RTCEN RCC_CSR_RTCEN_Msk
úRCC_CSR_RTCRST_Pos (19U)
ûRCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos)
üRCC_CSR_RTCRST RCC_CSR_RTCRST_Msk
þRCC_CSR_RMVF_Pos (23U)
ÿRCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
€ RCC_CSR_RMVF RCC_CSR_RMVF_Msk
 RCC_CSR_FWRSTF_Pos (24U)
‚ RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos)
ƒ RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
„ RCC_CSR_OBLRSTF_Pos (25U)
… RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
† RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
‡ RCC_CSR_PINRSTF_Pos (26U)
ˆ RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
‰ RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
Š RCC_CSR_PORRSTF_Pos (27U)
‹ RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
Œ RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
 RCC_CSR_SFTRSTF_Pos (28U)
Ž RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
 RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
 RCC_CSR_IWDGRSTF_Pos (29U)
‘ RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
’ RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
“ RCC_CSR_WWDGRSTF_Pos (30U)
” RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
• RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
– RCC_CSR_LPWRRSTF_Pos (31U)
— RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
˜ RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
› RCC_CSR_OBL RCC_CSR_OBLRSTF
¦ RTC_TAMPER1_SUPPORT 
§ RTC_TAMPER2_SUPPORT 
¨ RTC_TAMPER3_SUPPORT 
© RTC_WAKEUP_SUPPORT 
ª RTC_BACKUP_SUPPORT 
­ RTC_TR_PM_Pos (22U)
® RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
¯ RTC_TR_PM RTC_TR_PM_Msk
° RTC_TR_HT_Pos (20U)
± RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
² RTC_TR_HT RTC_TR_HT_Msk
³ RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
´ RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
µ RTC_TR_HU_Pos (16U)
¶ RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
· RTC_TR_HU RTC_TR_HU_Msk
¸ RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
¹ RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
º RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
» RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
¼ RTC_TR_MNT_Pos (12U)
½ RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
¾ RTC_TR_MNT RTC_TR_MNT_Msk
¿ RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
À RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
Á RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
 RTC_TR_MNU_Pos (8U)
àRTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
Ä RTC_TR_MNU RTC_TR_MNU_Msk
Å RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
Æ RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
Ç RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
È RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
É RTC_TR_ST_Pos (4U)
Ê RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
Ë RTC_TR_ST RTC_TR_ST_Msk
Ì RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
Í RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
ΠRTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
Ï RTC_TR_SU_Pos (0U)
РRTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
Ñ RTC_TR_SU RTC_TR_SU_Msk
Ò RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
Ó RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
Ô RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
Õ RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
Ø RTC_DR_YT_Pos (20U)
Ù RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
Ú RTC_DR_YT RTC_DR_YT_Msk
Û RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
Ü RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
Ý RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
Þ RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
ß RTC_DR_YU_Pos (16U)
à RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
á RTC_DR_YU RTC_DR_YU_Msk
â RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
ã RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
ä RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
å RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
æ RTC_DR_WDU_Pos (13U)
ç RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
è RTC_DR_WDU RTC_DR_WDU_Msk
é RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
ê RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
ë RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
ì RTC_DR_MT_Pos (12U)
í RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
î RTC_DR_MT RTC_DR_MT_Msk
ï RTC_DR_MU_Pos (8U)
ð RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
ñ RTC_DR_MU RTC_DR_MU_Msk
ò RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
ó RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
ô RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
õ RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
ö RTC_DR_DT_Pos (4U)
÷ RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
ø RTC_DR_DT RTC_DR_DT_Msk
ù RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
ú RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
û RTC_DR_DU_Pos (0U)
ü RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
ý RTC_DR_DU RTC_DR_DU_Msk
þ RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
ÿ RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
€!RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
!RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
„!RTC_CR_COE_Pos (23U)
…!RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
†!RTC_CR_COE RTC_CR_COE_Msk
‡!RTC_CR_OSEL_Pos (21U)
ˆ!RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
‰!RTC_CR_OSEL RTC_CR_OSEL_Msk
Š!RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
‹!RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
Œ!RTC_CR_POL_Pos (20U)
!RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
Ž!RTC_CR_POL RTC_CR_POL_Msk
!RTC_CR_COSEL_Pos (19U)
!RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
‘!RTC_CR_COSEL RTC_CR_COSEL_Msk
’!RTC_CR_BKP_Pos (18U)
“!RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
”!RTC_CR_BKP RTC_CR_BKP_Msk
•!RTC_CR_SUB1H_Pos (17U)
–!RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
—!RTC_CR_SUB1H RTC_CR_SUB1H_Msk
˜!RTC_CR_ADD1H_Pos (16U)
™!RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
š!RTC_CR_ADD1H RTC_CR_ADD1H_Msk
›!RTC_CR_TSIE_Pos (15U)
œ!RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
!RTC_CR_TSIE RTC_CR_TSIE_Msk
ž!RTC_CR_WUTIE_Pos (14U)
Ÿ!RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
 !RTC_CR_WUTIE RTC_CR_WUTIE_Msk
¡!RTC_CR_ALRBIE_Pos (13U)
¢!RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
£!RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
¤!RTC_CR_ALRAIE_Pos (12U)
¥!RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
¦!RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
§!RTC_CR_TSE_Pos (11U)
¨!RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
©!RTC_CR_TSE RTC_CR_TSE_Msk
ª!RTC_CR_WUTE_Pos (10U)
«!RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
¬!RTC_CR_WUTE RTC_CR_WUTE_Msk
­!RTC_CR_ALRBE_Pos (9U)
®!RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
¯!RTC_CR_ALRBE RTC_CR_ALRBE_Msk
°!RTC_CR_ALRAE_Pos (8U)
±!RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
²!RTC_CR_ALRAE RTC_CR_ALRAE_Msk
³!RTC_CR_FMT_Pos (6U)
´!RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
µ!RTC_CR_FMT RTC_CR_FMT_Msk
¶!RTC_CR_BYPSHAD_Pos (5U)
·!RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
¸!RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
¹!RTC_CR_REFCKON_Pos (4U)
º!RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
»!RTC_CR_REFCKON RTC_CR_REFCKON_Msk
¼!RTC_CR_TSEDGE_Pos (3U)
½!RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
¾!RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
¿!RTC_CR_WUCKSEL_Pos (0U)
À!RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
Á!RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
Â!RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
Ã!RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
Ä!RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
Ç!RTC_ISR_RECALPF_Pos (16U)
È!RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
É!RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
Ê!RTC_ISR_TAMP3F_Pos (15U)
Ë!RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
Ì!RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
Í!RTC_ISR_TAMP2F_Pos (14U)
Î!RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
Ï!RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
Ð!RTC_ISR_TAMP1F_Pos (13U)
Ñ!RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
Ò!RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
Ó!RTC_ISR_TSOVF_Pos (12U)
Ô!RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
Õ!RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
Ö!RTC_ISR_TSF_Pos (11U)
×!RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
Ø!RTC_ISR_TSF RTC_ISR_TSF_Msk
Ù!RTC_ISR_WUTF_Pos (10U)
Ú!RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
Û!RTC_ISR_WUTF RTC_ISR_WUTF_Msk
Ü!RTC_ISR_ALRBF_Pos (9U)
Ý!RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
Þ!RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
ß!RTC_ISR_ALRAF_Pos (8U)
à!RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
á!RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
â!RTC_ISR_INIT_Pos (7U)
ã!RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
ä!RTC_ISR_INIT RTC_ISR_INIT_Msk
å!RTC_ISR_INITF_Pos (6U)
æ!RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
ç!RTC_ISR_INITF RTC_ISR_INITF_Msk
è!RTC_ISR_RSF_Pos (5U)
é!RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
ê!RTC_ISR_RSF RTC_ISR_RSF_Msk
ë!RTC_ISR_INITS_Pos (4U)
ì!RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
í!RTC_ISR_INITS RTC_ISR_INITS_Msk
î!RTC_ISR_SHPF_Pos (3U)
ï!RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
ð!RTC_ISR_SHPF RTC_ISR_SHPF_Msk
ñ!RTC_ISR_WUTWF_Pos (2U)
ò!RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
ó!RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
ô!RTC_ISR_ALRBWF_Pos (1U)
õ!RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
ö!RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
÷!RTC_ISR_ALRAWF_Pos (0U)
ø!RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
ù!RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
ü!RTC_PRER_PREDIV_A_Pos (16U)
ý!RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
þ!RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
ÿ!RTC_PRER_PREDIV_S_Pos (0U)
€"RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
"RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
„"RTC_WUTR_WUT_Pos (0U)
…"RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
†"RTC_WUTR_WUT RTC_WUTR_WUT_Msk
‰"RTC_ALRMAR_MSK4_Pos (31U)
Š"RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
‹"RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
Œ"RTC_ALRMAR_WDSEL_Pos (30U)
"RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
Ž"RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
"RTC_ALRMAR_DT_Pos (28U)
"RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
‘"RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
’"RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
“"RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
”"RTC_ALRMAR_DU_Pos (24U)
•"RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
–"RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
—"RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
˜"RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
™"RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
š"RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
›"RTC_ALRMAR_MSK3_Pos (23U)
œ"RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
"RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
ž"RTC_ALRMAR_PM_Pos (22U)
Ÿ"RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
 "RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
¡"RTC_ALRMAR_HT_Pos (20U)
¢"RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
£"RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
¤"RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
¥"RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
¦"RTC_ALRMAR_HU_Pos (16U)
§"RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
¨"RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
©"RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
ª"RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
«"RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
¬"RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
­"RTC_ALRMAR_MSK2_Pos (15U)
®"RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
¯"RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
°"RTC_ALRMAR_MNT_Pos (12U)
±"RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
²"RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
³"RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
´"RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
µ"RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
¶"RTC_ALRMAR_MNU_Pos (8U)
·"RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
¸"RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
¹"RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
º"RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
»"RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
¼"RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
½"RTC_ALRMAR_MSK1_Pos (7U)
¾"RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
¿"RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
À"RTC_ALRMAR_ST_Pos (4U)
Á"RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
Â"RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
Ã"RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
Ä"RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
Å"RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
Æ"RTC_ALRMAR_SU_Pos (0U)
Ç"RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
È"RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
É"RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
Ê"RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
Ë"RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
Ì"RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
Ï"RTC_ALRMBR_MSK4_Pos (31U)
Ð"RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
Ñ"RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
Ò"RTC_ALRMBR_WDSEL_Pos (30U)
Ó"RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
Ô"RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
Õ"RTC_ALRMBR_DT_Pos (28U)
Ö"RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
×"RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
Ø"RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
Ù"RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
Ú"RTC_ALRMBR_DU_Pos (24U)
Û"RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
Ü"RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
Ý"RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
Þ"RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
ß"RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
à"RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
á"RTC_ALRMBR_MSK3_Pos (23U)
â"RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
ã"RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
ä"RTC_ALRMBR_PM_Pos (22U)
å"RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
æ"RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
ç"RTC_ALRMBR_HT_Pos (20U)
è"RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
é"RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
ê"RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
ë"RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
ì"RTC_ALRMBR_HU_Pos (16U)
í"RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
î"RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
ï"RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
ð"RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
ñ"RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
ò"RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
ó"RTC_ALRMBR_MSK2_Pos (15U)
ô"RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
õ"RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
ö"RTC_ALRMBR_MNT_Pos (12U)
÷"RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
ø"RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
ù"RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
ú"RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
û"RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
ü"RTC_ALRMBR_MNU_Pos (8U)
ý"RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
þ"RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
ÿ"RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
€#RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
#RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
‚#RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
ƒ#RTC_ALRMBR_MSK1_Pos (7U)
„#RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
…#RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
†#RTC_ALRMBR_ST_Pos (4U)
‡#RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
ˆ#RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
‰#RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
Š#RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
‹#RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
Œ#RTC_ALRMBR_SU_Pos (0U)
#RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
Ž#RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
#RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
‘#RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
’#RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
•#RTC_WPR_KEY_Pos (0U)
–#RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
—#RTC_WPR_KEY RTC_WPR_KEY_Msk
š#RTC_SSR_SS_Pos (0U)
›#RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
œ#RTC_SSR_SS RTC_SSR_SS_Msk
Ÿ#RTC_SHIFTR_SUBFS_Pos (0U)
 #RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
¡#RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
¢#RTC_SHIFTR_ADD1S_Pos (31U)
£#RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
¤#RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
§#RTC_TSTR_PM_Pos (22U)
¨#RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
©#RTC_TSTR_PM RTC_TSTR_PM_Msk
ª#RTC_TSTR_HT_Pos (20U)
«#RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
¬#RTC_TSTR_HT RTC_TSTR_HT_Msk
­#RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
®#RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
¯#RTC_TSTR_HU_Pos (16U)
°#RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
±#RTC_TSTR_HU RTC_TSTR_HU_Msk
²#RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
³#RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
´#RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
µ#RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
¶#RTC_TSTR_MNT_Pos (12U)
·#RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
¸#RTC_TSTR_MNT RTC_TSTR_MNT_Msk
¹#RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
º#RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
»#RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
¼#RTC_TSTR_MNU_Pos (8U)
½#RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
¾#RTC_TSTR_MNU RTC_TSTR_MNU_Msk
¿#RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
À#RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
Á#RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
Â#RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
Ã#RTC_TSTR_ST_Pos (4U)
Ä#RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
Å#RTC_TSTR_ST RTC_TSTR_ST_Msk
Æ#RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
Ç#RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
È#RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
É#RTC_TSTR_SU_Pos (0U)
Ê#RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
Ë#RTC_TSTR_SU RTC_TSTR_SU_Msk
Ì#RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
Í#RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
Î#RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
Ï#RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
Ò#RTC_TSDR_WDU_Pos (13U)
Ó#RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
Ô#RTC_TSDR_WDU RTC_TSDR_WDU_Msk
Õ#RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
Ö#RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
×#RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
Ø#RTC_TSDR_MT_Pos (12U)
Ù#RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
Ú#RTC_TSDR_MT RTC_TSDR_MT_Msk
Û#RTC_TSDR_MU_Pos (8U)
Ü#RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
Ý#RTC_TSDR_MU RTC_TSDR_MU_Msk
Þ#RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
ß#RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
à#RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
á#RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
â#RTC_TSDR_DT_Pos (4U)
ã#RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
ä#RTC_TSDR_DT RTC_TSDR_DT_Msk
å#RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
æ#RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
ç#RTC_TSDR_DU_Pos (0U)
è#RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
é#RTC_TSDR_DU RTC_TSDR_DU_Msk
ê#RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
ë#RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
ì#RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
í#RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
ð#RTC_TSSSR_SS_Pos (0U)
ñ#RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
ò#RTC_TSSSR_SS RTC_TSSSR_SS_Msk
õ#RTC_CALR_CALP_Pos (15U)
ö#RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
÷#RTC_CALR_CALP RTC_CALR_CALP_Msk
ø#RTC_CALR_CALW8_Pos (14U)
ù#RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
ú#RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
û#RTC_CALR_CALW16_Pos (13U)
ü#RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
ý#RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
þ#RTC_CALR_CALM_Pos (0U)
ÿ#RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
€$RTC_CALR_CALM RTC_CALR_CALM_Msk
$RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
‚$RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
ƒ$RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
„$RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
…$RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
†$RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
‡$RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
ˆ$RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
‰$RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
Œ$RTC_CAL_CALP RTC_CALR_CALP
$RTC_CAL_CALW8 RTC_CALR_CALW8
Ž$RTC_CAL_CALW16 RTC_CALR_CALW16
$RTC_CAL_CALM RTC_CALR_CALM
$RTC_CAL_CALM_0 RTC_CALR_CALM_0
‘$RTC_CAL_CALM_1 RTC_CALR_CALM_1
’$RTC_CAL_CALM_2 RTC_CALR_CALM_2
“$RTC_CAL_CALM_3 RTC_CALR_CALM_3
”$RTC_CAL_CALM_4 RTC_CALR_CALM_4
•$RTC_CAL_CALM_5 RTC_CALR_CALM_5
–$RTC_CAL_CALM_6 RTC_CALR_CALM_6
—$RTC_CAL_CALM_7 RTC_CALR_CALM_7
˜$RTC_CAL_CALM_8 RTC_CALR_CALM_8
›$RTC_TAMPCR_TAMP3MF_Pos (24U)
œ$RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
$RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
ž$RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
Ÿ$RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
 $RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
¡$RTC_TAMPCR_TAMP3IE_Pos (22U)
¢$RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
£$RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
¤$RTC_TAMPCR_TAMP2MF_Pos (21U)
¥$RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
¦$RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
§$RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
¨$RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
©$RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
ª$RTC_TAMPCR_TAMP2IE_Pos (19U)
«$RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
¬$RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
­$RTC_TAMPCR_TAMP1MF_Pos (18U)
®$RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
¯$RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
°$RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
±$RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
²$RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
³$RTC_TAMPCR_TAMP1IE_Pos (16U)
´$RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
µ$RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
¶$RTC_TAMPCR_TAMPPUDIS_Pos (15U)
·$RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
¸$RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
¹$RTC_TAMPCR_TAMPPRCH_Pos (13U)
º$RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
»$RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
¼$RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
½$RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
¾$RTC_TAMPCR_TAMPFLT_Pos (11U)
¿$RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
À$RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
Á$RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
Â$RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
Ã$RTC_TAMPCR_TAMPFREQ_Pos (8U)
Ä$RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
Å$RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
Æ$RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
Ç$RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
È$RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
É$RTC_TAMPCR_TAMPTS_Pos (7U)
Ê$RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
Ë$RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
Ì$RTC_TAMPCR_TAMP3TRG_Pos (6U)
Í$RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
Î$RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
Ï$RTC_TAMPCR_TAMP3E_Pos (5U)
Ð$RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
Ñ$RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
Ò$RTC_TAMPCR_TAMP2TRG_Pos (4U)
Ó$RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
Ô$RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
Õ$RTC_TAMPCR_TAMP2E_Pos (3U)
Ö$RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
×$RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
Ø$RTC_TAMPCR_TAMPIE_Pos (2U)
Ù$RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
Ú$RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
Û$RTC_TAMPCR_TAMP1TRG_Pos (1U)
Ü$RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
Ý$RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
Þ$RTC_TAMPCR_TAMP1E_Pos (0U)
ß$RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
à$RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
ã$RTC_ALRMASSR_MASKSS_Pos (24U)
ä$RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
å$RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
æ$RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
ç$RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
è$RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
é$RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
ê$RTC_ALRMASSR_SS_Pos (0U)
ë$RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
ì$RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
ï$RTC_ALRMBSSR_MASKSS_Pos (24U)
ð$RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
ñ$RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
ò$RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
ó$RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
ô$RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
õ$RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
ö$RTC_ALRMBSSR_SS_Pos (0U)
÷$RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
ø$RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
û$RTC_OR_OUT_RMP_Pos (1U)
ü$RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
ý$RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
þ$RTC_OR_ALARMOUTTYPE_Pos (0U)
ÿ$RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
€%RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
ƒ%RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
†%RTC_BKP0R_Pos (0U)
‡%RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
ˆ%RTC_BKP0R RTC_BKP0R_Msk
‹%RTC_BKP1R_Pos (0U)
Œ%RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
%RTC_BKP1R RTC_BKP1R_Msk
%RTC_BKP2R_Pos (0U)
‘%RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
’%RTC_BKP2R RTC_BKP2R_Msk
•%RTC_BKP3R_Pos (0U)
–%RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
—%RTC_BKP3R RTC_BKP3R_Msk
š%RTC_BKP4R_Pos (0U)
›%RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
œ%RTC_BKP4R RTC_BKP4R_Msk
Ÿ%RTC_BKP_NUMBER (0x00000005U)
ª%SPI_I2S_SUPPORT 
­%SPI_CR1_CPHA_Pos (0U)
®%SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
¯%SPI_CR1_CPHA SPI_CR1_CPHA_Msk
°%SPI_CR1_CPOL_Pos (1U)
±%SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
²%SPI_CR1_CPOL SPI_CR1_CPOL_Msk
³%SPI_CR1_MSTR_Pos (2U)
´%SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
µ%SPI_CR1_MSTR SPI_CR1_MSTR_Msk
¶%SPI_CR1_BR_Pos (3U)
·%SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
¸%SPI_CR1_BR SPI_CR1_BR_Msk
¹%SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
º%SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
»%SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
¼%SPI_CR1_SPE_Pos (6U)
½%SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
¾%SPI_CR1_SPE SPI_CR1_SPE_Msk
¿%SPI_CR1_LSBFIRST_Pos (7U)
À%SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
Á%SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
Â%SPI_CR1_SSI_Pos (8U)
Ã%SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
Ä%SPI_CR1_SSI SPI_CR1_SSI_Msk
Å%SPI_CR1_SSM_Pos (9U)
Æ%SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
Ç%SPI_CR1_SSM SPI_CR1_SSM_Msk
È%SPI_CR1_RXONLY_Pos (10U)
É%SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
Ê%SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
Ë%SPI_CR1_DFF_Pos (11U)
Ì%SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
Í%SPI_CR1_DFF SPI_CR1_DFF_Msk
Î%SPI_CR1_CRCNEXT_Pos (12U)
Ï%SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
Ð%SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
Ñ%SPI_CR1_CRCEN_Pos (13U)
Ò%SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
Ó%SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
Ô%SPI_CR1_BIDIOE_Pos (14U)
Õ%SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
Ö%SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
×%SPI_CR1_BIDIMODE_Pos (15U)
Ø%SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
Ù%SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
Ü%SPI_CR2_RXDMAEN_Pos (0U)
Ý%SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
Þ%SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
ß%SPI_CR2_TXDMAEN_Pos (1U)
à%SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
á%SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
â%SPI_CR2_SSOE_Pos (2U)
ã%SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
ä%SPI_CR2_SSOE SPI_CR2_SSOE_Msk
å%SPI_CR2_FRF_Pos (4U)
æ%SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
ç%SPI_CR2_FRF SPI_CR2_FRF_Msk
è%SPI_CR2_ERRIE_Pos (5U)
é%SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
ê%SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
ë%SPI_CR2_RXNEIE_Pos (6U)
ì%SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
í%SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
î%SPI_CR2_TXEIE_Pos (7U)
ï%SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
ð%SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
ó%SPI_SR_RXNE_Pos (0U)
ô%SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
õ%SPI_SR_RXNE SPI_SR_RXNE_Msk
ö%SPI_SR_TXE_Pos (1U)
÷%SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
ø%SPI_SR_TXE SPI_SR_TXE_Msk
ù%SPI_SR_CHSIDE_Pos (2U)
ú%SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
û%SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
ü%SPI_SR_UDR_Pos (3U)
ý%SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
þ%SPI_SR_UDR SPI_SR_UDR_Msk
ÿ%SPI_SR_CRCERR_Pos (4U)
€&SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
&SPI_SR_CRCERR SPI_SR_CRCERR_Msk
‚&SPI_SR_MODF_Pos (5U)
ƒ&SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
„&SPI_SR_MODF SPI_SR_MODF_Msk
…&SPI_SR_OVR_Pos (6U)
†&SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
‡&SPI_SR_OVR SPI_SR_OVR_Msk
ˆ&SPI_SR_BSY_Pos (7U)
‰&SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
Š&SPI_SR_BSY SPI_SR_BSY_Msk
‹&SPI_SR_FRE_Pos (8U)
Œ&SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
&SPI_SR_FRE SPI_SR_FRE_Msk
&SPI_DR_DR_Pos (0U)
‘&SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
’&SPI_DR_DR SPI_DR_DR_Msk
•&SPI_CRCPR_CRCPOLY_Pos (0U)
–&SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
—&SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
š&SPI_RXCRCR_RXCRC_Pos (0U)
›&SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
œ&SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
Ÿ&SPI_TXCRCR_TXCRC_Pos (0U)
 &SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
¡&SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
¤&SPI_I2SCFGR_CHLEN_Pos (0U)
¥&SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
¦&SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
§&SPI_I2SCFGR_DATLEN_Pos (1U)
¨&SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
©&SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
ª&SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
«&SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
¬&SPI_I2SCFGR_CKPOL_Pos (3U)
­&SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
®&SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
¯&SPI_I2SCFGR_I2SSTD_Pos (4U)
°&SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
±&SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
²&SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
³&SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
´&SPI_I2SCFGR_PCMSYNC_Pos (7U)
µ&SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
¶&SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
·&SPI_I2SCFGR_I2SCFG_Pos (8U)
¸&SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
¹&SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
º&SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
»&SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
¼&SPI_I2SCFGR_I2SE_Pos (10U)
½&SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
¾&SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
¿&SPI_I2SCFGR_I2SMOD_Pos (11U)
À&SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
Á&SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
Â&SPI_I2SCFGR_ASTRTEN_Pos (12U)
Ã&SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
Ä&SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
Æ&SPI_I2SPR_I2SDIV_Pos (0U)
Ç&SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
È&SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
É&SPI_I2SPR_ODD_Pos (8U)
Ê&SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
Ë&SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
Ì&SPI_I2SPR_MCKOE_Pos (9U)
Í&SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
Î&SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
Ö&SYSCFG_CFGR1_MEM_MODE_Pos (0U)
×&SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)
Ø&SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk
Ù&SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)
Ú&SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)
Û&SYSCFG_CFGR1_UFB_Pos (3U)
Ü&SYSCFG_CFGR1_UFB_Msk (0x1UL << SYSCFG_CFGR1_UFB_Pos)
Ý&SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk
Þ&SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
ß&SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos)
à&SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk
á&SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos)
â&SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos)
å&SYSCFG_CFGR2_FWDISEN_Pos (0U)
æ&SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos)
ç&SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk
è&SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
é&SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos)
ê&SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk
ë&SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
ì&SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos)
í&SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk
î&SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
ï&SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos)
ð&SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk
ñ&SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
ò&SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos)
ó&SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk
ô&SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
õ&SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos)
ö&SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk
÷&SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
ø&SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos)
ù&SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk
ú&SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
û&SYSCFG_CFGR2_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos)
ü&SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk
ÿ&SYSCFG_EXTICR1_EXTI0_Pos (0U)
€'SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
'SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
‚'SYSCFG_EXTICR1_EXTI1_Pos (4U)
ƒ'SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
„'SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
…'SYSCFG_EXTICR1_EXTI2_Pos (8U)
†'SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
‡'SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
ˆ'SYSCFG_EXTICR1_EXTI3_Pos (12U)
‰'SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
Š'SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
'SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)
'SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
‘'SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
’'SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
“'SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
”'SYSCFG_EXTICR1_EXTI0_PH (0x00000005U)
™'SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)
š'SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
›'SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
œ'SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
'SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
ž'SYSCFG_EXTICR1_EXTI1_PH (0x00000050U)
£'SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)
¤'SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
¥'SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
¦'SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
§'SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
¬'SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)
­'SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
®'SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
¯'SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
°'SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
³'SYSCFG_EXTICR2_EXTI4_Pos (0U)
´'SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
µ'SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
¶'SYSCFG_EXTICR2_EXTI5_Pos (4U)
·'SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
¸'SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
¹'SYSCFG_EXTICR2_EXTI6_Pos (8U)
º'SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
»'SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
¼'SYSCFG_EXTICR2_EXTI7_Pos (12U)
½'SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
¾'SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
Ã'SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)
Ä'SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
Å'SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
Æ'SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
Ç'SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
Ì'SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)
Í'SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
Î'SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
Ï'SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
Ð'SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
Õ'SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)
Ö'SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
×'SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
Ø'SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
Ù'SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
Þ'SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)
ß'SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
à'SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
á'SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
â'SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
å'SYSCFG_EXTICR3_EXTI8_Pos (0U)
æ'SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
ç'SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
è'SYSCFG_EXTICR3_EXTI9_Pos (4U)
é'SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
ê'SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
ë'SYSCFG_EXTICR3_EXTI10_Pos (8U)
ì'SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
í'SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
î'SYSCFG_EXTICR3_EXTI11_Pos (12U)
ï'SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
ð'SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
õ'SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)
ö'SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
÷'SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
ø'SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
ù'SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
þ'SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)
ÿ'SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
€(SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
(SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
‚(SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
ƒ(SYSCFG_EXTICR3_EXTI9_PH (0x00000050U)
ˆ(SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)
‰(SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
Š(SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
‹(SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
Œ(SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
(SYSCFG_EXTICR3_EXTI10_PH (0x00000500U)
’(SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)
“(SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
”(SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
•(SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
–(SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
™(SYSCFG_EXTICR4_EXTI12_Pos (0U)
š(SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
›(SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
œ(SYSCFG_EXTICR4_EXTI13_Pos (4U)
(SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
ž(SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
Ÿ(SYSCFG_EXTICR4_EXTI14_Pos (8U)
 (SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
¡(SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
¢(SYSCFG_EXTICR4_EXTI15_Pos (12U)
£(SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
¤(SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
©(SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)
ª(SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
«(SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
¬(SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
­(SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
²(SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)
³(SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
´(SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
µ(SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
¶(SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
»(SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)
¼(SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
½(SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
¾(SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
¿(SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
Ä(SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)
Å(SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
Æ(SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
Ç(SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
È(SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
Ì(SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
Í(SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos)
Î(SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk
Ï(SYSCFG_CFGR3_VREF_OUT_Pos (4U)
Ð(SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos)
Ñ(SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk
Ò(SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos)
Ó(SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos)
Ô(SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
Õ(SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos)
Ö(SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk
×(SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
Ø(SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos)
Ù(SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk
Ú(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
Û(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos)
Ü(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk
Ý(SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
Þ(SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos)
ß(SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk
à(SYSCFG_CFGR3_REF_LOCK_Pos (31U)
á(SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos)
â(SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk
æ(SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
ç(SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
è(SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
é(SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
ê(SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
ë(SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
ì(SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
ö(TIM_TIM2_REMAP_HSI_SUPPORT 
÷(TIM_TIM2_REMAP_HSI48_SUPPORT 
ú(TIM_CR1_CEN_Pos (0U)
û(TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
ü(TIM_CR1_CEN TIM_CR1_CEN_Msk
ý(TIM_CR1_UDIS_Pos (1U)
þ(TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
ÿ(TIM_CR1_UDIS TIM_CR1_UDIS_Msk
€)TIM_CR1_URS_Pos (2U)
)TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
‚)TIM_CR1_URS TIM_CR1_URS_Msk
ƒ)TIM_CR1_OPM_Pos (3U)
„)TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
…)TIM_CR1_OPM TIM_CR1_OPM_Msk
†)TIM_CR1_DIR_Pos (4U)
‡)TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
ˆ)TIM_CR1_DIR TIM_CR1_DIR_Msk
Š)TIM_CR1_CMS_Pos (5U)
‹)TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
Œ)TIM_CR1_CMS TIM_CR1_CMS_Msk
)TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
Ž)TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
)TIM_CR1_ARPE_Pos (7U)
‘)TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
’)TIM_CR1_ARPE TIM_CR1_ARPE_Msk
”)TIM_CR1_CKD_Pos (8U)
•)TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
–)TIM_CR1_CKD TIM_CR1_CKD_Msk
—)TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
˜)TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
›)TIM_CR2_CCDS_Pos (3U)
œ)TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
)TIM_CR2_CCDS TIM_CR2_CCDS_Msk
Ÿ)TIM_CR2_MMS_Pos (4U)
 )TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
¡)TIM_CR2_MMS TIM_CR2_MMS_Msk
¢)TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
£)TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
¤)TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
¦)TIM_CR2_TI1S_Pos (7U)
§)TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
¨)TIM_CR2_TI1S TIM_CR2_TI1S_Msk
«)TIM_SMCR_SMS_Pos (0U)
¬)TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
­)TIM_SMCR_SMS TIM_SMCR_SMS_Msk
®)TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
¯)TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
°)TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
²)TIM_SMCR_TS_Pos (4U)
³)TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
´)TIM_SMCR_TS TIM_SMCR_TS_Msk
µ)TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
¶)TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
·)TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
¹)TIM_SMCR_MSM_Pos (7U)
º)TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
»)TIM_SMCR_MSM TIM_SMCR_MSM_Msk
½)TIM_SMCR_ETF_Pos (8U)
¾)TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
¿)TIM_SMCR_ETF TIM_SMCR_ETF_Msk
À)TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
Á)TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
Â)TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
Ã)TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
Å)TIM_SMCR_ETPS_Pos (12U)
Æ)TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
Ç)TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
È)TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
É)TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
Ë)TIM_SMCR_ECE_Pos (14U)
Ì)TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
Í)TIM_SMCR_ECE TIM_SMCR_ECE_Msk
Î)TIM_SMCR_ETP_Pos (15U)
Ï)TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
Ð)TIM_SMCR_ETP TIM_SMCR_ETP_Msk
Ó)TIM_DIER_UIE_Pos (0U)
Ô)TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
Õ)TIM_DIER_UIE TIM_DIER_UIE_Msk
Ö)TIM_DIER_CC1IE_Pos (1U)
×)TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
Ø)TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
Ù)TIM_DIER_CC2IE_Pos (2U)
Ú)TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
Û)TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
Ü)TIM_DIER_CC3IE_Pos (3U)
Ý)TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
Þ)TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
ß)TIM_DIER_CC4IE_Pos (4U)
à)TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
á)TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
â)TIM_DIER_TIE_Pos (6U)
ã)TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
ä)TIM_DIER_TIE TIM_DIER_TIE_Msk
å)TIM_DIER_UDE_Pos (8U)
æ)TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
ç)TIM_DIER_UDE TIM_DIER_UDE_Msk
è)TIM_DIER_CC1DE_Pos (9U)
é)TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
ê)TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
ë)TIM_DIER_CC2DE_Pos (10U)
ì)TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
í)TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
î)TIM_DIER_CC3DE_Pos (11U)
ï)TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
ð)TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
ñ)TIM_DIER_CC4DE_Pos (12U)
ò)TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
ó)TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
ô)TIM_DIER_TDE_Pos (14U)
õ)TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
ö)TIM_DIER_TDE TIM_DIER_TDE_Msk
ù)TIM_SR_UIF_Pos (0U)
ú)TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
û)TIM_SR_UIF TIM_SR_UIF_Msk
ü)TIM_SR_CC1IF_Pos (1U)
ý)TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
þ)TIM_SR_CC1IF TIM_SR_CC1IF_Msk
ÿ)TIM_SR_CC2IF_Pos (2U)
€*TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
*TIM_SR_CC2IF TIM_SR_CC2IF_Msk
‚*TIM_SR_CC3IF_Pos (3U)
ƒ*TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
„*TIM_SR_CC3IF TIM_SR_CC3IF_Msk
…*TIM_SR_CC4IF_Pos (4U)
†*TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
‡*TIM_SR_CC4IF TIM_SR_CC4IF_Msk
ˆ*TIM_SR_TIF_Pos (6U)
‰*TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
Š*TIM_SR_TIF TIM_SR_TIF_Msk
‹*TIM_SR_CC1OF_Pos (9U)
Œ*TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
*TIM_SR_CC1OF TIM_SR_CC1OF_Msk
Ž*TIM_SR_CC2OF_Pos (10U)
*TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
*TIM_SR_CC2OF TIM_SR_CC2OF_Msk
‘*TIM_SR_CC3OF_Pos (11U)
’*TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
“*TIM_SR_CC3OF TIM_SR_CC3OF_Msk
”*TIM_SR_CC4OF_Pos (12U)
•*TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
–*TIM_SR_CC4OF TIM_SR_CC4OF_Msk
™*TIM_EGR_UG_Pos (0U)
š*TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
›*TIM_EGR_UG TIM_EGR_UG_Msk
œ*TIM_EGR_CC1G_Pos (1U)
*TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
ž*TIM_EGR_CC1G TIM_EGR_CC1G_Msk
Ÿ*TIM_EGR_CC2G_Pos (2U)
 *TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
¡*TIM_EGR_CC2G TIM_EGR_CC2G_Msk
¢*TIM_EGR_CC3G_Pos (3U)
£*TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
¤*TIM_EGR_CC3G TIM_EGR_CC3G_Msk
¥*TIM_EGR_CC4G_Pos (4U)
¦*TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
§*TIM_EGR_CC4G TIM_EGR_CC4G_Msk
¨*TIM_EGR_TG_Pos (6U)
©*TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
ª*TIM_EGR_TG TIM_EGR_TG_Msk
­*TIM_CCMR1_CC1S_Pos (0U)
®*TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
¯*TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
°*TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
±*TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
³*TIM_CCMR1_OC1FE_Pos (2U)
´*TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
µ*TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
¶*TIM_CCMR1_OC1PE_Pos (3U)
·*TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
¸*TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
º*TIM_CCMR1_OC1M_Pos (4U)
»*TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
¼*TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
½*TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
¾*TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
¿*TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
Á*TIM_CCMR1_OC1CE_Pos (7U)
Â*TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
Ã*TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
Å*TIM_CCMR1_CC2S_Pos (8U)
Æ*TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
Ç*TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
È*TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
É*TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
Ë*TIM_CCMR1_OC2FE_Pos (10U)
Ì*TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
Í*TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
Î*TIM_CCMR1_OC2PE_Pos (11U)
Ï*TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
Ð*TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
Ò*TIM_CCMR1_OC2M_Pos (12U)
Ó*TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
Ô*TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
Õ*TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
Ö*TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
×*TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
Ù*TIM_CCMR1_OC2CE_Pos (15U)
Ú*TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
Û*TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
ß*TIM_CCMR1_IC1PSC_Pos (2U)
à*TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
á*TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
â*TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
ã*TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
å*TIM_CCMR1_IC1F_Pos (4U)
æ*TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
ç*TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
è*TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
é*TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
ê*TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
ë*TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
í*TIM_CCMR1_IC2PSC_Pos (10U)
î*TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
ï*TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
ð*TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
ñ*TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
ó*TIM_CCMR1_IC2F_Pos (12U)
ô*TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
õ*TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
ö*TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
÷*TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
ø*TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
ù*TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
ü*TIM_CCMR2_CC3S_Pos (0U)
ý*TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
þ*TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
ÿ*TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
€+TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
‚+TIM_CCMR2_OC3FE_Pos (2U)
ƒ+TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
„+TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
…+TIM_CCMR2_OC3PE_Pos (3U)
†+TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
‡+TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
‰+TIM_CCMR2_OC3M_Pos (4U)
Š+TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
‹+TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
Œ+TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
+TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
Ž+TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
+TIM_CCMR2_OC3CE_Pos (7U)
‘+TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
’+TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
”+TIM_CCMR2_CC4S_Pos (8U)
•+TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
–+TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
—+TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
˜+TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
š+TIM_CCMR2_OC4FE_Pos (10U)
›+TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
œ+TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
+TIM_CCMR2_OC4PE_Pos (11U)
ž+TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
Ÿ+TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
¡+TIM_CCMR2_OC4M_Pos (12U)
¢+TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
£+TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
¤+TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
¥+TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
¦+TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
¨+TIM_CCMR2_OC4CE_Pos (15U)
©+TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
ª+TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
®+TIM_CCMR2_IC3PSC_Pos (2U)
¯+TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
°+TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
±+TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
²+TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
´+TIM_CCMR2_IC3F_Pos (4U)
µ+TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
¶+TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
·+TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
¸+TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
¹+TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
º+TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
¼+TIM_CCMR2_IC4PSC_Pos (10U)
½+TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
¾+TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
¿+TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
À+TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
Â+TIM_CCMR2_IC4F_Pos (12U)
Ã+TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
Ä+TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
Å+TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
Æ+TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
Ç+TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
È+TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
Ë+TIM_CCER_CC1E_Pos (0U)
Ì+TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
Í+TIM_CCER_CC1E TIM_CCER_CC1E_Msk
Î+TIM_CCER_CC1P_Pos (1U)
Ï+TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
Ð+TIM_CCER_CC1P TIM_CCER_CC1P_Msk
Ñ+TIM_CCER_CC1NP_Pos (3U)
Ò+TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
Ó+TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
Ô+TIM_CCER_CC2E_Pos (4U)
Õ+TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
Ö+TIM_CCER_CC2E TIM_CCER_CC2E_Msk
×+TIM_CCER_CC2P_Pos (5U)
Ø+TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
Ù+TIM_CCER_CC2P TIM_CCER_CC2P_Msk
Ú+TIM_CCER_CC2NP_Pos (7U)
Û+TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
Ü+TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
Ý+TIM_CCER_CC3E_Pos (8U)
Þ+TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
ß+TIM_CCER_CC3E TIM_CCER_CC3E_Msk
à+TIM_CCER_CC3P_Pos (9U)
á+TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
â+TIM_CCER_CC3P TIM_CCER_CC3P_Msk
ã+TIM_CCER_CC3NP_Pos (11U)
ä+TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
å+TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
æ+TIM_CCER_CC4E_Pos (12U)
ç+TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
è+TIM_CCER_CC4E TIM_CCER_CC4E_Msk
é+TIM_CCER_CC4P_Pos (13U)
ê+TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
ë+TIM_CCER_CC4P TIM_CCER_CC4P_Msk
ì+TIM_CCER_CC4NP_Pos (15U)
í+TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
î+TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
ñ+TIM_CNT_CNT_Pos (0U)
ò+TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos)
ó+TIM_CNT_CNT TIM_CNT_CNT_Msk
ö+TIM_PSC_PSC_Pos (0U)
÷+TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
ø+TIM_PSC_PSC TIM_PSC_PSC_Msk
û+TIM_ARR_ARR_Pos (0U)
ü+TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos)
ý+TIM_ARR_ARR TIM_ARR_ARR_Msk
€,TIM_CCR1_CCR1_Pos (0U)
,TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
‚,TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
…,TIM_CCR2_CCR2_Pos (0U)
†,TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
‡,TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
Š,TIM_CCR3_CCR3_Pos (0U)
‹,TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
Œ,TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
,TIM_CCR4_CCR4_Pos (0U)
,TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
‘,TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
”,TIM_DCR_DBA_Pos (0U)
•,TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
–,TIM_DCR_DBA TIM_DCR_DBA_Msk
—,TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
˜,TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
™,TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
š,TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
›,TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
,TIM_DCR_DBL_Pos (8U)
ž,TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
Ÿ,TIM_DCR_DBL TIM_DCR_DBL_Msk
 ,TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
¡,TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
¢,TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
£,TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
¤,TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
§,TIM_DMAR_DMAB_Pos (0U)
¨,TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
©,TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
¬,TIM2_OR_ETR_RMP_Pos (0U)
­,TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos)
®,TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk
¯,TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos)
°,TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos)
±,TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos)
²,TIM2_OR_TI4_RMP_Pos (3U)
³,TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos)
´,TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk
µ,TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos)
¶,TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos)
¸,TIM21_OR_ETR_RMP_Pos (0U)
¹,TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos)
º,TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk
»,TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos)
¼,TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos)
½,TIM21_OR_TI1_RMP_Pos (2U)
¾,TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos)
¿,TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk
À,TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos)
Á,TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos)
Â,TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos)
Ã,TIM21_OR_TI2_RMP_Pos (5U)
Ä,TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos)
Å,TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk
Ç,TIM22_OR_ETR_RMP_Pos (0U)
È,TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos)
É,TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk
Ê,TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos)
Ë,TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos)
Ì,TIM22_OR_TI1_RMP_Pos (2U)
Í,TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos)
Î,TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk
Ï,TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos)
Ð,TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos)
Ò,TIM3_OR_ETR_RMP_Pos (0U)
Ó,TIM3_OR_ETR_RMP_Msk (0x3UL << TIM3_OR_ETR_RMP_Pos)
Ô,TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk
Õ,TIM3_OR_ETR_RMP_0 (0x1UL << TIM3_OR_ETR_RMP_Pos)
Ö,TIM3_OR_ETR_RMP_1 (0x2UL << TIM3_OR_ETR_RMP_Pos)
×,TIM3_OR_TI1_RMP_Pos (2U)
Ø,TIM3_OR_TI1_RMP_Msk (0x1UL << TIM3_OR_TI1_RMP_Pos)
Ù,TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk
Ú,TIM3_OR_TI2_RMP_Pos (3U)
Û,TIM3_OR_TI2_RMP_Msk (0x1UL << TIM3_OR_TI2_RMP_Pos)
Ü,TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk
Ý,TIM3_OR_TI4_RMP_Pos (4U)
Þ,TIM3_OR_TI4_RMP_Msk (0x1UL << TIM3_OR_TI4_RMP_Pos)
ß,TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk
î,USART_CR1_UE_Pos (0U)
ï,USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
ð,USART_CR1_UE USART_CR1_UE_Msk
ñ,USART_CR1_UESM_Pos (1U)
ò,USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
ó,USART_CR1_UESM USART_CR1_UESM_Msk
ô,USART_CR1_RE_Pos (2U)
õ,USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
ö,USART_CR1_RE USART_CR1_RE_Msk
÷,USART_CR1_TE_Pos (3U)
ø,USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
ù,USART_CR1_TE USART_CR1_TE_Msk
ú,USART_CR1_IDLEIE_Pos (4U)
û,USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
ü,USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
ý,USART_CR1_RXNEIE_Pos (5U)
þ,USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
ÿ,USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
€-USART_CR1_TCIE_Pos (6U)
-USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
‚-USART_CR1_TCIE USART_CR1_TCIE_Msk
ƒ-USART_CR1_TXEIE_Pos (7U)
„-USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
…-USART_CR1_TXEIE USART_CR1_TXEIE_Msk
†-USART_CR1_PEIE_Pos (8U)
‡-USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
ˆ-USART_CR1_PEIE USART_CR1_PEIE_Msk
‰-USART_CR1_PS_Pos (9U)
Š-USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
‹-USART_CR1_PS USART_CR1_PS_Msk
Œ-USART_CR1_PCE_Pos (10U)
-USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
Ž-USART_CR1_PCE USART_CR1_PCE_Msk
-USART_CR1_WAKE_Pos (11U)
-USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
‘-USART_CR1_WAKE USART_CR1_WAKE_Msk
’-USART_CR1_M_Pos (12U)
“-USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
”-USART_CR1_M USART_CR1_M_Msk
•-USART_CR1_M0_Pos (12U)
–-USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
—-USART_CR1_M0 USART_CR1_M0_Msk
˜-USART_CR1_MME_Pos (13U)
™-USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
š-USART_CR1_MME USART_CR1_MME_Msk
›-USART_CR1_CMIE_Pos (14U)
œ-USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
-USART_CR1_CMIE USART_CR1_CMIE_Msk
ž-USART_CR1_OVER8_Pos (15U)
Ÿ-USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
 -USART_CR1_OVER8 USART_CR1_OVER8_Msk
¡-USART_CR1_DEDT_Pos (16U)
¢-USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
£-USART_CR1_DEDT USART_CR1_DEDT_Msk
¤-USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
¥-USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
¦-USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
§-USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
¨-USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
©-USART_CR1_DEAT_Pos (21U)
ª-USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
«-USART_CR1_DEAT USART_CR1_DEAT_Msk
¬-USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
­-USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
®-USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
¯-USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
°-USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
±-USART_CR1_RTOIE_Pos (26U)
²-USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
³-USART_CR1_RTOIE USART_CR1_RTOIE_Msk
´-USART_CR1_EOBIE_Pos (27U)
µ-USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
¶-USART_CR1_EOBIE USART_CR1_EOBIE_Msk
·-USART_CR1_M1_Pos (28U)
¸-USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
¹-USART_CR1_M1 USART_CR1_M1_Msk
»-USART_CR2_ADDM7_Pos (4U)
¼-USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
½-USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
¾-USART_CR2_LBDL_Pos (5U)
¿-USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
À-USART_CR2_LBDL USART_CR2_LBDL_Msk
Á-USART_CR2_LBDIE_Pos (6U)
Â-USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
Ã-USART_CR2_LBDIE USART_CR2_LBDIE_Msk
Ä-USART_CR2_LBCL_Pos (8U)
Å-USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
Æ-USART_CR2_LBCL USART_CR2_LBCL_Msk
Ç-USART_CR2_CPHA_Pos (9U)
È-USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
É-USART_CR2_CPHA USART_CR2_CPHA_Msk
Ê-USART_CR2_CPOL_Pos (10U)
Ë-USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
Ì-USART_CR2_CPOL USART_CR2_CPOL_Msk
Í-USART_CR2_CLKEN_Pos (11U)
Î-USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
Ï-USART_CR2_CLKEN USART_CR2_CLKEN_Msk
Ð-USART_CR2_STOP_Pos (12U)
Ñ-USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
Ò-USART_CR2_STOP USART_CR2_STOP_Msk
Ó-USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
Ô-USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
Õ-USART_CR2_LINEN_Pos (14U)
Ö-USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
×-USART_CR2_LINEN USART_CR2_LINEN_Msk
Ø-USART_CR2_SWAP_Pos (15U)
Ù-USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
Ú-USART_CR2_SWAP USART_CR2_SWAP_Msk
Û-USART_CR2_RXINV_Pos (16U)
Ü-USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
Ý-USART_CR2_RXINV USART_CR2_RXINV_Msk
Þ-USART_CR2_TXINV_Pos (17U)
ß-USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
à-USART_CR2_TXINV USART_CR2_TXINV_Msk
á-USART_CR2_DATAINV_Pos (18U)
â-USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
ã-USART_CR2_DATAINV USART_CR2_DATAINV_Msk
ä-USART_CR2_MSBFIRST_Pos (19U)
å-USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
æ-USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
ç-USART_CR2_ABREN_Pos (20U)
è-USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
é-USART_CR2_ABREN USART_CR2_ABREN_Msk
ê-USART_CR2_ABRMODE_Pos (21U)
ë-USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
ì-USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
í-USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
î-USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
ï-USART_CR2_RTOEN_Pos (23U)
ð-USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
ñ-USART_CR2_RTOEN USART_CR2_RTOEN_Msk
ò-USART_CR2_ADD_Pos (24U)
ó-USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
ô-USART_CR2_ADD USART_CR2_ADD_Msk
÷-USART_CR3_EIE_Pos (0U)
ø-USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
ù-USART_CR3_EIE USART_CR3_EIE_Msk
ú-USART_CR3_IREN_Pos (1U)
û-USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
ü-USART_CR3_IREN USART_CR3_IREN_Msk
ý-USART_CR3_IRLP_Pos (2U)
þ-USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
ÿ-USART_CR3_IRLP USART_CR3_IRLP_Msk
€.USART_CR3_HDSEL_Pos (3U)
.USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
‚.USART_CR3_HDSEL USART_CR3_HDSEL_Msk
ƒ.USART_CR3_NACK_Pos (4U)
„.USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
….USART_CR3_NACK USART_CR3_NACK_Msk
†.USART_CR3_SCEN_Pos (5U)
‡.USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
ˆ.USART_CR3_SCEN USART_CR3_SCEN_Msk
‰.USART_CR3_DMAR_Pos (6U)
Š.USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
‹.USART_CR3_DMAR USART_CR3_DMAR_Msk
Œ.USART_CR3_DMAT_Pos (7U)
.USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
Ž.USART_CR3_DMAT USART_CR3_DMAT_Msk
.USART_CR3_RTSE_Pos (8U)
.USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
‘.USART_CR3_RTSE USART_CR3_RTSE_Msk
’.USART_CR3_CTSE_Pos (9U)
“.USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
”.USART_CR3_CTSE USART_CR3_CTSE_Msk
•.USART_CR3_CTSIE_Pos (10U)
–.USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
—.USART_CR3_CTSIE USART_CR3_CTSIE_Msk
˜.USART_CR3_ONEBIT_Pos (11U)
™.USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
š.USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
›.USART_CR3_OVRDIS_Pos (12U)
œ.USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
.USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
ž.USART_CR3_DDRE_Pos (13U)
Ÿ.USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
 .USART_CR3_DDRE USART_CR3_DDRE_Msk
¡.USART_CR3_DEM_Pos (14U)
¢.USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
£.USART_CR3_DEM USART_CR3_DEM_Msk
¤.USART_CR3_DEP_Pos (15U)
¥.USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
¦.USART_CR3_DEP USART_CR3_DEP_Msk
§.USART_CR3_SCARCNT_Pos (17U)
¨.USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
©.USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
ª.USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
«.USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
¬.USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
­.USART_CR3_WUS_Pos (20U)
®.USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
¯.USART_CR3_WUS USART_CR3_WUS_Msk
°.USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
±.USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
².USART_CR3_WUFIE_Pos (22U)
³.USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
´.USART_CR3_WUFIE USART_CR3_WUFIE_Msk
µ.USART_CR3_UCESM_Pos (23U)
¶.USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)
·.USART_CR3_UCESM USART_CR3_UCESM_Msk
º.USART_BRR_DIV_FRACTION_Pos (0U)
».USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
¼.USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
½.USART_BRR_DIV_MANTISSA_Pos (4U)
¾.USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
¿.USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
Â.USART_GTPR_PSC_Pos (0U)
Ã.USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
Ä.USART_GTPR_PSC USART_GTPR_PSC_Msk
Å.USART_GTPR_GT_Pos (8U)
Æ.USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
Ç.USART_GTPR_GT USART_GTPR_GT_Msk
Ë.USART_RTOR_RTO_Pos (0U)
Ì.USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
Í.USART_RTOR_RTO USART_RTOR_RTO_Msk
Î.USART_RTOR_BLEN_Pos (24U)
Ï.USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
Ð.USART_RTOR_BLEN USART_RTOR_BLEN_Msk
Ó.USART_RQR_ABRRQ_Pos (0U)
Ô.USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
Õ.USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
Ö.USART_RQR_SBKRQ_Pos (1U)
×.USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
Ø.USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
Ù.USART_RQR_MMRQ_Pos (2U)
Ú.USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
Û.USART_RQR_MMRQ USART_RQR_MMRQ_Msk
Ü.USART_RQR_RXFRQ_Pos (3U)
Ý.USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
Þ.USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
ß.USART_RQR_TXFRQ_Pos (4U)
à.USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
á.USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
ä.USART_ISR_PE_Pos (0U)
å.USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
æ.USART_ISR_PE USART_ISR_PE_Msk
ç.USART_ISR_FE_Pos (1U)
è.USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
é.USART_ISR_FE USART_ISR_FE_Msk
ê.USART_ISR_NE_Pos (2U)
ë.USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
ì.USART_ISR_NE USART_ISR_NE_Msk
í.USART_ISR_ORE_Pos (3U)
î.USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
ï.USART_ISR_ORE USART_ISR_ORE_Msk
ð.USART_ISR_IDLE_Pos (4U)
ñ.USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
ò.USART_ISR_IDLE USART_ISR_IDLE_Msk
ó.USART_ISR_RXNE_Pos (5U)
ô.USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
õ.USART_ISR_RXNE USART_ISR_RXNE_Msk
ö.USART_ISR_TC_Pos (6U)
÷.USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
ø.USART_ISR_TC USART_ISR_TC_Msk
ù.USART_ISR_TXE_Pos (7U)
ú.USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
û.USART_ISR_TXE USART_ISR_TXE_Msk
ü.USART_ISR_LBDF_Pos (8U)
ý.USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
þ.USART_ISR_LBDF USART_ISR_LBDF_Msk
ÿ.USART_ISR_CTSIF_Pos (9U)
€/USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
/USART_ISR_CTSIF USART_ISR_CTSIF_Msk
‚/USART_ISR_CTS_Pos (10U)
ƒ/USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
„/USART_ISR_CTS USART_ISR_CTS_Msk
…/USART_ISR_RTOF_Pos (11U)
†/USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
‡/USART_ISR_RTOF USART_ISR_RTOF_Msk
ˆ/USART_ISR_EOBF_Pos (12U)
‰/USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
Š/USART_ISR_EOBF USART_ISR_EOBF_Msk
‹/USART_ISR_ABRE_Pos (14U)
Œ/USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
/USART_ISR_ABRE USART_ISR_ABRE_Msk
Ž/USART_ISR_ABRF_Pos (15U)
/USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
/USART_ISR_ABRF USART_ISR_ABRF_Msk
‘/USART_ISR_BUSY_Pos (16U)
’/USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
“/USART_ISR_BUSY USART_ISR_BUSY_Msk
”/USART_ISR_CMF_Pos (17U)
•/USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
–/USART_ISR_CMF USART_ISR_CMF_Msk
—/USART_ISR_SBKF_Pos (18U)
˜/USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
™/USART_ISR_SBKF USART_ISR_SBKF_Msk
š/USART_ISR_RWU_Pos (19U)
›/USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
œ/USART_ISR_RWU USART_ISR_RWU_Msk
/USART_ISR_WUF_Pos (20U)
ž/USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
Ÿ/USART_ISR_WUF USART_ISR_WUF_Msk
 /USART_ISR_TEACK_Pos (21U)
¡/USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
¢/USART_ISR_TEACK USART_ISR_TEACK_Msk
£/USART_ISR_REACK_Pos (22U)
¤/USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
¥/USART_ISR_REACK USART_ISR_REACK_Msk
¨/USART_ICR_PECF_Pos (0U)
©/USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
ª/USART_ICR_PECF USART_ICR_PECF_Msk
«/USART_ICR_FECF_Pos (1U)
¬/USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
­/USART_ICR_FECF USART_ICR_FECF_Msk
®/USART_ICR_NCF_Pos (2U)
¯/USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
°/USART_ICR_NCF USART_ICR_NCF_Msk
±/USART_ICR_ORECF_Pos (3U)
²/USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
³/USART_ICR_ORECF USART_ICR_ORECF_Msk
´/USART_ICR_IDLECF_Pos (4U)
µ/USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
¶/USART_ICR_IDLECF USART_ICR_IDLECF_Msk
·/USART_ICR_TCCF_Pos (6U)
¸/USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
¹/USART_ICR_TCCF USART_ICR_TCCF_Msk
º/USART_ICR_LBDCF_Pos (8U)
»/USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
¼/USART_ICR_LBDCF USART_ICR_LBDCF_Msk
½/USART_ICR_CTSCF_Pos (9U)
¾/USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
¿/USART_ICR_CTSCF USART_ICR_CTSCF_Msk
À/USART_ICR_RTOCF_Pos (11U)
Á/USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
Â/USART_ICR_RTOCF USART_ICR_RTOCF_Msk
Ã/USART_ICR_EOBCF_Pos (12U)
Ä/USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
Å/USART_ICR_EOBCF USART_ICR_EOBCF_Msk
Æ/USART_ICR_CMCF_Pos (17U)
Ç/USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
È/USART_ICR_CMCF USART_ICR_CMCF_Msk
É/USART_ICR_WUCF_Pos (20U)
Ê/USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
Ë/USART_ICR_WUCF USART_ICR_WUCF_Msk
Î/USART_ICR_NECF USART_ICR_NCF
Ñ/USART_RDR_RDR_Pos (0U)
Ò/USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
Ó/USART_RDR_RDR USART_RDR_RDR_Msk
Ö/USART_TDR_TDR_Pos (0U)
×/USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
Ø/USART_TDR_TDR USART_TDR_TDR_Msk
á/WWDG_CR_T_Pos (0U)
â/WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
ã/WWDG_CR_T WWDG_CR_T_Msk
ä/WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
å/WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
æ/WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
ç/WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
è/WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
é/WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
ê/WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
í/WWDG_CR_T0 WWDG_CR_T_0
î/WWDG_CR_T1 WWDG_CR_T_1
ï/WWDG_CR_T2 WWDG_CR_T_2
ð/WWDG_CR_T3 WWDG_CR_T_3
ñ/WWDG_CR_T4 WWDG_CR_T_4
ò/WWDG_CR_T5 WWDG_CR_T_5
ó/WWDG_CR_T6 WWDG_CR_T_6
õ/WWDG_CR_WDGA_Pos (7U)
ö/WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
÷/WWDG_CR_WDGA WWDG_CR_WDGA_Msk
ú/WWDG_CFR_W_Pos (0U)
û/WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
ü/WWDG_CFR_W WWDG_CFR_W_Msk
ý/WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
þ/WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
ÿ/WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
€0WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
0WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
‚0WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
ƒ0WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
†0WWDG_CFR_W0 WWDG_CFR_W_0
‡0WWDG_CFR_W1 WWDG_CFR_W_1
ˆ0WWDG_CFR_W2 WWDG_CFR_W_2
‰0WWDG_CFR_W3 WWDG_CFR_W_3
Š0WWDG_CFR_W4 WWDG_CFR_W_4
‹0WWDG_CFR_W5 WWDG_CFR_W_5
Œ0WWDG_CFR_W6 WWDG_CFR_W_6
Ž0WWDG_CFR_WDGTB_Pos (7U)
0WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
0WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
‘0WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
’0WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
•0WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
–0WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
˜0WWDG_CFR_EWI_Pos (9U)
™0WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
š0WWDG_CFR_EWI WWDG_CFR_EWI_Msk
0WWDG_SR_EWIF_Pos (0U)
ž0WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
Ÿ0WWDG_SR_EWIF WWDG_SR_EWIF_Msk
®0IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
¯0IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
²0IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))
µ0IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
¸0IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
»0IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5) || ((INSTANCE) == DMA1_Channel6) || ((INSTANCE) == DMA1_Channel7))
Ä0IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE) || ((INSTANCE) == GPIOH))
Ë0IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE))
Ò0IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2) || ((INSTANCE) == I2C3))
×0IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C3))
Ü0IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
à0IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
ã0IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C3))
ç0IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2))
ë0IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
î0IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
ñ0IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
ù0IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
ÿ0IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
…1IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))
‰1IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))
1IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7))
“1IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))
—1IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))
›1IS_TIM_CCX_INSTANCE(INSTANCE,CHANNEL) (((((INSTANCE) == TIM2) || ((INSTANCE) == TIM3)) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM21) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM22) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))))
­1IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
³1IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21))
¸1IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
¾1IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21))
Ã1IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
É1IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
Ï1IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
Õ1IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
Û1IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
ã1IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
é1IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM21) || ((INSTANCE) == TIM22))
ï1IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))
ó1IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM3))
÷1IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5))
ý1IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5))
„2IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))
ˆ2IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == LPUART1))
2IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == LPUART1))
–2IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))
š2IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == LPUART1))
Ÿ2IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART4) || ((INSTANCE) == USART5) || ((INSTANCE) == LPUART1))
¦2IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))
ª2IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2))
®2IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
±2IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
´2IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Ä2RNG_LPUART1_IRQn LPUART1_IRQn
Å2AES_LPUART1_IRQn LPUART1_IRQn
Æ2AES_RNG_LPUART1_IRQn LPUART1_IRQn
Ç2TIM6_DAC_IRQn TIM6_IRQn
È2RCC_CRS_IRQn RCC_IRQn
É2DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
Ê2ADC1_IRQn ADC1_COMP_IRQn
Ë2SVC_IRQn SVCall_IRQn
Î2RNG_LPUART1_IRQHandler LPUART1_IRQHandler
Ï2AES_LPUART1_IRQHandler LPUART1_IRQHandler
Ð2AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
Ñ2TIM6_DAC_IRQHandler TIM6_IRQHandler
Ò2RCC_CRS_IRQHandler RCC_IRQHandler
Ó2DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
Ô2ADC1_IRQHandler ADC1_COMP_IRQHandlerÐÅ
 




../Drivers/CMSIS/Device/ST/STM32L0xx/Include/../Drivers/CMSIS/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\stm32l071xx.h
core_cm0plus.hsystem_stm32l0xx.h
stdint.h

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../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM½
NonMaskableInt_IRQnrHardFault_IRQnsSVCall_IRQn{PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQn
RTC_IRQnFLASH_IRQnRCC_IRQnEXTI0_1_IRQnEXTI2_3_IRQnEXTI4_15_IRQnDMA1_Channel1_IRQn    DMA1_Channel2_3_IRQn
DMA1_Channel4_5_6_7_IRQnADC1_COMP_IRQnLPTIM1_IRQn USART4_5_IRQnTIM2_IRQnTIM3_IRQnTIM6_IRQnTIM7_IRQnTIM21_IRQnI2C3_IRQnTIM22_IRQnI2C1_IRQnI2C2_IRQnSPI1_IRQnSPI2_IRQnUSART1_IRQnUSART2_IRQnLPUART1_IRQnPIRQn_Type×
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__STM32L0xx_HAL_H 
?SYSCFG_BOOT_MAINFLASH (0x00000000U)
@SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_BOOT_MODE_0
ASYSCFG_BOOT_SRAM SYSCFG_CFGR1_BOOT_MODE
JDBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP
KDBGMCU_STOP DBGMCU_CR_DBG_STOP
LDBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
MIS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U))
kSYSCFG_VREFINT_OUT_NONE (0x00000000U)
lSYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0
mSYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1
nSYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT
pIS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1))
{SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF
}IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY))
‰
SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP
Œ
SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP
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SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP
’
SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP
•
IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) )
«
__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
¬
__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
³
__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
´
__HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
»
__HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
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__HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
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__HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
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__HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
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__HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
Ì
__HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
Ó
__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
Ô
__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
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__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
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__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
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__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
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__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
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__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
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__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
ó
__HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
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__HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
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__HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
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__HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
ƒ__HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
„__HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
‹__HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
Œ__HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
‘__HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
•__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
š__HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1)
£__HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); } while (0)
Ë__HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)
Ó__HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))
Ü__HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); }while(0)
æ__HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); }while(0)
òIS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p
 




../Drivers/STM32L0xx_HAL_Driver/Inc/../Core/Inc/stm32l0xx_hal.h
stm32l0xx_hal_conf.h

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../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM±
HAL_TICK_FREQ_10HZdHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
PHAL_TickFreqTypeDefÐ
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(__STM32L0xx_H 
6STM32L0 
h__STM32L0xx_CMSIS_VERSION_MAIN (0x01)
i__STM32L0xx_CMSIS_VERSION_SUB1 (0x09)
j__STM32L0xx_CMSIS_VERSION_SUB2 (0x03)
k__STM32L0xx_CMSIS_VERSION_RC (0x00)
l__STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24) |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16) |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 ) |(__STM32L0xx_CMSIS_VERSION_RC))“

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IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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SET_BIT(REG,BIT) ((REG) |= (BIT))
Æ
CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
È
READ_BIT(REG,BIT) ((REG) & (BIT))
Ê
CLEAR_REG(REG) ((REG) = (0x0))
Ì
WRITE_REG(REG,VAL) ((REG) = (VAL))
Î
READ_REG(REG) ((REG))
Ð
MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
Ô
ATOMIC_SET_BIT(REG,BIT) do { uint32_t primask; primask = __get_PRIMASK(); __set_PRIMASK(1); SET_BIT((REG), (BIT)); __set_PRIMASK(primask); } while(0)
Þ
ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t primask; primask = __get_PRIMASK(); __set_PRIMASK(1); CLEAR_BIT((REG), (BIT)); __set_PRIMASK(primask); } while(0)
è
ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t primask; primask = __get_PRIMASK(); __set_PRIMASK(1); MODIFY_REG((REG), (CLEARMSK), (SETMASK)); __set_PRIMASK(primask); } while(0)
ò
ATOMIC_SETH_BIT(REG,BIT) ATOMIC_SET_BIT(REG, BIT)
õ
ATOMIC_CLEARH_BIT(REG,BIT) ATOMIC_CLEAR_BIT(REG, BIT)
ø
ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)ÿ
¤™
 




../Drivers/CMSIS/Device/ST/STM32L0xx/Include/../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx.h
stm32l071xx.h
stm32l0xx_hal.h

l

../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARMê

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PFlagStatusÕ
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PITStatusÕ
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DISABLEENABLE
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SUCCESSERROR
PErrorStatus@

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STM32_HAL_LEGACY 
#AES_FLAG_RDERR CRYP_FLAG_RDERR
$AES_FLAG_WRERR CRYP_FLAG_WRERR
%AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
&AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
'AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
9ADC_RESOLUTION12b ADC_RESOLUTION_12B
:ADC_RESOLUTION10b ADC_RESOLUTION_10B
;ADC_RESOLUTION8b ADC_RESOLUTION_8B
<ADC_RESOLUTION6b ADC_RESOLUTION_6B
=OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
>OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
?EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
@EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AEOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
BREGULAR_GROUP ADC_REGULAR_GROUP
CINJECTED_GROUP ADC_INJECTED_GROUP
DREGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
EAWD_EVENT ADC_AWD_EVENT
FAWD1_EVENT ADC_AWD1_EVENT
GAWD2_EVENT ADC_AWD2_EVENT
HAWD3_EVENT ADC_AWD3_EVENT
IOVR_EVENT ADC_OVR_EVENT
JJQOVF_EVENT ADC_JQOVF_EVENT
KALL_CHANNELS ADC_ALL_CHANNELS
LREGULAR_CHANNELS ADC_REGULAR_CHANNELS
MINJECTED_CHANNELS ADC_INJECTED_CHANNELS
NSYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
OSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
PADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
QADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
RADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
SADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
TADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
UADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
VADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
WADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
XADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
YADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
ZADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
[ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
\ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
]ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
^ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
_ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
`ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
bHAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
cHAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
dHAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
eHAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
fHAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
gHAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
hHAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
__HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
ˆ
COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
‰
COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Š
COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
‹
COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Œ
COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3

COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
Ž
COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5

COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6

COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
’
COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U)
•
COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
œ
COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
ž
COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
Ÿ
COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
 
COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
¡
COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
¢
COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
£
COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
¥
COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
¦
COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
§
COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
¨
COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
©
COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
ª
COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
«
COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
¬
COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
­
COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
²
COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
³
COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
¸
COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
¹
COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
»
COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
¼
COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
Ã
COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
Ó
COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
Ô
COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
é
__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
ø
HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
ú
HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
…CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
†CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
DAC1_CHANNEL_1 DAC_CHANNEL_1
‘DAC1_CHANNEL_2 DAC_CHANNEL_2
’DAC2_CHANNEL_1 DAC_CHANNEL_1
“DAC_WAVE_NONE 0x00000000U
”DAC_WAVE_NOISE DAC_CR_WAVE1_0
•DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
–DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
—DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
˜DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
¸HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
¹HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
ºHAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
»HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
¼HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
½HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
¾HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
¿HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
ÀHAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
ÁHAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
ÂHAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
ÃHAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
ÄHAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
ÅHAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
ÇIS_HAL_REMAPDMA IS_DMA_REMAP
È__HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
É__HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
ÇTYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
ÈTYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
ÉTYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
ÊTYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
ËTYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
ÌTYPEERASE_PAGES FLASH_TYPEERASE_PAGES
ÍTYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
ÎTYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
ÏWRPSTATE_DISABLE OB_WRPSTATE_DISABLE
ÐWRPSTATE_ENABLE OB_WRPSTATE_ENABLE
ÑHAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
ÒOBEX_PCROP OPTIONBYTE_PCROP
ÓOBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
ÔPCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
ÕPCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
ÖTYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
×TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
ØTYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
ÙTYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
ÚTYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
ÛTYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
ÜTYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
ÝTYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
ÞTYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
ßPAGESIZE FLASH_PAGE_SIZE
àTYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
áTYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
âTYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
ãVOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
äVOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
åVOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
æVOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
çTYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
èTYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
éWRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
êWRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
ëWRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
ìWRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
íIWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
îIWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
ïIWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
ðIWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
ñFLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
òFLASH_ERROR_RD HAL_FLASH_ERROR_RD
óFLASH_ERROR_PG HAL_FLASH_ERROR_PROG
ôFLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
õFLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
öFLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
÷FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
øFLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
ùFLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
úFLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
ûFLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
üFLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
ýFLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
þFLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
ÿFLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
€FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
‚FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
ƒFLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
„OB_WDG_SW OB_IWDG_SW
…OB_WDG_HW OB_IWDG_HW
†OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
‡OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
ˆOB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
‰OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
ŠIS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
‹OB_RDP_LEVEL0 OB_RDP_LEVEL_0
ŒOB_RDP_LEVEL1 OB_RDP_LEVEL_1
OB_RDP_LEVEL2 OB_RDP_LEVEL_2
’OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
“OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
ÅHAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
ÆHAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
ÇHAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
ÈHAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
ÉHAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
ÊHAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
ËHAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
ÌHAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
ÍHAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
ÕFSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
ÖFSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
ÞGET_GPIO_SOURCE GPIO_GET_INDEX
ßGET_GPIO_INDEX GPIO_GET_INDEX
GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
‚GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
ƒGPIO_AF2_LPTIM GPIO_AF2_LPTIM1
‡GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
ˆGPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
‰GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
ŠGPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
šGPIO_AF6_DFSDM GPIO_AF6_DFSDM1
ÆHRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
ÇHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
ÈHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
ÉHRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
ÊHRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
ËHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
ÌHRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
ÍHRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
ÎHRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Ð__HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
Ñ__HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
Ò__HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
Ó__HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
Ô__HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
Õ__HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
Ö__HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
×__HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
ëI2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
ìI2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
íI2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
îI2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
ïI2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
ðI2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
ñI2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
òI2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
ƒIRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
„IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
KR_KEY_RELOAD IWDG_KEY_RELOAD
ŽKR_KEY_ENABLE IWDG_KEY_ENABLE
KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
™LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
šLPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
›LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
œLPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
žLPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
ŸLPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
 LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
¢LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
£LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
¤LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
¥LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
©LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
ªLPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
«LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
±HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
ÂHAL_NAND_Read_Page HAL_NAND_Read_Page_8b
ÃHAL_NAND_Write_Page HAL_NAND_Write_Page_8b
ÄHAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
ÅHAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
ÇNAND_AddressTypedef NAND_AddressTypeDef
É__ARRAY_ADDRESS ARRAY_ADDRESS
Ê__ADDR_1st_CYCLE ADDR_1ST_CYCLE
Ë__ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Ì__ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Í__ADDR_4th_CYCLE ADDR_4TH_CYCLE
ÕNOR_StatusTypedef HAL_NOR_StatusTypeDef
ÖNOR_SUCCESS HAL_NOR_STATUS_SUCCESS
×NOR_ONGOING HAL_NOR_STATUS_ONGOING
ØNOR_ERROR HAL_NOR_STATUS_ERROR
ÙNOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Û__NOR_WRITE NOR_WRITE
Ü__NOR_ADDR_SHIFT NOR_ADDR_SHIFT
åOPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
æOPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
çOPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
èOPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
êOPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
ëOPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
ìOPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
íOPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
ïOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
ðOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
òIOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
óIOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
õOPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
öOPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
øOPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
úOPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
ûOPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
üOPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
    I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
¦    CF_DATA ATA_DATA
§    CF_SECTOR_COUNT ATA_SECTOR_COUNT
¨    CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
©    CF_CYLINDER_LOW ATA_CYLINDER_LOW
ª    CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
«    CF_CARD_HEAD ATA_CARD_HEAD
¬    CF_STATUS_CMD ATA_STATUS_CMD
­    CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
®    CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
±    CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
²    CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
³    CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
´    CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
¶    PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
·    PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
¸    PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
¹    PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
º    PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
à   FORMAT_BIN RTC_FORMAT_BIN
Ä    FORMAT_BCD RTC_FORMAT_BCD
Æ    RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Ç    RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
È    RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
É    RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Ë    RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Ì    RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Í    RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Π   RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Ï    RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Ñ    RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Ò    RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
Ó    RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
Ô    RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
Ö    RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
×    RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Ø    RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
Ú    RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
Û    RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
Ü    RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
ý    RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
þ    RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
ÿ    RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
€
RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
‹
SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Œ
SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Ž
SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE

SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE

SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
‘
SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
“
SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
”
SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
–
SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
—
SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
 
SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
¡
SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
¢
SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
£
SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
¤
SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
¥
SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
¦
SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
§
SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
¨
SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
©
SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
ª
HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
²
SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
³
SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
µ
SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
¶
SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
¸
SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
¹
SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Ñ
CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Ò
CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Ô
TIM_DMABase_CR1 TIM_DMABASE_CR1
Õ
TIM_DMABase_CR2 TIM_DMABASE_CR2
Ö
TIM_DMABase_SMCR TIM_DMABASE_SMCR
×
TIM_DMABase_DIER TIM_DMABASE_DIER
Ø
TIM_DMABase_SR TIM_DMABASE_SR
Ù
TIM_DMABase_EGR TIM_DMABASE_EGR
Ú
TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Û
TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Ü
TIM_DMABase_CCER TIM_DMABASE_CCER
Ý
TIM_DMABase_CNT TIM_DMABASE_CNT
Þ
TIM_DMABase_PSC TIM_DMABASE_PSC
ß
TIM_DMABase_ARR TIM_DMABASE_ARR
à
TIM_DMABase_RCR TIM_DMABASE_RCR
á
TIM_DMABase_CCR1 TIM_DMABASE_CCR1
â
TIM_DMABase_CCR2 TIM_DMABASE_CCR2
ã
TIM_DMABase_CCR3 TIM_DMABASE_CCR3
ä
TIM_DMABase_CCR4 TIM_DMABASE_CCR4
å
TIM_DMABase_BDTR TIM_DMABASE_BDTR
æ
TIM_DMABase_DCR TIM_DMABASE_DCR
ç
TIM_DMABase_DMAR TIM_DMABASE_DMAR
è
TIM_DMABase_OR1 TIM_DMABASE_OR1
é
TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
ê
TIM_DMABase_CCR5 TIM_DMABASE_CCR5
ë
TIM_DMABase_CCR6 TIM_DMABASE_CCR6
ì
TIM_DMABase_OR2 TIM_DMABASE_OR2
í
TIM_DMABase_OR3 TIM_DMABASE_OR3
î
TIM_DMABase_OR TIM_DMABASE_OR
ð
TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
ñ
TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
ò
TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
ó
TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
ô
TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
õ
TIM_EventSource_COM TIM_EVENTSOURCE_COM
ö
TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
÷
TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
ø
TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
ú
TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
û
TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
ü
TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
ý
TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
þ
TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
ÿ
TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
€TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
‚TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
ƒTIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
„TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
…TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
†TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
‡TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
ˆTIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
‰TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
ŠTIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
‹TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
ŽTIM22_TI1_GPIO1 TIM22_TI1_GPIO
TIM22_TI1_GPIO2 TIM22_TI1_GPIO
³TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
´TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
¼UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
½UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
¾UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
¿UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Á__HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Â__HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Ä__DIV_SAMPLING16 UART_DIV_SAMPLING16
Å__DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Æ__DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Ç__UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
É__DIV_SAMPLING8 UART_DIV_SAMPLING8
Ê__DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Ë__DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Ì__UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Î__DIV_LPUART UART_DIV_LPUART
ÐUART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
ÑUART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
ÜUSART_CLOCK_DISABLED USART_CLOCK_DISABLE
ÝUSART_CLOCK_ENABLED USART_CLOCK_ENABLE
ßUSARTNACK_ENABLED USART_NACK_ENABLE
àUSARTNACK_DISABLED USART_NACK_DISABLE
èCFR_BASE WWDG_CFR_BASE
ñCAN_FilterFIFO0 CAN_FILTER_FIFO0
òCAN_FilterFIFO1 CAN_FILTER_FIFO1
óCAN_IT_RQCP0 CAN_IT_TME
ôCAN_IT_RQCP1 CAN_IT_TME
õCAN_IT_RQCP2 CAN_IT_TME
öINAK_TIMEOUT CAN_TIMEOUT_VALUE
÷SLAK_TIMEOUT CAN_TIMEOUT_VALUE
øCAN_TXSTATUS_FAILED ((uint8_t)0x00U)
ùCAN_TXSTATUS_OK ((uint8_t)0x01U)
úCAN_TXSTATUS_PENDING ((uint8_t)0x02U)
„VLAN_TAG ETH_VLAN_TAG
…MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
†MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
‡JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
ˆMACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
‰MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
ŠMACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
‹DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
ETH_MMCCR 0x00000100U
ŽETH_MMCRIR 0x00000104U
ETH_MMCTIR 0x00000108U
ETH_MMCRIMR 0x0000010CU
‘ETH_MMCTIMR 0x00000110U
’ETH_MMCTGFSCCR 0x0000014CU
“ETH_MMCTGFMSCCR 0x00000150U
”ETH_MMCTGFCR 0x00000168U
•ETH_MMCRFCECR 0x00000194U
–ETH_MMCRFAECR 0x00000198U
—ETH_MMCRGUFCR 0x000001C4U
™ETH_MAC_TXFIFO_FULL 0x02000000U
šETH_MAC_TXFIFONOT_EMPTY 0x01000000U
›ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U
œETH_MAC_TXFIFO_IDLE 0x00000000U
ETH_MAC_TXFIFO_READ 0x00100000U
ŸETH_MAC_TXFIFO_WAITING 0x00200000U
¡ETH_MAC_TXFIFO_WRITING 0x00300000U
£ETH_MAC_TRANSMISSION_PAUSE 0x00080000U
¤ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U
¥ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U
§ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U
©ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U
«ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U
¬ETH_MAC_RXFIFO_EMPTY 0x00000000U
­ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U
¯ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U
±ETH_MAC_RXFIFO_FULL 0x00000300U
´ETH_MAC_READCONTROLLER_IDLE 0x00000000U
µETH_MAC_READCONTROLLER_READING_DATA 0x00000020U
¶ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U
¹ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U
»ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U
¼ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U
½ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U
¾ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U
¿ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U
ÀETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U
ÉHAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
ÊDCMI_IT_OVF DCMI_IT_OVR
ËDCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
ÌDCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
ÎHAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
ÏHAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
ÐHAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
 HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
£ HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler
¬ HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
­ HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
® HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
¯ HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
° HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
± HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
µ HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
¶ HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
· HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
¸ HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
º HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
» HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
½ HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
¾ HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Þ HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
ß HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
à HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
á HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
â HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
ã HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
ä HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
ç HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
è HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
í HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
î HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
€FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
‚FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
ƒHAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
„HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
…HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
†HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
‘HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
’HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
”HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) ((cmd == ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
›HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
œHAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
žHAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
£HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
¤HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
¥HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
¦HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
ÁHAL_PWR_PVDConfig HAL_PWR_ConfigPVD
ÂHAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
ÃHAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
ÄHAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
ÅHAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
ÆHAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
ÇHAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
ÈHAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
ÉHAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
ÊHAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
ËHAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
ÌHAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
ÍHAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
ÎHAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
ÏHAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
ÐHAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
ÒPWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
ÓPWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
ÔPWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
ÕPWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
ÖPWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
×PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
ØPWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
ÚCR_OFFSET_BB PWR_CR_OFFSET_BB
ÛCSR_OFFSET_BB PWR_CSR_OFFSET_BB
ÜPMODE_BIT_NUMBER VOS_BIT_NUMBER
ÝCR_PMODE_BB CR_VOS_BB
ßDBP_BitNumber DBP_BIT_NUMBER
àPVDE_BitNumber PVDE_BIT_NUMBER
áPMODE_BitNumber PMODE_BIT_NUMBER
âEWUP_BitNumber EWUP_BIT_NUMBER
ãFPDS_BitNumber FPDS_BIT_NUMBER
äODEN_BitNumber ODEN_BIT_NUMBER
åODSWEN_BitNumber ODSWEN_BIT_NUMBER
æMRLVDS_BitNumber MRLVDS_BIT_NUMBER
çLPLVDS_BitNumber LPLVDS_BIT_NUMBER
èBRE_BitNumber BRE_BIT_NUMBER
êPWR_MODE_EVT PWR_PVD_MODE_NORMAL
ØHAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
ÙHAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
ÚHAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
âHAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
êHAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
ëHAL_TIM_DMAError TIM_DMAError
ìHAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
íHAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
ðHAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
ñHAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
òHAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
óHAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
ôHAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
õHAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
þHAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
†HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
‡HAL_LTDC_Relaod HAL_LTDC_Reload
ˆHAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
‰HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
œAES_IT_CC CRYP_IT_CC
AES_IT_ERR CRYP_IT_ERR
žAES_FLAG_CCF CRYP_FLAG_CCF
¦__HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
§__HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
¨__HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
©__HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
ª__HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
«__HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
¬__HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
­__HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
®__HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
¯__HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
°__HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
±__HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
²__HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
³__HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
µSYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
¶SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
·IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
¸UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
¹CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Ã__ADC_ENABLE __HAL_ADC_ENABLE
Ä__ADC_DISABLE __HAL_ADC_DISABLE
Å__HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Æ__HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Ç__HAL_ADC_IS_ENABLED ADC_IS_ENABLE
È__ADC_IS_ENABLED ADC_IS_ENABLE
É__HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Ê__HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Ë__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Ì__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Í__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Î__HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Ï__HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Ñ__HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Ò__HAL_ADC_JSQR_RK ADC_JSQR_RK
Ó__HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Ô__HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Õ__HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Ö__HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
×__HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Ø__HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Ù__HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Ú__HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Û__HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Ü__HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Ý__HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Þ__HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
ß__HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
à__HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
á__HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
â__HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
ã__HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
ä__HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
æ__HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
ç__HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
è__HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
é__HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
ê__HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
ë__HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
ì__ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
í__HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
î__HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
ï__HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
ñ__HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
ò__HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
ó__HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
ô__HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
õ__HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
ö__HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
÷__HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
ø__HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
ú__HAL_ADC_SQR1 ADC_SQR1
û__HAL_ADC_SMPR1 ADC_SMPR1
ü__HAL_ADC_SMPR2 ADC_SMPR2
ý__HAL_ADC_SQR3_RK ADC_SQR3_RK
þ__HAL_ADC_SQR2_RK ADC_SQR2_RK
ÿ__HAL_ADC_SQR1_RK ADC_SQR1_RK
€__HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
__HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
‚__HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
ƒ__HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
„__HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
…__HAL_ADC_JSQR ADC_JSQR
‡__HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
ˆ__HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
‰__HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Š__HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
‹__HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Œ__HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
__HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Ž__HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
—__HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
˜__HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
™__HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
šIS_DAC_GENERATE_WAVE IS_DAC_WAVE
£__HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
¤__HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
¥__HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
¦__HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
§__HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
¨__HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
©__HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
ª__HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
«__HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
¬__HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
­__HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
®__HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
¯__HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
°__HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
±__HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
²__HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
´__HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
µ__HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
¶__HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
·__HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
¸__HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
¹__HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
º__HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
»__HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
¼__HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
½__HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
¾__HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
¿__HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
À__HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Á__HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Ä__HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Å__HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Æ__HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Ç__HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
È__HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
É__HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Ê__HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Ë__HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Ò__HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Ó__HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Ô__HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Õ__HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
×__HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Ø__HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Ù__HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Ú__HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Û__HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Ü__HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Ý__HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Þ__HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
ß__HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
à__HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
á__HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
â__HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
ú__HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
ü__HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
þ__HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
€__HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
‚__HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
„__HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
†__HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
ˆ__HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Œ__HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
“__HAL_COMP_GET_FLAG(__HANDLE__,__FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
HAL_COMP_Start_IT HAL_COMP_Start
ŸHAL_COMP_Stop_IT HAL_COMP_Stop
ªIS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE)|| ((WAVE) == DAC_WAVE_TRIANGLE))
¶IS_WRPAREA IS_OB_WRPAREA
·IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
¸IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
¹IS_TYPEERASE IS_FLASH_TYPEERASE
ºIS_NBSECTORS IS_FLASH_NBSECTORS
»IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Å__HAL_I2C_RESET_CR2 I2C_RESET_CR2
Æ__HAL_I2C_GENERATE_START I2C_GENERATE_START
Ê__HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Ì__HAL_I2C_RISE_TIME I2C_RISE_TIME
Í__HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Î__HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Ï__HAL_I2C_SPEED I2C_SPEED
Ð__HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Ñ__HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Ò__HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Ó__HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Ô__HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Õ__HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Ö__HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
×__HAL_I2C_FREQRANGE I2C_FREQRANGE
àIS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
áIS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
ï__IRDA_DISABLE __HAL_IRDA_DISABLE
ð__IRDA_ENABLE __HAL_IRDA_ENABLE
ò__HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
ó__HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
ô__IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
õ__IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
÷IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
‚__HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
ƒ__HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
__HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Ž__HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
__HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
™__OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
š__OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
›__OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
œ__OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
__OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
ž__OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Ÿ__OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
 __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
¡__OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
¢__OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
£__OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
¤__OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
¥__OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
¯__HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
°__HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
±__HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
²__HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
³__HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
´__HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
µ__HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
¶__HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
·__HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
¸__HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
¹__HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
º__HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
»__HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
¼__HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
½__HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
¾__HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
¿__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
Â__HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Ã__HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Ä__HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Å__HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Æ__HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Ç__HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
È__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
É__HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Ê__HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
Í__HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
Ð__HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Ñ__HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Ò__HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Ó__HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Ô__HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Õ__HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Ö__HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
×__HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
à__HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
á__HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
â__HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
ã__HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
ä__HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
ïRCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
ðRCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
òHAL_RCC_CCSCallback HAL_RCC_CSSCallback
óHAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
ö__ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
÷__ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
ø__ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
ù__ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
ú__ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
û__ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
ü__ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
ý__ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
þ__ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
ÿ__ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
€__ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
__ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
‚__ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
ƒ__ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
„__ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
…__ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
†__ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
‡__ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
ˆ__ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
‰__ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Š__AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
‹__AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Œ__AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
__AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Ž__AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
__AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
__CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
‘__CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
’__CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
“__CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
”__CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
•__CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
–__AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
—__AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
˜__AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
™__AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
š__AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
›__AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
œ__AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
__AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
ž__AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Ÿ__AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
 __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
¡__AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
¢__APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
£__APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
¤__APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
¥__APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
¦__BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
§__BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
¨__BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
©__BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
ª__CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
«__CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
¬__CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
­__CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
®__CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
¯__CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
°__CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
±__CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
²__CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
³__CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
´__CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
µ__CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
¶__CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
·__CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
¸__CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
¹__CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
º__COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
»__COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
¼__COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
½__COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
¾__COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
¿__COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
À__CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Á__CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Â__CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Ã__CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Ä__CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Å__CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Æ__CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Ç__CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
È__DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
É__DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Ê__DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Ë__DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Ì__DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Í__DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Î__DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Ï__DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Ð__DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Ñ__DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Ò__DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Ó__DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Ô__DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Õ__DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Ö__DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
×__DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Ø__DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Ù__DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Ú__DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Û__DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Ü__DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Ý__DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Þ__DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
ß__DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
à__DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
á__DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
â__DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
ã__DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
ä__DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
å__DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
æ__DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
ç__DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
è__ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
é__ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
ê__ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
ë__ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
ì__ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
í__ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
î__ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
ï__ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
ð__FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
ñ__FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
ò__FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
ó__FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
ô__FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
õ__FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
ö__FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
÷__FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
ø__FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
ù__FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
ú__FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
û__FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
ü__FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
ý__FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
þ__FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
ÿ__FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
€__FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
__FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
‚__FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
ƒ__FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
„__FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
…__FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
†__GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
‡__GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
ˆ__GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
‰__GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Š__GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
‹__GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Œ__GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
__GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Ž__GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
__GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
__GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
‘__GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
’__GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
“__GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
”__GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
•__GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
–__GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
—__GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
˜__GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
™__GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
š__GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
›__GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
œ__GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
__GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
ž__GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Ÿ__GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
 __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
¡__GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
¢__GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
£__GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
¤__GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
¥__GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
¦__GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
§__GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
¨__GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
©__GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
ª__GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
«__GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
¬__GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
­__GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
®__GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
¯__GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
°__GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
±__GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
²__GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
³__GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
´__GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
µ__GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
¶__I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
·__I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
¸__I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
¹__I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
º__I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
»__I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
¼__I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
½__I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
¾__I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
¿__I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
À__I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Á__I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Â__I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Ã__I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Ä__I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Å__I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Æ__I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Ç__I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
È__LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
É__LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Ê__LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Ë__LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Ì__LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Í__LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Î__LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Ï__LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Ð__LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Ñ__LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Ò__LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Ó__LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Ô__LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Õ__LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Ö__LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
×__LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Ø__LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Ù__LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Ú__LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Û__LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Ü__LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Ý__LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Þ__LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
ß__LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
à__OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
á__OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
â__OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
ã__OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
ä__OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
å__OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
æ__OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
ç__OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
è__OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
é__OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
ê__OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
ë__OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
ì__PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
í__PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
î__PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
ï__PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
ð__PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
ñ__PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
ò__QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
ó__QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
ô__QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
õ__QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
ö__QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
÷__QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
‡__RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
ˆ__RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
‰__RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Š__RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
‹__RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Œ__RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
__SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Ž__SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
__SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
__SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
‘__SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
’__SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
“__SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
”__SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
•__SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
–__SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
—__SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
˜__SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
™__SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
š__SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
›__SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
œ__SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
__SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
ž__SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Ÿ__SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
 __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
¡__SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
¢__SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
£__SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
¤__SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
¥__SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
¦__SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
§__SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
¨__SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
©__SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
ª__SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
«__SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
¬__SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
­__SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
®__SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
¯__SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
°__SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
±__SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
²__SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
³__SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
´__SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
µ__SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
¶__SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
·__SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
¸__SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
¹__SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
º__SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
»__SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
¼__SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
½__SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
¾__SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
¿__SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
À__SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Á__SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Â__SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Ã__SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Ä__SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Å__TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Æ__TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Ç__TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
È__TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
É__TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Ê__TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Ë__TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Ì__TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Í__TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Î__TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Ï__TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Ð__TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Ñ__TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Ò__TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Ó__TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Ô__TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Õ__TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Ö__TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
×__TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Ø__TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Ù__TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Ú__TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Û__TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Ü__TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Ý__TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Þ__TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
ß__TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
à__TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
á__TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
â__TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
ã__TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
ä__TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
å__TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
æ__TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
ç__TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
è__TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
é__TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
ê__TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
ë__TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
ì__TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
í__TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
î__TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
ï__TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
ð__TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
ñ__TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
ò__TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
ó__TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
ô__TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
õ__TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
ö__TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
÷__TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
ø__TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
ù__TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
ú__TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
û__TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
ü__TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
ý__TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
þ__TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
ÿ__TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
€__TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
__TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
‚__TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
ƒ__TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
„__TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
…__TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
†__TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
‡__TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
ˆ__TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
‰__TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Š__TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
‹__TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Œ__TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
__TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Ž__TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
__TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
__TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
‘__TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
’__TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
“__TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
”__TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
•__TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
–__TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
—__TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
˜__TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
™__TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
š__TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
›__TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
œ__TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
__TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
ž__TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Ÿ__TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
 __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
¡__TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
¢__TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
£__TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
¤__TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
¥__UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
¦__UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
§__UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
¨__UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
©__UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
ª__UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
«__UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
¬__UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
­__UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
®__UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
¯__UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
°__UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
±__USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
²__USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
³__USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
´__USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
µ__USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
¶__USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
·__USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
¸__USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
¹__USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
º__USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
»__USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
¼__USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
½__USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
¾__USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
¿__USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
À__USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Á__USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Â__USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Ã__USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Ä__USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Å__USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Æ__USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Ç__USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
È__USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
É__USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Ê__USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Ë__USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Ì__USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Í__USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Î__USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Ï__USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Ð__USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Ñ__USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Ò__USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Ó__USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Ô__USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Õ__USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Ö__USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
×__USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Ø__USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Ù__USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Ú__USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Û__USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Ü__USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Ý__USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Þ__USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
ó__WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
ô__WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
õ__WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
ö__WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
÷__WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
ø__WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
ú__TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
û__TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
ü__TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
ý__TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
þ__TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
ÿ__TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
€__TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
__TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
‚__TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
ƒ__TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
„__TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
…__TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
†__CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
‡__CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
ˆ__CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
‰__CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Š__CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
‹__CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Œ__RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
__RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
__USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
__USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
‘__USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
’__USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
“__USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
”__USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
•__USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
–__USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
—__TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
˜__TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
™__TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
š__TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
›__TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
œ__TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
__ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
ž__ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Ÿ__ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
 __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
¡__HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
¢__HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
£__HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
¤__HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
¥__HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
¦__HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
§__SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
¨__SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
©__SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
ª__SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
«__SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
¬__SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
­__SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
®__SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
¯__SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
°__SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
±__SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
²__SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
³__LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
´__LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
µ__LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
¶__LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
·__LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
¸__ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
¹__ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
º__ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
»__ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
¼__ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
½__ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
¾__TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
¿__TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
À__TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Á__TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Â__TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Ã__TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Ä__BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Å__BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Æ__BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Ç__BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
È__CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
É__CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Ê__USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Ë__USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Ì__USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Í__USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Î__USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Ï__USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Ð__SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Ñ__SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Ò__SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Ó__SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Ô__SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Õ__SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Ö__GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
×__GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Ø__GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Ù__GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Ú__GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Û__GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Ü__GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Ý__GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Þ__GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
ß__GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
à__GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
á__GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
â__GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
ã__GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
ä__GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
å__GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
æ__GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
ç__ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
è__ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
é__DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
ê__DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
ë__DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
ì__DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
í__DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
î__DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
ï__UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
ð__UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
ñ__UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
ò__UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
ó__UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
ô__UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
õ__UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
ö__UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
÷__UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
ø__UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
ù__UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
ú__UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
û__OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
ü__OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
ý__OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
þ__OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
ÿ__OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
€__OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
__HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
‚__HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
ƒ__HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
„__HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
…__HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
†__HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
‡__HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
ˆ__HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
‰__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Š__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
‹__SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Œ__CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
__CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Ž__DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
__DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
__ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
‘__ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
’__ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
“__ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
”__FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
•__FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
–__FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
—__FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
˜__SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
™__SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
š__SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
›__SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
œ__DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
__DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
ž__DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Ÿ__DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
 __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
¡__DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
¤__HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
¥__HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
§__ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
¨__ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
©__ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
ª__ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
«__DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
¬__DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
­__TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
®__TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
¯__TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
°__TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
±__TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
²__TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
³__HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
´__HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
µ__SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
¶__SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
·__SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
¸__SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
¹__SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
º__SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
¼__ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
½__ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
¾__ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
¿__ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
À__DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
Á__DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
Â__TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
Ã__TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
Ä__TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
Å__TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
Æ__TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
Ç__TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
È__HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
É__HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
Ê__SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
Ë__SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
Ì__SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
Í__SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
Î__SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
Ï__SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
Ñ__ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
Ò__ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
Ó__ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
Ô__ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
Õ__ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
Ö__ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
×__CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
Ø__CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
Ù__CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
Ú__CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
Û__DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
Ü__DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
Ý__DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
Þ__DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
ß__DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
à__DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
á__DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
â__DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
ã__FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
ä__FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
å__FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
æ__FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
ç__GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
è__GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
é__GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
ê__GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
ë__GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
ì__GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
í__GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
î__GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
ï__GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
ð__GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
ñ__GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
ò__GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
ó__GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
ô__GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
õ__GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
ö__GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
÷__HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
ø__HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
ù__I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
ú__I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
û__I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
ü__I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
ý__I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
þ__I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
ÿ__PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
€__PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
__SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
‚__SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
ƒ__SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
„__SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
…__SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
†__SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
‡__SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
ˆ__SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
‰__SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
Š__SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
‹__SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
Œ__SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
__SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
Ž__SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
__SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
__SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
‘__SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
’__SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
“__TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
”__TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
•__TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
–__TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
—__TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
˜__TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
™__TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
š__TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
›__TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
œ__TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
__TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
ž__TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
Ÿ__TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
 __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
¡__TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
¢__TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
£__TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
¤__TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
¥__TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
¦__TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
§__TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
¨__TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
©__TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
ª__TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
«__TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
¬__TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
­__TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
®__TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
¯__TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
°__TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
±__TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
²__TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
³__TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
´__TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
µ__TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
¶__TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
·__UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
¸__UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
¹__UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
º__UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
»__USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
¼__USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
½__USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
¾__USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
¿__USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
À__USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
Á__USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
Â__USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
Ã__WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
Ä__WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
Œ__HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
__HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
__RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
‘IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
’IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
“IS_RCC_SYSCLK_DIV IS_RCC_HCLK
”IS_RCC_HCLK_DIV IS_RCC_PCLK
•IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
—RCC_IT_HSI14 RCC_IT_HSI14RDY
™RCC_IT_CSSLSE RCC_IT_LSECSS
šRCC_IT_CSSHSE RCC_IT_CSS
œRCC_PLLMUL_3 RCC_PLL_MUL3
RCC_PLLMUL_4 RCC_PLL_MUL4
žRCC_PLLMUL_6 RCC_PLL_MUL6
ŸRCC_PLLMUL_8 RCC_PLL_MUL8
 RCC_PLLMUL_12 RCC_PLL_MUL12
¡RCC_PLLMUL_16 RCC_PLL_MUL16
¢RCC_PLLMUL_24 RCC_PLL_MUL24
£RCC_PLLMUL_32 RCC_PLL_MUL32
¤RCC_PLLMUL_48 RCC_PLL_MUL48
¦RCC_PLLDIV_2 RCC_PLL_DIV2
§RCC_PLLDIV_3 RCC_PLL_DIV3
¨RCC_PLLDIV_4 RCC_PLL_DIV4
ªIS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
«__HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
¬RCC_MCO_NODIV RCC_MCODIV_1
­RCC_MCO_DIV1 RCC_MCODIV_1
®RCC_MCO_DIV2 RCC_MCODIV_2
¯RCC_MCO_DIV4 RCC_MCODIV_4
°RCC_MCO_DIV8 RCC_MCODIV_8
±RCC_MCO_DIV16 RCC_MCODIV_16
²RCC_MCO_DIV32 RCC_MCODIV_32
³RCC_MCO_DIV64 RCC_MCODIV_64
´RCC_MCO_DIV128 RCC_MCODIV_128
µRCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
¶RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
·RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
¸RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
¹RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
ºRCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
»RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
¼RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
½RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
¾RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
¿RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
ÅRCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
ÈRCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
ÉRCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
ÊRCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
ËRCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
ÌRCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
ÍRCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
ÎRCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
ÏRCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
ÑHSION_BitNumber RCC_HSION_BIT_NUMBER
ÒHSION_BITNUMBER RCC_HSION_BIT_NUMBER
ÓHSEON_BitNumber RCC_HSEON_BIT_NUMBER
ÔHSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
ÕMSION_BITNUMBER RCC_MSION_BIT_NUMBER
ÖCSSON_BitNumber RCC_CSSON_BIT_NUMBER
×CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
ØPLLON_BitNumber RCC_PLLON_BIT_NUMBER
ÙPLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
ÚPLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
ÛI2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
ÜRTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
ÝRTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
ÞBDRST_BitNumber RCC_BDRST_BIT_NUMBER
ßBDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
àRTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
áLSION_BitNumber RCC_LSION_BIT_NUMBER
âLSION_BITNUMBER RCC_LSION_BIT_NUMBER
ãLSEON_BitNumber RCC_LSEON_BIT_NUMBER
äLSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
åLSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
æPLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
çTIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
èRMVF_BitNumber RCC_RMVF_BIT_NUMBER
éRMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
êRCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
ëCR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
ìCIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
íCIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
îBDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
ïDBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
ðLSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
òCR_HSION_BB RCC_CR_HSION_BB
óCR_CSSON_BB RCC_CR_CSSON_BB
ôCR_PLLON_BB RCC_CR_PLLON_BB
õCR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
öCR_MSION_BB RCC_CR_MSION_BB
÷CSR_LSION_BB RCC_CSR_LSION_BB
øCSR_LSEON_BB RCC_CSR_LSEON_BB
ùCSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
úCSR_RTCEN_BB RCC_CSR_RTCEN_BB
ûCSR_RTCRST_BB RCC_CSR_RTCRST_BB
üCFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
ýBDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
þBDCR_BDRST_BB RCC_BDCR_BDRST_BB
ÿCR_HSEON_BB RCC_CR_HSEON_BB
€CSR_RMVF_BB RCC_CSR_RMVF_BB
CR_PLLSAION_BB RCC_CR_PLLSAION_BB
‚DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
„__HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
…__HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
†__HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
‡__HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
ˆ__HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
Š__HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
ŒRCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
‘RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
’RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
“IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
”RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
–__HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
—__HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
˜__HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
™__HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
š__HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
›__HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
œ__HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
__HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
ž__HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
Ÿ__HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
 DfsdmClockSelection Dfsdm1ClockSelection
¡RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
¢RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
£RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
¤__HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
¥__HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
¦RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
§RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
¨RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
©RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
«RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
¬RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
­RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
®RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
¯RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
°RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
±RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
°HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
½__HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
¿__HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
À__HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Í__HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Ð__HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Ó__HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Ö__HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Ù__HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
ÞIS_ALARM IS_RTC_ALARM
ßIS_ALARM_MASK IS_RTC_ALARM_MASK
àIS_TAMPER IS_RTC_TAMPER
áIS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
âIS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
ãIS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
äIS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
åIS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
æIS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
çIS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
èIS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
éIS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
êIS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
ëIS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
í__RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
î__RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
ýSD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
þSD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
‚eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
ƒeMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
…SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
†SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
×__SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Ø__SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Ù__SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Ú__SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Û__SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Ü__SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Þ__HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
ß__SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
áIS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
ê__HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
ë__HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
ì__HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
í__HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
î__HAL_SMBUS_GET_DIR SMBUS_GET_DIR
ï__HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
ð__HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
ñ__HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
ú__HAL_SPI_1LINE_TX SPI_1LINE_TX
û__HAL_SPI_1LINE_RX SPI_1LINE_RX
ü__HAL_SPI_RESET_CRC SPI_RESET_CRC
† __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
‡ __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
ˆ __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
‰ __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
‹ IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
 IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Ž IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
™ __USART_ENABLE_IT __HAL_USART_ENABLE_IT
š __USART_DISABLE_IT __HAL_USART_DISABLE_IT
› __USART_ENABLE __HAL_USART_ENABLE
œ __USART_DISABLE __HAL_USART_DISABLE
ž __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Ÿ __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
¯ USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
± USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
² USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
³ USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
´ USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
¶ USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
· USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
¸ USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
¹ USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
» __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
¼ __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
½ __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
¾ __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
¿ __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
À __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Á __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
à__HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Ä __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Å __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Æ __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Ç __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
È __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
É __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Ê __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Ì __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Í __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Π__HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Ï __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Р__HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Ñ __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Ò __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Ó __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Õ HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Ö HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Ø HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Ù HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
á __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
â __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
ä TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
å TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
ç __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
é __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
ê __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
ë __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
ì __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
í __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
î __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
ï __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
ð __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
ñ __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
ò __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
ó __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
ô __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
ö TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
ÿ __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
€!__HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
!__HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
‚!__HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
ƒ!__HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
„!__HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
…!__HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
‡!ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
ˆ!ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
‰!IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
‘!__HAL_LTDC_LAYER LTDC_LAYER
’!__HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
š!SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
›!SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
œ!SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
!SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
ž!SAI_STREOMODE SAI_STEREOMODE
Ÿ!SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
 !SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
¡!SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
¢!SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
£!SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
¤!SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
¥!IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
¦!SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
§!SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE`U
 




../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h


Ø
../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
ëìí

__stddef_h 
__ARMCLIB_VERSION 5060037
__STDDEF_DECLS __CLIBNS
 __CLIBNS SNULL
TNULL 0
[offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb)))PD
 




C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h



C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]intunsigned intunsigned shortlong doublePptrdiff_tŠ
&Psize_t‘
.Pwchar_t¡
@Pmax_align_t³
_
ïðñ

__STM32L0xx_HAL_DEF 
:UNUSED(X) (void)X
=HAL_MAX_DELAY 0xFFFFFFFFU
?HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) == (BIT))
@HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == 0U)
B__HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0)
W__HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
___HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0)
k__HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0)
–
__ALIGN_END 
š
__ALIGN_BEGIN __align(4)
®
__RAM_FUNC 
°
__NOINLINE __attribute__ ( (noinline) )äÚ
 




../Drivers/STM32L0xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32L0xx/Include/C:\Keil_v5\ARM\ARMCC\Bin\..\include\stm32l0xx_hal_def.h
stm32l0xx.hLegacy/stm32_hal_legacy.h
stddef.h

\

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM‹
HAL_OKHAL_ERROR
HAL_BUSYHAL_TIMEOUTPHAL_StatusTypeDefÔ
,Ç
HAL_UNLOCKEDHAL_LOCKED
PHAL_LockTypeDef$

5
óôõ

__STM32L0xx_HAL_RCC_EX_H 
VIS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
\IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
bIS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
gIS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
lIS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
qIS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
„
IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK1) || ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
‰
IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
Œ
IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
•RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19)
žRCC_PERIPHCLK_USART1 (0x00000001U)
 RCC_PERIPHCLK_USART2 (0x00000002U)
¡RCC_PERIPHCLK_LPUART1 (0x00000004U)
¢RCC_PERIPHCLK_I2C1 (0x00000008U)
£RCC_PERIPHCLK_I2C2 (0x00000010U)
¤RCC_PERIPHCLK_RTC (0x00000020U)
¨RCC_PERIPHCLK_LPTIM1 (0x00000080U)
­RCC_PERIPHCLK_I2C3 (0x00000100U)
¸RCC_USART1CLKSOURCE_PCLK2 (0x00000000U)
¹RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
ºRCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
»RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
ÄRCC_USART2CLKSOURCE_PCLK1 (0x00000000U)
ÅRCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
ÆRCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
ÇRCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
ÏRCC_LPUART1CLKSOURCE_PCLK1 (0x00000000U)
ÐRCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
ÑRCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
ÒRCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
ÚRCC_I2C1CLKSOURCE_PCLK1 (0x00000000U)
ÛRCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
ÜRCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
æRCC_I2C3CLKSOURCE_PCLK1 (0x00000000U)
çRCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
èRCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
ñRCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
òRCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
žRCC_LPTIM1CLKSOURCE_PCLK1 (0x00000000U)
ŸRCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
 RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
¡RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
ªRCC_STOP_WAKEUPCLOCK_MSI (0x00000000U)
«RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
´RCC_LSEDRIVE_LOW (0x00000000U)
µRCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
¶RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
·RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
ù__HAL_RCC_GPIOE_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); UNUSED(tmpreg); } while(0)
__HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
ƒ__HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != 0U)
„__HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == 0U)
ˆ__HAL_RCC_GPIOD_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); UNUSED(tmpreg); } while(0)
__HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
‘__HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U)
’__HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U)
ˆ__HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
‰__HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
Š__HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
‹__HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
Œ__HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
__HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
Ž__HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
__HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
__HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
‘__HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
’__HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
“__HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
”__HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
•__HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
—__HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
˜__HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
™__HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
š__HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
›__HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
œ__HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
__HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
ž__HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
Ÿ__HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
 __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
¡__HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
¢__HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
£__HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
¤__HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
¦__HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U)
§__HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != 0U)
¨__HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U)
©__HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != 0U)
ª__HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U)
«__HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)
¬__HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != 0U)
­__HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != 0U)
®__HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U)
¯__HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U)
°__HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U)
±__HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != 0U)
²__HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U)
³__HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U)
´__HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U)
µ__HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == 0U)
¶__HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U)
·__HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == 0U)
¸__HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U)
¹__HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)
º__HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == 0U)
»__HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == 0U)
¼__HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U)
½__HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U)
¾__HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U)
¿__HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == 0U)
À__HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U)
Á__HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U)
×__HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
Ù__HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
Û__HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
Ü__HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
Ý__HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
ß__HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
á__HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
ã__HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
ä__HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
å__HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
ç__HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
è__HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
ë__HAL_RCC_TIM21_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != 0U)
í__HAL_RCC_TIM22_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != 0U)
ï__HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != 0U)
ð__HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
ñ__HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
ó__HAL_RCC_TIM21_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN) == 0U)
õ__HAL_RCC_TIM22_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN) == 0U)
÷__HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == 0U)
ø__HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN) == 0U)
ù__HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN) == 0U)
û__HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != 0U)
ü__HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN) == 0U)
¤__HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
¦__HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
­__HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
®__HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
å__HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
æ__HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
ç__HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
è__HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
é__HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
ê__HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
ë__HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
ì__HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
í__HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
î__HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
ï__HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
ð__HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
ñ__HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
ò__HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
ô__HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
õ__HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
ö__HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
÷__HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
ø__HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
ù__HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
ú__HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
û__HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
ü__HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
ý__HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
þ__HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
ÿ__HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
€__HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
__HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
¢__HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
£__HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
¤__HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
¥__HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
¦__HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
¨__HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
©__HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
ª__HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
«__HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
¬__HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
ø__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
ù__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
û__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != 0U)
ü__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == 0U)
‚    __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
ƒ    __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
…    __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != 0U)
†    __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == 0U)
Æ    __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Ç    __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
È    __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
É    __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
Ê    __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
Ë    __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Ì    __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
Í    __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
Π   __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Ï    __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
Р   __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
Ñ    __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
Ò    __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
Ó    __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
Õ    __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
Ö    __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
×    __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
Ø    __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
Ù    __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
Ú    __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
Û    __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
Ü    __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
Ý    __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
Þ    __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
ß    __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
à    __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
á    __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
â    __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
ä    __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U)
å    __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != 0U)
æ    __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U)
ç    __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != 0U)
è    __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U)
é    __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U)
ê    __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != 0U)
ë    __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != 0U)
ì    __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U)
í    __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U)
î    __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U)
ï    __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != 0U)
ð    __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U)
ñ    __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U)
ò    __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U)
ó    __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == 0U)
ô    __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U)
õ    __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == 0U)
ö    __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U)
÷    __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U)
ø    __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == 0U)
ù    __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == 0U)
ú    __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U)
û    __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U)
ü    __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U)
ý    __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == 0U)
þ    __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U)
ÿ    __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U)
Ê
__HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
Ì
__HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
Î
__HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
Ï
__HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
Ð
__HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
Ò
__HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
Ô
__HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
Ö
__HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
×
__HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
Ø
__HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
Ú
__HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != 0U)
Ü
__HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != 0U)
Þ
__HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != 0U)
ß
__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
à
__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
â
__HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN) == 0U)
ä
__HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN) == 0U)
æ
__HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN) == 0U)
ç
__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN) == 0U)
è
__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN) == 0U)
ù
__HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
ÿ
__HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
…__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
‹__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
’__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
™__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
¦__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
¬__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); } while(0)
¶__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); } while(0)
À__HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
Æ__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
Ì__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
ü__HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
…__HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
__HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
™__HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
§__HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
±__HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
½__HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Ç__HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Ò__HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Ü__HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
ç__HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
ñ__HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
´ __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
» __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
Ç __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Ò __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
å__HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
ë__HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h
stm32l0xx_hal_def.h


ä

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*Å PeriphClockSelectionY
#RTCClockSelectionY
#Usart1ClockSelectionY
#Usart2ClockSelectionY
#Lpuart1ClockSelectionY
#I2c1ClockSelectionY
#I2c3ClockSelectionY
#LptimClockSelectionY
#PRCC_PeriphCLKInitTypeDef×
Ò

÷øù

__STM32L0xx_HAL_RCC_H 
.RCC_DBP_TIMEOUT_VALUE (100U)
0RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1CLOCKSWITCH_TIMEOUT_VALUE (5000U)
2HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
3MSI_TIMEOUT_VALUE (2U)
4HSI_TIMEOUT_VALUE (2U)
5LSI_TIMEOUT_VALUE (2U)
6PLL_TIMEOUT_VALUE (2U)
CRCC_OFFSET (RCC_BASE - PERIPH_BASE)
FRCC_CR_OFFSET (RCC_OFFSET + 0x00U)
IRCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
KRCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
NRCC_CR_BYTE2_ADDRESS (0x40023802U)
QCIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
XCR_REG_INDEX ((uint8_t)1)
YCSR_REG_INDEX ((uint8_t)2)
ZCRRCR_REG_INDEX ((uint8_t)3)
\RCC_FLAG_MASK ((uint8_t)0x1F)
pIS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
wIS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
yIS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
{IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
~IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_ON)) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_DIV4)))
…
IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
†
IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
‡
IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || ((__RANGE__) == RCC_MSIRANGE_1) || ((__RANGE__) == RCC_MSIRANGE_2) || ((__RANGE__) == RCC_MSIRANGE_3) || ((__RANGE__) == RCC_MSIRANGE_4) || ((__RANGE__) == RCC_MSIRANGE_5) || ((__RANGE__) == RCC_MSIRANGE_6))
Ž
IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
‘
IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
“
IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
–
IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || ((__MUL__) == RCC_PLL_MUL48))
›
IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
Ÿ
IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
£
IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
§
IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
¬
IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
°
IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2) || ((__MCO__) == RCC_MCO3))
µ
IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || ((__DIV__) == RCC_MCODIV_16))
¿
IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Ä
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
³RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
´RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
½RCC_OSCILLATORTYPE_NONE (0x00000000U)
¾RCC_OSCILLATORTYPE_HSE (0x00000001U)
¿RCC_OSCILLATORTYPE_HSI (0x00000002U)
ÀRCC_OSCILLATORTYPE_LSE (0x00000004U)
ÁRCC_OSCILLATORTYPE_LSI (0x00000008U)
ÂRCC_OSCILLATORTYPE_MSI (0x00000010U)
ÍRCC_HSE_OFF (0x00000000U)
ÎRCC_HSE_ON RCC_CR_HSEON
ÏRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
×RCC_LSE_OFF (0x00000000U)
ØRCC_LSE_ON RCC_CSR_LSEON
ÙRCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))
âRCC_HSI_OFF (0x00000000U)
ãRCC_HSI_ON RCC_CR_HSION
äRCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)
æRCC_HSI_OUTEN RCC_CR_HSIOUTEN
êRCC_HSICALIBRATION_DEFAULT (0x10U)
ôRCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0
õRCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1
öRCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2
÷RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3
øRCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4
ùRCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5
úRCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6
ƒRCC_LSI_OFF (0x00000000U)
„RCC_LSI_ON RCC_CSR_LSION
RCC_MSI_OFF (0x00000000U)
ŽRCC_MSI_ON (0x00000001U)
RCC_MSICALIBRATION_DEFAULT (0x00000000U)
¥RCC_PLL_NONE (0x00000000U)
¦RCC_PLL_OFF (0x00000001U)
§RCC_PLL_ON (0x00000002U)
°RCC_CLOCKTYPE_SYSCLK (0x00000001U)
±RCC_CLOCKTYPE_HCLK (0x00000002U)
²RCC_CLOCKTYPE_PCLK1 (0x00000004U)
³RCC_CLOCKTYPE_PCLK2 (0x00000008U)
¼RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
½RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
¾RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
¿RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
ÈRCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
ÉRCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
ÊRCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
ËRCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
ÔRCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
ÕRCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
ÖRCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
×RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
ØRCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
ÙRCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
ÚRCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
ÛRCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
ÜRCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
åRCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
æRCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
çRCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
èRCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
éRCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
òRCC_RTC_HSE_DIV_2 (0x00000000U)
óRCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0
ôRCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1
õRCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE
ýRCC_RTCCLKSOURCE_NO_CLK (0x00000000U)
þRCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
ÿRCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
€RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE)
‚RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE)
ƒRCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE)
„RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)
RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
ŽRCC_PLL_DIV3 RCC_CFGR_PLLDIV3
RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
™RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
šRCC_PLL_MUL4 RCC_CFGR_PLLMUL4
›RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
œRCC_PLL_MUL8 RCC_CFGR_PLLMUL8
RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
žRCC_PLL_MUL16 RCC_CFGR_PLLMUL16
ŸRCC_PLL_MUL24 RCC_CFGR_PLLMUL24
 RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
¡RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
ªRCC_MCO1 (0x00000000U)
«RCC_MCO2 (0x00000001U)
­RCC_MCO3 (0x00000002U)
±MCO3_GPIO_AF GPIO_AF2_MCO
¼RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
½RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
¾RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
¿RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
ÀRCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
ÉRCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
ÊRCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
ËRCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
ÌRCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
ÍRCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
ÎRCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
ÏRCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
ÐRCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
ÛRCC_IT_LSIRDY RCC_CIFR_LSIRDYF
ÜRCC_IT_LSERDY RCC_CIFR_LSERDYF
ÝRCC_IT_HSIRDY RCC_CIFR_HSIRDYF
ÞRCC_IT_HSERDY RCC_CIFR_HSERDYF
ßRCC_IT_PLLRDY RCC_CIFR_PLLRDYF
àRCC_IT_MSIRDY RCC_CIFR_MSIRDYF
áRCC_IT_LSECSS RCC_CIFR_CSSLSEF
ãRCC_IT_CSS RCC_CIFR_CSSHSEF
÷RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_Pos))
øRCC_FLAG_HSIDIV ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIDIVF_Pos))
ùRCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_MSIRDY_Pos))
úRCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_Pos))
ûRCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_Pos))
ýRCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_Pos))
þRCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSERDY_Pos))
ÿRCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSECSSD_Pos))
€RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_Pos))
RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_Pos))
‚RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_Pos))
ƒRCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_Pos))
„RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_Pos))
…RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_Pos))
†RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_Pos))
ˆRCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_FWRSTF_Pos))
¤__HAL_RCC_DMA1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); UNUSED(tmpreg); } while(0)
¬__HAL_RCC_MIF_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN); UNUSED(tmpreg); } while(0)
´__HAL_RCC_CRC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); UNUSED(tmpreg); } while(0)
½__HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
¾__HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
¿__HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
Ì__HAL_RCC_GPIOA_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); UNUSED(tmpreg); } while(0)
Ô__HAL_RCC_GPIOB_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); UNUSED(tmpreg); } while(0)
Ü__HAL_RCC_GPIOC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); UNUSED(tmpreg); } while(0)
ä__HAL_RCC_GPIOH_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN); tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN); UNUSED(tmpreg); } while(0)
í__HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
î__HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
ï__HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
ð__HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
ý__HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
þ__HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
€__HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
__HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
__HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
Ž__HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
__HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
‘__HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
ž__HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
Ÿ__HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != 0U)
 __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)
¡__HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)
¢__HAL_RCC_MIF_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == 0U)
£__HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)
±__HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U)
²__HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U)
³__HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U)
´__HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != 0U)
µ__HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U)
¶__HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U)
·__HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U)
¸__HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == 0U)
Å__HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != 0U)
Æ__HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U)
Ç__HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == 0U)
È__HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U)
Õ__HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
Ö__HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != 0U)
×__HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
Ø__HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == 0U)
â__HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
ã__HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
ä__HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
å__HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
ç__HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
è__HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
é__HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
ê__HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
ó__HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU)
ô__HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
õ__HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
ö__HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
÷__HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
ù__HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00000000U)
ú__HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
û__HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
ü__HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
ý__HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
‡__HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
ˆ__HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
‰__HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
‹__HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
Œ__HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
__HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
—__HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
˜__HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
™__HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
›__HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
œ__HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
__HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
«__HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
¬__HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
­__HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
®__HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
°__HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
±__HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
²__HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
³__HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
Á__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
Â__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
Ã__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
Ä__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
Æ__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
Ç__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
È__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
É__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
Ö__HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
×__HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
Ù__HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
Ú__HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
è__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
é__HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
ë__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
ì__HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
ú__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != 0U)
û__HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != 0U)
ü__HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != 0U)
ý__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != 0U)
þ__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == 0U)
ÿ__HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == 0U)
€__HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == 0U)
__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == 0U)
__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != 0U)
__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != 0U)
‘__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != 0U)
’__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != 0U)
“__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == 0U)
”__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == 0U)
•__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == 0U)
–__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == 0U)
¤__HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != 0U)
¥__HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != 0U)
¦__HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == 0U)
§__HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == 0U)
µ__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
¶__HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != 0U)
·__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
¸__HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == 0U)
Ñ__HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
â__HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
ã__HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
ì__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
ü__HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
ƒ    __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
£    __HAL_RCC_HSE_CONFIG(__STATE__) do{ __IO uint32_t tmpreg; if ((__STATE__) == RCC_HSE_ON) { SET_BIT(RCC->CR, RCC_CR_HSEON); } else if ((__STATE__) == RCC_HSE_BYPASS) { SET_BIT(RCC->CR, RCC_CR_HSEBYP); SET_BIT(RCC->CR, RCC_CR_HSEON); } else { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); UNUSED(tmpreg); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } }while(0)
Ò    __HAL_RCC_LSE_CONFIG(__STATE__) do{ if ((__STATE__) == RCC_LSE_ON) { SET_BIT(RCC->CSR, RCC_CSR_LSEON); } else if ((__STATE__) == RCC_LSE_OFF) { CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); } else if ((__STATE__) == RCC_LSE_BYPASS) { SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); SET_BIT(RCC->CSR, RCC_CSR_LSEON); } else { CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); } }while(0)
ö    __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
ƒ
__HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
Ž
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
 
__HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
®
__HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
¾
__HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Ã
__HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
á
__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__,__PLLMUL__,__PLLDIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
ê
__HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
ý
__HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
ˆ__HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
¶__HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__,__MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Û__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) { MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); } } while (0)
â__HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); } while (0)
î__HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
ú__HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
ÿ__HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
„__HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
‹__HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
__HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
¬__HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
À__HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Ï__HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Þ__HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
å__HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
€ __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )Œ Œ€
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h
stm32l0xx_hal_def.h
stm32l0xx_hal_rcc_ex.h


¸
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*žPLLStateY
#PLLSourceY
#PLLMULY
#PLLDIVY
#PRCC_PLLInitTypeDefÔ
æ
*Œ4OscillatorTypeY
#HSEStateY
#LSEStateY
#HSIStateY
#HSICalibrationValueY
#LSIStateY
#MSIStateY
#MSICalibrationValueY
#MSIClockRangeY
# PLL
#$PRCC_OscInitTypeDef9

*œClockTypeY
#SYSCLKSourceY
#AHBCLKDividerY
#APB1CLKDividerY
#APB2CLKDividerY
#PRCC_ClkInitTypeDef'
¤
ûüý

__STM32L0xx_HAL_EXTI_H 
ZEXTI_LINE_0 (EXTI_GPIO | 0x00u)
[EXTI_LINE_1 (EXTI_GPIO | 0x01u)
\EXTI_LINE_2 (EXTI_GPIO | 0x02u)
]EXTI_LINE_3 (EXTI_GPIO | 0x03u)
^EXTI_LINE_4 (EXTI_GPIO | 0x04u)
_EXTI_LINE_5 (EXTI_GPIO | 0x05u)
`EXTI_LINE_6 (EXTI_GPIO | 0x06u)
aEXTI_LINE_7 (EXTI_GPIO | 0x07u)
bEXTI_LINE_8 (EXTI_GPIO | 0x08u)
cEXTI_LINE_9 (EXTI_GPIO | 0x09u)
dEXTI_LINE_10 (EXTI_GPIO | 0x0Au)
eEXTI_LINE_11 (EXTI_GPIO | 0x0Bu)
fEXTI_LINE_12 (EXTI_GPIO | 0x0Cu)
gEXTI_LINE_13 (EXTI_GPIO | 0x0Du)
hEXTI_LINE_14 (EXTI_GPIO | 0x0Eu)
iEXTI_LINE_15 (EXTI_GPIO | 0x0Fu)
kEXTI_LINE_16 (EXTI_CONFIG | 0x10u)
oEXTI_LINE_17 (EXTI_CONFIG | 0x11u)
qEXTI_LINE_18 (EXTI_DIRECT | 0x12u)
uEXTI_LINE_19 (EXTI_CONFIG | 0x13u)
vEXTI_LINE_20 (EXTI_CONFIG | 0x14u)
xEXTI_LINE_21 (EXTI_CONFIG | 0x15u)
}EXTI_LINE_22 (EXTI_CONFIG | 0x16u)

EXTI_LINE_23 (EXTI_DIRECT | 0x17u)
ƒ
EXTI_LINE_24 (EXTI_DIRECT | 0x18u)
ˆ
EXTI_LINE_25 (EXTI_DIRECT | 0x19u)
Œ
EXTI_LINE_26 (EXTI_DIRECT | 0x1Au)

EXTI_LINE_27 (EXTI_RESERVED | 0x1Bu)
Ž
EXTI_LINE_28 (EXTI_DIRECT | 0x1Cu)

EXTI_LINE_29 (EXTI_DIRECT | 0x1Du)
˜
EXTI_MODE_NONE 0x00000000u
™
EXTI_MODE_INTERRUPT 0x00000001u
š
EXTI_MODE_EVENT 0x00000002u
¢
EXTI_TRIGGER_NONE 0x00000000u
£
EXTI_TRIGGER_RISING 0x00000001u
¤
EXTI_TRIGGER_FALLING 0x00000002u
¥
EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
®
EXTI_GPIOA 0x00000000u
¯
EXTI_GPIOB 0x00000001u
°
EXTI_GPIOC 0x00000002u
²
EXTI_GPIOD 0x00000003u
µ
EXTI_GPIOE 0x00000004u
¸
EXTI_GPIOH 0x00000007u
Ò
EXTI_PROPERTY_SHIFT 24u
Ó
EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
Ô
EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
Õ
EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
Ö
EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
×
EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
Ü
EXTI_PIN_MASK 0x0000001Fu
á
EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
æ
EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
ë
EXTI_LINE_NB 30u
õ
IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
ú
IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
ý
IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
ÿ
IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
“IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOH))
›IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)˜
 




../Drivers/STM32L0xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx_hal_exti.h
stm32l0xx.h

ì

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM¦
HAL_EXTI_COMMON_CB_IDHAL_EXTI_RISING_CB_ID
HAL_EXTI_FALLING_CB_IDPEXTI_CallbackIDTypeDefÕ
0*öLineY
#OÚ"V
PendingCallbackZ
#PEXTI_HandleTypeDefD

:*ÓLineY
#ModeY
#TriggerY
#GPIOSelY
#PEXTI_ConfigTypeDef

J
ÿ


__STM32L0xx_HAL_GPIO_EX_H 
ŠGPIO_AF0_EVENTOUT ((uint8_t)0x00U)
‹GPIO_AF0_TIM21 ((uint8_t)0x00U)
ŒGPIO_AF0_SPI1 ((uint8_t)0x00U)
GPIO_AF0_MCO ((uint8_t)0x00U)
ŽGPIO_AF0_SWDIO ((uint8_t)0x00U)
GPIO_AF0_SWCLK ((uint8_t)0x00U)
GPIO_AF0_USART1 ((uint8_t)0x00U)
‘GPIO_AF0_SPI2 ((uint8_t)0x00U)
’GPIO_AF0_LPTIM1 ((uint8_t)0x00U)
“GPIO_AF0_TIM22 ((uint8_t)0x00U)
”GPIO_AF0_LPUART1 ((uint8_t)0x00U)
•GPIO_AF0_USART2 ((uint8_t)0x00U)
–GPIO_AF0_TIM2 ((uint8_t)0x00U)
ŸGPIO_AF1_I2C1 ((uint8_t)0x01U)
 GPIO_AF1_SPI2 ((uint8_t)0x01U)
¡GPIO_AF1_TIM21 ((uint8_t)0x01U)
ªGPIO_AF2_TIM2 ((uint8_t)0x02U)
«GPIO_AF2_TIM3 ((uint8_t)0x02U)
¬GPIO_AF2_EVENTOUT ((uint8_t)0x02U)
­GPIO_AF2_LPTIM1 ((uint8_t)0x02U)
®GPIO_AF2_LPUART1 ((uint8_t)0x02U)
¯GPIO_AF2_MCO ((uint8_t)0x02U)
°GPIO_AF2_RTC ((uint8_t)0x02U)
±GPIO_AF2_SPI2 ((uint8_t)0x02U)
²GPIO_AF2_USART5 ((uint8_t)0x02U)
³GPIO_AF2_SPI1 ((uint8_t)0x02U)
¼GPIO_AF3_EVENTOUT ((uint8_t)0x03U)
½GPIO_AF3_I2C1 ((uint8_t)0x03U)
ÆGPIO_AF4_USART2 ((uint8_t)0x04U)
ÇGPIO_AF4_LPUART1 ((uint8_t)0x04U)
ÈGPIO_AF4_USART1 ((uint8_t)0x04U)
ÉGPIO_AF4_EVENTOUT ((uint8_t)0x04U)
ÊGPIO_AF4_TIM22 ((uint8_t)0x04U)
ËGPIO_AF4_TIM3 ((uint8_t)0x04U)
ÌGPIO_AF4_I2C1 ((uint8_t)0x04U)
ÕGPIO_AF5_TIM2 ((uint8_t)0x05U)
ÖGPIO_AF5_TIM21 ((uint8_t)0x05U)
×GPIO_AF5_TIM22 ((uint8_t)0x05U)
ØGPIO_AF5_USART1 ((uint8_t)0x05U)
ÙGPIO_AF5_SPI2 ((uint8_t)0x05U)
ÚGPIO_AF5_I2C2 ((uint8_t)0x05U)
ãGPIO_AF6_USART4 ((uint8_t)0x06U)
äGPIO_AF6_LPUART1 ((uint8_t)0x06U)
åGPIO_AF6_EVENTOUT ((uint8_t)0x06U)
æGPIO_AF6_I2C1 ((uint8_t)0x06U)
çGPIO_AF6_I2C2 ((uint8_t)0x06U)
èGPIO_AF6_USART5 ((uint8_t)0x06U)
éGPIO_AF6_TIM21 ((uint8_t)0x06U)
òGPIO_AF7_COMP1 ((uint8_t)0x07U)
óGPIO_AF7_COMP2 ((uint8_t)0x07U)
ôGPIO_AF7_I2C3 ((uint8_t)0x07U)
õGPIO_AF7_LPUART1 ((uint8_t)0x07U)
‰IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
¢GPIOA_PIN_AVAILABLE GPIO_PIN_All
£GPIOB_PIN_AVAILABLE GPIO_PIN_All
¤GPIOC_PIN_AVAILABLE GPIO_PIN_All
¥GPIOD_PIN_AVAILABLE GPIO_PIN_All
¦GPIOE_PIN_AVAILABLE GPIO_PIN_All
§GPIOH_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_9 | GPIO_PIN_10)
²GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U : ((__GPIOx__) == (GPIOB))? 1U : ((__GPIOx__) == (GPIOC))? 2U : ((__GPIOx__) == (GPIOD))? 3U : ((__GPIOx__) == (GPIOE))? 4U : ((__GPIOx__) == (GPIOH))? 5U : 6U)
¹IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))tj
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h
stm32l0xx_hal_def.h


Ø
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM


__STM32L0xx_HAL_GPIO_H 
XIS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET))
hGPIO_PIN_0 (0x0001U)
iGPIO_PIN_1 (0x0002U)
jGPIO_PIN_2 (0x0004U)
kGPIO_PIN_3 (0x0008U)
lGPIO_PIN_4 (0x0010U)
mGPIO_PIN_5 (0x0020U)
nGPIO_PIN_6 (0x0040U)
oGPIO_PIN_7 (0x0080U)
pGPIO_PIN_8 (0x0100U)
qGPIO_PIN_9 (0x0200U)
rGPIO_PIN_10 (0x0400U)
sGPIO_PIN_11 (0x0800U)
tGPIO_PIN_12 (0x1000U)
uGPIO_PIN_13 (0x2000U)
vGPIO_PIN_14 (0x4000U)
wGPIO_PIN_15 (0x8000U)
xGPIO_PIN_All (0xFFFFU)
}GPIO_PIN_MASK (0x0000FFFFU)
~IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) && (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
Š
GPIO_MODE_INPUT MODE_INPUT
‹
GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
Œ
GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)

GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
Ž
GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)

GPIO_MODE_ANALOG MODE_ANALOG
’
GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
“
GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
”
GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
–
GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
—
GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
˜
GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)
ž
IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) || ((__MODE__) == GPIO_MODE_OUTPUT_PP) || ((__MODE__) == GPIO_MODE_OUTPUT_OD) || ((__MODE__) == GPIO_MODE_AF_PP) || ((__MODE__) == GPIO_MODE_AF_OD) || ((__MODE__) == GPIO_MODE_IT_RISING) || ((__MODE__) == GPIO_MODE_IT_FALLING) || ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) || ((__MODE__) == GPIO_MODE_EVT_RISING) || ((__MODE__) == GPIO_MODE_EVT_FALLING) || ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) || ((__MODE__) == GPIO_MODE_ANALOG))
°
GPIO_SPEED_FREQ_LOW (0x00000000U)
±
GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
²
GPIO_SPEED_FREQ_HIGH (0x00000002U)
³
GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)
¹
IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW ) || ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM ) || ((__SPEED__) == GPIO_SPEED_FREQ_HIGH ) || ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
Á
GPIO_NOPULL (0x00000000U)
Â
GPIO_PULLUP (0x00000001U)
Ã
GPIO_PULLDOWN (0x00000002U)
É
IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || ((__PULL__) == GPIO_PULLDOWN))
Ý
__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
å
__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
í
__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
õ
__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
ý
__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))ƒ
¯GPIO_MODE_Pos 0U
°GPIO_MODE (0x3UL << GPIO_MODE_Pos)
±MODE_INPUT (0x0UL << GPIO_MODE_Pos)
²MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
³MODE_AF (0x2UL << GPIO_MODE_Pos)
´MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
µOUTPUT_TYPE_Pos 4U
¶OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
·OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
¸OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
¹EXTI_MODE_Pos 16U
ºEXTI_MODE (0x3UL << EXTI_MODE_Pos)
»EXTI_IT (0x1UL << EXTI_MODE_Pos)
¼EXTI_EVT (0x2UL << EXTI_MODE_Pos)
½TRIGGER_MODE_Pos 20U
¾TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
¿TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
ÀTRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)Œ‚
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h
stm32l0xx_hal_def.h
stm32l0xx_hal_gpio_ex.h


x

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*¥PinY
#ModeY
#PullY
#SpeedY
#AlternateY
#PGPIO_InitTypeDefÕ
Cä
GPIO_PIN_RESETGPIO_PIN_SET
PGPIO_PinState=

R
    

STM32L0xx_HAL_DMA_H 
™
HAL_DMA_ERROR_NONE 0x00000000U
š
HAL_DMA_ERROR_TE 0x00000001U
›
HAL_DMA_ERROR_NO_XFER 0x00000004U
œ
HAL_DMA_ERROR_TIMEOUT 0x00000020U

HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
á
DMA_REQUEST_0 0U
â
DMA_REQUEST_1 1U
ã
DMA_REQUEST_2 2U
ä
DMA_REQUEST_3 3U
å
DMA_REQUEST_4 4U
æ
DMA_REQUEST_5 5U
ç
DMA_REQUEST_6 6U
è
DMA_REQUEST_7 7U
é
DMA_REQUEST_8 8U
ê
DMA_REQUEST_9 9U
ë
DMA_REQUEST_10 10U
ì
DMA_REQUEST_12 12U
í
DMA_REQUEST_13 13U
î
DMA_REQUEST_14 14U
ï
DMA_REQUEST_15 15U
ñ
IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || ((REQUEST) == DMA_REQUEST_1) || ((REQUEST) == DMA_REQUEST_2) || ((REQUEST) == DMA_REQUEST_3) || ((REQUEST) == DMA_REQUEST_4) || ((REQUEST) == DMA_REQUEST_5) || ((REQUEST) == DMA_REQUEST_6) || ((REQUEST) == DMA_REQUEST_7) || ((REQUEST) == DMA_REQUEST_8) || ((REQUEST) == DMA_REQUEST_9) || ((REQUEST) == DMA_REQUEST_10) || ((REQUEST) == DMA_REQUEST_12) || ((REQUEST) == DMA_REQUEST_13) || ((REQUEST) == DMA_REQUEST_14) || ((REQUEST) == DMA_REQUEST_15))
ŒDMA_PERIPH_TO_MEMORY 0x00000000U
DMA_MEMORY_TO_PERIPH DMA_CCR_DIR
ŽDMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
–DMA_PINC_ENABLE DMA_CCR_PINC
—DMA_PINC_DISABLE 0x00000000U
ŸDMA_MINC_ENABLE DMA_CCR_MINC
 DMA_MINC_DISABLE 0x00000000U
¨DMA_PDATAALIGN_BYTE 0x00000000U
©DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
ªDMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
²DMA_MDATAALIGN_BYTE 0x00000000U
³DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
´DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
¼DMA_NORMAL 0x00000000U
½DMA_CIRCULAR DMA_CCR_CIRC
ÅDMA_PRIORITY_LOW 0x00000000U
ÆDMA_PRIORITY_MEDIUM DMA_CCR_PL_0
ÇDMA_PRIORITY_HIGH DMA_CCR_PL_1
ÈDMA_PRIORITY_VERY_HIGH DMA_CCR_PL
ÑDMA_IT_TC DMA_CCR_TCIE
ÒDMA_IT_HT DMA_CCR_HTIE
ÓDMA_IT_TE DMA_CCR_TEIE
ÛDMA_FLAG_GL1 DMA_ISR_GIF1
ÜDMA_FLAG_TC1 DMA_ISR_TCIF1
ÝDMA_FLAG_HT1 DMA_ISR_HTIF1
ÞDMA_FLAG_TE1 DMA_ISR_TEIF1
ßDMA_FLAG_GL2 DMA_ISR_GIF2
àDMA_FLAG_TC2 DMA_ISR_TCIF2
áDMA_FLAG_HT2 DMA_ISR_HTIF2
âDMA_FLAG_TE2 DMA_ISR_TEIF2
ãDMA_FLAG_GL3 DMA_ISR_GIF3
äDMA_FLAG_TC3 DMA_ISR_TCIF3
åDMA_FLAG_HT3 DMA_ISR_HTIF3
æDMA_FLAG_TE3 DMA_ISR_TEIF3
çDMA_FLAG_GL4 DMA_ISR_GIF4
èDMA_FLAG_TC4 DMA_ISR_TCIF4
éDMA_FLAG_HT4 DMA_ISR_HTIF4
êDMA_FLAG_TE4 DMA_ISR_TEIF4
ëDMA_FLAG_GL5 DMA_ISR_GIF5
ìDMA_FLAG_TC5 DMA_ISR_TCIF5
íDMA_FLAG_HT5 DMA_ISR_HTIF5
îDMA_FLAG_TE5 DMA_ISR_TEIF5
ïDMA_FLAG_GL6 DMA_ISR_GIF6
ðDMA_FLAG_TC6 DMA_ISR_TCIF6
ñDMA_FLAG_HT6 DMA_ISR_HTIF6
òDMA_FLAG_TE6 DMA_ISR_TEIF6
óDMA_FLAG_GL7 DMA_ISR_GIF7
ôDMA_FLAG_TC7 DMA_ISR_TCIF7
õDMA_FLAG_HT7 DMA_ISR_HTIF7
öDMA_FLAG_TE7 DMA_ISR_TEIF7
ˆ__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
__HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
–__HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
©__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 : DMA_FLAG_TC7)
¿__HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 : DMA_FLAG_HT7)
Õ__HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 : DMA_FLAG_TE7)
ë__HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 : DMA_ISR_GIF7)
€__HAL_DMA_GET_FLAG(__HANDLE__,__FLAG__) (DMA1->ISR & (__FLAG__))
Ž__HAL_DMA_CLEAR_FLAG(__HANDLE__,__FLAG__) (DMA1->IFCR = (__FLAG__))
š__HAL_DMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
¦__HAL_DMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
²__HAL_DMA_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
¹__HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
óIS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
÷IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
ùIS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
üIS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
ÿIS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
ƒIS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD ))
‡IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || ((MODE) == DMA_CIRCULAR))
ŠIS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))pf
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h
stm32l0xx_hal_def.h


ˆ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARMuvoid"Ô"MtY
"žPDMA_InitTypeDef€

JPHAL_DMA_StateTypeDef#
UPHAL_DMA_LevelCompleteTypeDef…
^PHAL_DMA_CallbackIDTypeDef¼
kPDMA_HandleTypeDefM
Š
*£ RequestY
#DirectionY
#PeriphIncY
#MemIncY
#PeriphDataAlignmentY
#MemDataAlignmentY
#ModeY
#PriorityY
#…
HAL_DMA_STATE_RESETHAL_DMA_STATE_READY
HAL_DMA_STATE_BUSYHAL_DMA_STATE_TIMEOUT¼
HAL_DMA_FULL_TRANSFERHAL_DMA_HALF_TRANSFER
Í
HAL_DMA_XFER_CPLT_CB_IDHAL_DMA_XFER_HALFCPLT_CB_ID
HAL_DMA_XFER_ERROR_CB_IDHAL_DMA_XFER_ABORT_CB_IDHAL_DMA_XFER_ALL_CB_ID)þ__DMA_HandleTypeDefHInstance~#Initî#LockG
#$State„#%ParentÚ#(O²%Þ"ªXferCpltCallback²#,OÖ%Þ"ÎXferHalfCpltCallbackÖ#0Oþ%Þ"öXferErrorCallbackþ#4O£%Þ"XferAbortCallback##8ErrorCodeâ#<DmaBaseAddressè#@ChannelIndexY
#D"ft

 

__STM32L0xx_HAL_CORTEX_H 
ZIS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x10U)
\IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0)
aSYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
bSYSTICK_CLKSOURCE_HCLK (0x00000004U)
cIS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
mMPU_HFNMI_PRIVDEF_NONE (0x00000000U)
nMPU_HARDFAULT_NMI (0x00000002U)
oMPU_PRIVILEGED_DEFAULT (0x00000004U)
pMPU_HFNMI_PRIVDEF (0x00000006U)
xMPU_REGION_ENABLE ((uint8_t)0x01)
yMPU_REGION_DISABLE ((uint8_t)0x00)

MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
‚
MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
Š
MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
‹
MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
“
MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
”
MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
œ
MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
¥
MPU_REGION_SIZE_32B ((uint8_t)0x04)
¦
MPU_REGION_SIZE_64B ((uint8_t)0x05)
§
MPU_REGION_SIZE_128B ((uint8_t)0x06)
¨
MPU_REGION_SIZE_256B ((uint8_t)0x07)
©
MPU_REGION_SIZE_512B ((uint8_t)0x08)
ª
MPU_REGION_SIZE_1KB ((uint8_t)0x09)
«
MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
¬
MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
­
MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
®
MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
¯
MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
°
MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
±
MPU_REGION_SIZE_128KB ((uint8_t)0x10)
²
MPU_REGION_SIZE_256KB ((uint8_t)0x11)
³
MPU_REGION_SIZE_512KB ((uint8_t)0x12)
´
MPU_REGION_SIZE_1MB ((uint8_t)0x13)
µ
MPU_REGION_SIZE_2MB ((uint8_t)0x14)
¶
MPU_REGION_SIZE_4MB ((uint8_t)0x15)
·
MPU_REGION_SIZE_8MB ((uint8_t)0x16)
¸
MPU_REGION_SIZE_16MB ((uint8_t)0x17)
¹
MPU_REGION_SIZE_32MB ((uint8_t)0x18)
º
MPU_REGION_SIZE_64MB ((uint8_t)0x19)
»
MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
¼
MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
½
MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
¾
MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
¿
MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
À
MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
È
MPU_REGION_NO_ACCESS ((uint8_t)0x00)
É
MPU_REGION_PRIV_RW ((uint8_t)0x01)
Ê
MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
Ë
MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
Ì
MPU_REGION_PRIV_RO ((uint8_t)0x05)
Í
MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
Õ
MPU_REGION_NUMBER0 ((uint8_t)0x00)
Ö
MPU_REGION_NUMBER1 ((uint8_t)0x01)
×
MPU_REGION_NUMBER2 ((uint8_t)0x02)
Ø
MPU_REGION_NUMBER3 ((uint8_t)0x03)
Ù
MPU_REGION_NUMBER4 ((uint8_t)0x04)
Ú
MPU_REGION_NUMBER5 ((uint8_t)0x05)
Û
MPU_REGION_NUMBER6 ((uint8_t)0x06)
Ü
MPU_REGION_NUMBER7 ((uint8_t)0x07)
›IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
žIS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
¡IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
¤IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
§IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
ªIS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) || ((TYPE) == MPU_REGION_PRIV_RO_URO))
±IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
ºIS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
ÔIS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h
stm32l0xx_hal_def.h


Ü

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*¾BaseAddressY
#Enable:
#Number:
#Size:
#SubRegionDisable:
#TypeExtField:
#AccessPermission:
#    DisableExec:
#
IsShareable:
#IsCacheable:
#IsBufferable:
# PMPU_Region_InitTypeDef×
H


__STM32L0xx_HAL_ADC_EX_H 
0ADC_SINGLE_ENDED 0x00000000U
8ADC_EXTERNALTRIGCONV_T6_TRGO (0x00000000U)
9ADC_EXTERNALTRIGCONV_T21_CC2 (ADC_CFGR1_EXTSEL_0)
:ADC_EXTERNALTRIGCONV_T2_TRGO (ADC_CFGR1_EXTSEL_1)
;ADC_EXTERNALTRIGCONV_T2_CC4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
<ADC_EXTERNALTRIGCONV_T22_TRGO (ADC_CFGR1_EXTSEL_2)
=ADC_EXTERNALTRIGCONV_T3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1)
>ADC_EXTERNALTRIGCONV_EXT_IT11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
?ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + 1U)
IADC_EXTERNALTRIGCONV_T21_TRGO (ADC_EXTERNALTRIGCONV_T22_TRGO)
SADC_EXTERNALTRIGCONV_T2_CC3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0)
]ADC_FLAG_SENSOR SYSCFG_CFGR3_VREFINT_RDYF
^ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYF
mIS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) ((SING_DIFF) == ADC_SINGLE_ENDED)
wIS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
ƒ
IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3 ) || ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO ) || ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || ((CONV) == ADC_SOFTWARE_START))ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h
stm32l0xx_hal_def.h


Ø
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM


__STM32L0xx_HAL_ADC_H 
å
HAL_ADC_STATE_RESET (0x00000000U)
æ
HAL_ADC_STATE_READY (0x00000001U)
ç
HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U)
è
HAL_ADC_STATE_TIMEOUT (0x00000004U)
ë
HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U)
ì
HAL_ADC_STATE_ERROR_CONFIG (0x00000020U)
í
HAL_ADC_STATE_ERROR_DMA (0x00000040U)
ð
HAL_ADC_STATE_REG_BUSY (0x00000100U)
ò
HAL_ADC_STATE_REG_EOC (0x00000200U)
ó
HAL_ADC_STATE_REG_OVR (0x00000400U)
ô
HAL_ADC_STATE_REG_EOSMP (0x00000800U)
÷
HAL_ADC_STATE_INJ_BUSY (0x00001000U)
ù
HAL_ADC_STATE_INJ_EOC (0x00002000U)
ú
HAL_ADC_STATE_INJ_JQOVF (0x00004000U)
ý
HAL_ADC_STATE_AWD1 (0x00010000U)
þ
HAL_ADC_STATE_AWD2 (0x00020000U)
ÿ
HAL_ADC_STATE_AWD3 (0x00040000U)
‚HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U)
ÆHAL_ADC_ERROR_NONE (0x00U)
ÇHAL_ADC_ERROR_INTERNAL (0x01U)
ÉHAL_ADC_ERROR_OVR (0x02U)
ÊHAL_ADC_ERROR_DMA (0x04U)
ÜADC_ENABLE_TIMEOUT 10U
ÝADC_DISABLE_TIMEOUT 10U
ÞADC_STOP_CONVERSION_TIMEOUT 10U
âADC_DELAY_10US_MIN_CPU_CYCLES 1800U
êADC_CLOCK_ASYNC_DIV1 (0x00000000U)
ëADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
ìADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1)
íADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
îADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2)
ïADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
ðADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)
ñADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
òADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
óADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
ôADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
õADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
÷ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE)
ûADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0)
üADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1)
…ADC_RESOLUTION_12B (0x00000000U)
†ADC_RESOLUTION_10B (ADC_CFGR1_RES_0)
‡ADC_RESOLUTION_8B (ADC_CFGR1_RES_1)
ˆADC_RESOLUTION_6B (ADC_CFGR1_RES)
ADC_DATAALIGN_RIGHT (0x00000000U)
‘ADC_DATAALIGN_LEFT (ADC_CFGR1_ALIGN)
™ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
šADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR1_EXTEN_0)
›ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR1_EXTEN_1)
œADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR1_EXTEN)
¤ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
¥ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
­ADC_OVR_DATA_PRESERVED (0x00000000U)
®ADC_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD)
·ADC_RANK_CHANNEL_NUMBER (0x00001000U)
¸ADC_RANK_NONE (0x00001001U)
ÁADC_CHANNEL_0 (ADC_CHSELR_CHSEL0)
ÂADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)
ÃADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)
ÄADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
ÅADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)
ÆADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
ÇADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
ÈADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
ÉADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)
ÊADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)
ËADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)
ÌADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
ÍADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)
ÎADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
ÏADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
ÐADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
ÔADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
ÕADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
ÛADC_CHANNEL_VREFINT ADC_CHANNEL_17
ÝADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
æADC_CHANNEL_MASK (0x0007FFFFU)
çADC_CHANNEL_AWD_MASK (0x7C000000U)
ïADC_SAMPLETIME_1CYCLE_5 (0x00000000U)
ðADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR_SMPR_0)
ñADC_SAMPLETIME_7CYCLES_5 (ADC_SMPR_SMPR_1)
òADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0))
óADC_SAMPLETIME_19CYCLES_5 (ADC_SMPR_SMPR_2)
ôADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0))
õADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1))
öADC_SAMPLETIME_160CYCLES_5 (ADC_SMPR_SMPR)
‰ADC_SCAN_DIRECTION_FORWARD (0x00000001U)
ŠADC_SCAN_DIRECTION_BACKWARD (0x00000002U)
ŒADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD
•ADC_OVERSAMPLING_RATIO_2 (0x00000000U)
–ADC_OVERSAMPLING_RATIO_4 (0x00000004U)
—ADC_OVERSAMPLING_RATIO_8 (0x00000008U)
˜ADC_OVERSAMPLING_RATIO_16 (0x0000000CU)
™ADC_OVERSAMPLING_RATIO_32 (0x00000010U)
šADC_OVERSAMPLING_RATIO_64 (0x00000014U)
›ADC_OVERSAMPLING_RATIO_128 (0x00000018U)
œADC_OVERSAMPLING_RATIO_256 (0x0000001CU)
¤ADC_RIGHTBITSHIFT_NONE (0x00000000U)
¥ADC_RIGHTBITSHIFT_1 (0x00000020U)
¦ADC_RIGHTBITSHIFT_2 (0x00000040U)
§ADC_RIGHTBITSHIFT_3 (0x00000060U)
¨ADC_RIGHTBITSHIFT_4 (0x00000080U)
©ADC_RIGHTBITSHIFT_5 (0x000000A0U)
ªADC_RIGHTBITSHIFT_6 (0x000000C0U)
«ADC_RIGHTBITSHIFT_7 (0x000000E0U)
¬ADC_RIGHTBITSHIFT_8 (0x00000100U)
´ADC_TRIGGEREDMODE_SINGLE_TRIGGER (0x00000000U)
µADC_TRIGGEREDMODE_MULTI_TRIGGER (0x00000200U)
½ADC_ANALOGWATCHDOG_NONE (0x00000000U)
¾ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
¿ADC_ANALOGWATCHDOG_ALL_REG ( ADC_CFGR1_AWDEN)
ÇADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
ÏADC_AWD_EVENT (ADC_FLAG_AWD)
ÐADC_OVR_EVENT (ADC_FLAG_OVR)
ØADC_IT_RDY ADC_IER_ADRDYIE
ÙADC_IT_EOSMP ADC_IER_EOSMPIE
ÚADC_IT_EOC ADC_IER_EOCIE
ÛADC_IT_EOS ADC_IER_EOSEQIE
ÜADC_IT_OVR ADC_IER_OVRIE
ÝADC_IT_AWD ADC_IER_AWDIE
ÞADC_IT_EOCAL ADC_IER_EOCALIE
æADC_FLAG_RDY ADC_ISR_ADRDY
çADC_FLAG_EOSMP ADC_ISR_EOSMP
èADC_FLAG_EOC ADC_ISR_EOC
éADC_FLAG_EOS ADC_ISR_EOSEQ
êADC_FLAG_OVR ADC_ISR_OVR
ëADC_FLAG_AWD ADC_ISR_AWD
ìADC_FLAG_EOCAL ADC_ISR_EOCAL
ïADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)
‹__HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
“__HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
šADC_ENABLING_CONDITIONS(__HANDLE__) (( ( ((__HANDLE__)->Instance->CR) & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) ) == RESET ) ? SET : RESET)
¦__HAL_ADC_DISABLE(__HANDLE__) do{ (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); } while(0)
±ADC_DISABLING_CONDITIONS(__HANDLE__) (( ( ((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN ) ? SET : RESET)
»ADC_IS_ENABLE(__HANDLE__) (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) ) ? SET : RESET)
ÅADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
ÌADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
ÖADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET ) ? RESET : SET)
ßADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
æADC_SCANDIR(_SCAN_MODE_) ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) )? (ADC_CFGR1_SCANDIR) : (0x00000000U) )
ð__HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
÷ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
þ__HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
…__HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
ŒADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
“__HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
¡ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__,_Offset_) ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
°ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__,_Threshold_) ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
¹__HAL_ADC_Value_Shift_left(_Value_,_Shift_) ((_Value_) << (_Shift_))
Â__HAL_ADC_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Ë__HAL_ADC_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Õ__HAL_ADC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
ß__HAL_ADC_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
è__HAL_ADC_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
óADC_STATE_CLR_SET MODIFY_REG
úADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
„__HAL_ADC_CLOCK_PRESCALER(__HANDLE__) do{ if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) { (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; } else { (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); ADC->CCR &= ~(ADC_CCR_PRESC); ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; } } while(0)
—IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) || ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
¨IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || ((RESOLUTION) == ADC_RESOLUTION_10B) || ((RESOLUTION) == ADC_RESOLUTION_8B) || ((RESOLUTION) == ADC_RESOLUTION_6B))
­IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || ((RESOLUTION) == ADC_RESOLUTION_6B))
°IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))
³IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
¸IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
»IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
¾IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || ((WATCHDOG) == ADC_RANK_NONE))
ÖIS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5) || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || ((CHANNEL) == ADC_CHANNEL_VREFINT))
üIS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || ((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || ((TIME) == ADC_SAMPLETIME_160CYCLES_5))
…IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
ˆIS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
‘IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
›IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
žIS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
¢IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
¤IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || ((EVENT) == ADC_OVR_EVENT))
¬IS_ADC_RANGE(RESOLUTION,ADC_VALUE) ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))))
¸IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))ÂŒ€
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h
stm32l0xx_hal_def.h
stm32l0xx_hal_adc_ex.h


d
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*–RatioY
#RightBitShiftY
#TriggeredModeY
#PADC_OversamplingTypeDefÔ
8*áHClockPrescalerY
#ResolutionY
#DataAlignY
#ScanConvModeY
#EOCSelectionY
#LowPowerAutoWaitY
#LowPowerAutoPowerOffY
#ContinuousConvMode(
#DiscontinuousConvMode(
#ExternalTrigConvY
# ExternalTrigConvEdgeY
#$DMAContinuousRequests(
#(OverrunY
#,LowPowerFrequencyModeY
#0SamplingTimeY
#4OversamplingModeY
#8Oversample
#<PADC_InitTypeDef5

ª
*ChannelY
#RankY
#PADC_ChannelConfTypeDefù
¿
*¥WatchdogModeY
#ChannelY
#ITMode(
#HighThresholdY
#LowThresholdY
#PADC_AnalogWDGConfTypeDef<
Ú
)¹__ADC_HandleTypeDef\Instance9#Initá#DMA_Handle?#LLockG
#PStateE#TErrorCodeE#X"Ã"f
tY
PADC_HandleTypeDefÆ
 


__STM32L0xx_HAL_FLASH_EX_H 
)FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE)
+WRP_MASK_LOW (0x0000FFFFU)
,WRP_MASK_HIGH (0xFFFF0000U)
6IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
8IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1)))
;IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || ((__VALUE__) == OB_WRPSTATE_ENABLE))
>IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
@IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) || ((__LEVEL__) == OB_RDP_LEVEL_1) || ((__LEVEL__) == OB_RDP_LEVEL_2))
DIS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || ((__LEVEL__) == OB_BOR_LEVEL1) || ((__LEVEL__) == OB_BOR_LEVEL2) || ((__LEVEL__) == OB_BOR_LEVEL3) || ((__LEVEL__) == OB_BOR_LEVEL4) || ((__LEVEL__) == OB_BOR_LEVEL5))
KIS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
MIS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
OIS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
SIS_OBEX(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_PCROP | OPTIONBYTE_BOOTCONFIG)) && ((__VALUE__) != 0U))
aIS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || ((__VALUE__) == OB_PCROP_STATE_ENABLE))
dIS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
iIS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
mIS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))
nIS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD))
tIS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
uIS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END))
vIS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
wIS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
xIS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1))))
yIS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
ñ
FLASH_TYPEERASE_PAGES (0x00U)
ú
OPTIONBYTE_WRP (0x01U)
û
OPTIONBYTE_RDP (0x02U)
ü
OPTIONBYTE_USER (0x04U)
ý
OPTIONBYTE_BOR (0x08U)
þ
OPTIONBYTE_BOOT_BIT1 (0x10U)
‡OB_WRPSTATE_DISABLE (0x00U)
ˆOB_WRPSTATE_ENABLE (0x01U)
»OB_WRP_Pages0to31 (0x00000001U)
¼OB_WRP_Pages32to63 (0x00000002U)
½OB_WRP_Pages64to95 (0x00000004U)
¾OB_WRP_Pages96to127 (0x00000008U)
¿OB_WRP_Pages128to159 (0x00000010U)
ÀOB_WRP_Pages160to191 (0x00000020U)
ÁOB_WRP_Pages192to223 (0x00000040U)
ÂOB_WRP_Pages224to255 (0x00000080U)
ÃOB_WRP_Pages256to287 (0x00000100U)
ÄOB_WRP_Pages288to319 (0x00000200U)
ÅOB_WRP_Pages320to351 (0x00000400U)
ÆOB_WRP_Pages352to383 (0x00000800U)
ÇOB_WRP_Pages384to415 (0x00001000U)
ÈOB_WRP_Pages416to447 (0x00002000U)
ÉOB_WRP_Pages448to479 (0x00004000U)
ÊOB_WRP_Pages480to511 (0x00008000U)
ËOB_WRP_Pages512to543 (0x00010000U)
ÌOB_WRP_Pages544to575 (0x00020000U)
ÍOB_WRP_Pages576to607 (0x00040000U)
ÎOB_WRP_Pages608to639 (0x00080000U)
ÏOB_WRP_Pages640to671 (0x00100000U)
ÐOB_WRP_Pages672to703 (0x00200000U)
ÑOB_WRP_Pages704to735 (0x00400000U)
ÒOB_WRP_Pages736to767 (0x00800000U)
ÓOB_WRP_Pages768to799 (0x01000000U)
ÔOB_WRP_Pages800to831 (0x02000000U)
ÕOB_WRP_Pages832to863 (0x04000000U)
ÖOB_WRP_Pages864to895 (0x08000000U)
×OB_WRP_Pages896to927 (0x10000000U)
ØOB_WRP_Pages928to959 (0x20000000U)
ÙOB_WRP_Pages960to991 (0x40000000U)
ÚOB_WRP_Pages992to1023 (0x80000000U)
ÛOB_WRP_AllPages (0xFFFFFFFFU)
ãOB_WRP2_Pages1024to1055 (0x00000001U)
äOB_WRP2_Pages1056to1087 (0x00000002U)
åOB_WRP2_Pages1088to1119 (0x00000004U)
æOB_WRP2_Pages1120to1151 (0x00000008U)
çOB_WRP2_Pages1152to1183 (0x00000010U)
èOB_WRP2_Pages1184to1215 (0x00000020U)
éOB_WRP2_Pages1216to1247 (0x00000040U)
êOB_WRP2_Pages1248to1279 (0x00000080U)
ëOB_WRP2_Pages1280to1311 (0x00000100U)
ìOB_WRP2_Pages1312to1343 (0x00000200U)
íOB_WRP2_Pages1344to1375 (0x00000400U)
îOB_WRP2_Pages1376to1407 (0x00000800U)
ïOB_WRP2_Pages1408to1439 (0x00001000U)
ðOB_WRP2_Pages1440to1471 (0x00002000U)
ñOB_WRP2_Pages1472to1503 (0x00004000U)
òOB_WRP2_Pages1504to1535 (0x00008000U)
óOB_WRP2_AllPages (0x0000FFFFU)
üOB_RDP_LEVEL_0 ((uint8_t)0xAA)
ýOB_RDP_LEVEL_1 ((uint8_t)0xBB)
þOB_RDP_LEVEL_2 ((uint8_t)0xCC)
‰OB_BOR_OFF ((uint8_t)0x00)
‹OB_BOR_LEVEL1 ((uint8_t)0x08)
ŒOB_BOR_LEVEL2 ((uint8_t)0x09)
OB_BOR_LEVEL3 ((uint8_t)0x0A)
ŽOB_BOR_LEVEL4 ((uint8_t)0x0B)
OB_BOR_LEVEL5 ((uint8_t)0x0C)
™OB_IWDG_SW ((uint8_t)0x10)
šOB_IWDG_HW ((uint8_t)0x00)
¤OB_STOP_NORST ((uint8_t)0x20)
¥OB_STOP_RST ((uint8_t)0x00)
®OB_STDBY_NORST ((uint8_t)0x40)
¯OB_STDBY_RST ((uint8_t)0x00)
»OPTIONBYTE_PCROP (0x01U)
ÉOPTIONBYTE_BOOTCONFIG (0x02U)
ÖOB_PCROP_STATE_DISABLE (0x00U)
×OB_PCROP_STATE_ENABLE (0x01U)
àOB_PCROP_DESELECTED ((uint16_t)0x0000)
áOB_PCROP_SELECTED ((uint16_t)FLASH_OPTR_WPRMOD)
–OB_PCROP_Pages0to31 (0x00000001U)
—OB_PCROP_Pages32to63 (0x00000002U)
˜OB_PCROP_Pages64to95 (0x00000004U)
™OB_PCROP_Pages96to127 (0x00000008U)
šOB_PCROP_Pages128to159 (0x00000010U)
›OB_PCROP_Pages160to191 (0x00000020U)
œOB_PCROP_Pages192to223 (0x00000040U)
OB_PCROP_Pages224to255 (0x00000080U)
žOB_PCROP_Pages256to287 (0x00000100U)
ŸOB_PCROP_Pages288to319 (0x00000200U)
 OB_PCROP_Pages320to351 (0x00000400U)
¡OB_PCROP_Pages352to383 (0x00000800U)
¢OB_PCROP_Pages384to415 (0x00001000U)
£OB_PCROP_Pages416to447 (0x00002000U)
¤OB_PCROP_Pages448to479 (0x00004000U)
¥OB_PCROP_Pages480to511 (0x00008000U)
¦OB_PCROP_Pages512to543 (0x00010000U)
§OB_PCROP_Pages544to575 (0x00020000U)
¨OB_PCROP_Pages576to607 (0x00040000U)
©OB_PCROP_Pages608to639 (0x00080000U)
ªOB_PCROP_Pages640to671 (0x00100000U)
«OB_PCROP_Pages672to703 (0x00200000U)
¬OB_PCROP_Pages704to735 (0x00400000U)
­OB_PCROP_Pages736to767 (0x00800000U)
®OB_PCROP_Pages768to799 (0x01000000U)
¯OB_PCROP_Pages800to831 (0x02000000U)
°OB_PCROP_Pages832to863 (0x04000000U)
±OB_PCROP_Pages864to895 (0x08000000U)
²OB_PCROP_Pages896to927 (0x10000000U)
³OB_PCROP_Pages928to959 (0x20000000U)
´OB_PCROP_Pages960to991 (0x40000000U)
µOB_PCROP_Pages992to1023 (0x80000000U)
¶OB_PCROP_AllPages (0xFFFFFFFFU)
¾OB_PCROP2_Pages1024to1055 (0x00000001U)
¿OB_PCROP2_Pages1056to1087 (0x00000002U)
ÀOB_PCROP2_Pages1088to1119 (0x00000004U)
ÁOB_PCROP2_Pages1120to1151 (0x00000008U)
ÂOB_PCROP2_Pages1152to1183 (0x00000010U)
ÃOB_PCROP2_Pages1184to1215 (0x00000020U)
ÄOB_PCROP2_Pages1216to1247 (0x00000040U)
ÅOB_PCROP2_Pages1248to1279 (0x00000080U)
ÆOB_PCROP2_Pages1280to1311 (0x00000100U)
ÇOB_PCROP2_Pages1312to1343 (0x00000200U)
ÈOB_PCROP2_Pages1344to1375 (0x00000400U)
ÉOB_PCROP2_Pages1376to1407 (0x00000800U)
ÊOB_PCROP2_Pages1408to1439 (0x00001000U)
ËOB_PCROP2_Pages1440to1471 (0x00002000U)
ÌOB_PCROP2_Pages1472to1503 (0x00004000U)
ÍOB_PCROP2_Pages1504to1535 (0x00008000U)
ÎOB_PCROP2_AllPages (0x0000FFFFU)
×OB_BOOT_BIT1_RESET (uint8_t)(0x00)
ØOB_BOOT_BIT1_SET (uint8_t)(0x01)
àFLASH_TYPEPROGRAMDATA_BYTE (0x00U)
áFLASH_TYPEPROGRAMDATA_HALFWORD (0x01U)
âFLASH_TYPEPROGRAMDATA_WORD (0x02U)
îOB_BOOT_BANK1 ((uint8_t)0x00)
ðOB_BOOT_BANK2 ((uint8_t)(FLASH_OPTR_BFB2 >> 16))
Š__HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
”__HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
š__HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
 __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
¦__HAL_FLASH_BUFFER_CACHE_ENABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
¬__HAL_FLASH_BUFFER_CACHE_DISABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
²__HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
¸__HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
¾__HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Ä__HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Ë__HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; FLASH->PDKEYR = FLASH_PDKEY2; SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); } while (0)
Õ__HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; FLASH->PDKEYR = FLASH_PDKEY2; CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); } while (0)tk
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h
stm32l0xx_hal_def.h


Œ
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*—TypeEraseY
#PageAddressY
#NbPagesY
#PFLASH_EraseInitTypeDefÙ
£
*ØOptionTypeY
#WRPStateY
#WRPSectorY
#WRPSector2Y
#RDPLevel:
#BORLevel:
#USERConfig:
#BOOTBit1Config:
#PFLASH_OBProgramInitTypeDef6

Ä
*çOptionTypeY
#PCROPStateY
#PCROPSectorY
#PCROPSector2Y
#BootConfigI
#PFLASH_AdvOBProgramInitTypeDefû

à



__STM32L0xx_FLASH_RAMFUNC_H |p
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h
stm32l0xx_hal_def.h


Ü
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
 !"

__STM32L0xx_HAL_FLASH_H 
(FLASH_TIMEOUT_VALUE (50000U)
)FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
2IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
4IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1))
jHAL_FLASH_ERROR_NONE 0x00U
kHAL_FLASH_ERROR_PGA 0x01U
lHAL_FLASH_ERROR_WRP 0x02U
mHAL_FLASH_ERROR_OPTV 0x04U
nHAL_FLASH_ERROR_SIZE 0x08U
oHAL_FLASH_ERROR_RD 0x10U
pHAL_FLASH_ERROR_FWWERR 0x20U
qHAL_FLASH_ERROR_NOTZERO 0x40U
{FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U)
|FLASH_PAGE_SIZE (128U)
~FLASH_END (FLASH_BASE + FLASH_SIZE - 1)

FLASH_BANK2_BASE (FLASH_BASE + (FLASH_SIZE >> 1))
‚
FLASH_BANK1_END (FLASH_BANK2_BASE - 1)
ƒ
FLASH_BANK2_END (FLASH_END)

FLASH_TYPEPROGRAM_WORD (0x02U)
–
FLASH_LATENCY_0 (0x00000000U)
—
FLASH_LATENCY_1 FLASH_ACR_LATENCY
¡
FLASH_IT_EOP FLASH_PECR_EOPIE
¢
FLASH_IT_ERR FLASH_PECR_ERRIE
«
FLASH_FLAG_BSY FLASH_SR_BSY
¬
FLASH_FLAG_EOP FLASH_SR_EOP
­
FLASH_FLAG_ENDHV FLASH_SR_HVOFF
®
FLASH_FLAG_READY FLASH_SR_READY
¯
FLASH_FLAG_WRPERR FLASH_SR_WRPERR
°
FLASH_FLAG_PGAERR FLASH_SR_PGAERR
±
FLASH_FLAG_SIZERR FLASH_SR_SIZERR
²
FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
³
FLASH_FLAG_RDERR FLASH_SR_RDERR
´
FLASH_FLAG_FWWERR FLASH_SR_FWWERR
µ
FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR
¿
FLASH_PDKEY1 (0x04152637U)
À
FLASH_PDKEY2 (0xFAFBFCFDU)
Ã
FLASH_PEKEY1 (0x89ABCDEFU)
Ä
FLASH_PEKEY2 (0x02030405U)
È
FLASH_PRGKEY1 (0x8C9DAEBFU)
É
FLASH_PRGKEY2 (0x13141516U)
Ì
FLASH_OPTKEY1 (0xFBEAD9C8U)
Í
FLASH_OPTKEY2 (0x24252627U)
ò
__HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__))
ü
__HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))
__HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
Ÿ__HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))ª«°¥
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h
stm32l0xx_hal_def.h
stm32l0xx_hal_flash_ex.h
stm32l0xx_hal_flash_ramfunc.h


Ø

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARMœ
FLASH_PROC_NONEFLASH_PROC_PAGEERASE
FLASH_PROC_PROGRAMPFLASH_ProcedureTypeDefÖ
H*§ProcedureOnGoing§
#NbPagesToErase«
#Address«
#Page«
#LockG
#ErrorCode«
#t
tY
PFLASH_ProcessTypeDef:

[qpFlash±


Ü
Í
pFlash
$%&

STM32L0xx_HAL_I2C_EX_H 
/I2C_ANALOGFILTER_ENABLE 0x00000000U
0I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
8I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
:I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP
;I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP
AI2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP
BI2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP
HI2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP
MI2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP
RI2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMP
›
IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || ((FILTER) == I2C_ANALOGFILTER_DISABLE))
ž
IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
 
IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h
stm32l0xx_hal_def.h


Ø
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
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STM32L0xx_HAL_I2C_H 
¥
HAL_I2C_ERROR_NONE (0x00000000U)
¦
HAL_I2C_ERROR_BERR (0x00000001U)
§
HAL_I2C_ERROR_ARLO (0x00000002U)
¨
HAL_I2C_ERROR_AF (0x00000004U)
©
HAL_I2C_ERROR_OVR (0x00000008U)
ª
HAL_I2C_ERROR_DMA (0x00000010U)
«
HAL_I2C_ERROR_TIMEOUT (0x00000020U)
¬
HAL_I2C_ERROR_SIZE (0x00000040U)
­
HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
±
HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)
¯I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
°I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
±I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
²I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
³I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
´I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
¹I2C_OTHER_FRAME (0x000000AAU)
ºI2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
ÂI2C_ADDRESSINGMODE_7BIT (0x00000001U)
ÃI2C_ADDRESSINGMODE_10BIT (0x00000002U)
ËI2C_DUALADDRESS_DISABLE (0x00000000U)
ÌI2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
ÔI2C_OA2_NOMASK ((uint8_t)0x00U)
ÕI2C_OA2_MASK01 ((uint8_t)0x01U)
ÖI2C_OA2_MASK02 ((uint8_t)0x02U)
×I2C_OA2_MASK03 ((uint8_t)0x03U)
ØI2C_OA2_MASK04 ((uint8_t)0x04U)
ÙI2C_OA2_MASK05 ((uint8_t)0x05U)
ÚI2C_OA2_MASK06 ((uint8_t)0x06U)
ÛI2C_OA2_MASK07 ((uint8_t)0x07U)
ãI2C_GENERALCALL_DISABLE (0x00000000U)
äI2C_GENERALCALL_ENABLE I2C_CR1_GCEN
ìI2C_NOSTRETCH_DISABLE (0x00000000U)
íI2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
õI2C_MEMADD_SIZE_8BIT (0x00000001U)
öI2C_MEMADD_SIZE_16BIT (0x00000002U)
þI2C_DIRECTION_TRANSMIT (0x00000000U)
ÿI2C_DIRECTION_RECEIVE (0x00000001U)
‡I2C_RELOAD_MODE I2C_CR2_RELOAD
ˆI2C_AUTOEND_MODE I2C_CR2_AUTOEND
‰I2C_SOFTEND_MODE (0x00000000U)
‘I2C_NO_STARTSTOP (0x00000000U)
’I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
“I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
”I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
ŸI2C_IT_ERRI I2C_CR1_ERRIE
 I2C_IT_TCI I2C_CR1_TCIE
¡I2C_IT_STOPI I2C_CR1_STOPIE
¢I2C_IT_NACKI I2C_CR1_NACKIE
£I2C_IT_ADDRI I2C_CR1_ADDRIE
¤I2C_IT_RXI I2C_CR1_RXIE
¥I2C_IT_TXI I2C_CR1_TXIE
­I2C_FLAG_TXE I2C_ISR_TXE
®I2C_FLAG_TXIS I2C_ISR_TXIS
¯I2C_FLAG_RXNE I2C_ISR_RXNE
°I2C_FLAG_ADDR I2C_ISR_ADDR
±I2C_FLAG_AF I2C_ISR_NACKF
²I2C_FLAG_STOPF I2C_ISR_STOPF
³I2C_FLAG_TC I2C_ISR_TC
´I2C_FLAG_TCR I2C_ISR_TCR
µI2C_FLAG_BERR I2C_ISR_BERR
¶I2C_FLAG_ARLO I2C_ISR_ARLO
·I2C_FLAG_OVR I2C_ISR_OVR
¸I2C_FLAG_PECERR I2C_ISR_PECERR
¹I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
ºI2C_FLAG_ALERT I2C_ISR_ALERT
»I2C_FLAG_BUSY I2C_ISR_BUSY
¼I2C_FLAG_DIR I2C_ISR_DIR
Ö__HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
ç__HAL_I2C_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
÷__HAL_I2C_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
‡__HAL_I2C_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
¡I2C_FLAG_MASK (0x0001FFFFU)
¢__HAL_I2C_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
¶__HAL_I2C_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
¾__HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Ä__HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Ê__HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))Ð
ãIS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || ((MODE) == I2C_ADDRESSINGMODE_10BIT))
æIS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
éIS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || ((MASK) == I2C_OA2_MASK01) || ((MASK) == I2C_OA2_MASK02) || ((MASK) == I2C_OA2_MASK03) || ((MASK) == I2C_OA2_MASK04) || ((MASK) == I2C_OA2_MASK05) || ((MASK) == I2C_OA2_MASK06) || ((MASK) == I2C_OA2_MASK07))
òIS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
õIS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
øIS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
ûIS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || ((MODE) == I2C_AUTOEND_MODE) || ((MODE) == I2C_SOFTEND_MODE))
ÿIS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || ((REQUEST) == I2C_GENERATE_START_READ) || ((REQUEST) == I2C_GENERATE_START_WRITE) || ((REQUEST) == I2C_NO_STARTSTOP))
„IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
ŒIS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
”I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
–I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
˜I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
™I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
šI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
œIS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
ŸI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
¡I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
£I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
«I2C_CHECK_FLAG(__ISR__,__FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
­I2C_CHECK_IT_SOURCE(__CR1__,__IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)Œ€
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h
stm32l0xx_hal_def.h
stm32l0xx_hal_i2c_ex.h


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../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*Ž TimingY
#OwnAddress1Y
#AddressingModeY
#DualAddressModeY
#OwnAddress2Y
#OwnAddress2MasksY
#GeneralCallModeY
#NoStretchModeY
#PI2C_InitTypeDefÔ
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HAL_I2C_STATE_RESETHAL_I2C_STATE_READY HAL_I2C_STATE_BUSY$HAL_I2C_STATE_BUSY_TX!HAL_I2C_STATE_BUSY_RX"HAL_I2C_STATE_LISTEN(HAL_I2C_STATE_BUSY_TX_LISTEN)HAL_I2C_STATE_BUSY_RX_LISTEN*HAL_I2C_STATE_ABORT`HAL_I2C_STATE_TIMEOUT HAL_I2C_STATE_ERRORàPHAL_I2C_StateTypeDef¥

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HAL_I2C_MODE_NONEHAL_I2C_MODE_MASTERHAL_I2C_MODE_SLAVE HAL_I2C_MODE_MEM@PHAL_I2C_ModeTypeDefÛ
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STM32L0xx_HAL_LPTIM_H 
,LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_IM29
Ä
LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
Å
LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
Í
LPTIM_PRESCALER_DIV1 0x00000000U
Î
LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
Ï
LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
Ð
LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
Ñ
LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
Ò
LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
Ó
LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
Ô
LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
Ý
LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
Þ
LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
æ
LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
ç
LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
è
LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
é
LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
ñ
LPTIM_CLOCKPOLARITY_RISING 0x00000000U
ò
LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
ó
LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
û
LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
ü
LPTIM_TRIGSOURCE_0 0x00000000U
ý
LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
þ
LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
ÿ
LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
€LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
‚LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
ƒLPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
‹LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
ŒLPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
•LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
–LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
—LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
˜LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
¡LPTIM_UPDATE_IMMEDIATE 0x00000000U
¢LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
«LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
¬LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
µLPTIM_FLAG_DOWN LPTIM_ISR_DOWN
¶LPTIM_FLAG_UP LPTIM_ISR_UP
·LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
¸LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
¹LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
ºLPTIM_FLAG_ARRM LPTIM_ISR_ARRM
»LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
ÃLPTIM_IT_DOWN LPTIM_IER_DOWNIE
ÄLPTIM_IT_UP LPTIM_IER_UPIE
ÅLPTIM_IT_ARROK LPTIM_IER_ARROKIE
ÆLPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
ÇLPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
ÈLPTIM_IT_ARRM LPTIM_IER_ARRMIE
ÉLPTIM_IT_CMPM LPTIM_IER_CMPMIE
â__HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
ê__HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
ö__HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
ý__HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
ƒ__HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Œ__HAL_LPTIM_AUTORELOAD_SET(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
•__HAL_LPTIM_COMPARE_SET(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
¥__HAL_LPTIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
µ__HAL_LPTIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Æ__HAL_LPTIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
×__HAL_LPTIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
è__HAL_LPTIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
ï__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
ö__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
ý__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
„__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
«IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
¯IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
¸IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
ºIS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
½IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
ÂIS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
ÆIS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || ((__TRIG__) == LPTIM_TRIGSOURCE_0) || ((__TRIG__) == LPTIM_TRIGSOURCE_1) || ((__TRIG__) == LPTIM_TRIGSOURCE_2) || ((__TRIG__) == LPTIM_TRIGSOURCE_3) || ((__TRIG__) == LPTIM_TRIGSOURCE_4) || ((__TRIG__) == LPTIM_TRIGSOURCE_5) || ((__TRIG__) == LPTIM_TRIGSOURCE_6) || ((__TRIG__) == LPTIM_TRIGSOURCE_7))
ÐIS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
ÔIS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
ÙIS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
ÜIS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
ßIS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) && ((__AUTORELOAD__) <= 0x0000FFFFUL))
âIS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
äIS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) && ((__PERIOD__) <= 0x0000FFFFUL))
çIS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)th
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h
stm32l0xx_hal_def.h


t
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*þ
SourceY
#PrescalerY
#PLPTIM_ClockConfigTypeDefÖ
9*ÉPolarityY
#SampleTimeY
#PLPTIM_ULPClockConfigTypeDef

K*©SourceY
#ActiveEdgeY
#SampleTimeY
#PLPTIM_TriggerConfigTypeDefl

\*É(Clockþ#UltraLowPowerClockI
#Trigger©
#OutputPolarityY
#UpdateModeY
# CounterSourceY
#$PLPTIM_InitTypeDefË

så
HAL_LPTIM_STATE_RESETHAL_LPTIM_STATE_READY
HAL_LPTIM_STATE_BUSYHAL_LPTIM_STATE_TIMEOUTHAL_LPTIM_STATE_ERRORPHAL_LPTIM_StateTypeDefb
*Ï0InstanceO#InitI#Status
#,LockG
#-StateU#."GtåPLPTIM_HandleTypeDef
Ÿ

012

__STM32L0xx_HAL_PWR_EX_H 
/__HAL_PWR_FLASHWAKEUP_ENABLE() CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF)
6__HAL_PWR_FLASHWAKEUP_DISABLE() SET_BIT(PWR->CR, PWR_CR_DSEEKOFF)ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h
stm32l0xx_hal_def.h


Ø
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
456

__STM32L0xx_HAL_PWR_H 
APWR_EXTI_LINE_PVD EXTI_FTSR_TR16
OPWR_WAKEUP_PIN1 PWR_CSR_EWUP1
RPWR_WAKEUP_PIN2 PWR_CSR_EWUP2
WPWR_WAKEUP_PIN3 PWR_CSR_EWUP3
aPWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
bPWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
cPWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
dPWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
ePWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
fPWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
gPWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
hPWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
qPWR_PVD_MODE_NORMAL (0x00000000U)
rPWR_PVD_MODE_IT_RISING (0x00010001U)
sPWR_PVD_MODE_IT_FALLING (0x00010002U)
tPWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
uPWR_PVD_MODE_EVENT_RISING (0x00020001U)
vPWR_PVD_MODE_EVENT_FALLING (0x00020002U)
wPWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)
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PWR_MAINREGULATOR_ON (0x00000000U)

PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
Š
PWR_SLEEPENTRY_WFI (0x01U)
‹
PWR_SLEEPENTRY_WFE (0x02U)
“
PWR_STOPENTRY_WFI (0x01U)
”
PWR_STOPENTRY_WFE (0x02U)

PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
ž
PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
Ÿ
PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
¡
IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
«
PWR_FLAG_WU PWR_CSR_WUF
¬
PWR_FLAG_SB PWR_CSR_SBF
®
PWR_FLAG_PVDO PWR_CSR_PVDO
°
PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
±
PWR_FLAG_VOS PWR_CSR_VOSF
²
PWR_FLAG_REGLP PWR_CSR_REGLPF
Ò
__HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
î
__HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
ö
__HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U)
ý
__HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
ƒ__HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
‰__HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
__HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
•__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
›__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
¡__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
¨__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
®__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0);
µ__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0);
»__HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Á__HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Ç__HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
ÓIS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
ØIS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
ßIS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || ((PIN) == PWR_WAKEUP_PIN3))
íIS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
ïIS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
ñIS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))øŒ€
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h
stm32l0xx_hal_def.h
stm32l0xx_hal_pwr_ex.h




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*ù
PVDLevelY
#ModeY
#PPWR_PVDTypeDefÔ
5
89:

STM32L0xx_HAL_RTC_EX_H 
]RTC_BKP_DR0 0x00000000U
^RTC_BKP_DR1 0x00000001U
_RTC_BKP_DR2 0x00000002U
`RTC_BKP_DR3 0x00000003U
aRTC_BKP_DR4 0x00000004U
iRTC_TIMESTAMPEDGE_RISING 0x00000000U
jRTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
rRTC_TIMESTAMPPIN_DEFAULT 0x00000000U
{RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
}RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
ˆ
RTC_TAMPERPIN_DEFAULT 0x00000000U

RTC_IT_TAMP RTC_TAMPCR_TAMPIE
’
RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE
”
RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE
–
RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE
Ÿ
RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
 
RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
¡
RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
¢
RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
ª
RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000U
«
RTC_TAMPER_ERASE_BACKUP_DISABLE 0x00020000U
³
RTC_TAMPERMASK_FLAG_DISABLE 0x00000000U
´
RTC_TAMPERMASK_FLAG_ENABLE 0x00040000U
¼
RTC_TAMPERFILTER_DISABLE 0x00000000U
¾
RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
À
RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
Â
RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
Ä
RTC_TAMPERFILTER_MASK RTC_TAMPCR_TAMPFLT
Í
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
Ï
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0
Ñ
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1
Ó
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1)
Õ
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2
×
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2)
Ù
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2)
Û
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAMPCR_TAMPFREQ
Ý
RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAMPCR_TAMPFREQ
æ
RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
è
RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
ê
RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
ì
RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH
î
RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAMPCR_TAMPPRCH
÷
RTC_TAMPER_PULLUP_ENABLE 0x00000000U
ø
RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS
ù
RTC_TAMPER_PULLUP_MASK RTC_TAMPCR_TAMPPUDIS
RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS
‚RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U
ƒRTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAMPCR_TAMPTS
‹RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
ŒRTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
ŽRTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
˜RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U
šRTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
œRTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8
¥RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
¨RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U
±RTC_SHIFTADD1S_RESET 0x00000000U
²RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
ºRTC_CALIBOUTPUT_512HZ 0x00000000U
»RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
Õ__HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Ü__HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
æ__HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
ð__HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
ú__HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
„__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
__HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
™__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Ÿ__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
¥__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
«__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
±__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
·__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
½__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Ã__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
É__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Ï__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0U)
Ù__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0U)
â__HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
è__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
î__HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
ÿ__HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
†__HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
__HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
š__HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
¤__HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
®__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
¹__HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
Ä__HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Ö__HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Ý__HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
å__HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
ì__HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
ô__HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
û__HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
‹__HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
š__HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
¨__HAL_RTC_TAMPER_GET_IT(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
·__HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Å__HAL_RTC_TAMPER_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
Ó__HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
á__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
ç__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
í__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
ó__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
ù__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
ÿ__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
…__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
‹__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
‘__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0U)
›__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0U)
¤__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
ª__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
°__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
À__HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Ç__HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Î__HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Õ__HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
ß__HAL_RTC_SHIFT_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
ÇRTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_IM19
ÈRTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_IM20
ÓRTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3))
×RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F))
ñRTC_TAMPER_IT_ENABLE_BITS_MASK ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3 | RTC_IT_TAMP))
‘IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
“IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
–IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U))
˜IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT)
šIS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT)
œIS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & ((uint32_t)~RTC_TAMPER_IT_ENABLE_BITS_MASK )) == 0x00U) && ((INTERRUPT) != 0U))
žIS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
£IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
¦IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
©IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
®IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER,TRIGGER) ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))
¶IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
¿IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
ÄIS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
ÇIS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
ÊIS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
ÑIS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
ÓIS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
×IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
ÚIS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
ÜIS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || ((SEL) == RTC_SHIFTADD1S_SET))
ßIS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
áIS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h
stm32l0xx_hal_def.h


Ì

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*³(TamperY
#InterruptY
#TriggerY
#NoEraseY
#MaskFlagY
#FilterY
#SamplingFrequencyY
#PrechargeDurationY
#TamperPullUpY
# TimeStampOnTamperDetectionY
#$PRTC_TamperTypeDef×
O
<=>

STM32L0xx_HAL_RTC_H 
ö
RTC_HOURFORMAT_24 0x00000000U
÷
RTC_HOURFORMAT_12 RTC_CR_FMT
ÿ
RTC_OUTPUT_DISABLE 0x00000000U
€RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
‚RTC_OUTPUT_WAKEUP RTC_CR_OSEL
ŠRTC_OUTPUT_REMAP_NONE 0x00000000U
‹RTC_OUTPUT_REMAP_POS1 RTC_OR_OUT_RMP
“RTC_OUTPUT_POLARITY_HIGH 0x00000000U
”RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
œRTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
¥RTC_HOURFORMAT12_AM ((uint8_t)0x00)
¦RTC_HOURFORMAT12_PM ((uint8_t)0x01)
®RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
¯RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
°RTC_DAYLIGHTSAVING_NONE 0x00000000U
¸RTC_STOREOPERATION_RESET 0x00000000U
¹RTC_STOREOPERATION_SET RTC_CR_BKP
ÁRTC_FORMAT_BIN 0x00000000U
ÂRTC_FORMAT_BCD 0x00000001U
ÊRTC_MONTH_JANUARY ((uint8_t)0x01)
ËRTC_MONTH_FEBRUARY ((uint8_t)0x02)
ÌRTC_MONTH_MARCH ((uint8_t)0x03)
ÍRTC_MONTH_APRIL ((uint8_t)0x04)
ÎRTC_MONTH_MAY ((uint8_t)0x05)
ÏRTC_MONTH_JUNE ((uint8_t)0x06)
ÐRTC_MONTH_JULY ((uint8_t)0x07)
ÑRTC_MONTH_AUGUST ((uint8_t)0x08)
ÒRTC_MONTH_SEPTEMBER ((uint8_t)0x09)
ÓRTC_MONTH_OCTOBER ((uint8_t)0x10)
ÔRTC_MONTH_NOVEMBER ((uint8_t)0x11)
ÕRTC_MONTH_DECEMBER ((uint8_t)0x12)
ÝRTC_WEEKDAY_MONDAY ((uint8_t)0x01)
ÞRTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
ßRTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
àRTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
áRTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
âRTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
ãRTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
ëRTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
ìRTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
ôRTC_ALARMMASK_NONE 0x00000000U
õRTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
öRTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
÷RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
øRTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
ùRTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
„RTC_ALARM_A RTC_CR_ALRAE
…RTC_ALARM_B RTC_CR_ALRBE
ŽRTC_ALARMSUBSECONDMASK_ALL 0x00000000U
RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
’RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
”RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
–RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
˜RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
šRTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
œRTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
žRTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
 RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
¢RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
¤RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
¦RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
¨RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
ªRTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
¬RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
´RTC_IT_TS RTC_CR_TSIE
µRTC_IT_WUT RTC_CR_WUTIE
¶RTC_IT_ALRB RTC_CR_ALRBIE
·RTC_IT_ALRA RTC_CR_ALRAIE
¿RTC_FLAG_RECALPF RTC_ISR_RECALPF
ÁRTC_FLAG_TAMP3F RTC_ISR_TAMP3F
ÃRTC_FLAG_TAMP2F RTC_ISR_TAMP2F
ÅRTC_FLAG_TAMP1F RTC_ISR_TAMP1F
ÇRTC_FLAG_TSOVF RTC_ISR_TSOVF
ÈRTC_FLAG_TSF RTC_ISR_TSF
ÉRTC_FLAG_WUTF RTC_ISR_WUTF
ÊRTC_FLAG_ALRBF RTC_ISR_ALRBF
ËRTC_FLAG_ALRAF RTC_ISR_ALRAF
ÌRTC_FLAG_INITF RTC_ISR_INITF
ÍRTC_FLAG_RSF RTC_ISR_RSF
ÎRTC_FLAG_INITS RTC_ISR_INITS
ÏRTC_FLAG_SHPF RTC_ISR_SHPF
ÐRTC_FLAG_WUTWF RTC_ISR_WUTWF
ÑRTC_FLAG_ALRBWF RTC_ISR_ALRBWF
ÒRTC_FLAG_ALRAWF RTC_ISR_ALRAWF
ì__HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
ô__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { (__HANDLE__)->Instance->WPR = 0xCAU; (__HANDLE__)->Instance->WPR = 0x53U; } while(0U)
þ__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { (__HANDLE__)->Instance->WPR = 0xFFU; } while(0U)
‡__HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
Ž__HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
•__HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
œ__HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
£__HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
®__HAL_RTC_ALARM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
¹__HAL_RTC_ALARM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Ä__HAL_RTC_ALARM_GET_IT(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
Ñ__HAL_RTC_ALARM_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Ü__HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
ç__HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
í__HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
ó__HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
ù__HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
ÿ__HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
…__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
‹__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
‘__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
—__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); } while(0U)
¦__HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); } while(0U)
¯__HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
µ__HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
»__HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)Á
›RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU | RTC_TR_PM))
ŸRTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_WDU))
£RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT))
¤RTC_INIT_MASK 0xFFFFFFFFU
¥RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
¦RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTF | RTC_FLAG_WUTWF | RTC_FLAG_RECALPF | RTC_FLAG_SHPF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
®RTC_TIMEOUT_VALUE 1000U
°RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17
¾IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || ((FORMAT) == RTC_HOURFORMAT_24))
ÁIS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || ((OUTPUT) == RTC_OUTPUT_ALARMA) || ((OUTPUT) == RTC_OUTPUT_ALARMB) || ((OUTPUT) == RTC_OUTPUT_WAKEUP))
ÆIS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || ((REMAP) == RTC_OUTPUT_REMAP_POS1))
ÉIS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || ((POL) == RTC_OUTPUT_POLARITY_LOW))
ÌIS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
ÏIS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
ÐIS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
ÒIS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
ÓIS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
ÔIS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
ÕIS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
×IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
ÚIS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
ÞIS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || ((OPERATION) == RTC_STOREOPERATION_SET))
áIS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
ãIS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
äIS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
åIS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
çIS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
ïIS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
ñIS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
ùIS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
üIS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U)
þIS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
€IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
‚IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))Œ€
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h
stm32l0xx_hal_def.h
stm32l0xx_hal_rtc_ex.h


,
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARMÍ
HAL_RTC_STATE_RESETHAL_RTC_STATE_READY
HAL_RTC_STATE_BUSYHAL_RTC_STATE_TIMEOUTHAL_RTC_STATE_ERRORPHAL_RTCStateTypeDefÔ
7*ýHourFormatY
#AsynchPredivY
#SynchPredivY
#OutPutY
#OutPutRemapY
#OutPutPolarityY
#OutPutTypeY
#PRTC_InitTypeDefh

R*ºHours:
#Minutes:
#
Seconds:
#TimeFormat:
#SubSecondsY
#SecondFractionY
#DayLightSavingY
#StoreOperationY
#PRTC_TimeTypeDef
u*’WeekDay:
#Month:
#
Date:
#Year:
#PRTC_DateTypeDefÑ
ˆ
*µ(AlarmTimeº#AlarmMaskY
#AlarmSubSecondMaskY
#AlarmDateWeekDaySelY
#AlarmDateWeekDay:
# AlarmY
#$PRTC_AlarmTypeDef*
 
*Š$Instance
#Initý
#LockG
# State#!"útM
PRTC_HandleTypeDefÎ
Ì

@AB

STM32L0xx_HAL_SPI_H 
¼
HAL_SPI_ERROR_NONE (0x00000000U)
½
HAL_SPI_ERROR_MODF (0x00000001U)
¾
HAL_SPI_ERROR_CRC (0x00000002U)
¿
HAL_SPI_ERROR_OVR (0x00000004U)
À
HAL_SPI_ERROR_FRE (0x00000008U)
Á
HAL_SPI_ERROR_DMA (0x00000010U)
Â
HAL_SPI_ERROR_FLAG (0x00000020U)
Ã
HAL_SPI_ERROR_ABORT (0x00000040U)
Î
SPI_MODE_SLAVE (0x00000000U)
Ï
SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
×
SPI_DIRECTION_2LINES (0x00000000U)
Ø
SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
Ù
SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
á
SPI_DATASIZE_8BIT (0x00000000U)
â
SPI_DATASIZE_16BIT SPI_CR1_DFF
ê
SPI_POLARITY_LOW (0x00000000U)
ë
SPI_POLARITY_HIGH SPI_CR1_CPOL
ó
SPI_PHASE_1EDGE (0x00000000U)
ô
SPI_PHASE_2EDGE SPI_CR1_CPHA
ü
SPI_NSS_SOFT SPI_CR1_SSM
ý
SPI_NSS_HARD_INPUT (0x00000000U)
þ
SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
†SPI_BAUDRATEPRESCALER_2 (0x00000000U)
‡SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
ˆSPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
‰SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
ŠSPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
‹SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
ŒSPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
•SPI_FIRSTBIT_MSB (0x00000000U)
–SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
žSPI_TIMODE_DISABLE (0x00000000U)
ŸSPI_TIMODE_ENABLE SPI_CR2_FRF
§SPI_CRCCALCULATION_DISABLE (0x00000000U)
¨SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
°SPI_IT_TXE SPI_CR2_TXEIE
±SPI_IT_RXNE SPI_CR2_RXNEIE
²SPI_IT_ERR SPI_CR2_ERRIE
ºSPI_FLAG_RXNE SPI_SR_RXNE
»SPI_FLAG_TXE SPI_SR_TXE
¼SPI_FLAG_BSY SPI_SR_BSY
½SPI_FLAG_CRCERR SPI_SR_CRCERR
¾SPI_FLAG_MODF SPI_SR_MODF
¿SPI_FLAG_OVR SPI_SR_OVR
ÀSPI_FLAG_FRE SPI_SR_FRE
ÁSPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
Ü__HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
é__HAL_SPI_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
õ__HAL_SPI_DISABLE_IT(__HANDLE__,__INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
__HAL_SPI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
’__HAL_SPI_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
™__HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
 __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_modf = 0x00U; tmpreg_modf = (__HANDLE__)->Instance->SR; CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); UNUSED(tmpreg_modf); } while(0U)
­__HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_ovr = 0x00U; tmpreg_ovr = (__HANDLE__)->Instance->DR; tmpreg_ovr = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_ovr); } while(0U)
º__HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_fre = 0x00U; tmpreg_fre = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_fre); }while(0U)
Æ__HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Í__HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
ÝSPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
äSPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
ëSPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
ûSPI_CHECK_FLAG(__SR__,__FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
‡SPI_CHECK_IT_SOURCE(__CR2__,__INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
—IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || ((__MODE__) == SPI_DIRECTION_1LINE))
ŸIS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
¥IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || ((__MODE__) == SPI_DIRECTION_1LINE))
­IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || ((__DATASIZE__) == SPI_DATASIZE_8BIT))
µIS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || ((__CPOL__) == SPI_POLARITY_HIGH))
½IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || ((__CPHA__) == SPI_PHASE_2EDGE))
ÅIS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || ((__NSS__) == SPI_NSS_HARD_INPUT) || ((__NSS__) == SPI_NSS_HARD_OUTPUT))
ÎIS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
ÜIS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || ((__BIT__) == SPI_FIRSTBIT_LSB))
äIS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || ((__MODE__) == SPI_TIMODE_ENABLE))
ìIS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
ôIS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
üIS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
‚IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U)pf
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h
stm32l0xx_hal_def.h



../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*¬,ModeY
#DirectionY
#DataSizeY
#CLKPolarityY
#CLKPhaseY
#NSSY
#BaudRatePrescalerY
#FirstBitY
#TIModeY
# CRCCalculationY
#$CRCPolynomialY
#(PSPI_InitTypeDefÔ
Tˆ
HAL_SPI_STATE_RESETHAL_SPI_STATE_READY
HAL_SPI_STATE_BUSYHAL_SPI_STATE_BUSY_TXHAL_SPI_STATE_BUSY_RXHAL_SPI_STATE_BUSY_TX_RXHAL_SPI_STATE_ERRORHAL_SPI_STATE_ABORTPHAL_SPI_StateTypeDefÃ

c)Å__SPI_HandleTypeDefXInstanceÅ#Init¬
#pTxBuffPtrË#0TxXferSizeI
#4TxXferCountÑ#6pRxBuffPtrË#8RxXferSizeI
#<RxXferCountÑ#>OÒ%×"JRxISRR#@Oë%×"cTxISRk#DhdmatxÛ#HhdmarxÛ#LLockG
#PStateá#QErrorCodeå#T"‚ ":
tI
"¤"f
tˆtY
PSPI_HandleTypeDef¤
•

DEF

STM32L0xx_HAL_TIM_EX_H 
8TIM2_ETR_GPIO 0x00000000U
<TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
=TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
?TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
@TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
CTIM2_TI4_GPIO 0x00000000U
ETIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0
FTIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1
NTIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP
OTIM3_TI2_GPIO_DEF 0x00000000U
PTIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP
VTIM3_TI1_GPIO TIM3_OR_TI1_RMP
WTIM3_ETR_GPIO 0x00000000U
XTIM3_ETR_HSI TIM3_OR_ETR_RMP_1
[TIM21_ETR_GPIO 0x00000000U
]TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0
^TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1
`TIM21_ETR_LSE TIM21_OR_ETR_RMP
bTIM21_TI1_GPIO 0x00000000U
cTIM21_TI1_MCO TIM21_OR_TI1_RMP
dTIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0
eTIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1
fTIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1)
gTIM21_TI1_LSE TIM21_OR_TI1_RMP_2
hTIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0)
jTIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1)
mTIM21_TI2_GPIO 0x00000000U
oTIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP
sTIM22_ETR_GPIO 0x00000000U
uTIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0
vTIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1
xTIM22_ETR_LSE TIM22_OR_ETR_RMP
zTIM22_TI1_GPIO 0x00000000U
|TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0
}TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1
™
IS_TIM_REMAP(__INSTANCE__,__TIM_REMAP__) ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || (((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP))))
Ÿ
IS_CHANNEL_AVAILABLE(__INSTANCE__,__CHANNEL__) ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))) || (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))))ti
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h
stm32l0xx_hal_def.h


Ø
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM
HIJ

STM32L0xx_HAL_TIM_H 
îTIM_CLEARINPUTSOURCE_NONE 0x00000000U
ïTIM_CLEARINPUTSOURCE_ETR 0x00000001U
÷TIM_DMABASE_CR1 0x00000000U
øTIM_DMABASE_CR2 0x00000001U
ùTIM_DMABASE_SMCR 0x00000002U
úTIM_DMABASE_DIER 0x00000003U
ûTIM_DMABASE_SR 0x00000004U
üTIM_DMABASE_EGR 0x00000005U
ýTIM_DMABASE_CCMR1 0x00000006U
þTIM_DMABASE_CCMR2 0x00000007U
ÿTIM_DMABASE_CCER 0x00000008U
€TIM_DMABASE_CNT 0x00000009U
TIM_DMABASE_PSC 0x0000000AU
‚TIM_DMABASE_ARR 0x0000000BU
ƒTIM_DMABASE_CCR1 0x0000000DU
„TIM_DMABASE_CCR2 0x0000000EU
…TIM_DMABASE_CCR3 0x0000000FU
†TIM_DMABASE_CCR4 0x00000010U
‡TIM_DMABASE_DCR 0x00000012U
ˆTIM_DMABASE_DMAR 0x00000013U
‰TIM_DMABASE_OR 0x00000014U
‘TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
’TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
“TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
”TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
•TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
–TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
žTIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
ŸTIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
 TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
¨TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
©TIM_ETRPOLARITY_NONINVERTED 0x00000000U
±TIM_ETRPRESCALER_DIV1 0x00000000U
²TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
³TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
´TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
¼TIM_COUNTERMODE_UP 0x00000000U
½TIM_COUNTERMODE_DOWN TIM_CR1_DIR
¾TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
¿TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
ÀTIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
ÈTIM_CLOCKDIVISION_DIV1 0x00000000U
ÉTIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
ÊTIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
ÒTIM_OUTPUTSTATE_DISABLE 0x00000000U
ÓTIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
ÛTIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
ÜTIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
åTIM_OCFAST_DISABLE 0x00000000U
æTIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
îTIM_OUTPUTNSTATE_DISABLE 0x00000000U
ïTIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
÷TIM_OCPOLARITY_HIGH 0x00000000U
øTIM_OCPOLARITY_LOW TIM_CCER_CC1P
€TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
‚TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
ŠTIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
‹TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
“TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
”TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
•TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
TIM_ICPSC_DIV1 0x00000000U
žTIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
ŸTIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
 TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
¨TIM_OPMODE_SINGLE TIM_CR1_OPM
©TIM_OPMODE_REPETITIVE 0x00000000U
±TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
²TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
³TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
»TIM_IT_UPDATE TIM_DIER_UIE
¼TIM_IT_CC1 TIM_DIER_CC1IE
½TIM_IT_CC2 TIM_DIER_CC2IE
¾TIM_IT_CC3 TIM_DIER_CC3IE
¿TIM_IT_CC4 TIM_DIER_CC4IE
ÀTIM_IT_TRIGGER TIM_DIER_TIE
ÈTIM_DMA_UPDATE TIM_DIER_UDE
ÉTIM_DMA_CC1 TIM_DIER_CC1DE
ÊTIM_DMA_CC2 TIM_DIER_CC2DE
ËTIM_DMA_CC3 TIM_DIER_CC3DE
ÌTIM_DMA_CC4 TIM_DIER_CC4DE
ÍTIM_DMA_TRIGGER TIM_DIER_TDE
ÕTIM_CCDMAREQUEST_CC 0x00000000U
ÖTIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
ÞTIM_FLAG_UPDATE TIM_SR_UIF
ßTIM_FLAG_CC1 TIM_SR_CC1IF
àTIM_FLAG_CC2 TIM_SR_CC2IF
áTIM_FLAG_CC3 TIM_SR_CC3IF
âTIM_FLAG_CC4 TIM_SR_CC4IF
ãTIM_FLAG_TRIGGER TIM_SR_TIF
äTIM_FLAG_CC1OF TIM_SR_CC1OF
åTIM_FLAG_CC2OF TIM_SR_CC2OF
æTIM_FLAG_CC3OF TIM_SR_CC3OF
çTIM_FLAG_CC4OF TIM_SR_CC4OF
ïTIM_CHANNEL_1 0x00000000U
ðTIM_CHANNEL_2 0x00000004U
ñTIM_CHANNEL_3 0x00000008U
òTIM_CHANNEL_4 0x0000000CU
óTIM_CHANNEL_ALL 0x0000003CU
ûTIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
üTIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
ýTIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
þTIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
ÿTIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
€TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
‚TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
ƒTIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
„TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
ŒTIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
ŽTIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
˜TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
™TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
šTIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
›TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
£TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
¤TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
¬TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
­TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
®TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
¯TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
·TIM_TRGO_RESET 0x00000000U
¸TIM_TRGO_ENABLE TIM_CR2_MMS_0
¹TIM_TRGO_UPDATE TIM_CR2_MMS_1
ºTIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
»TIM_TRGO_OC1REF TIM_CR2_MMS_2
¼TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
½TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
¾TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
ÆTIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
ÇTIM_MASTERSLAVEMODE_DISABLE 0x00000000U
ÏTIM_SLAVEMODE_DISABLE 0x00000000U
ÐTIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
ÑTIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
ÒTIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
ÓTIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
ÛTIM_OCMODE_TIMING 0x00000000U
ÜTIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
ÝTIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
ÞTIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
ßTIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
àTIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
áTIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
âTIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
êTIM_TS_ITR0 0x00000000U
ëTIM_TS_ITR1 TIM_SMCR_TS_0
ìTIM_TS_ITR2 TIM_SMCR_TS_1
íTIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
îTIM_TS_TI1F_ED TIM_SMCR_TS_2
ïTIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
ðTIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
ñTIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
òTIM_TS_NONE 0x0000FFFFU
úTIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
ûTIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
üTIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
ýTIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
þTIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
†TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
‡TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
ˆTIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
‰TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
‘TIM_TI1SELECTION_CH1 0x00000000U
’TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
šTIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
›TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
œTIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
žTIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
ŸTIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
 TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
¡TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
¢TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
£TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
¤TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
¥TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
¦TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
§TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
¨TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
©TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
ªTIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
«TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
³TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
´TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
µTIM_DMA_ID_CC2 ((uint16_t) 0x0002)
¶TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
·TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
¸TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
ÀTIM_CCx_ENABLE 0x00000001U
ÁTIM_CCx_DISABLE 0x00000000U
ê__HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { (__HANDLE__)->State = HAL_TIM_STATE_RESET; (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; } while(0)
ù__HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
€__HAL_TIM_DISABLE(__HANDLE__) do { if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); } } while(0)
”__HAL_TIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
¢__HAL_TIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
°__HAL_TIM_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
¾__HAL_TIM_DISABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Ð__HAL_TIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
â__HAL_TIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
ñ__HAL_TIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
€__HAL_TIM_CLEAR_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
‰__HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
‘__HAL_TIM_SET_PRESCALER(__HANDLE__,__PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
™__HAL_TIM_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
 __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
¨__HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0)
³__HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
¿__HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0)
Î__HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
â__HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0)
÷__HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
‰    __HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
š    __HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))
«    __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
¼    __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
Ñ    __HAL_TIM_ENABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
æ    __HAL_TIM_DISABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
ô    __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)

__HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
’
__HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0)
 
__HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__,__CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
®
TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
¸
IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
»
IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_OR))
Í
IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
Ï
IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
Õ
IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
Ù
IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
Ü
IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))
ß
IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW))
â
IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
å
IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
é
IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC))
í
IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8))
ò
IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE))
õ
IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12))
ù
IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
û
IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || ((__CHANNEL__) == TIM_CHANNEL_ALL))
IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))
„IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU))
†IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU)
ˆIS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
“IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
™IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
žIS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
 IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
£IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
¨IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
ªIS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF))
³IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
¶IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || ((__MODE__) == TIM_SLAVEMODE_RESET) || ((__MODE__) == TIM_SLAVEMODE_GATED) || ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
¼IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2))
¿IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
ÆIS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_TI1F_ED) || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF))
ÏIS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_NONE))
ÕIS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
ÛIS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
àIS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
âIS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
åIS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
øIS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
úIS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
üIS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
þTIM_SET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__,__ICPSC__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
„TIM_RESET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
ŠTIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
TIM_RESET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
–TIM_CHANNEL_STATE_GET(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] : (__HANDLE__)->ChannelState[3])
œTIM_CHANNEL_STATE_SET(__HANDLE__,__CHANNEL__,__CHANNEL_STATE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
¢TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__) do { (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); } while(0)¯Œ€
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h
stm32l0xx_hal_def.h
stm32l0xx_hal_tim_ex.h


Ü
../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*ÃPrescalerY
#CounterModeY
#PeriodY
#ClockDivisionY
#AutoReloadPreloadY
#PTIM_Base_InitTypeDefÔ
?*«OCModeY
#PulseY
#OCPolarityY
#OCFastModeY
#PTIM_OC_InitTypeDef_

R*¸OCModeY
#PulseY
#OCPolarityY
#ICPolarityY
#ICSelectionY
#ICFilterY
#PTIM_OnePulse_InitTypeDefÅ

j*­ICPolarityY
#ICSelectionY
#ICPrescalerY
#ICFilterY
#PTIM_IC_InitTypeDefX
|*‰$EncoderModeY
#IC1PolarityY
#IC1SelectionY
#IC1PrescalerY
#IC1FilterY
#IC2PolarityY
#IC2SelectionY
#IC2PrescalerY
#IC2FilterY
# PTIM_Encoder_InitTypeDefÇ

*‡ClockSourceY
#ClockPolarityY
#ClockPrescalerY
#ClockFilterY
#PTIM_ClockConfigTypeDef©
¬
*±    ClearInputStateY
#ClearInputSourceY
#ClearInputPolarityY
#ClearInputPrescalerY
#ClearInputFilterY
#PTIM_ClearInputConfigTypeDef&
¾
*
MasterOutputTriggerY
#MasterSlaveModeY
#PTIM_MasterConfigTypeDefÕ
Î
*¨SlaveModeY
#InputTriggerY
#TriggerPolarityY
#TriggerPrescalerY
#TriggerFilterY
#PTIM_SlaveConfigTypeDef0
à
À
HAL_TIM_STATE_RESETHAL_TIM_STATE_READY
HAL_TIM_STATE_BUSYHAL_TIM_STATE_TIMEOUTHAL_TIM_STATE_ERRORPHAL_TIM_StateTypeDefÇ
ì
¾ 
HAL_TIM_CHANNEL_STATE_RESETHAL_TIM_CHANNEL_STATE_READY
HAL_TIM_CHANNEL_STATE_BUSYPHAL_TIM_ChannelStateTypeDef]
ö
½
HAL_DMA_BURST_STATE_RESETHAL_DMA_BURST_STATE_READY
HAL_DMA_BURST_STATE_BUSYPHAL_TIM_DMABurstStateTypeDefâ
€ù
HAL_TIM_ACTIVE_CHANNEL_1
HAL_TIM_ACTIVE_CHANNEL_2HAL_TIM_ACTIVE_CHANNEL_3HAL_TIM_ACTIVE_CHANNEL_4HAL_TIM_ACTIVE_CHANNEL_CLEAREDPHAL_TIM_ActiveChannelb
Œ*©@Instance©#InitC
#Channelù#ϯ
hdmaF#LockG
#8Stateµ#9ÿ¹
ChannelStatev#:DMABurstState½#>"ž"f
t@t¾t=PTIM_HandleTypeDef
¹
LMN

STM32L0xx_HAL_UART_EX_H 
GUART_WORDLENGTH_7B USART_CR1_M1
HUART_WORDLENGTH_8B 0x00000000U
IUART_WORDLENGTH_9B USART_CR1_M0
QUART_ADDRESS_DETECT_4B 0x00000000U
RUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
 UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else if((__HANDLE__)->Instance == USART4) { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; } else if((__HANDLE__)->Instance == USART5) { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; } else if((__HANDLE__)->Instance == LPUART1) { switch(__HAL_RCC_GET_LPUART1_SOURCE()) { case RCC_LPUART1CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_LPUART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_LPUART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_LPUART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; break; } } else { (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; } } while(0)
ûUART_MASK_COMPUTATION(__HANDLE__) do { if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x01FFU ; } else { (__HANDLE__)->Mask = 0x00FFU ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x00FFU ; } else { (__HANDLE__)->Mask = 0x007FU ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x007FU ; } else { (__HANDLE__)->Mask = 0x003FU ; } } else { (__HANDLE__)->Mask = 0x0000U; } } while(0U)
©IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || ((__LENGTH__) == UART_WORDLENGTH_8B) || ((__LENGTH__) == UART_WORDLENGTH_9B))
²IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))tj
 




../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h
stm32l0xx_hal_def.h


4

../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\WXK\Desktop\STM32L071RB+lora\STM32L071RB+lora\MDK-ARM*šWakeUpEventY
#AddressLengthI
#Address:
#PUART_WakeUpTypeDefØ
9
PQR

STM32L0xx_HAL_UART_H 
ÂHAL_UART_STATE_RESET 0x00000000U
ÄHAL_UART_STATE_READY 0x00000020U
ÆHAL_UART_STATE_BUSY 0x00000024U
ÈHAL_UART_STATE_BUSY_TX 0x00000021U
ÊHAL_UART_STATE_BUSY_RX 0x00000022U
ÌHAL_UART_STATE_BUSY_TX_RX 0x00000023U
ÏHAL_UART_STATE_TIMEOUT 0x000000A0U
ÑHAL_UART_STATE_ERROR 0x000000E0U
ÚHAL_UART_ERROR_NONE (0x00000000U)
ÛHAL_UART_ERROR_PE (0x00000001U)
ÜHAL_UART_ERROR_NE (0x00000002U)
ÝHAL_UART_ERROR_FE (0x00000004U)
ÞHAL_UART_ERROR_ORE (0x00000008U)
ßHAL_UART_ERROR_DMA (0x00000010U)
àHAL_UART_ERROR_RTO (0x00000020U)
ìUART_STOPBITS_0_5 USART_CR2_STOP_0
íUART_STOPBITS_1 0x00000000U
îUART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
ïUART_STOPBITS_2 USART_CR2_STOP_1
÷UART_PARITY_NONE 0x00000000U
øUART_PARITY_EVEN USART_CR1_PCE
ùUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
UART_HWCONTROL_NONE 0x00000000U
‚UART_HWCONTROL_RTS USART_CR3_RTSE
ƒUART_HWCONTROL_CTS USART_CR3_CTSE
„UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
ŒUART_MODE_RX USART_CR1_RE
UART_MODE_TX USART_CR1_TE
ŽUART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
–UART_STATE_DISABLE 0x00000000U
—UART_STATE_ENABLE USART_CR1_UE
ŸUART_OVERSAMPLING_16 0x00000000U
 UART_OVERSAMPLING_8 USART_CR1_OVER8
¨UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
©UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
±UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
³UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
µUART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
·UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE
ÀUART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
ÁUART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN
ÉUART_LIN_DISABLE 0x00000000U
ÊUART_LIN_ENABLE USART_CR2_LINEN
ÒUART_LINBREAKDETECTLENGTH_10B 0x00000000U
ÓUART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL
ÛUART_DMA_TX_DISABLE 0x00000000U
ÜUART_DMA_TX_ENABLE USART_CR3_DMAT
äUART_DMA_RX_DISABLE 0x00000000U
åUART_DMA_RX_ENABLE USART_CR3_DMAR
íUART_HALF_DUPLEX_DISABLE 0x00000000U
îUART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL
öUART_WAKEUPMETHOD_IDLELINE 0x00000000U
÷UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE
ÿUART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
€UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
‚UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
ƒUART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
‹UART_ADVFEATURE_NO_INIT 0x00000000U
ŒUART_ADVFEATURE_TXINVERT_INIT 0x00000001U
UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
ŽUART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
UART_ADVFEATURE_SWAP_INIT 0x00000008U
UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
‘UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
’UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
“UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U
›UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
œUART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
¤UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
¥UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
­UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
®UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
¶UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
·UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
¿UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
ÀUART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
ÈUART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
ÉUART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN
ÑUART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
ÒUART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
ÚUART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
ÜUART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
åUART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
æUART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM
îUART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
ïUART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME
÷UART_CR2_ADDRESS_LSB_POS 24U
ÿUART_WAKEUP_ON_ADDRESS 0x00000000U
€UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS
ŠUART_DE_POLARITY_HIGH 0x00000000U
‹UART_DE_POLARITY_LOW USART_CR3_DEP
“UART_CR1_DEAT_ADDRESS_LSB_POS 21U
œUART_CR1_DEDT_ADDRESS_LSB_POS 16U
¥UART_IT_MASK 0x001FU
­HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
·UART_FLAG_REACK USART_ISR_REACK
¸UART_FLAG_TEACK USART_ISR_TEACK
¹UART_FLAG_WUF USART_ISR_WUF
ºUART_FLAG_RWU USART_ISR_RWU
»UART_FLAG_SBKF USART_ISR_SBKF
¼UART_FLAG_CMF USART_ISR_CMF
½UART_FLAG_BUSY USART_ISR_BUSY
¾UART_FLAG_ABRF USART_ISR_ABRF
¿UART_FLAG_ABRE USART_ISR_ABRE
ÀUART_FLAG_RTOF USART_ISR_RTOF
ÁUART_FLAG_CTS USART_ISR_CTS
ÂUART_FLAG_CTSIF USART_ISR_CTSIF
ÃUART_FLAG_LBDF USART_ISR_LBDF
ÄUART_FLAG_TXE USART_ISR_TXE
ÅUART_FLAG_TC USART_ISR_TC
ÆUART_FLAG_RXNE USART_ISR_RXNE
ÇUART_FLAG_IDLE USART_ISR_IDLE
ÈUART_FLAG_ORE USART_ISR_ORE
ÉUART_FLAG_NE USART_ISR_NE
ÊUART_FLAG_FE USART_ISR_FE
ËUART_FLAG_PE USART_ISR_PE
âUART_IT_PE 0x0028U
ãUART_IT_TXE 0x0727U
äUART_IT_TC 0x0626U
åUART_IT_RXNE 0x0525U
æUART_IT_IDLE 0x0424U
çUART_IT_LBD 0x0846U
èUART_IT_CTS 0x096AU
éUART_IT_CM 0x112EU
êUART_IT_WUF 0x1476U
ëUART_IT_RTO 0x0B3AU
íUART_IT_ERR 0x0060U
ïUART_IT_ORE 0x0300U
ðUART_IT_NE 0x0200U
ñUART_IT_FE 0x0100U
ùUART_CLEAR_PEF USART_ICR_PECF
úUART_CLEAR_FEF USART_ICR_FECF
ûUART_CLEAR_NEF USART_ICR_NCF
üUART_CLEAR_OREF USART_ICR_ORECF
ýUART_CLEAR_IDLEF USART_ICR_IDLECF
þUART_CLEAR_TCF USART_ICR_TCCF
ÿUART_CLEAR_LBDF USART_ICR_LBDCF
€UART_CLEAR_CTSF USART_ICR_CTSCF
UART_CLEAR_CMF USART_ICR_CMCF
‚UART_CLEAR_WUF USART_ICR_WUCF
ƒUART_CLEAR_RTOF USART_ICR_RTOCF
‹HAL_UART_RECEPTION_STANDARD (0x00000000U)
ŒHAL_UART_RECEPTION_TOIDLE (0x00000001U)
HAL_UART_RECEPTION_TORTO (0x00000002U)
ŽHAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)
–HAL_UART_RXEVENT_TC (0x00000000U)
—HAL_UART_RXEVENT_HT (0x00000001U)
˜HAL_UART_RXEVENT_IDLE (0x00000002U)
²__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U)
¼__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); } while(0U)
Ó__HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Ù__HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
ß__HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
å__HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
ë__HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
ñ__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Ž__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
¡__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ( ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
¼__HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ( ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
×__HAL_UART_GET_IT(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
ë__HAL_UART_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
…__HAL_UART_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
’__HAL_UART_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
˜__HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
ž__HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
¤__HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
ª__HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
¹__HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) do{ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; } while(0U)
Ì__HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) do{ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); } while(0U)
ß__HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) do{ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; } while(0U)
ò__HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) do{ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); } while(0U)
…    UART_DIV_LPUART(__PCLK__,__BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__))
Œ    UART_DIV_SAMPLING8(__PCLK__,__BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
“    UART_DIV_SAMPLING16(__PCLK__,__BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
™    UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
¡    IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
§    IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
­    IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
´    IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || ((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_1_5) || ((__STOPBITS__) == UART_STOPBITS_2))
¾    IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_2))
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Ï    IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__) (((__CONTROL__) == UART_HWCONTROL_NONE) || ((__CONTROL__) == UART_HWCONTROL_RTS) || ((__CONTROL__) == UART_HWCONTROL_CTS) || ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
Ú    IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
á    IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || ((__STATE__) == UART_STATE_ENABLE))
é    IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || ((__SAMPLING__) == UART_OVERSAMPLING_8))
ñ    IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
ù    IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
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IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
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IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
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IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || ((__LIN__) == UART_LIN_ENABLE))
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IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
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IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || ((__DMATX__) == UART_DMA_TX_ENABLE))
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IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || ((__DMARX__) == UART_DMA_RX_ENABLE))
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IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
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IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | UART_ADVFEATURE_TXINVERT_INIT | UART_ADVFEATURE_RXINVERT_INIT | UART_ADVFEATURE_DATAINVERT_INIT | UART_ADVFEATURE_SWAP_INIT | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | UART_ADVFEATURE_DMADISABLEONERROR_INIT | UART_ADVFEATURE_AUTOBAUDRATE_INIT | UART_ADVFEATURE_MSBFIRST_INIT))
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IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
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../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h
stm32l0xx_hal_def.h
stm32l0xx_hal_uart_ex.h


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dHSI_VALUE ((uint32_t)16000000U)
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../Core/Inc/../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf.h
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../Drivers/STM32L0xx_HAL_Driver/Inc/../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.cstm32l0xx_hal.h


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Input Comments:pbdcc-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0+ --fpu=SoftVFP --apcs=/interwork/interwork --no_divide stm32l0xx_hal_tim.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c -ostm32l071rb\stm32l0xx_hal_tim.o --depend=stm32l071rb\stm32l0xx_hal_tim.d --cpu=Cortex-M0+ --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../HIDOLibrary/Include -I../FML/Internet/Module/AIR780E -I../FML/Internet/Module -I../FML/Internet -I../FML -I../HAL -I../APL -I../radio -I../decadriver -I.\RTE\_STM32L071RB -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32L0xx_DFP\2.2.0\Drivers\CMSIS\Device\ST\STM32L0xx\Include -D__MICROLIB -D__UVISION_VERSION=530 -D_RTE_ -DSTM32L071xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32L071xx -D_RTK_MODE_ --omf_browse=stm32l071rb\stm32l0xx_hal_tim.crf ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.ccs
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õ    õõBõWõmõ‰õ—õÂõÜõõõõ<õ]õõ¤õÀõÎõõõ1õ?õ.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.reli.TIM_SlaveTimer_SetConfig.reli.TIM_DMATriggerHalfCplt.reli.TIM_DMATriggerCplt.reli.TIM_DMAPeriodElapsedHalfCplt.reli.TIM_DMAPeriodElapsedCplt.reli.TIM_DMAError.reli.TIM_DMADelayPulseHalfCplt.reli.TIM_DMADelayPulseCplt.reli.TIM_DMACaptureHalfCplt.reli.TIM_DMACaptureCplt.reli.HAL_TIM_SlaveConfigSynchro_IT.reli.HAL_TIM_SlaveConfigSynchro.reli.HAL_TIM_PWM_Stop_IT.reli.HAL_TIM_PWM_Stop_DMA.reli.HAL_TIM_PWM_Stop.reli.HAL_TIM_PWM_Start_IT.reli.HAL_TIM_PWM_Start_DMA.reli.HAL_TIM_PWM_Start.reli.HAL_TIM_PWM_Init.reli.HAL_TIM_PWM_DeInit.reli.HAL_TIM_PWM_ConfigChannel.reli.HAL_TIM_OnePulse_Stop_IT.reli.HAL_TIM_OnePulse_Stop.reli.HAL_TIM_OnePulse_Start_IT.reli.HAL_TIM_OnePulse_Start.reli.HAL_TIM_OnePulse_Init.reli.HAL_TIM_OnePulse_DeInit.reli.HAL_TIM_OnePulse_ConfigChannel.reli.HAL_TIM_OC_Stop_IT.reli.HAL_TIM_OC_Stop_DMA.reli.HAL_TIM_OC_Stop.reli.HAL_TIM_OC_Start_IT.reli.HAL_TIM_OC_Start_DMA.reli.HAL_TIM_OC_Start.reli.HAL_TIM_OC_Init.reli.HAL_TIM_OC_DeInit.reli.HAL_TIM_OC_ConfigChannel.reli.HAL_TIM_IRQHandler.reli.HAL_TIM_IC_Stop_IT.reli.HAL_TIM_IC_Stop_DMA.reli.HAL_TIM_IC_Stop.reli.HAL_TIM_IC_Start_IT.reli.HAL_TIM_IC_Start_DMA.reli.HAL_TIM_IC_Start.reli.HAL_TIM_IC_Init.reli.HAL_TIM_IC_DeInit.reli.HAL_TIM_IC_ConfigChannel.reli.HAL_TIM_Encoder_Stop_IT.reli.HAL_TIM_Encoder_Stop_DMA.reli.HAL_TIM_Encoder_Stop.reli.HAL_TIM_Encoder_Start_IT.reli.HAL_TIM_Encoder_Start_DMA.reli.HAL_TIM_Encoder_Start.reli.HAL_TIM_Encoder_Init.reli.HAL_TIM_Encoder_DeInit.reli.HAL_TIM_DMABurst_WriteStop.reli.HAL_TIM_DMABurst_WriteStart.reli.HAL_TIM_DMABurst_ReadStop.reli.HAL_TIM_DMABurst_ReadStart.reli.HAL_TIM_DMABurst_MultiWriteStart.reli.HAL_TIM_DMABurst_MultiReadStart.reli.HAL_TIM_ConfigOCrefClear.reli.HAL_TIM_ConfigClockSource.reli.HAL_TIM_Base_Stop_DMA.reli.HAL_TIM_Base_Start_DMA.reli.HAL_TIM_Base_Init.reli.HAL_TIM_Base_DeInit.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__ARM_grp.stm32l0xx_hal_tim.c.2_so_000_uNgd_3YmBob_520000__ARM_grp.stm32l0xx_hal_conf.h.2_Iq1000_TtKHBiADR48_300000__ARM_grp.stm32l0xx_hal_uart.h.2_YZ_000_VE1qE2yIuHb_910000__ARM_grp.stm32l0xx_hal_uart_ex.h.2_YF2000_c1QbxzeLA80_900000__ARM_grp.stm32l0xx_hal_tim.h.2_o54100_kGC0fQmuQY2_p10000__ARM_grp.stm32l0xx_hal_tim_ex.h.2_8H1000_YJQWQ7ZRO0d_300000__ARM_grp.stm32l0xx_hal_spi.h.2_8yW000_4V6H6KDmu_5_Z00000__ARM_grp.stm32l0xx_hal_rtc.h.2_Q2X000_GTPKljS1zt4_Q00000__ARM_grp.stm32l0xx_hal_rtc_ex.h.2_sZ7000_lAiOimpWYa6_g00000__ARM_grp.stm32l0xx_hal_pwr.h.2_U63000_2zpv2BOtLV4_800000__ARM_grp.stm32l0xx_hal_pwr_ex.h.2_gz0000_YYpCteHi2za_300000__ARM_grp.stm32l0xx_hal_lptim.h.2_k7V000_qnKHDImYaA6_D00000__ARM_grp.stm32l0xx_hal_i2c.h.2_c6X000_68Me2tARJQ4_Y00000__ARM_grp.stm32l0xx_hal_i2c_ex.h.2_M41000_M52sOjZ980c_300000__ARM_grp.stm32l0xx_hal_flash.h.2_hE4000_4ypufzEAsm1_n00000__ARM_grp.stm32l0xx_hal_flash_ramfunc.h.2_kv0000_t2ubZKPodP5_300000__ARM_grp.stm32l0xx_hal_flash_ex.h.2_4J5000_rNIAs8fp4Id_m00000__ARM_grp.stm32l0xx_hal_adc.h.2_Qa$000_2LoaSsph6L4_b10000__ARM_grp.stm32l0xx_hal_adc_ex.h.2_g91000_WAvMxy67Cge_300000__ARM_grp.stm32l0xx_hal_cortex.h.2_sB3000_StV5gVMa$Ef_h00000__ARM_grp.stm32l0xx_hal_dma.h.2_M3V000_5PCkluviL41_D00000__ARM_grp.stm32l0xx_hal_gpio.h.2_gZ2000_MHFCZr3DuQ9_b00000__ARM_grp.stm32l0xx_hal_gpio_ex.h.2_U42000_grytRTBjDDb_300000__ARM_grp.stm32l0xx_hal_exti.h.2_sK2000_7lwdWjm88Be_b00000__ARM_grp.stm32l0xx_hal_rcc.h.2_gId000_GVlfS6n8Zmb_o00000__ARM_grp.stm32l0xx_hal_rcc_ex.h.2_cMd000_I7evWw$Gsz6_e00000__ARM_grp.stm32l0xx_hal_def.h.2_IW0000_R0Zk5$6fuN0_300000__ARM_grp.stddef.h.2_Qy0000_WtInCL_KHBf_300000__ARM_grp.stm32_hal_legacy.h.2_U4Q000_BAjWBd9LeV8_300000__ARM_grp.stm32l0xx.h.2_sf1000_jIYSWEKXKb5_300000__ARM_grp.stm32l0xx_hal.h.2_X26000_mM2iIkXzQ9a_h00000__ARM_grp.stm32l071xx.h.2_0lE100_HGop9tXVns2_k00000__ARM_grp.system_stm32l0xx.h.2_6v2000_WU3hkpypIja_h00000__ARM_grp.core_cm0plus.h.2_cjV000_bsmQg$K3Rxf_s10000__ARM_grp.mpu_armv7.h.2_QF2000_qYnXs3m3yif_k00000__ARM_grp.cmsis_compiler.h.2_kv0000_VSkayAa7jsd_300000__ARM_grp.cmsis_armcc.h.2_w02000_9qZ1AHJ$EB9_R00000__ARM_grp.cmsis_version.h.2_Ax0000_hEOKoiRkYy7_300000__ARM_grp.stdint.h.2_8G1000_Y8yz6lqXnp2_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loci.__ARM_common_switch8i.TIM_TI2_SetConfigi.TIM_TI2_ConfigInputStagei.TIM_TI1_SetConfigi.TIM_TI1_ConfigInputStagei.TIM_OC4_SetConfigi.TIM_OC3_SetConfigi.TIM_OC2_SetConfigi.TIM_OC1_SetConfigi.TIM_ITRx_SetConfigi.TIM_ETR_SetConfigi.TIM_CCxChannelCmdi.TIM_Base_SetConfigi.HAL_TIM_TriggerHalfCpltCallbacki.HAL_TIM_TriggerCallbacki.HAL_TIM_ReadCapturedValuei.HAL_TIM_PeriodElapsedHalfCpltCallbacki.HAL_TIM_PeriodElapsedCallbacki.HAL_TIM_PWM_PulseFinishedHalfCpltCallbacki.HAL_TIM_PWM_PulseFinishedCallbacki.HAL_TIM_PWM_MspIniti.HAL_TIM_PWM_MspDeIniti.HAL_TIM_PWM_GetStatei.HAL_TIM_OnePulse_MspIniti.HAL_TIM_OnePulse_MspDeIniti.HAL_TIM_OnePulse_GetStatei.HAL_TIM_OC_MspIniti.HAL_TIM_OC_MspDeIniti.HAL_TIM_OC_GetStatei.HAL_TIM_OC_DelayElapsedCallbacki.HAL_TIM_IC_MspIniti.HAL_TIM_IC_MspDeIniti.HAL_TIM_IC_GetStatei.HAL_TIM_IC_CaptureHalfCpltCallbacki.HAL_TIM_IC_CaptureCallbacki.HAL_TIM_GetChannelStatei.HAL_TIM_GetActiveChanneli.HAL_TIM_GenerateEventi.HAL_TIM_ErrorCallbacki.HAL_TIM_Encoder_MspIniti.HAL_TIM_Encoder_MspDeIniti.HAL_TIM_Encoder_GetStatei.HAL_TIM_DMABurstStatei.HAL_TIM_ConfigTI1Inputi.HAL_TIM_Base_Stop_ITi.HAL_TIM_Base_Stopi.HAL_TIM_Base_Start_ITi.HAL_TIM_Base_Starti.HAL_TIM_Base_MspIniti.HAL_TIM_Base_MspDeIniti.HAL_TIM_Base_GetState.revsh_text.rev16_textLib$$Request$$armlibHAL_DMA_Start_ITHAL_DMA_Abort_IT__ARM_grp..debug_pubnames$system_stm32l0xx.h$.2_6v2000_WU3hkpypIja_h00000__ARM_grp..debug_pubnames$stm32l0xx_hal_flash.h$.2_hE4000_4ypufzEAsm1_n00000__ARM_grp..debug_pubnames$stm32l0xx_hal.h$.2_X26000_mM2iIkXzQ9a_h00000__ARM_grp..debug_macinfo$system_stm32l0xx.h$.2_6v2000_WU3hkpypIja_h00000__ARM_grp..debug_macinfo$stm32l0xx_hal_uart_ex.h$.2_YF2000_c1QbxzeLA80_900000__ARM_grp..debug_macinfo$stm32l0xx_hal_uart.h$.2_YZ_000_VE1qE2yIuHb_910000__ARM_grp..debug_macinfo$stm32l0xx_hal_tim_ex.h$.2_8H1000_YJQWQ7ZRO0d_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_tim.h$.2_o54100_kGC0fQmuQY2_p10000__ARM_grp..debug_macinfo$stm32l0xx_hal_tim.c$.2_so_000_uNgd_3YmBob_520000__ARM_grp..debug_macinfo$stm32l0xx_hal_spi.h$.2_8yW000_4V6H6KDmu_5_Z00000__ARM_grp..debug_macinfo$stm32l0xx_hal_rtc_ex.h$.2_sZ7000_lAiOimpWYa6_g00000__ARM_grp..debug_macinfo$stm32l0xx_hal_rtc.h$.2_Q2X000_GTPKljS1zt4_Q00000__ARM_grp..debug_macinfo$stm32l0xx_hal_rcc_ex.h$.2_cMd000_I7evWw$Gsz6_e00000__ARM_grp..debug_macinfo$stm32l0xx_hal_rcc.h$.2_gId000_GVlfS6n8Zmb_o00000__ARM_grp..debug_macinfo$stm32l0xx_hal_pwr_ex.h$.2_gz0000_YYpCteHi2za_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_pwr.h$.2_U63000_2zpv2BOtLV4_800000__ARM_grp..debug_macinfo$stm32l0xx_hal_lptim.h$.2_k7V000_qnKHDImYaA6_D00000__ARM_grp..debug_macinfo$stm32l0xx_hal_i2c_ex.h$.2_M41000_M52sOjZ980c_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_i2c.h$.2_c6X000_68Me2tARJQ4_Y00000__ARM_grp..debug_macinfo$stm32l0xx_hal_gpio_ex.h$.2_U42000_grytRTBjDDb_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_gpio.h$.2_gZ2000_MHFCZr3DuQ9_b00000__ARM_grp..debug_macinfo$stm32l0xx_hal_flash_ramfunc.h$.2_kv0000_t2ubZKPodP5_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_flash_ex.h$.2_4J5000_rNIAs8fp4Id_m00000__ARM_grp..debug_macinfo$stm32l0xx_hal_flash.h$.2_hE4000_4ypufzEAsm1_n00000__ARM_grp..debug_macinfo$stm32l0xx_hal_exti.h$.2_sK2000_7lwdWjm88Be_b00000__ARM_grp..debug_macinfo$stm32l0xx_hal_dma.h$.2_M3V000_5PCkluviL41_D00000__ARM_grp..debug_macinfo$stm32l0xx_hal_def.h$.2_IW0000_R0Zk5$6fuN0_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_cortex.h$.2_sB3000_StV5gVMa$Ef_h00000__ARM_grp..debug_macinfo$stm32l0xx_hal_conf.h$.2_Iq1000_TtKHBiADR48_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_adc_ex.h$.2_g91000_WAvMxy67Cge_300000__ARM_grp..debug_macinfo$stm32l0xx_hal_adc.h$.2_Qa$000_2LoaSsph6L4_b10000__ARM_grp..debug_macinfo$stm32l0xx_hal.h$.2_X26000_mM2iIkXzQ9a_h00000__ARM_grp..debug_macinfo$stm32l0xx.h$.2_sf1000_jIYSWEKXKb5_300000__ARM_grp..debug_macinfo$stm32l071xx.h$.2_0lE100_HGop9tXVns2_k00000__ARM_grp..debug_macinfo$stm32_hal_legacy.h$.2_U4Q000_BAjWBd9LeV8_300000__ARM_grp..debug_macinfo$stdint.h$.2_8G1000_Y8yz6lqXnp2_300000__ARM_grp..debug_macinfo$stddef.h$.2_Qy0000_WtInCL_KHBf_300000__ARM_grp..debug_macinfo$mpu_armv7.h$.2_QF2000_qYnXs3m3yif_k00000__ARM_grp..debug_macinfo$core_cm0plus.h$.2_cjV000_bsmQg$K3Rxf_s10000__ARM_grp..debug_macinfo$cmsis_version.h$.2_Ax0000_hEOKoiRkYy7_300000__ARM_grp..debug_macinfo$cmsis_compiler.h$.2_kv0000_VSkayAa7jsd_300000__ARM_grp..debug_macinfo$cmsis_armcc.h$.2_w02000_9qZ1AHJ$EB9_R00000__ARM_grp..debug_line$system_stm32l0xx.h$.2_6v2000_WU3hkpypIja_h00000__ARM_grp..debug_line$stm32l0xx_hal_uart_ex.h$.2_YF2000_c1QbxzeLA80_900000__ARM_grp..debug_line$stm32l0xx_hal_uart.h$.2_YZ_000_VE1qE2yIuHb_910000__ARM_grp..debug_line$stm32l0xx_hal_tim_ex.h$.2_8H1000_YJQWQ7ZRO0d_300000__ARM_grp..debug_line$stm32l0xx_hal_tim.h$.2_o54100_kGC0fQmuQY2_p10000__ARM_grp..debug_line$stm32l0xx_hal_tim.c$.2_so_000_uNgd_3YmBob_520000__ARM_grp..debug_line$stm32l0xx_hal_spi.h$.2_8yW000_4V6H6KDmu_5_Z00000__ARM_grp..debug_line$stm32l0xx_hal_rtc_ex.h$.2_sZ7000_lAiOimpWYa6_g00000__ARM_grp..debug_line$stm32l0xx_hal_rtc.h$.2_Q2X000_GTPKljS1zt4_Q00000__ARM_grp..debug_line$stm32l0xx_hal_rcc_ex.h$.2_cMd000_I7evWw$Gsz6_e00000__ARM_grp..debug_line$stm32l0xx_hal_rcc.h$.2_gId000_GVlfS6n8Zmb_o00000__ARM_grp..debug_line$stm32l0xx_hal_pwr_ex.h$.2_gz0000_YYpCteHi2za_300000__ARM_grp..debug_line$stm32l0xx_hal_pwr.h$.2_U63000_2zpv2BOtLV4_800000__ARM_grp..debug_line$stm32l0xx_hal_lptim.h$.2_k7V000_qnKHDImYaA6_D00000__ARM_grp..debug_line$stm32l0xx_hal_i2c_ex.h$.2_M41000_M52sOjZ980c_300000__ARM_grp..debug_line$stm32l0xx_hal_i2c.h$.2_c6X000_68Me2tARJQ4_Y00000__ARM_grp..debug_line$stm32l0xx_hal_gpio_ex.h$.2_U42000_grytRTBjDDb_300000__ARM_grp..debug_line$stm32l0xx_hal_gpio.h$.2_gZ2000_MHFCZr3DuQ9_b00000__ARM_grp..debug_line$stm3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