#include "Rcc_Nvic_Systick.h"
|
|
//void Rcc_Init(void)
|
//{
|
// //----------ʹÓÃÄÚ²¿RC¾§ÕñHSI 64MHz-----------
|
// RCC_DeInit(); //½«ÍâÉèRCC¼Ä´æÆ÷ÖØÉèΪȱʡֵ
|
// RCC_HSICmd(ENABLE); //ÄÚ²¿Ê±ÖÓʹÄÜ
|
// while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY)== RESET); //µÈ´ýHSI¾ÍÐ÷
|
//
|
// FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); //Ñ¡ÔñFLASHԤȡָ»º´æµÄÄ£,Ԥȡָ»º´æʹÄÜ
|
// FLASH_SetLatency(FLASH_Latency_2); //ÉèÖÃFLASH´æ´¢Æ÷ÑÓʱʱÖÓÖÜÆÚÊýFLASH_Latency_2 2ÑÓʱÖÜÆÚ
|
//
|
//
|
// RCC_HCLKConfig(RCC_SYSCLK_Div1); //ÉèÖÃAHBʱÖÓ£¨HCLK£© RCC_SYSCLK_Div1¡ª¡ªAHBʱÖÓ = ϵͳʱÖÓ
|
// RCC_PCLK2Config(RCC_HCLK_Div1); //ÉèÖøßËÙAHBʱÖÓ£¨PCLK2£©RCC_HCLK_Div1¡ª¡ªAPB2ʱÖÓ = HCLK
|
// RCC_PCLK1Config(RCC_HCLK_Div2); //ÉèÖõÍËÙAHBʱÖÓ£¨PCLK1£©RCC_HCLK_Div2¡ª¡ªAPB1ʱÖÓ = HCLK/2
|
// RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_16); //ÉèÖÃPLLʱÖÓÔ´¼°±¶ÆµÏµÊý£¬ÆµÂÊΪ8/2*16=64Mhz
|
// RCC_PLLCmd(ENABLE); //ʹÄÜPLL
|
//
|
// while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); //¼ì²éÖ¸¶¨µÄRCC±ê־λ(PLL×¼±¸ºÃ±êÖ¾)ÉèÖÃÓë·ñ
|
// RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //ÉèÖÃϵͳʱÖÓ£¨SYSCLK£©
|
// while(RCC_GetSYSCLKSource() != 0x08); //0x08£ºPLL×÷ΪϵͳʱÖÓ
|
|
//// //----------ʹÓÃÍⲿRC¾§Õñ 72MHz-----------
|
//// RCC_DeInit(); //³õʼ»¯ÎªÈ±Ê¡Öµ
|
//// RCC_HSEConfig(RCC_HSE_ON); //ʹÄÜÍⲿµÄ¸ßËÙʱÖÓ
|
//// while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET); //µÈ´ýÍⲿ¸ßËÙʱÖÓʹÄܾÍÐ÷
|
////
|
//// FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); //Enable Prefetch Buffer
|
//// FLASH_SetLatency(FLASH_Latency_2); //Flash 2 wait state
|
////
|
//// RCC_HCLKConfig(RCC_SYSCLK_Div1); //HCLK = SYSCLK
|
//// RCC_PCLK2Config(RCC_HCLK_Div1); //PCLK2 = HCLK
|
//// RCC_PCLK1Config(RCC_HCLK_Div2); //PCLK1 = HCLK/2
|
//// RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_9); //PLLCLK = 8MHZ * 9 =72MHZ
|
//// RCC_PLLCmd(ENABLE); //Enable PLLCLK
|
////
|
//// while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); //Wait till PLLCLK is ready
|
//// RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //Select PLL as system clock
|
//// while(RCC_GetSYSCLKSource()!=0x08); //Wait till PLL is used as system clock source
|
//
|
//}
|
int RCC_Configuration(void)
|
{
|
ErrorStatus HSEStartUpStatus;
|
RCC_ClocksTypeDef RCC_ClockFreq;
|
|
/* RCC system reset(for debug purpose) */
|
RCC_DeInit();
|
|
/* Enable HSE */
|
RCC_HSEConfig(RCC_HSE_ON);
|
|
/* Wait till HSE is ready */
|
HSEStartUpStatus = RCC_WaitForHSEStartUp();
|
|
if(HSEStartUpStatus != ERROR)
|
{
|
SystemInit();
|
/* Enable Prefetch Buffer */
|
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
|
|
/****************************************************************/
|
/* HSE= up to 25MHz (on EVB1000 is 12MHz),
|
* HCLK=72MHz, PCLK2=72MHz, PCLK1=36MHz */
|
/****************************************************************/
|
/* Flash 2 wait state */
|
FLASH_SetLatency(FLASH_Latency_2);
|
/* HCLK = SYSCLK */
|
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
/* PCLK2 = HCLK */
|
RCC_PCLK2Config(RCC_HCLK_Div1);
|
/* PCLK1 = HCLK/2 */
|
RCC_PCLK1Config(RCC_HCLK_Div2);
|
/* ADCCLK = PCLK2/4 */
|
RCC_ADCCLKConfig(RCC_PCLK2_Div6);
|
}
|
// /* Configure PLLs *********************************************************/
|
// /* PLL2 configuration: PLL2CLK = (HSE / 4) * 8 = 24 MHz */
|
// RCC_PREDIV2Config(RCC_PREDIV2_Div4);
|
// RCC_PLL2Config(RCC_PLL2Mul_8);
|
|
// /* Enable PLL2 */
|
// RCC_PLL2Cmd(ENABLE);
|
|
// /* Wait till PLL2 is ready */
|
// while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET){}
|
|
// /* PLL1 configuration: PLLCLK = (PLL2 / 3) * 9 = 72 MHz */
|
// RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div3);
|
|
// RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
|
|
// /* Enable PLL */
|
// RCC_PLLCmd(ENABLE);
|
|
// /* Wait till PLL is ready */
|
// while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){}
|
|
// /* Select PLL as system clock source */
|
// RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
|
// /* Wait till PLL is used as system clock source */
|
// while (RCC_GetSYSCLKSource() != 0x08){}
|
// }
|
|
RCC_GetClocksFreq(&RCC_ClockFreq);
|
|
/* Enable SPI1 clock */
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
|
|
/* Enable SPI2 clock */
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
|
|
/* Enable GPIOs clocks */
|
RCC_APB2PeriphClockCmd(
|
RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
|
RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD |
|
RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO,
|
ENABLE);
|
|
return 0;
|
}
|
void Nvic_Init(void)
|
{
|
NVIC_InitTypeDef NVIC_InitStructure;
|
|
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
|
|
/* Enable and set EXTI Interrupt to the lowest priority */
|
NVIC_InitStructure.NVIC_IRQChannel = DECAIRQ_EXTI_IRQn;
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 15;
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
|
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
NVIC_Init(&NVIC_InitStructure);
|
|
NVIC_InitStructure.NVIC_IRQChannel = RTCAlarm_IRQn;
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
NVIC_InitStructure.NVIC_IRQChannelCmd =ENABLE;
|
|
NVIC_Init(&NVIC_InitStructure);
|
}
|
//?????3?????
|
//???????APB1?2?,?APB1?36M
|
//arr:??????
|
//psc:??????
|
//?????????3!
|
void TIM3_Int_Init(void)
|
{
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
NVIC_InitTypeDef NVIC_InitStructure;
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); //????
|
|
//???TIM3???
|
TIM_TimeBaseStructure.TIM_Period = 1000-1; //???????????????????????????
|
TIM_TimeBaseStructure.TIM_Prescaler =72-1; //??????TIMx???????????
|
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; //??????:TDTS = Tck_tim
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; //TIM??????
|
TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); //??????????TIMx???????
|
|
TIM_ITConfig(TIM3,TIM_IT_Update,ENABLE ); //?????TIM3??,??????
|
|
//?????NVIC??
|
NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; //TIM3??
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; //?????0?
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; //????3?
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //IRQ?????
|
NVIC_Init(&NVIC_InitStructure); //???NVIC???
|
|
|
TIM_Cmd(TIM3, ENABLE); //??TIMx
|
}
|
//???3??????
|
int Systick_Init(void)
|
{
|
int time_retry = 500;
|
if (SysTick_Config(72000))
|
{
|
/* Capture error */
|
while (time_retry--);
|
return 1;
|
}
|
NVIC_SetPriority(SysTick_IRQn, 5);
|
|
return 0;
|
|
}
|
|
void delay_us(uint32_t nTimer)
|
{
|
uint32_t i=0;
|
for(i=0; i<nTimer; i++) {
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
__NOP();
|
}
|
}
|
|
void delay_ms(uint32_t nTimer)
|
{
|
uint32_t i=1000*nTimer;
|
delay_us(i);
|
}
|
