Ø '] Ù@4../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.hÅצcÙ-!../Core/Inc/stm32l0xx_hal_conf.hÞêÛ§ÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.hÅצÄÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.hÅצÍÙE9../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.hÅצ?ÙG;../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.hÅצÓÙ4(../Drivers/CMSIS/Include/core_cm0plus.h¼×¦,Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$Ù5)../Drivers/CMSIS/Include/cmsis_version.h¼×¦rÙ6*../Drivers/CMSIS/Include/cmsis_compiler.h¼×¦Ù3'../Drivers/CMSIS/Include/cmsis_armcc.h¼×¦vÙ1%../Drivers/CMSIS/Include/mpu_armv7.h¼×¦`ÙL@../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.hÅצ-Ù@4../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.hÅצcÙJ>../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hÅצÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@ÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.hÅצÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.hÅצ@ÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.hÅצKÙH<../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.hÅצ ÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.hÅצÊÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.hÅצaÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.hÅצÔÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.hÅצÙF:../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.hÅצêÙI=../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.hÅצ¨ÙNB../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.hÅצÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.hÅצþÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.hÅצ¼ÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.hÅצOÙF:../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.hÅצÒÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.hÅצ£ÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.hÅצaÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.hÅצ°ÙD8../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.hÅצ²ÙG;../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.hÅצpÙE9../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.hÅצ>ÙH<../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.hÅצüÙG;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.cÅצ´ÚP__STM32L0xx_HAL_HKÚP __cplusplus
|
Ú P__STM32L0xx_HAL_CONF_H¼ÚPHAL_MODULE_ENABLEDcÚ PHAL_ADC_MODULE_ENABLED4Ú PHAL_IWDG_MODULE_ENABLEDÏÚ!PHAL_LPTIM_MODULE_ENABLEDrÚ PHAL_SPI_MODULE_ENABLEDÚ PHAL_TIM_MODULE_ENABLEDÚ PHAL_UART_MODULE_ENABLED¾Ú PHAL_GPIO_MODULE_ENABLEDËÚ PHAL_EXTI_MODULE_ENABLEDÀÚ PHAL_DMA_MODULE_ENABLED*Ú PHAL_I2C_MODULE_ENABLED>Ú PHAL_RCC_MODULE_ENABLED$Ú!PHAL_FLASH_MODULE_ENABLEDÚ PHAL_PWR_MODULE_ENABLEDÚ"PHAL_CORTEX_MODULE_ENABLED!ÚP
|
HSE_VALUEýÚ PHSE_STARTUP_TIMEOUTÚP
|
MSI_VALUEôÚP
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HSI_VALUEùÚP HSI48_VALUEÚP
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LSI_VALUEõÚP
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LSE_VALUEùÚ PLSE_STARTUP_TIMEOUT©ÚP
|
VDD_VALUEÿÚPTICK_INT_PRIORITYSÚP USE_RTOS'ÚPPREFETCH_ENABLEVÚPPREREAD_ENABLE¦Ú PBUFFER_CACHE_DISABLEãÚ'P USE_HAL_ADC_REGISTER_CALLBACKS¤Ú(P USE_HAL_COMP_REGISTER_CALLBACKS;Ú'P USE_HAL_DAC_REGISTER_CALLBACKS¤Ú'P USE_HAL_I2C_REGISTER_CALLBACKS®Ú'P USE_HAL_I2S_REGISTER_CALLBACKSÚ(P USE_HAL_IRDA_REGISTER_CALLBACKSJÚ)P!USE_HAL_LPTIM_REGISTER_CALLBACKSâÚ'P USE_HAL_PCD_REGISTER_CALLBACKSÚ'P USE_HAL_RNG_REGISTER_CALLBACKS
Ú'P USE_HAL_RTC_REGISTER_CALLBACKSÚ-P%USE_HAL_SMARTCARD_REGISTER_CALLBACKS¿Ú)P!USE_HAL_SMBUS_REGISTER_CALLBACKSÞÚ'P USE_HAL_SPI_REGISTER_CALLBACKSÚ'P USE_HAL_TIM_REGISTER_CALLBACKSÚ'P USE_HAL_TSC_REGISTER_CALLBACKSÚ(P USE_HAL_UART_REGISTER_CALLBACKS.Ú)P!USE_HAL_USART_REGISTER_CALLBACKSÙÚ(P USE_HAL_WWDG_REGISTER_CALLBACKS1Ú P__STM32L0xx_HAL_RCC_H Ú P__STM32L0xx_HAL_DEFÀÚP__STM32L0xx_HÚPSTM32L0èÚP STM32L071xxÚPUSE_HAL_DRIVERaÚ'P __STM32L0xx_CMSIS_VERSION_MAIN%Ú'P __STM32L0xx_CMSIS_VERSION_SUB1/Ú'P __STM32L0xx_CMSIS_VERSION_SUB2.Ú%P __STM32L0xx_CMSIS_VERSION_RC¹Ú"P__STM32L0xx_CMSIS_VERSION³ÚP__STM32L071xx_HÚP__CM0PLUS_REV£ÚP__MPU_PRESENTÚP__VTOR_PRESENT&ÚP__NVIC_PRIO_BITSÚ P__Vendor_SysTickConfigôÚ NonMaskableInt_IRQn¨Ú HardFault_IRQnÚ SVCall_IRQn Ú PendSV_IRQnþÚ SysTick_IRQnbÚ
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WWDG_IRQnùÚ PVD_IRQnJÚ RTC_IRQnKÚ FLASH_IRQnÂÚ RCC_IRQn\Ú EXTI0_1_IRQn2Ú EXTI2_3_IRQn.Ú EXTI4_15_IRQn÷Ú DMA1_Channel1_IRQnÔÚ DMA1_Channel2_3_IRQn=Ú! DMA1_Channel4_5_6_7_IRQnÚ ADC1_COMP_IRQn¡Ú LPTIM1_IRQnwÚ USART4_5_IRQnÓÚ
|
TIM2_IRQnÚ
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TIM3_IRQnÚ
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TIM6_IRQnÚ
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TIM7_IRQnÚ TIM21_IRQnãÚ
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I2C3_IRQnAÚ TIM22_IRQnâÚ
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I2C2_IRQnBÚ
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SPI1_IRQnÚ
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SPI2_IRQnÚ USART1_IRQnnÚ USART2_IRQnmÚ LPUART1_IRQn#Ú
|
IRQn_TypeÚ!P__CORE_CM0PLUS_H_GENERICNÚP __stdint_hÚP__ARMCLIB_VERSIONlÚP__INT64_TYPE__;ÚP__INT64ªÚP__INT64_C_SUFFIX__ÚP __PASTE2NÚP__PASTEÚP
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__INT64_CÚP __UINT64_CÚP__ARMCC_VERSIONÚP __LONGLONGÚP__STDINT_DECLSQÚP __CLIBNSBÚint8_tÚint16_tnÚint32_tpÚint64_tkÚuint8_t(Ú uint16_t÷Ú uint32_tùÚ uint64_tôÚ int_least8_tÚint_least16_têÚint_least32_tìÚint_least64_tçÚuint_least8_t¤Úuint_least16_tsÚuint_least32_tuÚuint_least64_tpÚ int_fast8_tÚ int_fast16_tWÚ int_fast32_tYÚ int_fast64_tTÚ uint_fast8_tÚuint_fast16_tàÚuint_fast32_tâÚuint_fast64_tÝÚP __sizeof_ptr®Ú intptr_t}Ú
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UINT8_MAXüÚP UINT16_MAXËÚP UINT32_MAXÍÚP UINT64_MAXÈÚPINT_LEAST8_MINqÚPINT_LEAST16_MIN@ÚPINT_LEAST32_MINBÚPINT_LEAST64_MIN=ÚPINT_LEAST8_MAXoÚPINT_LEAST16_MAX>ÚPINT_LEAST32_MAX@ÚPINT_LEAST64_MAX;ÚPUINT_LEAST8_MAXÚPUINT_LEAST16_MAXçÚPUINT_LEAST32_MAXéÚPUINT_LEAST64_MAXäÚPINT_FAST8_MIN¾ÚPINT_FAST16_MINÚPINT_FAST32_MINÚPINT_FAST64_MINÚPINT_FAST8_MAX¼ÚPINT_FAST16_MAXÚPINT_FAST32_MAXÚPINT_FAST64_MAXÚPUINT_FAST8_MAXeÚPUINT_FAST16_MAX4ÚPUINT_FAST32_MAX6ÚPUINT_FAST64_MAX1ÚP INTPTR_MINÚP INTPTR_MAXÚP UINTPTR_MAX:ÚP INTMAX_MIN£ÚP INTMAX_MAX¡ÚP UINTMAX_MAXJÚP PTRDIFF_MINcÚP PTRDIFF_MAXaÚPSIG_ATOMIC_MINmÚPSIG_ATOMIC_MAXkÚP SIZE_MAX;ÚP
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WCHAR_MINÚP
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UINTMAX_CñÚP__CMSIS_VERSION_H@Ú P__CM_CMSIS_VERSION_MAINhÚ P__CM_CMSIS_VERSION_SUB¥ÚP__CM_CMSIS_VERSIONöÚ%P __CM0PLUS_CMSIS_VERSION_MAINêÚ$P __CM0PLUS_CMSIS_VERSION_SUB'Ú P__CM0PLUS_CMSIS_VERSIONxÚP __CORTEX_MxÚP __FPU_USED~ÚP __CC_ARM6ÚP__CMSIS_COMPILER_H ÚP__CMSIS_ARMCC_HÚP__TARGET_ARCH_6S_MÚP__ARM_ARCH_6M__òÚP__ASM"ÚP __INLINE>ÚP__STATIC_INLINE Ú P__STATIC_FORCEINLINEÚP __NO_RETURNÚP__USEDÐÚP__WEAKÙÚP __PACKEDUÚP__PACKED_STRUCTÚP__PACKED_UNIONaÚP__UNALIGNED_UINT32NÚ!P__UNALIGNED_UINT16_WRITEVÚ P__UNALIGNED_UINT16_READÇÚ!P__UNALIGNED_UINT32_WRITEXÚ P__UNALIGNED_UINT32_READÉÚP
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__ALIGNEDÚP __RESTRICTÚ __get_CONTROL\Ú
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|
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|
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|
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"ÈvectorRÚ"ÈvectorsóÚ __NVIC_GetVectorôÚ,""ÌIRQnvÚ"ÌvectorsïÚ __NVIC_SystemResetûÚ __nopÓÚPARM_MPU_ARMV7_H Ú PARM_MPU_REGION_SIZE_32B©Ú PARM_MPU_REGION_SIZE_64B¤Ú!PARM_MPU_REGION_SIZE_128BqÚ!PARM_MPU_REGION_SIZE_256BoÚ!PARM_MPU_REGION_SIZE_512BtÚ PARM_MPU_REGION_SIZE_1KBÚ PARM_MPU_REGION_SIZE_2KBÚ PARM_MPU_REGION_SIZE_4KBÚ PARM_MPU_REGION_SIZE_8KBÚ!PARM_MPU_REGION_SIZE_16KBZÚ!PARM_MPU_REGION_SIZE_32KB\Ú!PARM_MPU_REGION_SIZE_64KBWÚ"PARM_MPU_REGION_SIZE_128KB$Ú"PARM_MPU_REGION_SIZE_256KB"Ú"PARM_MPU_REGION_SIZE_512KB'Ú PARM_MPU_REGION_SIZE_1MBÚ PARM_MPU_REGION_SIZE_2MBÚ PARM_MPU_REGION_SIZE_4MBÚ PARM_MPU_REGION_SIZE_8MBÚ!PARM_MPU_REGION_SIZE_16MBXÚ!PARM_MPU_REGION_SIZE_32MBZÚ!PARM_MPU_REGION_SIZE_64MBUÚ"PARM_MPU_REGION_SIZE_128MB"Ú"PARM_MPU_REGION_SIZE_256MB Ú"PARM_MPU_REGION_SIZE_512MB%Ú PARM_MPU_REGION_SIZE_1GBÚ PARM_MPU_REGION_SIZE_2GBÚ PARM_MPU_REGION_SIZE_4GBÚPARM_MPU_AP_NONEýÚPARM_MPU_AP_PRIVìÚPARM_MPU_AP_URO9ÚPARM_MPU_AP_FULLúÚPARM_MPU_AP_PRO>ÚPARM_MPU_AP_ROÚP ARM_MPU_RBARüÚPARM_MPU_ACCESS_ ÚPARM_MPU_RASR_EXéÚP ARM_MPU_RASRëÚ PARM_MPU_ACCESS_ORDEREDùÚ PARM_MPU_ACCESS_DEVICEPÚ PARM_MPU_ACCESS_NORMAL7Ú PARM_MPU_CACHEP_NOCACHEÚ PARM_MPU_CACHEP_WB_WRA,Ú PARM_MPU_CACHEP_WT_NWA Ú PARM_MPU_CACHEP_WB_NWA0Ú8
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"ÿRBARÚ
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"ÿRASRÚARM_MPU_Region_tÚ ARM_MPU_EnableÚ,
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" MPU_ControlíÚ"PSCB_SHCSR_MEMFAULTENA_MskÅÚ ARM_MPU_DisableÚ ARM_MPU_ClrRegion½Ú,
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"rnrÙÚ ARM_MPU_SetRegion²Ú,
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"rnrÔÚ,
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"rasrlÚ orderedCpyÏÚ,"dstÉÚ,"srcÌÚ,
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"lenãÚ
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"iáÚ ARM_MPU_LoadÌÚ,"tableÚ,
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"cntØÚ
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SystemCoreClockãÚ<AHBPrescTableóÚ<APBPrescTableóÚ< PLLMulTable°Ú SystemInit»Ú SystemCoreClockUpdateaÚ8
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"·CSR Ú COMP_TypeDefªÚ8
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ADC_TR_HTñÚPADC_TR_LT_PosTÚPADC_TR_LT_Msk[ÚP
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ADC_TR_LTíÚ PADC_CHSELR_CHSEL_Pos\Ú PADC_CHSELR_CHSEL_MskcÚPADC_CHSELR_CHSELõÚ PADC_CHSELR_CHSEL18_PosïÚ PADC_CHSELR_CHSEL18_MsköÚPADC_CHSELR_CHSEL18Ú PADC_CHSELR_CHSEL17_PosðÚ PADC_CHSELR_CHSEL17_Msk÷ÚPADC_CHSELR_CHSEL17Ú PADC_CHSELR_CHSEL15_PosòÚ PADC_CHSELR_CHSEL15_MskùÚPADC_CHSELR_CHSEL15Ú PADC_CHSELR_CHSEL14_PosóÚ PADC_CHSELR_CHSEL14_MskúÚPADC_CHSELR_CHSEL14Ú PADC_CHSELR_CHSEL13_PosôÚ PADC_CHSELR_CHSEL13_MskûÚPADC_CHSELR_CHSEL13Ú PADC_CHSELR_CHSEL12_PosõÚ PADC_CHSELR_CHSEL12_MsküÚPADC_CHSELR_CHSEL12Ú PADC_CHSELR_CHSEL11_PosöÚ PADC_CHSELR_CHSEL11_MskýÚPADC_CHSELR_CHSEL11Ú PADC_CHSELR_CHSEL10_Pos÷Ú PADC_CHSELR_CHSEL10_MskþÚPADC_CHSELR_CHSEL10Ú PADC_CHSELR_CHSEL9_Pos!Ú PADC_CHSELR_CHSEL9_Msk(ÚPADC_CHSELR_CHSEL9ºÚ PADC_CHSELR_CHSEL8_Pos"Ú PADC_CHSELR_CHSEL8_Msk)ÚPADC_CHSELR_CHSEL8»Ú PADC_CHSELR_CHSEL7_Pos#Ú PADC_CHSELR_CHSEL7_Msk*ÚPADC_CHSELR_CHSEL7¼Ú PADC_CHSELR_CHSEL6_Pos$Ú PADC_CHSELR_CHSEL6_Msk+ÚPADC_CHSELR_CHSEL6½Ú PADC_CHSELR_CHSEL5_Pos%Ú PADC_CHSELR_CHSEL5_Msk,ÚPADC_CHSELR_CHSEL5¾Ú PADC_CHSELR_CHSEL4_Pos&Ú PADC_CHSELR_CHSEL4_Msk-ÚPADC_CHSELR_CHSEL4¿Ú PADC_CHSELR_CHSEL3_Pos'Ú PADC_CHSELR_CHSEL3_Msk.ÚPADC_CHSELR_CHSEL3ÀÚ PADC_CHSELR_CHSEL2_Pos(Ú PADC_CHSELR_CHSEL2_Msk/ÚPADC_CHSELR_CHSEL2ÁÚ PADC_CHSELR_CHSEL1_Pos)Ú PADC_CHSELR_CHSEL1_Msk0ÚPADC_CHSELR_CHSEL1ÂÚ PADC_CHSELR_CHSEL0_Pos*Ú PADC_CHSELR_CHSEL0_Msk1ÚPADC_CHSELR_CHSEL0ÃÚPADC_DR_DATA_PosæÚPADC_DR_DATA_MskíÚP ADC_DR_DATAÚ PADC_CALFACT_CALFACT_PosªÚ PADC_CALFACT_CALFACT_Msk±Ú PADC_CALFACT_CALFACTCÚPADC_CCR_LFMEN_PosHÚPADC_CCR_LFMEN_MskOÚPADC_CCR_LFMENáÚPADC_CCR_TSEN_PosÚPADC_CCR_TSEN_MskÚP ADC_CCR_TSENÚPADC_CCR_VREFEN_PosòÚPADC_CCR_VREFEN_MskùÚPADC_CCR_VREFENÚPADC_CCR_PRESC_Pos=ÚPADC_CCR_PRESC_MskDÚPADC_CCR_PRESCÖÚPADC_CCR_PRESC_0CÚPADC_CCR_PRESC_1BÚPADC_CCR_PRESC_2AÚPADC_CCR_PRESC_3@Ú PCOMP_CSR_COMP1EN_PosJÚ PCOMP_CSR_COMP1EN_MskQÚPCOMP_CSR_COMP1ENãÚ!PCOMP_CSR_COMP1INNSEL_Pos Ú!PCOMP_CSR_COMP1INNSEL_MskÚ PCOMP_CSR_COMP1INNSEL¥Ú PCOMP_CSR_COMP1INNSEL_0Ú PCOMP_CSR_COMP1INNSEL_1Ú PCOMP_CSR_COMP1WM_Pos9Ú PCOMP_CSR_COMP1WM_Msk@ÚPCOMP_CSR_COMP1WMÒÚ$P COMP_CSR_COMP1LPTIM1IN1_PosPÚ$P COMP_CSR_COMP1LPTIM1IN1_MskWÚ PCOMP_CSR_COMP1LPTIM1IN1éÚ#PCOMP_CSR_COMP1POLARITY_Pos]Ú#PCOMP_CSR_COMP1POLARITY_MskdÚ PCOMP_CSR_COMP1POLARITYöÚ PCOMP_CSR_COMP1VALUE_PosZÚ PCOMP_CSR_COMP1VALUE_MskaÚ PCOMP_CSR_COMP1VALUEóÚ PCOMP_CSR_COMP1LOCK_Pos°Ú PCOMP_CSR_COMP1LOCK_Msk·ÚPCOMP_CSR_COMP1LOCKIÚ PCOMP_CSR_COMP2EN_PosIÚ PCOMP_CSR_COMP2EN_MskPÚPCOMP_CSR_COMP2ENâÚ PCOMP_CSR_COMP2SPEED_PoseÚ PCOMP_CSR_COMP2SPEED_MsklÚ PCOMP_CSR_COMP2SPEEDþÚ!PCOMP_CSR_COMP2INNSEL_Pos Ú!PCOMP_CSR_COMP2INNSEL_MskÚ PCOMP_CSR_COMP2INNSEL¤Ú PCOMP_CSR_COMP2INNSEL_0Ú PCOMP_CSR_COMP2INNSEL_1Ú PCOMP_CSR_COMP2INNSEL_2Ú!PCOMP_CSR_COMP2INPSEL_Pos Ú!PCOMP_CSR_COMP2INPSEL_MskÚ PCOMP_CSR_COMP2INPSEL¢Ú PCOMP_CSR_COMP2INPSEL_0Ú PCOMP_CSR_COMP2INPSEL_1Ú PCOMP_CSR_COMP2INPSEL_2 Ú$P COMP_CSR_COMP2LPTIM1IN2_PosNÚ$P COMP_CSR_COMP2LPTIM1IN2_MskUÚ PCOMP_CSR_COMP2LPTIM1IN2çÚ$P COMP_CSR_COMP2LPTIM1IN1_PosOÚ$P COMP_CSR_COMP2LPTIM1IN1_MskVÚ PCOMP_CSR_COMP2LPTIM1IN1èÚ#PCOMP_CSR_COMP2POLARITY_Pos\Ú#PCOMP_CSR_COMP2POLARITY_MskcÚ PCOMP_CSR_COMP2POLARITYõÚ PCOMP_CSR_COMP2VALUE_PosYÚ PCOMP_CSR_COMP2VALUE_Msk`Ú PCOMP_CSR_COMP2VALUEòÚ PCOMP_CSR_COMP2LOCK_Pos¯Ú PCOMP_CSR_COMP2LOCK_Msk¶ÚPCOMP_CSR_COMP2LOCKHÚ PCOMP_CSR_COMPxEN_PosÚ PCOMP_CSR_COMPxEN_Msk
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ÚPCOMP_CSR_COMPxENÚ#PCOMP_CSR_COMPxPOLARITY_PosÚ#PCOMP_CSR_COMPxPOLARITY_Msk Ú PCOMP_CSR_COMPxPOLARITY¯Ú#PCOMP_CSR_COMPxOUTVALUE_PosÚ#PCOMP_CSR_COMPxOUTVALUE_Msk Ú PCOMP_CSR_COMPxOUTVALUE®Ú PCOMP_CSR_COMPxLOCK_PosiÚ PCOMP_CSR_COMPxLOCK_MskpÚPCOMP_CSR_COMPxLOCKÚPCOMP_CSR_WINMODEÃÚPCRC_DR_DR_Pos^ÚPCRC_DR_DR_MskeÚP
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CRC_DR_DR÷ÚP CRC_IDR_IDRaÚPCRC_CR_RESET_PoslÚPCRC_CR_RESET_MsksÚP CRC_CR_RESETÚ PCRC_CR_POLYSIZE_PosjÚ PCRC_CR_POLYSIZE_MskqÚPCRC_CR_POLYSIZEÚPCRC_CR_POLYSIZE_0pÚPCRC_CR_POLYSIZE_1oÚPCRC_CR_REV_IN_Pos
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ÚPCRC_CR_REV_IN_MskÚPCRC_CR_REV_IN£ÚPCRC_CR_REV_IN_0ÚPCRC_CR_REV_IN_1ÚPCRC_CR_REV_OUT_Pos§ÚPCRC_CR_REV_OUT_Msk®ÚPCRC_CR_REV_OUT@ÚPCRC_INIT_INIT_PosÚPCRC_INIT_INIT_Msk!ÚPCRC_INIT_INIT³ÚPCRC_POL_POL_Pos°ÚPCRC_POL_POL_Msk·ÚP CRC_POL_POLIÚ!PDBGMCU_IDCODE_DEV_ID_Pos'Ú!PDBGMCU_IDCODE_DEV_ID_Msk.Ú PDBGMCU_IDCODE_DEV_IDÀÚ!PDBGMCU_IDCODE_REV_ID_PosÚ!PDBGMCU_IDCODE_REV_ID_Msk Ú PDBGMCU_IDCODE_REV_ID²Ú PDBGMCU_IDCODE_REV_ID_0 Ú PDBGMCU_IDCODE_REV_ID_1 Ú PDBGMCU_IDCODE_REV_ID_2 Ú PDBGMCU_IDCODE_REV_ID_3 Ú PDBGMCU_IDCODE_REV_ID_4Ú PDBGMCU_IDCODE_REV_ID_5Ú PDBGMCU_IDCODE_REV_ID_6Ú PDBGMCU_IDCODE_REV_ID_7Ú PDBGMCU_IDCODE_REV_ID_8Ú PDBGMCU_IDCODE_REV_ID_9Ú PDBGMCU_IDCODE_REV_ID_10ìÚ PDBGMCU_IDCODE_REV_ID_11ëÚ PDBGMCU_IDCODE_REV_ID_12êÚ PDBGMCU_IDCODE_REV_ID_13éÚ PDBGMCU_IDCODE_REV_ID_14èÚ PDBGMCU_IDCODE_REV_ID_15çÚPDBGMCU_CR_DBG_PosFÚPDBGMCU_CR_DBG_MskMÚPDBGMCU_CR_DBGßÚ PDBGMCU_CR_DBG_SLEEP_PosbÚ PDBGMCU_CR_DBG_SLEEP_MskiÚ PDBGMCU_CR_DBG_SLEEPûÚ PDBGMCU_CR_DBG_STOP_PosÚ PDBGMCU_CR_DBG_STOP_MskÚPDBGMCU_CR_DBG_STOP0Ú"PDBGMCU_CR_DBG_STANDBY_PosÂÚ"PDBGMCU_CR_DBG_STANDBY_MskÉÚ PDBGMCU_CR_DBG_STANDBY[Ú)P!DBGMCU_APB1_FZ_DBG_TIM2_STOP_PosÚ)P!DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk¡Ú%P DBGMCU_APB1_FZ_DBG_TIM2_STOP3Ú)P!DBGMCU_APB1_FZ_DBG_TIM3_STOP_PosÚ)P!DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk Ú%P DBGMCU_APB1_FZ_DBG_TIM3_STOP2Ú)P!DBGMCU_APB1_FZ_DBG_TIM6_STOP_PosÚ)P!DBGMCU_APB1_FZ_DBG_TIM6_STOP_MskÚ%P DBGMCU_APB1_FZ_DBG_TIM6_STOP/Ú)P!DBGMCU_APB1_FZ_DBG_TIM7_STOP_PosÚ)P!DBGMCU_APB1_FZ_DBG_TIM7_STOP_MskÚ%P DBGMCU_APB1_FZ_DBG_TIM7_STOP.Ú(P DBGMCU_APB1_FZ_DBG_RTC_STOP_PosÏÚ(P DBGMCU_APB1_FZ_DBG_RTC_STOP_MskÖÚ$P DBGMCU_APB1_FZ_DBG_RTC_STOPhÚ)P!DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos}Ú)P!DBGMCU_APB1_FZ_DBG_WWDG_STOP_MskÚ%P DBGMCU_APB1_FZ_DBG_WWDG_STOPÚ)P!DBGMCU_APB1_FZ_DBG_IWDG_STOP_PosÚ)P!DBGMCU_APB1_FZ_DBG_IWDG_STOP_MskÚ%P DBGMCU_APB1_FZ_DBG_IWDG_STOP$Ú)P!DBGMCU_APB1_FZ_DBG_I2C1_STOP_PosÇÚ)P!DBGMCU_APB1_FZ_DBG_I2C1_STOP_MskÎÚ%P DBGMCU_APB1_FZ_DBG_I2C1_STOP`Ú)P!DBGMCU_APB1_FZ_DBG_I2C2_STOP_PosÆÚ)P!DBGMCU_APB1_FZ_DBG_I2C2_STOP_MskÍÚ%P DBGMCU_APB1_FZ_DBG_I2C2_STOP_Ú)P!DBGMCU_APB1_FZ_DBG_I2C3_STOP_PosÅÚ)P!DBGMCU_APB1_FZ_DBG_I2C3_STOP_MskÌÚ%P DBGMCU_APB1_FZ_DBG_I2C3_STOP^Ú,P$DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_PosÚ,P$DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_MskÚ(P DBGMCU_APB1_FZ_DBG_LPTIMER_STOP,Ú*P"DBGMCU_APB2_FZ_DBG_TIM22_STOP_PoseÚ*P"DBGMCU_APB2_FZ_DBG_TIM22_STOP_MsklÚ&P DBGMCU_APB2_FZ_DBG_TIM22_STOPþÚ*P"DBGMCU_APB2_FZ_DBG_TIM21_STOP_PosfÚ*P"DBGMCU_APB2_FZ_DBG_TIM21_STOP_MskmÚ&P DBGMCU_APB2_FZ_DBG_TIM21_STOPÿÚPDMA_ISR_GIF1_PosÚPDMA_ISR_GIF1_MskÚP DMA_ISR_GIF1.ÚPDMA_ISR_TCIF1_PosCÚPDMA_ISR_TCIF1_MskJÚPDMA_ISR_TCIF1ÜÚPDMA_ISR_HTIF1_Pos>ÚPDMA_ISR_HTIF1_MskEÚPDMA_ISR_HTIF1×ÚPDMA_ISR_TEIF1_PosAÚPDMA_ISR_TEIF1_MskHÚPDMA_ISR_TEIF1ÚÚPDMA_ISR_GIF2_PosÚPDMA_ISR_GIF2_MskÚP DMA_ISR_GIF2-ÚPDMA_ISR_TCIF2_PosBÚPDMA_ISR_TCIF2_MskIÚPDMA_ISR_TCIF2ÛÚPDMA_ISR_HTIF2_Pos=ÚPDMA_ISR_HTIF2_MskDÚPDMA_ISR_HTIF2ÖÚPDMA_ISR_TEIF2_Pos@ÚPDMA_ISR_TEIF2_MskGÚPDMA_ISR_TEIF2ÙÚPDMA_ISR_GIF3_PosÚPDMA_ISR_GIF3_MskÚP DMA_ISR_GIF3,ÚPDMA_ISR_TCIF3_PosAÚPDMA_ISR_TCIF3_MskHÚPDMA_ISR_TCIF3ÚÚPDMA_ISR_HTIF3_Pos<ÚPDMA_ISR_HTIF3_MskCÚPDMA_ISR_HTIF3ÕÚPDMA_ISR_TEIF3_Pos?ÚPDMA_ISR_TEIF3_MskFÚPDMA_ISR_TEIF3ØÚPDMA_ISR_GIF4_PosÚPDMA_ISR_GIF4_MskÚP DMA_ISR_GIF4+ÚPDMA_ISR_TCIF4_Pos@ÚPDMA_ISR_TCIF4_MskGÚPDMA_ISR_TCIF4ÙÚPDMA_ISR_HTIF4_Pos;ÚPDMA_ISR_HTIF4_MskBÚPDMA_ISR_HTIF4ÔÚPDMA_ISR_TEIF4_Pos>ÚPDMA_ISR_TEIF4_MskEÚPDMA_ISR_TEIF4×ÚPDMA_ISR_GIF5_PosÚPDMA_ISR_GIF5_MskÚP DMA_ISR_GIF5*ÚPDMA_ISR_TCIF5_Pos?ÚPDMA_ISR_TCIF5_MskFÚPDMA_ISR_TCIF5ØÚPDMA_ISR_HTIF5_Pos:ÚPDMA_ISR_HTIF5_MskAÚPDMA_ISR_HTIF5ÓÚPDMA_ISR_TEIF5_Pos=ÚPDMA_ISR_TEIF5_MskDÚPDMA_ISR_TEIF5ÖÚPDMA_ISR_GIF6_PosÚPDMA_ISR_GIF6_MskÚP DMA_ISR_GIF6)ÚPDMA_ISR_TCIF6_Pos>ÚPDMA_ISR_TCIF6_MskEÚPDMA_ISR_TCIF6×ÚPDMA_ISR_HTIF6_Pos9ÚPDMA_ISR_HTIF6_Msk@ÚPDMA_ISR_HTIF6ÒÚPDMA_ISR_TEIF6_Pos<ÚPDMA_ISR_TEIF6_MskCÚPDMA_ISR_TEIF6ÕÚPDMA_ISR_GIF7_PosÚPDMA_ISR_GIF7_MskÚP DMA_ISR_GIF7(ÚPDMA_ISR_TCIF7_Pos=ÚPDMA_ISR_TCIF7_MskDÚPDMA_ISR_TCIF7ÖÚPDMA_ISR_HTIF7_Pos8ÚPDMA_ISR_HTIF7_Msk?ÚPDMA_ISR_HTIF7ÑÚPDMA_ISR_TEIF7_Pos;ÚPDMA_ISR_TEIF7_MskBÚPDMA_ISR_TEIF7ÔÚPDMA_IFCR_CGIF1_PosÚPDMA_IFCR_CGIF1_Msk ÚPDMA_IFCR_CGIF1±Ú PDMA_IFCR_CTCIF1_PosÆÚ PDMA_IFCR_CTCIF1_MskÍÚPDMA_IFCR_CTCIF1_Ú PDMA_IFCR_CHTIF1_PosÁÚ PDMA_IFCR_CHTIF1_MskÈÚPDMA_IFCR_CHTIF1ZÚ PDMA_IFCR_CTEIF1_PosÄÚ PDMA_IFCR_CTEIF1_MskËÚPDMA_IFCR_CTEIF1]ÚPDMA_IFCR_CGIF2_PosÚPDMA_IFCR_CGIF2_Msk ÚPDMA_IFCR_CGIF2°Ú PDMA_IFCR_CTCIF2_PosÅÚ PDMA_IFCR_CTCIF2_MskÌÚPDMA_IFCR_CTCIF2^Ú PDMA_IFCR_CHTIF2_PosÀÚ PDMA_IFCR_CHTIF2_MskÇÚPDMA_IFCR_CHTIF2YÚ PDMA_IFCR_CTEIF2_PosÃÚ PDMA_IFCR_CTEIF2_MskÊÚPDMA_IFCR_CTEIF2\ÚPDMA_IFCR_CGIF3_PosÚPDMA_IFCR_CGIF3_Msk ÚPDMA_IFCR_CGIF3¯Ú PDMA_IFCR_CTCIF3_PosÄÚ PDMA_IFCR_CTCIF3_MskËÚPDMA_IFCR_CTCIF3]Ú PDMA_IFCR_CHTIF3_Pos¿Ú PDMA_IFCR_CHTIF3_MskÆÚPDMA_IFCR_CHTIF3XÚ PDMA_IFCR_CTEIF3_PosÂÚ PDMA_IFCR_CTEIF3_MskÉÚPDMA_IFCR_CTEIF3[ÚPDMA_IFCR_CGIF4_PosÚPDMA_IFCR_CGIF4_Msk ÚPDMA_IFCR_CGIF4®Ú PDMA_IFCR_CTCIF4_PosÃÚ PDMA_IFCR_CTCIF4_MskÊÚPDMA_IFCR_CTCIF4\Ú PDMA_IFCR_CHTIF4_Pos¾Ú PDMA_IFCR_CHTIF4_MskÅÚPDMA_IFCR_CHTIF4WÚ PDMA_IFCR_CTEIF4_PosÁÚ PDMA_IFCR_CTEIF4_MskÈÚPDMA_IFCR_CTEIF4ZÚPDMA_IFCR_CGIF5_PosÚPDMA_IFCR_CGIF5_MskÚPDMA_IFCR_CGIF5Ú PDMA_IFCR_CTCIF5_PosÂÚ PDMA_IFCR_CTCIF5_MskÉÚPDMA_IFCR_CTCIF5[Ú PDMA_IFCR_CHTIF5_Pos½Ú PDMA_IFCR_CHTIF5_MskÄÚPDMA_IFCR_CHTIF5VÚ PDMA_IFCR_CTEIF5_PosÀÚ PDMA_IFCR_CTEIF5_MskÇÚPDMA_IFCR_CTEIF5YÚPDMA_IFCR_CGIF6_PosÚPDMA_IFCR_CGIF6_MskÚPDMA_IFCR_CGIF6¬Ú PDMA_IFCR_CTCIF6_PosÁÚ PDMA_IFCR_CTCIF6_MskÈÚPDMA_IFCR_CTCIF6ZÚ PDMA_IFCR_CHTIF6_Pos¼Ú PDMA_IFCR_CHTIF6_MskÃÚPDMA_IFCR_CHTIF6UÚ PDMA_IFCR_CTEIF6_Pos¿Ú PDMA_IFCR_CTEIF6_MskÆÚPDMA_IFCR_CTEIF6XÚPDMA_IFCR_CGIF7_PosÚPDMA_IFCR_CGIF7_MskÚPDMA_IFCR_CGIF7«Ú PDMA_IFCR_CTCIF7_PosÀÚ PDMA_IFCR_CTCIF7_MskÇÚPDMA_IFCR_CTCIF7YÚ PDMA_IFCR_CHTIF7_Pos»Ú PDMA_IFCR_CHTIF7_MskÂÚPDMA_IFCR_CHTIF7TÚ PDMA_IFCR_CTEIF7_Pos¾Ú PDMA_IFCR_CTEIF7_MskÅÚPDMA_IFCR_CTEIF7WÚPDMA_CCR_EN_Pos#ÚPDMA_CCR_EN_Msk*ÚP DMA_CCR_EN¼ÚPDMA_CCR_TCIE_PosÚPDMA_CCR_TCIE_MskÚP DMA_CCR_TCIE&ÚPDMA_CCR_HTIE_PosÚPDMA_CCR_HTIE_MskÚP DMA_CCR_HTIE!ÚPDMA_CCR_TEIE_PosÚPDMA_CCR_TEIE_MskÚP DMA_CCR_TEIE$ÚPDMA_CCR_DIR_PosÕÚPDMA_CCR_DIR_MskÜÚP DMA_CCR_DIRnÚPDMA_CCR_CIRC_PosÚPDMA_CCR_CIRC_MskÚP DMA_CCR_CIRC*ÚPDMA_CCR_PINC_PosÚPDMA_CCR_PINC_MskÚP DMA_CCR_PINC!ÚPDMA_CCR_MINC_PosÚPDMA_CCR_MINC_MskÚP DMA_CCR_MINC$ÚPDMA_CCR_PSIZE_Pos%ÚPDMA_CCR_PSIZE_Msk,ÚPDMA_CCR_PSIZE¾ÚPDMA_CCR_PSIZE_0+ÚPDMA_CCR_PSIZE_1*ÚPDMA_CCR_MSIZE_Pos(ÚPDMA_CCR_MSIZE_Msk/ÚPDMA_CCR_MSIZEÁÚPDMA_CCR_MSIZE_0.ÚPDMA_CCR_MSIZE_1-ÚPDMA_CCR_PL_PosÚPDMA_CCR_PL_Msk!ÚP DMA_CCR_PL³ÚP DMA_CCR_PL_0 ÚP DMA_CCR_PL_1 Ú PDMA_CCR_MEM2MEM_Pos¼Ú PDMA_CCR_MEM2MEM_MskÃÚPDMA_CCR_MEM2MEMUÚPDMA_CNDTR_NDT_Pos'ÚPDMA_CNDTR_NDT_Msk.ÚPDMA_CNDTR_NDTÀÚPDMA_CPAR_PA_PosÕÚPDMA_CPAR_PA_MskÜÚP DMA_CPAR_PAnÚPDMA_CMAR_MA_PosÛÚPDMA_CMAR_MA_MskâÚP DMA_CMAR_MAtÚPDMA_CSELR_C1S_PosHÚPDMA_CSELR_C1S_MskOÚPDMA_CSELR_C1SáÚPDMA_CSELR_C2S_PosGÚPDMA_CSELR_C2S_MskNÚPDMA_CSELR_C2SàÚPDMA_CSELR_C3S_PosFÚPDMA_CSELR_C3S_MskMÚPDMA_CSELR_C3SßÚPDMA_CSELR_C4S_PosEÚPDMA_CSELR_C4S_MskLÚPDMA_CSELR_C4SÞÚPDMA_CSELR_C5S_PosDÚPDMA_CSELR_C5S_MskKÚPDMA_CSELR_C5SÝÚPDMA_CSELR_C6S_PosCÚPDMA_CSELR_C6S_MskJÚPDMA_CSELR_C6SÜÚPDMA_CSELR_C7S_PosBÚPDMA_CSELR_C7S_MskIÚPDMA_CSELR_C7SÛÚPEXTI_IMR_IM0_PostÚPEXTI_IMR_IM0_Msk{ÚP EXTI_IMR_IM0 ÚPEXTI_IMR_IM1_PossÚPEXTI_IMR_IM1_MskzÚP EXTI_IMR_IM1 ÚPEXTI_IMR_IM2_PosrÚPEXTI_IMR_IM2_MskyÚP EXTI_IMR_IM2 ÚPEXTI_IMR_IM3_PosqÚPEXTI_IMR_IM3_MskxÚP EXTI_IMR_IM3
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PGPIO_PUPDR_PUPD1_Pos0Ú PGPIO_PUPDR_PUPD1_Msk7ÚPGPIO_PUPDR_PUPD1ÉÚPGPIO_PUPDR_PUPD1_06ÚPGPIO_PUPDR_PUPD1_15Ú PGPIO_PUPDR_PUPD2_Pos/Ú PGPIO_PUPDR_PUPD2_Msk6ÚPGPIO_PUPDR_PUPD2ÈÚPGPIO_PUPDR_PUPD2_05ÚPGPIO_PUPDR_PUPD2_14Ú PGPIO_PUPDR_PUPD3_Pos.Ú PGPIO_PUPDR_PUPD3_Msk5ÚPGPIO_PUPDR_PUPD3ÇÚPGPIO_PUPDR_PUPD3_04ÚPGPIO_PUPDR_PUPD3_13Ú PGPIO_PUPDR_PUPD4_Pos-Ú PGPIO_PUPDR_PUPD4_Msk4ÚPGPIO_PUPDR_PUPD4ÆÚPGPIO_PUPDR_PUPD4_03ÚPGPIO_PUPDR_PUPD4_12Ú PGPIO_PUPDR_PUPD5_Pos,Ú PGPIO_PUPDR_PUPD5_Msk3ÚPGPIO_PUPDR_PUPD5ÅÚPGPIO_PUPDR_PUPD5_02ÚPGPIO_PUPDR_PUPD5_11Ú PGPIO_PUPDR_PUPD6_Pos+Ú PGPIO_PUPDR_PUPD6_Msk2ÚPGPIO_PUPDR_PUPD6ÄÚPGPIO_PUPDR_PUPD6_01ÚPGPIO_PUPDR_PUPD6_10Ú PGPIO_PUPDR_PUPD7_Pos*Ú PGPIO_PUPDR_PUPD7_Msk1ÚPGPIO_PUPDR_PUPD7ÃÚPGPIO_PUPDR_PUPD7_00ÚPGPIO_PUPDR_PUPD7_1/Ú PGPIO_PUPDR_PUPD8_Pos)Ú PGPIO_PUPDR_PUPD8_Msk0ÚPGPIO_PUPDR_PUPD8ÂÚPGPIO_PUPDR_PUPD8_0/ÚPGPIO_PUPDR_PUPD8_1.Ú PGPIO_PUPDR_PUPD9_Pos(Ú PGPIO_PUPDR_PUPD9_Msk/ÚPGPIO_PUPDR_PUPD9ÁÚPGPIO_PUPDR_PUPD9_0.ÚPGPIO_PUPDR_PUPD9_1-Ú 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Ú PRCC_CFGR_PPRE2_DIV16ÙÚ PRCC_CFGR_STOPWUCK_PosØÚ PRCC_CFGR_STOPWUCK_MskßÚPRCC_CFGR_STOPWUCKqÚ PRCC_CFGR_PLLSRC_PosÚ PRCC_CFGR_PLLSRC_MskÚPRCC_CFGR_PLLSRC%Ú PRCC_CFGR_PLLSRC_HSIÚÚ PRCC_CFGR_PLLSRC_HSEÞÚ PRCC_CFGR_PLLMUL_PosÚ PRCC_CFGR_PLLMUL_MskÚPRCC_CFGR_PLLMUL ÚPRCC_CFGR_PLLMUL_0ÚPRCC_CFGR_PLLMUL_1ÚPRCC_CFGR_PLLMUL_2ÚPRCC_CFGR_PLLMUL_3ÚPRCC_CFGR_PLLMUL3êÚPRCC_CFGR_PLLMUL4éÚPRCC_CFGR_PLLMUL6çÚPRCC_CFGR_PLLMUL8åÚPRCC_CFGR_PLLMUL12¸ÚPRCC_CFGR_PLLMUL16´ÚPRCC_CFGR_PLLMUL24µÚPRCC_CFGR_PLLMUL32¶ÚPRCC_CFGR_PLLMUL48¯Ú PRCC_CFGR_PLLDIV_PosÚ PRCC_CFGR_PLLDIV_MskÚPRCC_CFGR_PLLDIV*ÚPRCC_CFGR_PLLDIV_0ÚPRCC_CFGR_PLLDIV_1Ú PRCC_CFGR_PLLDIV2_Pos]Ú PRCC_CFGR_PLLDIV2_MskdÚPRCC_CFGR_PLLDIV2öÚ PRCC_CFGR_PLLDIV3_Pos\Ú PRCC_CFGR_PLLDIV3_MskcÚPRCC_CFGR_PLLDIV3õÚ PRCC_CFGR_PLLDIV4_Pos[Ú PRCC_CFGR_PLLDIV4_MskbÚPRCC_CFGR_PLLDIV4ôÚ PRCC_CFGR_MCOSEL_PosÚ PRCC_CFGR_MCOSEL_Msk ÚPRCC_CFGR_MCOSEL2ÚPRCC_CFGR_MCOSEL_0ÚPRCC_CFGR_MCOSEL_1ÚPRCC_CFGR_MCOSEL_2ÚPRCC_CFGR_MCOSEL_3Ú PRCC_CFGR_MCOSEL_NOCLOCKºÚ#PRCC_CFGR_MCOSEL_SYSCLK_PosSÚ#PRCC_CFGR_MCOSEL_SYSCLK_MskZÚ PRCC_CFGR_MCOSEL_SYSCLKìÚ PRCC_CFGR_MCOSEL_HSI_PosNÚ PRCC_CFGR_MCOSEL_HSI_MskUÚ PRCC_CFGR_MCOSEL_HSIçÚ PRCC_CFGR_MCOSEL_MSI_PosIÚ PRCC_CFGR_MCOSEL_MSI_MskPÚ PRCC_CFGR_MCOSEL_MSIâÚ PRCC_CFGR_MCOSEL_HSE_PosRÚ PRCC_CFGR_MCOSEL_HSE_MskYÚ PRCC_CFGR_MCOSEL_HSEëÚ PRCC_CFGR_MCOSEL_PLL_PosJÚ PRCC_CFGR_MCOSEL_PLL_MskQÚ PRCC_CFGR_MCOSEL_PLLãÚ PRCC_CFGR_MCOSEL_LSI_PosJÚ PRCC_CFGR_MCOSEL_LSI_MskQÚ PRCC_CFGR_MCOSEL_LSIãÚ PRCC_CFGR_MCOSEL_LSE_PosNÚ PRCC_CFGR_MCOSEL_LSE_MskUÚ PRCC_CFGR_MCOSEL_LSEçÚ PRCC_CFGR_MCOPRE_PosÚ PRCC_CFGR_MCOPRE_MskÚPRCC_CFGR_MCOPRE/ÚPRCC_CFGR_MCOPRE_0ÚPRCC_CFGR_MCOPRE_1ÚPRCC_CFGR_MCOPRE_2Ú PRCC_CFGR_MCOPRE_DIV1²Ú PRCC_CFGR_MCOPRE_DIV2±Ú PRCC_CFGR_MCOPRE_DIV4¯Ú PRCC_CFGR_MCOPRE_DIV8«Ú PRCC_CFGR_MCOPRE_DIV16zÚ PRCC_CFGR_MCO_NOCLOCK¤Ú PRCC_CFGR_MCO_SYSCLKÖÚPRCC_CFGR_MCO_HSIÑÚPRCC_CFGR_MCO_MSIÌÚPRCC_CFGR_MCO_HSEÕÚPRCC_CFGR_MCO_PLLÍÚPRCC_CFGR_MCO_LSIÍÚPRCC_CFGR_MCO_LSEÑÚ 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PRCC_CIFR_MSIRDYF_Pos:Ú PRCC_CIFR_MSIRDYF_MskAÚPRCC_CIFR_MSIRDYFÓÚ PRCC_CIFR_CSSLSEF_PosEÚ PRCC_CIFR_CSSLSEF_MskLÚPRCC_CIFR_CSSLSEFÞÚ PRCC_CIFR_CSSHSEF_PosIÚ PRCC_CIFR_CSSHSEF_MskPÚPRCC_CIFR_CSSHSEFâÚPRCC_CIFR_LSECSSFÞÚPRCC_CIFR_CSSFÈÚ PRCC_CICR_LSIRDYC_PosAÚ PRCC_CICR_LSIRDYC_MskHÚPRCC_CICR_LSIRDYCÚÚ PRCC_CICR_LSERDYC_PosEÚ PRCC_CICR_LSERDYC_MskLÚPRCC_CICR_LSERDYCÞÚ PRCC_CICR_HSIRDYC_PosEÚ PRCC_CICR_HSIRDYC_MskLÚPRCC_CICR_HSIRDYCÞÚ PRCC_CICR_HSERDYC_PosIÚ PRCC_CICR_HSERDYC_MskPÚPRCC_CICR_HSERDYCâÚ PRCC_CICR_PLLRDYC_PosAÚ PRCC_CICR_PLLRDYC_MskHÚPRCC_CICR_PLLRDYCÚÚ PRCC_CICR_MSIRDYC_Pos@Ú PRCC_CICR_MSIRDYC_MskGÚPRCC_CICR_MSIRDYCÙÚ PRCC_CICR_CSSLSEC_PosKÚ PRCC_CICR_CSSLSEC_MskRÚPRCC_CICR_CSSLSECäÚ PRCC_CICR_CSSHSEC_PosOÚ PRCC_CICR_CSSHSEC_MskVÚPRCC_CICR_CSSHSECèÚPRCC_CICR_LSECSSCäÚPRCC_CICR_CSSCÎÚ PRCC_IOPRSTR_IOPARST_Pos!Ú PRCC_IOPRSTR_IOPARST_Msk(Ú PRCC_IOPRSTR_IOPARSTºÚ PRCC_IOPRSTR_IOPBRST_Pos Ú PRCC_IOPRSTR_IOPBRST_Msk'Ú PRCC_IOPRSTR_IOPBRST¹Ú PRCC_IOPRSTR_IOPCRST_Pos Ú PRCC_IOPRSTR_IOPCRST_Msk&Ú PRCC_IOPRSTR_IOPCRST¸Ú PRCC_IOPRSTR_IOPDRST_Pos Ú PRCC_IOPRSTR_IOPDRST_Msk%Ú PRCC_IOPRSTR_IOPDRST·Ú PRCC_IOPRSTR_IOPERST_Pos Ú PRCC_IOPRSTR_IOPERST_Msk$Ú PRCC_IOPRSTR_IOPERST¶Ú PRCC_IOPRSTR_IOPHRST_PosÚ PRCC_IOPRSTR_IOPHRST_Msk!Ú PRCC_IOPRSTR_IOPHRST³Ú PRCC_IOPRSTR_GPIOARSTqÚ PRCC_IOPRSTR_GPIOBRSTpÚ PRCC_IOPRSTR_GPIOCRSToÚ PRCC_IOPRSTR_GPIODRSTnÚ PRCC_IOPRSTR_GPIOERSTmÚ PRCC_IOPRSTR_GPIOHRSTjÚ PRCC_AHBRSTR_DMARST_PosÚ PRCC_AHBRSTR_DMARST_MskÚPRCC_AHBRSTR_DMARST0Ú PRCC_AHBRSTR_MIFRST_PosÚ PRCC_AHBRSTR_MIFRST_MskÚPRCC_AHBRSTR_MIFRST&Ú PRCC_AHBRSTR_CRCRST_PosÚ PRCC_AHBRSTR_CRCRST_MskÚPRCC_AHBRSTR_CRCRST*Ú PRCC_AHBRSTR_DMA1RSTýÚ#PRCC_APB2RSTR_SYSCFGRST_PosXÚ#PRCC_APB2RSTR_SYSCFGRST_Msk_Ú PRCC_APB2RSTR_SYSCFGRSTñÚ"PRCC_APB2RSTR_TIM21RST_PosÜÚ"PRCC_APB2RSTR_TIM21RST_MskãÚ PRCC_APB2RSTR_TIM21RSTuÚ"PRCC_APB2RSTR_TIM22RST_PosÛÚ"PRCC_APB2RSTR_TIM22RST_MskâÚ PRCC_APB2RSTR_TIM22RSTtÚ PRCC_APB2RSTR_ADCRST_PoseÚ PRCC_APB2RSTR_ADCRST_MsklÚ PRCC_APB2RSTR_ADCRSTþÚ!PRCC_APB2RSTR_SPI1RST_PosÚ!PRCC_APB2RSTR_SPI1RST_MskÚ PRCC_APB2RSTR_SPI1RST§Ú#PRCC_APB2RSTR_USART1RST_PosgÚ#PRCC_APB2RSTR_USART1RST_MsknÚ PRCC_APB2RSTR_USART1RSTÚ PRCC_APB2RSTR_DBGRST_Pos`Ú PRCC_APB2RSTR_DBGRST_MskgÚ PRCC_APB2RSTR_DBGRSTùÚ PRCC_APB2RSTR_ADC1RSTËÚ PRCC_APB2RSTR_DBGMCURSTÚ!PRCC_APB1RSTR_TIM2RST_PosÚ!PRCC_APB1RSTR_TIM2RST_MskÚ PRCC_APB1RSTR_TIM2RST©Ú!PRCC_APB1RSTR_TIM3RST_PosÚ!PRCC_APB1RSTR_TIM3RST_MskÚ PRCC_APB1RSTR_TIM3RST¨Ú!PRCC_APB1RSTR_TIM6RST_Pos Ú!PRCC_APB1RSTR_TIM6RST_MskÚ PRCC_APB1RSTR_TIM6RST¥Ú!PRCC_APB1RSTR_TIM7RST_Pos Ú!PRCC_APB1RSTR_TIM7RST_MskÚ PRCC_APB1RSTR_TIM7RST¤Ú!PRCC_APB1RSTR_WWDGRST_PosóÚ!PRCC_APB1RSTR_WWDGRST_MskúÚ PRCC_APB1RSTR_WWDGRSTÚ!PRCC_APB1RSTR_SPI2RST_PosÚ!PRCC_APB1RSTR_SPI2RST_MskÚ PRCC_APB1RSTR_SPI2RST§Ú#PRCC_APB1RSTR_USART2RST_PosgÚ#PRCC_APB1RSTR_USART2RST_MsknÚ PRCC_APB1RSTR_USART2RSTÚ$P RCC_APB1RSTR_LPUART1RST_Pos Ú$P RCC_APB1RSTR_LPUART1RST_Msk$Ú PRCC_APB1RSTR_LPUART1RST¶Ú#PRCC_APB1RSTR_USART4RST_PoseÚ#PRCC_APB1RSTR_USART4RST_MsklÚ PRCC_APB1RSTR_USART4RSTþÚ#PRCC_APB1RSTR_USART5RST_PosdÚ#PRCC_APB1RSTR_USART5RST_MskkÚ PRCC_APB1RSTR_USART5RSTýÚ!PRCC_APB1RSTR_I2C1RST_Pos=Ú!PRCC_APB1RSTR_I2C1RST_MskDÚ PRCC_APB1RSTR_I2C1RSTÖÚ!PRCC_APB1RSTR_I2C2RST_Pos<Ú!PRCC_APB1RSTR_I2C2RST_MskCÚ PRCC_APB1RSTR_I2C2RSTÕÚ PRCC_APB1RSTR_PWRRST_Pos5Ú PRCC_APB1RSTR_PWRRST_Msk<Ú PRCC_APB1RSTR_PWRRSTÎÚ!PRCC_APB1RSTR_I2C3RST_Pos;Ú!PRCC_APB1RSTR_I2C3RST_MskBÚ PRCC_APB1RSTR_I2C3RSTÔÚ#PRCC_APB1RSTR_LPTIM1RST_PosqÚ#PRCC_APB1RSTR_LPTIM1RST_MskxÚ PRCC_APB1RSTR_LPTIM1RST
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Ú PRCC_IOPENR_IOPAEN_PosñÚ PRCC_IOPENR_IOPAEN_MskøÚPRCC_IOPENR_IOPAENÚ PRCC_IOPENR_IOPBEN_PosðÚ PRCC_IOPENR_IOPBEN_Msk÷ÚPRCC_IOPENR_IOPBENÚ PRCC_IOPENR_IOPCEN_PosïÚ PRCC_IOPENR_IOPCEN_MsköÚPRCC_IOPENR_IOPCENÚ PRCC_IOPENR_IOPDEN_PosîÚ PRCC_IOPENR_IOPDEN_MskõÚPRCC_IOPENR_IOPDENÚ PRCC_IOPENR_IOPEEN_PosíÚ PRCC_IOPENR_IOPEEN_MskôÚPRCC_IOPENR_IOPEENÚ PRCC_IOPENR_IOPHEN_PosêÚ PRCC_IOPENR_IOPHEN_MskñÚPRCC_IOPENR_IOPHENÚPRCC_IOPENR_GPIOAENAÚPRCC_IOPENR_GPIOBEN@ÚPRCC_IOPENR_GPIOCEN?ÚPRCC_IOPENR_GPIODEN>ÚPRCC_IOPENR_GPIOEEN=ÚPRCC_IOPENR_GPIOHEN:Ú PRCC_AHBENR_DMAEN_PosgÚ PRCC_AHBENR_DMAEN_MsknÚPRCC_AHBENR_DMAENÚ PRCC_AHBENR_MIFEN_Pos]Ú PRCC_AHBENR_MIFEN_MskdÚPRCC_AHBENR_MIFENöÚ PRCC_AHBENR_CRCEN_PosaÚ PRCC_AHBENR_CRCEN_MskhÚPRCC_AHBENR_CRCENúÚPRCC_AHBENR_DMA1ENÍÚ!PRCC_APB2ENR_SYSCFGEN_Pos(Ú!PRCC_APB2ENR_SYSCFGEN_Msk/Ú PRCC_APB2ENR_SYSCFGENÁÚ PRCC_APB2ENR_TIM21EN_Pos¬Ú PRCC_APB2ENR_TIM21EN_Msk³Ú PRCC_APB2ENR_TIM21ENEÚ PRCC_APB2ENR_TIM22EN_Pos«Ú PRCC_APB2ENR_TIM22EN_Msk²Ú PRCC_APB2ENR_TIM22ENDÚ PRCC_APB2ENR_FWEN_PosbÚ PRCC_APB2ENR_FWEN_MskiÚPRCC_APB2ENR_FWENûÚ PRCC_APB2ENR_ADCEN_Pos5Ú PRCC_APB2ENR_ADCEN_Msk<ÚPRCC_APB2ENR_ADCENÎÚ PRCC_APB2ENR_SPI1EN_PosÞÚ PRCC_APB2ENR_SPI1EN_MskåÚPRCC_APB2ENR_SPI1ENwÚ!PRCC_APB2ENR_USART1EN_Pos7Ú!PRCC_APB2ENR_USART1EN_Msk>Ú PRCC_APB2ENR_USART1ENÐÚ PRCC_APB2ENR_DBGEN_Pos0Ú PRCC_APB2ENR_DBGEN_Msk7ÚPRCC_APB2ENR_DBGENÉÚPRCC_APB2ENR_MIFIENoÚPRCC_APB2ENR_ADC1ENÚ PRCC_APB2ENR_DBGMCUENÞÚ PRCC_APB1ENR_TIM2EN_PosàÚ PRCC_APB1ENR_TIM2EN_MskçÚPRCC_APB1ENR_TIM2ENyÚ PRCC_APB1ENR_TIM3EN_PosßÚ PRCC_APB1ENR_TIM3EN_MskæÚPRCC_APB1ENR_TIM3ENxÚ PRCC_APB1ENR_TIM6EN_PosÜÚ PRCC_APB1ENR_TIM6EN_MskãÚPRCC_APB1ENR_TIM6ENuÚ PRCC_APB1ENR_TIM7EN_PosÛÚ PRCC_APB1ENR_TIM7EN_MskâÚPRCC_APB1ENR_TIM7ENtÚ PRCC_APB1ENR_WWDGEN_PosÃÚ PRCC_APB1ENR_WWDGEN_MskÊÚPRCC_APB1ENR_WWDGEN\Ú PRCC_APB1ENR_SPI2EN_PosÞÚ PRCC_APB1ENR_SPI2EN_MskåÚPRCC_APB1ENR_SPI2ENwÚ!PRCC_APB1ENR_USART2EN_Pos7Ú!PRCC_APB1ENR_USART2EN_Msk>Ú PRCC_APB1ENR_USART2ENÐÚ"PRCC_APB1ENR_LPUART1EN_PosíÚ"PRCC_APB1ENR_LPUART1EN_MskôÚ PRCC_APB1ENR_LPUART1ENÚ!PRCC_APB1ENR_USART4EN_Pos5Ú!PRCC_APB1ENR_USART4EN_Msk<Ú PRCC_APB1ENR_USART4ENÎÚ!PRCC_APB1ENR_USART5EN_Pos4Ú!PRCC_APB1ENR_USART5EN_Msk;Ú PRCC_APB1ENR_USART5ENÍÚ PRCC_APB1ENR_I2C1EN_Pos Ú PRCC_APB1ENR_I2C1EN_MskÚPRCC_APB1ENR_I2C1EN¦Ú PRCC_APB1ENR_I2C2EN_Pos Ú PRCC_APB1ENR_I2C2EN_MskÚPRCC_APB1ENR_I2C2EN¥Ú PRCC_APB1ENR_PWREN_PosÚ PRCC_APB1ENR_PWREN_Msk ÚPRCC_APB1ENR_PWRENÚ PRCC_APB1ENR_I2C3EN_Pos Ú PRCC_APB1ENR_I2C3EN_MskÚPRCC_APB1ENR_I2C3EN¤Ú!PRCC_APB1ENR_LPTIM1EN_PosAÚ!PRCC_APB1ENR_LPTIM1EN_MskHÚ PRCC_APB1ENR_LPTIM1ENÚÚ"PRCC_IOPSMENR_IOPASMEN_Pos©Ú"PRCC_IOPSMENR_IOPASMEN_Msk°Ú PRCC_IOPSMENR_IOPASMENBÚ"PRCC_IOPSMENR_IOPBSMEN_Pos¨Ú"PRCC_IOPSMENR_IOPBSMEN_Msk¯Ú PRCC_IOPSMENR_IOPBSMENAÚ"PRCC_IOPSMENR_IOPCSMEN_Pos§Ú"PRCC_IOPSMENR_IOPCSMEN_Msk®Ú PRCC_IOPSMENR_IOPCSMEN@Ú"PRCC_IOPSMENR_IOPDSMEN_Pos¦Ú"PRCC_IOPSMENR_IOPDSMEN_MskÚ PRCC_IOPSMENR_IOPDSMEN?Ú"PRCC_IOPSMENR_IOPESMEN_Pos¥Ú"PRCC_IOPSMENR_IOPESMEN_Msk¬Ú PRCC_IOPSMENR_IOPESMEN>Ú"PRCC_IOPSMENR_IOPHSMEN_Pos¢Ú"PRCC_IOPSMENR_IOPHSMEN_Msk©Ú PRCC_IOPSMENR_IOPHSMEN;Ú PRCC_IOPSMENR_GPIOASMENùÚ PRCC_IOPSMENR_GPIOBSMENøÚ PRCC_IOPSMENR_GPIOCSMEN÷Ú PRCC_IOPSMENR_GPIODSMENöÚ PRCC_IOPSMENR_GPIOESMENõÚ PRCC_IOPSMENR_GPIOHSMENòÚ!PRCC_AHBSMENR_DMASMEN_Pos Ú!PRCC_AHBSMENR_DMASMEN_Msk&Ú PRCC_AHBSMENR_DMASMEN¸Ú!PRCC_AHBSMENR_MIFSMEN_PosÚ!PRCC_AHBSMENR_MIFSMEN_Msk Ú PRCC_AHBSMENR_MIFSMEN®Ú"PRCC_AHBSMENR_SRAMSMEN_Pos¼Ú"PRCC_AHBSMENR_SRAMSMEN_MskÃÚ PRCC_AHBSMENR_SRAMSMENUÚ!PRCC_AHBSMENR_CRCSMEN_PosÚ!PRCC_AHBSMENR_CRCSMEN_Msk Ú PRCC_AHBSMENR_CRCSMEN²Ú PRCC_AHBSMENR_DMA1SMEN
Ú%P RCC_APB2SMENR_SYSCFGSMEN_PosàÚ%P RCC_APB2SMENR_SYSCFGSMEN_MskçÚ!PRCC_APB2SMENR_SYSCFGSMENyÚ$P RCC_APB2SMENR_TIM21SMEN_PosdÚ$P RCC_APB2SMENR_TIM21SMEN_MskkÚ PRCC_APB2SMENR_TIM21SMENýÚ$P RCC_APB2SMENR_TIM22SMEN_PoscÚ$P RCC_APB2SMENR_TIM22SMEN_MskjÚ PRCC_APB2SMENR_TIM22SMENüÚ"PRCC_APB2SMENR_ADCSMEN_PosíÚ"PRCC_APB2SMENR_ADCSMEN_MskôÚ PRCC_APB2SMENR_ADCSMENÚ#PRCC_APB2SMENR_SPI1SMEN_PosÚ#PRCC_APB2SMENR_SPI1SMEN_MskÚ PRCC_APB2SMENR_SPI1SMEN/Ú%P RCC_APB2SMENR_USART1SMEN_PosïÚ%P RCC_APB2SMENR_USART1SMEN_MsköÚ!PRCC_APB2SMENR_USART1SMENÚ"PRCC_APB2SMENR_DBGSMEN_PosèÚ"PRCC_APB2SMENR_DBGSMEN_MskïÚ PRCC_APB2SMENR_DBGSMENÚ PRCC_APB2SMENR_ADC1SMENSÚ!PRCC_APB2SMENR_DBGMCUSMENÚ#PRCC_APB1SMENR_TIM2SMEN_PosÚ#PRCC_APB1SMENR_TIM2SMEN_MskÚ PRCC_APB1SMENR_TIM2SMEN1Ú#PRCC_APB1SMENR_TIM3SMEN_PosÚ#PRCC_APB1SMENR_TIM3SMEN_MskÚ PRCC_APB1SMENR_TIM3SMEN0Ú#PRCC_APB1SMENR_TIM6SMEN_PosÚ#PRCC_APB1SMENR_TIM6SMEN_MskÚ PRCC_APB1SMENR_TIM6SMEN-Ú#PRCC_APB1SMENR_TIM7SMEN_PosÚ#PRCC_APB1SMENR_TIM7SMEN_MskÚ PRCC_APB1SMENR_TIM7SMEN,Ú#PRCC_APB1SMENR_WWDGSMEN_Pos{Ú#PRCC_APB1SMENR_WWDGSMEN_MskÚ PRCC_APB1SMENR_WWDGSMENÚ#PRCC_APB1SMENR_SPI2SMEN_PosÚ#PRCC_APB1SMENR_SPI2SMEN_MskÚ PRCC_APB1SMENR_SPI2SMEN/Ú%P RCC_APB1SMENR_USART2SMEN_PosïÚ%P RCC_APB1SMENR_USART2SMEN_MsköÚ!PRCC_APB1SMENR_USART2SMENÚ&P RCC_APB1SMENR_LPUART1SMEN_Pos¥Ú&P RCC_APB1SMENR_LPUART1SMEN_Msk¬Ú"PRCC_APB1SMENR_LPUART1SMEN>Ú%P RCC_APB1SMENR_USART4SMEN_PosíÚ%P RCC_APB1SMENR_USART4SMEN_MskôÚ!PRCC_APB1SMENR_USART4SMENÚ%P RCC_APB1SMENR_USART5SMEN_PosìÚ%P RCC_APB1SMENR_USART5SMEN_MskóÚ!PRCC_APB1SMENR_USART5SMEN
Ú#PRCC_APB1SMENR_I2C1SMEN_PosÅÚ#PRCC_APB1SMENR_I2C1SMEN_MskÌÚ PRCC_APB1SMENR_I2C1SMEN^Ú#PRCC_APB1SMENR_I2C2SMEN_PosÄÚ#PRCC_APB1SMENR_I2C2SMEN_MskËÚ PRCC_APB1SMENR_I2C2SMEN]Ú"PRCC_APB1SMENR_PWRSMEN_Pos½Ú"PRCC_APB1SMENR_PWRSMEN_MskÄÚ PRCC_APB1SMENR_PWRSMENVÚ#PRCC_APB1SMENR_I2C3SMEN_PosÃÚ#PRCC_APB1SMENR_I2C3SMEN_MskÊÚ PRCC_APB1SMENR_I2C3SMEN\Ú%P RCC_APB1SMENR_LPTIM1SMEN_PosùÚ%P RCC_APB1SMENR_LPTIM1SMEN_MskÚ!PRCC_APB1SMENR_LPTIM1SMENÚ PRCC_CCIPR_USART1SEL_PosaÚ PRCC_CCIPR_USART1SEL_MskhÚ PRCC_CCIPR_USART1SELúÚ PRCC_CCIPR_USART1SEL_0gÚ PRCC_CCIPR_USART1SEL_1fÚ PRCC_CCIPR_USART2SEL_Pos`Ú PRCC_CCIPR_USART2SEL_MskgÚ PRCC_CCIPR_USART2SELùÚ PRCC_CCIPR_USART2SEL_0fÚ PRCC_CCIPR_USART2SEL_1eÚ!PRCC_CCIPR_LPUART1SEL_PosÚ!PRCC_CCIPR_LPUART1SEL_Msk Ú PRCC_CCIPR_LPUART1SEL¯Ú PRCC_CCIPR_LPUART1SEL_0 Ú PRCC_CCIPR_LPUART1SEL_1Ú PRCC_CCIPR_I2C1SEL_Pos6Ú PRCC_CCIPR_I2C1SEL_Msk=ÚPRCC_CCIPR_I2C1SELÏÚ PRCC_CCIPR_I2C1SEL_0<Ú PRCC_CCIPR_I2C1SEL_1;Ú PRCC_CCIPR_I2C3SEL_Pos4Ú PRCC_CCIPR_I2C3SEL_Msk;ÚPRCC_CCIPR_I2C3SELÍÚ PRCC_CCIPR_I2C3SEL_0:Ú PRCC_CCIPR_I2C3SEL_19Ú PRCC_CCIPR_LPTIM1SEL_PosjÚ PRCC_CCIPR_LPTIM1SEL_MskqÚ PRCC_CCIPR_LPTIM1SELÚ PRCC_CCIPR_LPTIM1SEL_0pÚ PRCC_CCIPR_LPTIM1SEL_1oÚPRCC_CSR_LSION_PosÚPRCC_CSR_LSION_Msk ÚPRCC_CSR_LSION®ÚPRCC_CSR_LSIRDY_PosÁÚPRCC_CSR_LSIRDY_MskÈÚPRCC_CSR_LSIRDYZÚPRCC_CSR_LSEON_PosÚPRCC_CSR_LSEON_Msk ÚPRCC_CSR_LSEON²ÚPRCC_CSR_LSERDY_PosÅÚPRCC_CSR_LSERDY_MskÌÚPRCC_CSR_LSERDY^ÚPRCC_CSR_LSEBYP_PosÉÚPRCC_CSR_LSEBYP_MskÐÚPRCC_CSR_LSEBYPbÚPRCC_CSR_LSEDRV_PosÈÚPRCC_CSR_LSEDRV_MskÏÚPRCC_CSR_LSEDRVaÚPRCC_CSR_LSEDRV_0ÎÚPRCC_CSR_LSEDRV_1ÍÚ PRCC_CSR_LSECSSON_Pos*Ú PRCC_CSR_LSECSSON_Msk1ÚPRCC_CSR_LSECSSONÃÚ PRCC_CSR_LSECSSD_Pos
Ú PRCC_CSR_LSECSSD_MskÚPRCC_CSR_LSECSSD ÚPRCC_CSR_RTCSEL_PosËÚPRCC_CSR_RTCSEL_MskÒÚPRCC_CSR_RTCSELdÚPRCC_CSR_RTCSEL_0ÑÚPRCC_CSR_RTCSEL_1ÐÚ PRCC_CSR_RTCSEL_NOCLOCKìÚ PRCC_CSR_RTCSEL_LSE_PosÚ PRCC_CSR_RTCSEL_LSE_MskÚPRCC_CSR_RTCSEL_LSEÚ PRCC_CSR_RTCSEL_LSI_Pos|Ú PRCC_CSR_RTCSEL_LSI_MskÚPRCC_CSR_RTCSEL_LSIÚ PRCC_CSR_RTCSEL_HSE_PosÚ PRCC_CSR_RTCSEL_HSE_MskÚPRCC_CSR_RTCSEL_HSE ÚPRCC_CSR_RTCEN_Pos ÚPRCC_CSR_RTCEN_Msk%ÚPRCC_CSR_RTCEN·ÚPRCC_CSR_RTCRST_Pos¶ÚPRCC_CSR_RTCRST_Msk½ÚPRCC_CSR_RTCRSTOÚPRCC_CSR_RMVF_PosaÚPRCC_CSR_RMVF_MskhÚP RCC_CSR_RMVFúÚPRCC_CSR_FWRSTF_Pos¼ÚPRCC_CSR_FWRSTF_MskÃÚPRCC_CSR_FWRSTFUÚ PRCC_CSR_OBLRSTF_PoszÚ PRCC_CSR_OBLRSTF_MskÚPRCC_CSR_OBLRSTFÚ PRCC_CSR_PINRSTF_PospÚ PRCC_CSR_PINRSTF_MskwÚPRCC_CSR_PINRSTF Ú PRCC_CSR_PORRSTF_PosfÚ PRCC_CSR_PORRSTF_MskmÚPRCC_CSR_PORRSTFÿÚ PRCC_CSR_SFTRSTF_PosjÚ PRCC_CSR_SFTRSTF_MskqÚPRCC_CSR_SFTRSTFÚ PRCC_CSR_IWDGRSTF_Pos*Ú PRCC_CSR_IWDGRSTF_Msk1ÚPRCC_CSR_IWDGRSTFÃÚ PRCC_CSR_WWDGRSTF_Pos Ú PRCC_CSR_WWDGRSTF_Msk#ÚPRCC_CSR_WWDGRSTFµÚ PRCC_CSR_LPWRRSTF_PosÚ PRCC_CSR_LPWRRSTF_MskÚPRCC_CSR_LPWRRSTF©ÚP RCC_CSR_OBLZÚ PRTC_TAMPER1_SUPPORTÇÚ PRTC_TAMPER2_SUPPORTÆÚ PRTC_TAMPER3_SUPPORTÅÚPRTC_WAKEUP_SUPPORTöÚPRTC_BACKUP_SUPPORT ÚPRTC_TR_PM_Pos6ÚPRTC_TR_PM_Msk=ÚP
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RTC_TR_PMÏÚPRTC_TR_HT_Pos7ÚPRTC_TR_HT_Msk>ÚP
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RTC_TR_HTÐÚP RTC_TR_HT_0=ÚP RTC_TR_HT_1<ÚPRTC_TR_HU_Pos6ÚPRTC_TR_HU_Msk=ÚP
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RTC_TR_HUÏÚP RTC_TR_HU_0<ÚP RTC_TR_HU_1;ÚP RTC_TR_HU_2:ÚP RTC_TR_HU_39ÚPRTC_TR_MNT_PosâÚPRTC_TR_MNT_MskéÚP RTC_TR_MNT{ÚP RTC_TR_MNT_0èÚP RTC_TR_MNT_1çÚP RTC_TR_MNT_2æÚPRTC_TR_MNU_PosáÚPRTC_TR_MNU_MskèÚP RTC_TR_MNUzÚP RTC_TR_MNU_0çÚP RTC_TR_MNU_1æÚP RTC_TR_MNU_2åÚP RTC_TR_MNU_3äÚPRTC_TR_ST_Pos,ÚPRTC_TR_ST_Msk3ÚP
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RTC_TR_STÅÚP RTC_TR_ST_02ÚP RTC_TR_ST_11ÚP RTC_TR_ST_20ÚPRTC_TR_SU_Pos+ÚPRTC_TR_SU_Msk2ÚP
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RTC_TR_SUÄÚP RTC_TR_SU_01ÚP RTC_TR_SU_10ÚP RTC_TR_SU_2/ÚP RTC_TR_SU_3.ÚPRTC_DR_YT_Pos6ÚPRTC_DR_YT_Msk=ÚP
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RTC_DR_YTÏÚP RTC_DR_YT_0<ÚP RTC_DR_YT_1;ÚP RTC_DR_YT_2:ÚP RTC_DR_YT_39ÚPRTC_DR_YU_Pos5ÚPRTC_DR_YU_Msk<ÚP
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RTC_DR_YUÎÚP RTC_DR_YU_0;ÚP RTC_DR_YU_1:ÚP RTC_DR_YU_29ÚP RTC_DR_YU_38ÚPRTC_DR_WDU_PosñÚPRTC_DR_WDU_MskøÚP RTC_DR_WDUÚP RTC_DR_WDU_0÷ÚP RTC_DR_WDU_1öÚP RTC_DR_WDU_2õÚPRTC_DR_MT_PosBÚPRTC_DR_MT_MskIÚP
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RTC_DR_MTÛÚPRTC_DR_MU_PosAÚPRTC_DR_MU_MskHÚP
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RTC_DR_MUÚÚP RTC_DR_MU_0GÚP RTC_DR_MU_1FÚP RTC_DR_MU_2EÚP RTC_DR_MU_3DÚPRTC_DR_DT_PosKÚPRTC_DR_DT_MskRÚP
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RTC_DR_DTäÚP RTC_DR_DT_0QÚP RTC_DR_DT_1PÚPRTC_DR_DU_PosJÚPRTC_DR_DU_MskQÚP
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ÚPRTC_CAL_CALM_8Ú PRTC_TAMPCR_TAMP3MF_Pos¨Ú PRTC_TAMPCR_TAMP3MF_Msk¯ÚPRTC_TAMPCR_TAMP3MFAÚ$P RTC_TAMPCR_TAMP3NOERASE_Pos$Ú$P RTC_TAMPCR_TAMP3NOERASE_Msk+Ú PRTC_TAMPCR_TAMP3NOERASE½Ú PRTC_TAMPCR_TAMP3IE_PosÚ PRTC_TAMPCR_TAMP3IE_Msk´ÚPRTC_TAMPCR_TAMP3IEFÚ PRTC_TAMPCR_TAMP2MF_Pos©Ú PRTC_TAMPCR_TAMP2MF_Msk°ÚPRTC_TAMPCR_TAMP2MFBÚ$P RTC_TAMPCR_TAMP2NOERASE_Pos%Ú$P RTC_TAMPCR_TAMP2NOERASE_Msk,Ú PRTC_TAMPCR_TAMP2NOERASE¾Ú PRTC_TAMPCR_TAMP2IE_Pos®Ú PRTC_TAMPCR_TAMP2IE_MskµÚPRTC_TAMPCR_TAMP2IEGÚ PRTC_TAMPCR_TAMP1MF_PosªÚ PRTC_TAMPCR_TAMP1MF_Msk±ÚPRTC_TAMPCR_TAMP1MFCÚ$P RTC_TAMPCR_TAMP1NOERASE_Pos&Ú$P RTC_TAMPCR_TAMP1NOERASE_Msk-Ú PRTC_TAMPCR_TAMP1NOERASE¿Ú PRTC_TAMPCR_TAMP1IE_Pos¯Ú PRTC_TAMPCR_TAMP1IE_Msk¶ÚPRTC_TAMPCR_TAMP1IEHÚ!PRTC_TAMPCR_TAMPPUDIS_PosåÚ!PRTC_TAMPCR_TAMPPUDIS_MskìÚ PRTC_TAMPCR_TAMPPUDIS~Ú PRTC_TAMPCR_TAMPPRCH_Pos?Ú PRTC_TAMPCR_TAMPPRCH_MskFÚ PRTC_TAMPCR_TAMPPRCHØÚ PRTC_TAMPCR_TAMPPRCH_0EÚ PRTC_TAMPCR_TAMPPRCH_1DÚ PRTC_TAMPCR_TAMPFLT_PosÚ PRTC_TAMPCR_TAMPFLT_MskÚPRTC_TAMPCR_TAMPFLT!Ú PRTC_TAMPCR_TAMPFLT_0Ú PRTC_TAMPCR_TAMPFLT_1Ú PRTC_TAMPCR_TAMPFREQ_Pos>Ú PRTC_TAMPCR_TAMPFREQ_MskEÚ PRTC_TAMPCR_TAMPFREQ×Ú PRTC_TAMPCR_TAMPFREQ_0DÚ PRTC_TAMPCR_TAMPFREQ_1CÚ PRTC_TAMPCR_TAMPFREQ_2BÚ PRTC_TAMPCR_TAMPTS_PosÉÚ PRTC_TAMPCR_TAMPTS_MskÐÚPRTC_TAMPCR_TAMPTSbÚ PRTC_TAMPCR_TAMP3TRG_PosLÚ PRTC_TAMPCR_TAMP3TRG_MskSÚ PRTC_TAMPCR_TAMP3TRGåÚ PRTC_TAMPCR_TAMP3E_PosøÚ PRTC_TAMPCR_TAMP3E_MskÿÚPRTC_TAMPCR_TAMP3EÚ PRTC_TAMPCR_TAMP2TRG_PosMÚ PRTC_TAMPCR_TAMP2TRG_MskTÚ PRTC_TAMPCR_TAMP2TRGæÚ PRTC_TAMPCR_TAMP2E_PosùÚ PRTC_TAMPCR_TAMP2E_MskÚPRTC_TAMPCR_TAMP2EÚ PRTC_TAMPCR_TAMPIE_PosâÚ PRTC_TAMPCR_TAMPIE_MskéÚPRTC_TAMPCR_TAMPIE{Ú PRTC_TAMPCR_TAMP1TRG_PosNÚ PRTC_TAMPCR_TAMP1TRG_MskUÚ PRTC_TAMPCR_TAMP1TRGçÚ PRTC_TAMPCR_TAMP1E_PosúÚ PRTC_TAMPCR_TAMP1E_MskÚPRTC_TAMPCR_TAMP1EÚ PRTC_ALRMASSR_MASKSS_Pos.Ú PRTC_ALRMASSR_MASKSS_Msk5Ú PRTC_ALRMASSR_MASKSSÇÚ PRTC_ALRMASSR_MASKSS_04Ú PRTC_ALRMASSR_MASKSS_13Ú PRTC_ALRMASSR_MASKSS_22Ú PRTC_ALRMASSR_MASKSS_31Ú PRTC_ALRMASSR_SS_PosbÚ PRTC_ALRMASSR_SS_MskiÚPRTC_ALRMASSR_SSûÚ PRTC_ALRMBSSR_MASKSS_Pos-Ú PRTC_ALRMBSSR_MASKSS_Msk4Ú PRTC_ALRMBSSR_MASKSSÆÚ PRTC_ALRMBSSR_MASKSS_03Ú PRTC_ALRMBSSR_MASKSS_12Ú PRTC_ALRMBSSR_MASKSS_21Ú PRTC_ALRMBSSR_MASKSS_30Ú PRTC_ALRMBSSR_SS_PosaÚ PRTC_ALRMBSSR_SS_MskhÚPRTC_ALRMBSSR_SSúÚPRTC_OR_OUT_RMP_PosÚPRTC_OR_OUT_RMP_MskÚPRTC_OR_OUT_RMP!Ú PRTC_OR_ALARMOUTTYPE_Pos Ú PRTC_OR_ALARMOUTTYPE_Msk$Ú PRTC_OR_ALARMOUTTYPE¶ÚPRTC_OR_RTC_OUT_RMPÑÚPRTC_BKP0R_PosyÚPRTC_BKP0R_MskÚP
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RTC_BKP0RÚPRTC_BKP1R_PosxÚPRTC_BKP1R_MskÚP
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RTC_BKP1RÚPRTC_BKP2R_PoswÚPRTC_BKP2R_Msk~ÚP
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RTC_BKP2RÚPRTC_BKP3R_PosvÚPRTC_BKP3R_Msk}ÚP
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RTC_BKP3RÚPRTC_BKP4R_PosuÚPRTC_BKP4R_Msk|ÚP
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RTC_BKP4RÚPRTC_BKP_NUMBERbÚPSPI_I2S_SUPPORTøÚPSPI_CR1_CPHA_PosÚPSPI_CR1_CPHA_MskÚP SPI_CR1_CPHA'ÚPSPI_CR1_CPOL_Pos|ÚPSPI_CR1_CPOL_MskÚP SPI_CR1_CPOLÚPSPI_CR1_MSTR_PosdÚPSPI_CR1_MSTR_MskkÚP SPI_CR1_MSTRýÚPSPI_CR1_BR_PosÚPSPI_CR1_BR_Msk!ÚP SPI_CR1_BR³ÚP SPI_CR1_BR_0 ÚP SPI_CR1_BR_1 ÚP SPI_CR1_BR_2 ÚPSPI_CR1_SPE_PosÄÚPSPI_CR1_SPE_MskËÚP SPI_CR1_SPE]Ú PSPI_CR1_LSBFIRST_Pos9Ú PSPI_CR1_LSBFIRST_Msk@ÚPSPI_CR1_LSBFIRSTÒÚPSPI_CR1_SSI_Pos½ÚPSPI_CR1_SSI_MskÄÚP SPI_CR1_SSIVÚPSPI_CR1_SSM_Pos¹ÚPSPI_CR1_SSM_MskÀÚP SPI_CR1_SSMRÚPSPI_CR1_RXONLY_PosºÚPSPI_CR1_RXONLY_MskÁÚPSPI_CR1_RXONLYSÚPSPI_CR1_DFF_PosÜÚPSPI_CR1_DFF_MskãÚP SPI_CR1_DFFuÚ PSPI_CR1_CRCNEXT_PosÚ PSPI_CR1_CRCNEXT_MskÚPSPI_CR1_CRCNEXT&ÚPSPI_CR1_CRCEN_Pos=ÚPSPI_CR1_CRCEN_MskDÚPSPI_CR1_CRCENÖÚPSPI_CR1_BIDIOE_PosúÚPSPI_CR1_BIDIOE_MskÚPSPI_CR1_BIDIOEÚ PSPI_CR1_BIDIMODE_PoseÚ PSPI_CR1_BIDIMODE_MsklÚPSPI_CR1_BIDIMODEþÚ PSPI_CR2_RXDMAEN_PosÚ PSPI_CR2_RXDMAEN_MskÚPSPI_CR2_RXDMAEN-Ú PSPI_CR2_TXDMAEN_PosÚ PSPI_CR2_TXDMAEN_MskÚPSPI_CR2_TXDMAEN+ÚPSPI_CR2_SSOE_PosoÚPSPI_CR2_SSOE_MskvÚP SPI_CR2_SSOEÚPSPI_CR2_FRF_PosÍÚPSPI_CR2_FRF_MskÔÚP SPI_CR2_FRFfÚPSPI_CR2_ERRIE_Pos0ÚPSPI_CR2_ERRIE_Msk7ÚPSPI_CR2_ERRIEÉÚPSPI_CR2_RXNEIE_PosÚÚPSPI_CR2_RXNEIE_MskáÚPSPI_CR2_RXNEIEsÚPSPI_CR2_TXEIE_Pos(ÚPSPI_CR2_TXEIE_Msk/ÚPSPI_CR2_TXEIEÁÚPSPI_SR_RXNE_PosÚPSPI_SR_RXNE_MskÚP SPI_SR_RXNE)ÚPSPI_SR_TXE_PosÞÚPSPI_SR_TXE_MskåÚP SPI_SR_TXEwÚPSPI_SR_CHSIDE_PosÚPSPI_SR_CHSIDE_Msk ÚPSPI_SR_CHSIDE²ÚPSPI_SR_UDR_PosäÚPSPI_SR_UDR_MskëÚP SPI_SR_UDR}ÚPSPI_SR_CRCERR_PosÚPSPI_SR_CRCERR_MskÚPSPI_SR_CRCERR¡ÚPSPI_SR_MODF_Pos§ÚPSPI_SR_MODF_Msk®ÚP SPI_SR_MODF@ÚPSPI_SR_OVR_PosØÚPSPI_SR_OVR_MskßÚP SPI_SR_OVRqÚPSPI_SR_BSY_PosáÚPSPI_SR_BSY_MskèÚP SPI_SR_BSYzÚPSPI_SR_FRE_PosòÚPSPI_SR_FRE_MskùÚP SPI_SR_FREÚPSPI_DR_DR_PosJÚPSPI_DR_DR_MskQÚP
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SPI_DR_DRãÚ PSPI_CRCPR_CRCPOLY_PosÐÚ PSPI_CRCPR_CRCPOLY_Msk×ÚPSPI_CRCPR_CRCPOLYiÚ PSPI_RXCRCR_RXCRC_PosÚ PSPI_RXCRCR_RXCRC_MskÚPSPI_RXCRCR_RXCRC«Ú PSPI_TXCRCR_TXCRC_PosÚ PSPI_TXCRCR_TXCRC_MskÚPSPI_TXCRCR_TXCRC§Ú PSPI_I2SCFGR_CHLEN_Pos Ú PSPI_I2SCFGR_CHLEN_MskÚPSPI_I2SCFGR_CHLEN¥Ú PSPI_I2SCFGR_DATLEN_Pos¼Ú PSPI_I2SCFGR_DATLEN_MskÃÚPSPI_I2SCFGR_DATLENUÚ PSPI_I2SCFGR_DATLEN_0ÂÚ PSPI_I2SCFGR_DATLEN_1ÁÚ PSPI_I2SCFGR_CKPOL_PosýÚ PSPI_I2SCFGR_CKPOL_MskÚPSPI_I2SCFGR_CKPOLÚ PSPI_I2SCFGR_I2SSTD_Pos»Ú PSPI_I2SCFGR_I2SSTD_MskÂÚPSPI_I2SCFGR_I2SSTDTÚ PSPI_I2SCFGR_I2SSTD_0ÁÚ PSPI_I2SCFGR_I2SSTD_1ÀÚ PSPI_I2SCFGR_PCMSYNC_PosUÚ PSPI_I2SCFGR_PCMSYNC_Msk\Ú PSPI_I2SCFGR_PCMSYNCîÚ PSPI_I2SCFGR_I2SCFG_PosÖÚ PSPI_I2SCFGR_I2SCFG_MskÝÚPSPI_I2SCFGR_I2SCFGoÚ PSPI_I2SCFGR_I2SCFG_0ÜÚ PSPI_I2SCFGR_I2SCFG_1ÛÚ PSPI_I2SCFGR_I2SE_PoseÚ PSPI_I2SCFGR_I2SE_MsklÚPSPI_I2SCFGR_I2SEþÚ PSPI_I2SCFGR_I2SMOD_PosÆÚ PSPI_I2SCFGR_I2SMOD_MskÍÚPSPI_I2SCFGR_I2SMOD_Ú PSPI_I2SCFGR_ASTRTEN_PosQÚ PSPI_I2SCFGR_ASTRTEN_MskXÚ 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Ú PUSART_ISR_REACK_PossÚ PUSART_ISR_REACK_MskzÚPUSART_ISR_REACK ÚPUSART_ICR_PECF_PosÍÚPUSART_ICR_PECF_MskÔÚPUSART_ICR_PECFfÚPUSART_ICR_FECF_Pos×ÚPUSART_ICR_FECF_MskÞÚPUSART_ICR_FECFpÚPUSART_ICR_NCF_PosÚPUSART_ICR_NCF_Msk ÚPUSART_ICR_NCF¯Ú PUSART_ICR_ORECF_PoszÚ PUSART_ICR_ORECF_MskÚPUSART_ICR_ORECFÚ PUSART_ICR_IDLECF_Pos@Ú PUSART_ICR_IDLECF_MskGÚPUSART_ICR_IDLECFÙÚPUSART_ICR_TCCF_PosËÚPUSART_ICR_TCCF_MskÒÚPUSART_ICR_TCCFdÚ PUSART_ICR_LBDCF_PosÚ PUSART_ICR_LBDCF_MskÚPUSART_ICR_LBDCF'Ú PUSART_ICR_CTSCF_PosvÚ PUSART_ICR_CTSCF_Msk}ÚPUSART_ICR_CTSCFÚ PUSART_ICR_RTOCF_PoskÚ PUSART_ICR_RTOCF_MskrÚPUSART_ICR_RTOCFÚ PUSART_ICR_EOBCF_PosÚ PUSART_ICR_EOBCF_MskÚPUSART_ICR_EOBCF#ÚPUSART_ICR_CMCF_PosÒÚPUSART_ICR_CMCF_MskÙÚPUSART_ICR_CMCFkÚPUSART_ICR_WUCF_Pos¶ÚPUSART_ICR_WUCF_Msk½ÚPUSART_ICR_WUCFOÚPUSART_ICR_NECFhÚPUSART_RDR_RDR_PosûÚPUSART_RDR_RDR_MskÚPUSART_RDR_RDRÚPUSART_TDR_TDR_Pos÷ÚPUSART_TDR_TDR_MskþÚPUSART_TDR_TDRÚPWWDG_CR_T_Pos@ÚPWWDG_CR_T_MskGÚP
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ADC1_IRQnÚP SVC_IRQnÚ PRNG_LPUART1_IRQHandlerGÚ PAES_LPUART1_IRQHandlerUÚ#PAES_RNG_LPUART1_IRQHandlerÚ PTIM6_DAC_IRQHandlerUÚPRCC_CRS_IRQHandlerÚ#PDMA1_Channel4_5_IRQHandler«ÚPADC1_IRQHandler«Ú RESETpÚ SET Ú FlagStatusïÚ ITStatusÐÚ DISABLEûÚ ENABLEJÚFunctionalStateÏÚ PIS_FUNCTIONAL_STATE×Ú SUCCESSÖÚ ERRORiÚ ErrorStatus]ÚPSET_BITÚP
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CLEAR_BITÚP READ_BITaÚP
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CLEAR_REGÚP
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WRITE_REGñÚP READ_REGbÚP MODIFY_REG²ÚPATOMIC_SET_BITiÚPATOMIC_CLEAR_BITêÚPATOMIC_MODIFY_REGÚPATOMIC_SETH_BIT ÚPATOMIC_CLEARH_BIT ÚPATOMIC_MODIFYH_REG>ÚPSTM32_HAL_LEGACY
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ÚPAES_FLAG_RDERRÚPAES_FLAG_WRERRlÚPAES_CLEARFLAG_CCFÅÚ PAES_CLEARFLAG_RDERRÚ PAES_CLEARFLAG_WRERRûÚPADC_RESOLUTION12b©ÚPADC_RESOLUTION10b«ÚPADC_RESOLUTION8bÖÚPADC_RESOLUTION6bØÚ POVR_DATA_OVERWRITTENkÚPOVR_DATA_PRESERVED(ÚPEOC_SINGLE_CONV ÚP EOC_SEQ_CONVÿÚ PEOC_SINGLE_SEQ_CONVÐÚPREGULAR_GROUP³ÚPINJECTED_GROUP}Ú PREGULAR_INJECTED_GROUPüÚP
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AWD_EVENTüÚP AWD1_EVENTÉÚP AWD2_EVENTÈÚP AWD3_EVENTÇÚP
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OVR_EVENTáÚP JQOVF_EVENTNÚP ALL_CHANNELS/ÚPREGULAR_CHANNELSîÚPINJECTED_CHANNELS¸Ú PSYSCFG_FLAG_SENSOR_ADC÷Ú PSYSCFG_FLAG_VREF_ADC¢Ú%P ADC_CLOCKPRESCALER_PCLK_DIV1cÚ%P ADC_CLOCKPRESCALER_PCLK_DIV2bÚ%P ADC_CLOCKPRESCALER_PCLK_DIV4`Ú%P ADC_CLOCKPRESCALER_PCLK_DIV6^Ú%P ADC_CLOCKPRESCALER_PCLK_DIV8\Ú"PADC_EXTERNALTRIG0_T6_TRGO%Ú"PADC_EXTERNALTRIG1_T21_CC2{Ú"PADC_EXTERNALTRIG2_T2_TRGO'Ú!PADC_EXTERNALTRIG3_T2_CC4ªÚ#PADC_EXTERNALTRIG4_T22_TRGOñÚ#PADC_EXTERNALTRIG7_EXT_IT11òÚPADC_CLOCK_ASYNC=Ú#PADC_EXTERNALTRIG_EDGE_NONEÔÚ%P ADC_EXTERNALTRIG_EDGE_RISING4Ú&P ADC_EXTERNALTRIG_EDGE_FALLINGÚ,P$ADC_EXTERNALTRIG_EDGE_RISINGFALLING)Ú PADC_SAMPLETIME_2CYCLE_5ðÚ PHAL_ADC_STATE_BUSY_REGäÚ PHAL_ADC_STATE_BUSY_INJáÚ PHAL_ADC_STATE_EOC_REGRÚ PHAL_ADC_STATE_EOC_INJOÚ PHAL_ADC_STATE_ERRORàÚPHAL_ADC_STATE_BUSY)ÚPHAL_ADC_STATE_AWDÚP__HAL_CEC_GET_IT³Ú!PCOMP_WINDOWMODE_DISABLEDyÚ PCOMP_WINDOWMODE_ENABLEDÈÚ#PCOMP_EXTI_LINE_COMP1_EVENT¨Ú#PCOMP_EXTI_LINE_COMP2_EVENT§Ú#PCOMP_EXTI_LINE_COMP3_EVENT¦Ú#PCOMP_EXTI_LINE_COMP4_EVENT¥Ú#PCOMP_EXTI_LINE_COMP5_EVENT¤Ú#PCOMP_EXTI_LINE_COMP6_EVENT£Ú#PCOMP_EXTI_LINE_COMP7_EVENT¢Ú%P COMP_LPTIMCONNECTION_ENABLEDEÚ&P COMP_OUTPUT_COMP6TIM2OCREFCLRâÚ PCOMP_WINDOWMODE_ENABLEÚ#PCOMP_NONINVERTINGINPUT_IO1°Ú#PCOMP_NONINVERTINGINPUT_IO2¯Ú#PCOMP_NONINVERTINGINPUT_IO3®Ú#PCOMP_NONINVERTINGINPUT_IO4Ú#PCOMP_NONINVERTINGINPUT_IO5¬Ú#PCOMP_NONINVERTINGINPUT_IO6«Ú'P COMP_INVERTINGINPUT_1_4VREFINTzÚ'P COMP_INVERTINGINPUT_1_2VREFINT|Ú'P COMP_INVERTINGINPUT_3_4VREFINTxÚ$P COMP_INVERTINGINPUT_VREFINTDÚ%P COMP_INVERTINGINPUT_DAC1_CH1LÚ%P COMP_INVERTINGINPUT_DAC1_CH2KÚ!PCOMP_INVERTINGINPUT_DAC1oÚ!PCOMP_INVERTINGINPUT_DAC2nÚ PCOMP_INVERTINGINPUT_IO1¡Ú PCOMP_INVERTINGINPUT_IO2 Ú PCOMP_INVERTINGINPUT_IO3Ú PCOMP_INVERTINGINPUT_IO4Ú PCOMP_INVERTINGINPUT_IO5Ú PCOMP_OUTPUTLEVEL_LOW[Ú PCOMP_OUTPUTLEVEL_HIGH+ÚPCOMP_FLAG_LOCKÚ PCOMP_MODE_HIGHSPEEDÚPCOMP_MODE_LOWSPEED2Ú'P __HAL_CORTEX_SYSTICKCLK_CONFIGPÚ#PHAL_CRC_Input_Data_ReverseÚ$P HAL_CRC_Output_Data_Reverse
Ú*P"CRC_OUTPUTDATA_INVERSION_DISABLEDÚ)P!CRC_OUTPUTDATA_INVERSION_ENABLEDãÚPDAC1_CHANNEL_1ÎÚPDAC1_CHANNEL_2ÍÚPDAC2_CHANNEL_1ÍÚPDAC_WAVE_NONEÈÚPDAC_WAVE_NOISExÚPDAC_WAVE_TRIANGLEÚ PDAC_WAVEGENERATION_NONEÈÚ!PDAC_WAVEGENERATION_NOISExÚ$P DAC_WAVEGENERATION_TRIANGLEÚ!PHAL_REMAPDMA_ADC_DMA_CH2¬Ú'P HAL_REMAPDMA_USART1_TX_DMA_CH4Ú'P HAL_REMAPDMA_USART1_RX_DMA_CH5Ú#PHAL_REMAPDMA_TIM16_DMA_CH4 Ú#PHAL_REMAPDMA_TIM17_DMA_CH2 Ú%P HAL_REMAPDMA_USART3_DMA_CH32wÚ#PHAL_REMAPDMA_TIM16_DMA_CH6Ú#PHAL_REMAPDMA_TIM17_DMA_CH7Ú#PHAL_REMAPDMA_SPI2_DMA_CH67Ú%P HAL_REMAPDMA_USART2_DMA_CH67pÚ#PHAL_REMAPDMA_I2C1_DMA_CH76FÚ"PHAL_REMAPDMA_TIM1_DMA_CH6SÚ"PHAL_REMAPDMA_TIM2_DMA_CH7QÚ"PHAL_REMAPDMA_TIM3_DMA_CH6QÚPIS_HAL_REMAPDMA7Ú&P __HAL_REMAPDMA_CHANNEL_ENABLEúÚ'P __HAL_REMAPDMA_CHANNEL_DISABLE«ÚPTYPEPROGRAM_BYTE¾Ú PTYPEPROGRAM_HALFWORDÚPTYPEPROGRAM_WORD¶Ú PTYPEPROGRAM_DOUBLEWORDïÚPTYPEERASE_SECTORSuÚPTYPEERASE_PAGES,Ú PTYPEERASE_PAGEERASEÚ PTYPEERASE_MASSERASEðÚPWRPSTATE_DISABLEÞÚPWRPSTATE_ENABLE-Ú PHAL_FLASH_TIMEOUT_VALUEÚP OBEX_PCROP¦ÚPOBEX_BOOTCONFIG6ÚPPCROPSTATE_DISABLEOÚPPCROPSTATE_ENABLEÚPTYPEERASEDATA_BYTEHÚ PTYPEERASEDATA_HALFWORD ÚPTYPEERASEDATA_WORD@Ú PTYPEPROGRAMDATA_BYTEÚ!PTYPEPROGRAMDATA_HALFWORDqÚ PTYPEPROGRAMDATA_WORDÚ!PTYPEPROGRAMDATA_FASTBYTEfÚ%P TYPEPROGRAMDATA_FASTHALFWORD;Ú!PTYPEPROGRAMDATA_FASTWORD^ÚP PAGESIZEcÚ PTYPEPROGRAM_FASTBYTEÚ!PTYPEPROGRAM_FASTHALFWORD]Ú PTYPEPROGRAM_FASTWORDÚPVOLTAGE_RANGE_1?ÚPVOLTAGE_RANGE_2>ÚPVOLTAGE_RANGE_3=ÚPVOLTAGE_RANGE_4<ÚPTYPEPROGRAM_FASTÄÚ"PTYPEPROGRAM_FAST_AND_LASTíÚ PWRPAREA_BANK1_AREAA.Ú PWRPAREA_BANK1_AREAB-Ú PWRPAREA_BANK2_AREAA-Ú PWRPAREA_BANK2_AREAB,ÚPIWDG_STDBY_FREEZEyÚPIWDG_STDBY_ACTIVE~ÚPIWDG_STOP_FREEZE»ÚPIWDG_STOP_ACTIVEÀÚPFLASH_ERROR_NONEÅÚPFLASH_ERROR_RDcÚPFLASH_ERROR_PGbÚPFLASH_ERROR_PGPÚPFLASH_ERROR_WRPþÚPFLASH_ERROR_OPTV¬Ú PFLASH_ERROR_OPTVUSR¬ÚPFLASH_ERROR_PROG½ÚPFLASH_ERROR_OPZÚPFLASH_ERROR_PGA ÚPFLASH_ERROR_SIZEºÚPFLASH_ERROR_SIZÚPFLASH_ERROR_PGS ÚPFLASH_ERROR_MISÚPFLASH_ERROR_FASTÇÚPFLASH_ERROR_FWWERRÚ PFLASH_ERROR_NOTZERO¾Ú PFLASH_ERROR_OPERATION:ÚPFLASH_ERROR_ERS ÚP
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OB_WDG_SWÞÚP
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OB_WDG_HWéÚ#POB_SDADC12_VDD_MONITOR_SETÖÚ%P OB_SDADC12_VDD_MONITOR_RESET;Ú POB_RAM_PARITY_CHECK_SETÚ"POB_RAM_PARITY_CHECK_RESETòÚ"PIS_OB_SDADC12_VDD_MONITOR(ÚPOB_RDP_LEVEL0ÔÚPOB_RDP_LEVEL1ÓÚPOB_RDP_LEVEL2ÒÚ"POB_BOOT_ENTRY_FORCED_NONEãÚ#POB_BOOT_ENTRY_FORCED_FLASH£Ú(P HAL_SYSCFG_FASTMODEPLUS_I2C_PA9NÚ)P!HAL_SYSCFG_FASTMODEPLUS_I2C_PA10$Ú(P HAL_SYSCFG_FASTMODEPLUS_I2C_PB6PÚ(P HAL_SYSCFG_FASTMODEPLUS_I2C_PB7OÚ(P HAL_SYSCFG_FASTMODEPLUS_I2C_PB8NÚ(P HAL_SYSCFG_FASTMODEPLUS_I2C_PB9MÚ%P HAL_SYSCFG_FASTMODEPLUS_I2C1LÚ%P HAL_SYSCFG_FASTMODEPLUS_I2C2KÚ%P HAL_SYSCFG_FASTMODEPLUS_I2C3JÚ PFSMC_NORSRAM_TYPEDEFÚ&P FSMC_NORSRAM_EXTENDED_TYPEDEFÇÚPGET_GPIO_SOURCEÚPGET_GPIO_INDEXjÚPGPIO_AF0_LPTIM
ÚPGPIO_AF1_LPTIMÚPGPIO_AF2_LPTIMÚPGPIO_SPEED_LOW_ÚPGPIO_SPEED_MEDIUMÚPGPIO_SPEED_FAST!ÚPGPIO_SPEED_HIGH/ÚPGPIO_AF6_DFSDMÚ,P$HRTIM_TIMDELAYEDPROTECTION_DISABLED"Ú5P-HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68zÚ5P-HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68yÚ5P-HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68vÚ2P*HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68wÚ6P.HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV792Ú6P.HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV791Ú5P-HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79tÚ2P*HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79uÚ P__HAL_HRTIM_SetCounter¾Ú P__HAL_HRTIM_GetCounterÊÚ P__HAL_HRTIM_SetPeriod=Ú P__HAL_HRTIM_GetPeriodIÚ&P __HAL_HRTIM_SetClockPrescalerÚ&P __HAL_HRTIM_GetClockPrescalerÚ P__HAL_HRTIM_SetCompare×Ú P__HAL_HRTIM_GetCompareãÚ!PI2C_DUALADDRESS_DISABLED»Ú PI2C_DUALADDRESS_ENABLED
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Ú!PI2C_GENERALCALL_DISABLEDÍÚ PI2C_GENERALCALL_ENABLED Ú PI2C_NOSTRETCH_DISABLED1Ú PI2C_NOSTRETCH_ENABLEDÚ!PI2C_ANALOGFILTER_ENABLED¼Ú"PI2C_ANALOGFILTER_DISABLEDmÚ%P IRDA_ONE_BIT_SAMPLE_DISABLED<Ú$P IRDA_ONE_BIT_SAMPLE_ENABLEDÚPKR_KEY_RELOAD¶ÚPKR_KEY_ENABLEÆÚP KR_KEY_EWAÚP KR_KEY_DWAÚ0P(LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTIONÃÚ,P$LPTIM_CLOCKSAMPLETIME_2TRANSISTIONSÚ,P$LPTIM_CLOCKSAMPLETIME_4TRANSISTIONSÿÚ,P$LPTIM_CLOCKSAMPLETIME_8TRANSISTIONSûÚ'P LPTIM_CLOCKPOLARITY_RISINGEDGEÚ(P LPTIM_CLOCKPOLARITY_FALLINGEDGEWÚ&P LPTIM_CLOCKPOLARITY_BOTHEDGESØÚ/P'LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTIONûÚ+P#LPTIM_TRIGSAMPLETIME_2TRANSISTIONS9Ú+P#LPTIM_TRIGSAMPLETIME_4TRANSISTIONS7Ú+P#LPTIM_TRIGSAMPLETIME_8TRANSISTIONS3Ú)P!LPTIM_TRIGSAMPLETIME_2TRANSITIONãÚ)P!LPTIM_TRIGSAMPLETIME_4TRANSITIONáÚ)P!LPTIM_TRIGSAMPLETIME_8TRANSITIONÝÚ PHAL_LPTIM_ReadCompareEÚPHAL_NAND_Read_PageÚ PHAL_NAND_Write_Page
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Ú PHAL_NAND_Read_SpareAreaÚ!PHAL_NAND_Write_SpareArea Ú PNAND_AddressTypedefÚP__ARRAY_ADDRESS ÚP__ADDR_1st_CYCLEÚP__ADDR_2nd_CYCLE ÚP__ADDR_3rd_CYCLEÚP__ADDR_4th_CYCLEÚPNOR_StatusTypedefÚP NOR_SUCCESSNÚP NOR_ONGOINGVÚP
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NOR_ERRORáÚP NOR_TIMEOUT@ÚP __NOR_WRITE ÚP__NOR_ADDR_SHIFT§Ú$P OPAMP_NONINVERTINGINPUT_VP0SÚ$P OPAMP_NONINVERTINGINPUT_VP1RÚ$P OPAMP_NONINVERTINGINPUT_VP2QÚ$P OPAMP_NONINVERTINGINPUT_VP3PÚ(P OPAMP_SEC_NONINVERTINGINPUT_VP0Ú(P OPAMP_SEC_NONINVERTINGINPUT_VP1Ú(P OPAMP_SEC_NONINVERTINGINPUT_VP2Ú(P OPAMP_SEC_NONINVERTINGINPUT_VP3Ú!POPAMP_INVERTINGINPUT_VM0GÚ!POPAMP_INVERTINGINPUT_VM1FÚ"PIOPAMP_INVERTINGINPUT_VM0üÚ"PIOPAMP_INVERTINGINPUT_VM1ûÚ%P OPAMP_SEC_INVERTINGINPUT_VM0Ú%P OPAMP_SEC_INVERTINGINPUT_VM1Ú"POPAMP_INVERTINGINPUT_VINMÞÚ POPAMP_PGACONNECT_NOëÚ POPAMP_PGACONNECT_VM0³Ú POPAMP_PGACONNECT_VM1²Ú PI2S_STANDARD_PHILLIPS_ÚPCF_DATA»ÚPCF_SECTOR_COUNT ÚPCF_SECTOR_NUMBERËÚPCF_CYLINDER_LOWÚPCF_CYLINDER_HIGHêÚP CF_CARD_HEAD@ÚPCF_STATUS_CMD²Ú PCF_STATUS_CMD_ALTERNATEÚ PCF_COMMON_DATA_AREAÚPCF_READ_SECTOR_CMDAÚ PCF_WRITE_SECTOR_CMDÐÚ PCF_ERASE_SECTOR_CMDëÚPCF_IDENTIFY_CMD6Ú PPCCARD_StatusTypedefBÚPPCCARD_SUCCESSÚPPCCARD_ONGOINGÚP PCCARD_ERROR ÚPPCCARD_TIMEOUT|ÚP FORMAT_BIN¶ÚP FORMAT_BCDÆÚ$P RTC_ALARMSUBSECONDMASK_None Ú'P RTC_TAMPERERASEBACKUP_DISABLEDÁÚ%P RTC_TAMPERMASK_FLAG_DISABLEDFÚ$P RTC_TAMPERMASK_FLAG_ENABLEDÚ$P RTC_MASKTAMPERFLAG_DISABLED§Ú#PRTC_MASKTAMPERFLAG_ENABLEDöÚ&P RTC_TAMPERERASEBACKUP_ENABLEDÚ PRTC_TAMPER1_2_INTERRUPTÚ"PRTC_TAMPER1_2_3_INTERRUPTÚ PRTC_TIMESTAMPPIN_PC13hÚ PRTC_TIMESTAMPPIN_PA0 Ú PRTC_TIMESTAMPPIN_PI8Ú PRTC_TIMESTAMPPIN_PC1Ú PRTC_OUTPUT_REMAP_PC13>Ú PRTC_OUTPUT_REMAP_PB14>Ú PRTC_OUTPUT_REMAP_PB2sÚPRTC_TAMPERPIN_PC13YÚPRTC_TAMPERPIN_PA0ÚPRTC_TAMPERPIN_PI8Ú PRTC_TAMPER1_INTERRUPT3Ú PRTC_TAMPER2_INTERRUPT2Ú PRTC_TAMPER3_INTERRUPT1Ú!PRTC_ALL_TAMPER_INTERRUPT&Ú PSMARTCARD_NACK_ENABLED8Ú PSMARTCARD_NACK_DISABLEDéÚ+P#SMARTCARD_ONEBIT_SAMPLING_DISABLEDuÚ*P"SMARTCARD_ONEBIT_SAMPLING_ENABLEDÄÚ*P"SMARTCARD_ONEBIT_SAMPLING_DISABLE»Ú)P!SMARTCARD_ONEBIT_SAMPLING_ENABLE
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Ú#PSMARTCARD_TIMEOUT_DISABLEDÙÚ"PSMARTCARD_TIMEOUT_ENABLED(Ú#PSMARTCARD_LASTBIT_DISABLEDíÚ"PSMARTCARD_LASTBIT_ENABLED<Ú#PSMBUS_DUALADDRESS_DISABLEDëÚ"PSMBUS_DUALADDRESS_ENABLED:Ú#PSMBUS_GENERALCALL_DISABLEDýÚ"PSMBUS_GENERALCALL_ENABLEDLÚ!PSMBUS_NOSTRETCH_DISABLEDaÚ PSMBUS_NOSTRETCH_ENABLED°Ú#PSMBUS_ANALOGFILTER_ENABLEDìÚ$P SMBUS_ANALOGFILTER_DISABLEDÚPSMBUS_PEC_DISABLEDOÚPSMBUS_PEC_ENABLEDÚ%P HAL_SMBUS_STATE_SLAVE_LISTENíÚ PSPI_TIMODE_DISABLEDÚPSPI_TIMODE_ENABLEDPÚ$P SPI_CRCCALCULATION_DISABLED¬Ú#PSPI_CRCCALCULATION_ENABLEDûÚ PSPI_NSS_PULSE_DISABLEDáÚ PSPI_NSS_PULSE_ENABLED0ÚPCCER_CCxE_MASKeÚPCCER_CCxNE_MASKÚPTIM_DMABase_CR1òÚPTIM_DMABase_CR2ñÚPTIM_DMABase_SMCRÚPTIM_DMABase_DIERÚPTIM_DMABase_SRÚPTIM_DMABase_EGRÚÚPTIM_DMABase_CCMR1^ÚPTIM_DMABase_CCMR2]ÚPTIM_DMABase_CCERÚPTIM_DMABase_CNTÓÚPTIM_DMABase_PSCÒÚPTIM_DMABase_ARRÓÚPTIM_DMABase_RCRÑÚPTIM_DMABase_CCR1ÚPTIM_DMABase_CCR2¬ÚPTIM_DMABase_CCR3«ÚPTIM_DMABase_CCR4ªÚPTIM_DMABase_BDTRÚPTIM_DMABase_DCRßÚPTIM_DMABase_DMARÚPTIM_DMABase_OR1æÚPTIM_DMABase_CCMR3\ÚPTIM_DMABase_CCR5©ÚPTIM_DMABase_CCR6¨ÚPTIM_DMABase_OR2åÚPTIM_DMABase_OR3äÚPTIM_DMABase_ORÚ PTIM_EventSource_Update!Ú PTIM_EventSource_CC1ÓÚ PTIM_EventSource_CC2ÒÚ PTIM_EventSource_CC3ÑÚ PTIM_EventSource_CC4ÐÚ PTIM_EventSource_COM«Ú PTIM_EventSource_Trigger®Ú PTIM_EventSource_Break¡Ú PTIM_EventSource_Break2mÚ%P TIM_DMABurstLength_1Transfer1Ú&P TIM_DMABurstLength_2Transfers»Ú&P TIM_DMABurstLength_3TransfersºÚ&P TIM_DMABurstLength_4Transfers¹Ú&P TIM_DMABurstLength_5Transfers¸Ú&P TIM_DMABurstLength_6Transfers·Ú&P TIM_DMABurstLength_7Transfers¶Ú&P TIM_DMABurstLength_8TransfersµÚ&P TIM_DMABurstLength_9Transfers´Ú'P TIM_DMABurstLength_10TransfersÚ'P TIM_DMABurstLength_11TransfersÚ'P TIM_DMABurstLength_12TransfersÚ'P TIM_DMABurstLength_13TransfersÚ'P TIM_DMABurstLength_14TransfersÚ'P TIM_DMABurstLength_15Transfers
Ú'P TIM_DMABurstLength_16TransfersÚ'P TIM_DMABurstLength_17TransfersÚ'P TIM_DMABurstLength_18TransfersÚPTIM22_TI1_GPIO1sÚPTIM22_TI1_GPIO2rÚPTSC_SYNC_POL_FALL[Ú PTSC_SYNC_POL_RISE_HIGH¾Ú&P UART_ONEBIT_SAMPLING_DISABLEDäÚ%P UART_ONEBIT_SAMPLING_ENABLED3Ú%P UART_ONE_BIT_SAMPLE_DISABLED Ú$P UART_ONE_BIT_SAMPLE_ENABLEDoÚ!P__HAL_UART_ONEBIT_ENABLEGÚ"P__HAL_UART_ONEBIT_DISABLEøÚP__DIV_SAMPLING16éÚ P__DIVMANT_SAMPLING16±Ú P__DIVFRAQ_SAMPLING16·Ú P__UART_BRR_SAMPLING16AÚP__DIV_SAMPLING8Ú P__DIVMANT_SAMPLING8âÚ P__DIVFRAQ_SAMPLING8èÚ P__UART_BRR_SAMPLING8rÚP __DIV_LPUARTÛÚ$P UART_WAKEUPMETHODE_IDLELINEÚ'P UART_WAKEUPMETHODE_ADDRESSMARKÚ PUSART_CLOCK_DISABLED²Ú PUSART_CLOCK_ENABLEDÚPUSARTNACK_ENABLED³ÚPUSARTNACK_DISABLEDdÚP CFR_BASEfÚPCAN_FilterFIFO0ÂÚPCAN_FilterFIFO1ÁÚP CAN_IT_RQCP0 ÚP CAN_IT_RQCP1 ÚP CAN_IT_RQCP2 ÚP INAK_TIMEOUT
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ÚP SLAK_TIMEOUTÚ PCAN_TXSTATUS_FAILEDàÚPCAN_TXSTATUS_OKóÚ PCAN_TXSTATUS_PENDING~ÚP VLAN_TAGOÚPMIN_ETH_PAYLOAD ÚPMAX_ETH_PAYLOAD Ú PJUMBO_FRAME_PAYLOADõÚPMACMIIAR_CR_MASKéÚPMACCR_CLEAR_MASKôÚPMACFCR_CLEAR_MASK¬ÚPDMAOMR_CLEAR_MASKÚP
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ETH_MMCCRÚP ETH_MMCRIRÚP ETH_MMCTIR«ÚP ETH_MMCRIMR^ÚP ETH_MMCTIMR\ÚPETH_MMCTGFSCCRÚPETH_MMCTGFMSCCR7ÚP ETH_MMCTGFCR ÚPETH_MMCRFCECRßÚPETH_MMCRFAECRáÚPETH_MMCRGUFCRËÚ PETH_MAC_TXFIFO_FULLÓÚ PETH_MAC_TXFIFONOT_EMPTY~Ú$P ETH_MAC_TXFIFO_WRITE_ACTIVEPÚ PETH_MAC_TXFIFO_IDLEèÚ PETH_MAC_TXFIFO_READêÚ PETH_MAC_TXFIFO_WAITINGíÚ PETH_MAC_TXFIFO_WRITINGÜÚ#PETH_MAC_TRANSMISSION_PAUSE Ú-P%ETH_MAC_TRANSMITFRAMECONTROLLER_IDLEµÚ0P(ETH_MAC_TRANSMITFRAMECONTROLLER_WAITINGºÚ6P.ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCFêÚ5P-ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING.Ú$P ETH_MAC_MII_TRANSMIT_ACTIVEZÚ PETH_MAC_RXFIFO_EMPTYwÚ'P ETH_MAC_RXFIFO_BELOW_THRESHOLDmÚ'P ETH_MAC_RXFIFO_ABOVE_THRESHOLDyÚ PETH_MAC_RXFIFO_FULLÕÚ$P ETH_MAC_READCONTROLLER_IDLEÚ,P$ETH_MAC_READCONTROLLER_READING_DATA#Ú.PÐ_MAC_READCONTROLLER_READING_STATUSUÚ(P ETH_MAC_READCONTROLLER_FLUSHING>Ú$P ETH_MAC_RXFIFO_WRITE_ACTIVERÚ%P ETH_MAC_SMALL_FIFO_NOTACTIVEÚ'P ETH_MAC_SMALL_FIFO_READ_ACTIVEÚ(P ETH_MAC_SMALL_FIFO_WRITE_ACTIVE Ú%P ETH_MAC_SMALL_FIFO_RW_ACTIVEÚ,P$ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVEèÚPHAL_DCMI_ERROR_OVF#ÚP DCMI_IT_OVFRÚPDCMI_FLAG_OVFRI2ÚPDCMI_FLAG_OVFMI7Ú PHAL_DCMI_ConfigCROPkÚ PHAL_DCMI_EnableCROPzÚ PHAL_DCMI_DisableCROP Ú)P!HAL_CRYP_ComputationCpltCallbackÚ PHAL_HASHEx_IRQHandlerÚ PHAL_HASH_STATETypeDef¸Ú PHAL_HASHPhaseTypeDef©Ú PHAL_HMAC_MD5_FinishsÚ PHAL_HMAC_SHA1_Finish*Ú PHAL_HMAC_SHA224_Finish¿Ú PHAL_HMAC_SHA256_FinishºÚ PHASH_AlgoSelection_SHA1
Ú"PHASH_AlgoSelection_SHA224Ú"PHASH_AlgoSelection_SHA256Ú PHASH_AlgoSelection_MD5ÎÚPHASH_AlgoMode_HASHÚPHASH_AlgoMode_HMAC¤Ú"PHASH_HMACKeyType_ShortKeyÚ!PHASH_HMACKeyType_LongKey Ú PHAL_EnableDBGSleepModeÙÚ PHAL_DisableDBGSleepModejÚ PHAL_EnableDBGStopMode.Ú PHAL_DisableDBGStopMode¿Ú!PHAL_EnableDBGStandbyModeùÚ"PHAL_DisableDBGStandbyModeÚ PHAL_DBG_LowPowerConfigªÚ!PHAL_VREFINT_OutputSelectùÚP HAL_Lock_CmdÚ!PHAL_ADC_EnableBuffer_Cmd,Ú'P HAL_ADC_EnableBufferSensor_Cmd¦Ú PFLASH_HalfPageProgramÚ!PFLASH_EnableRunPowerDownÚ"PFLASH_DisableRunPowerDown>Ú!PHAL_DATA_EEPROMEx_UnlockÚ PHAL_DATA_EEPROMEx_Lock
Ú PHAL_DATA_EEPROMEx_Erase Ú"PHAL_DATA_EEPROMEx_Program0Ú&P HAL_I2CEx_AnalogFilter_ConfigÚ'P HAL_I2CEx_DigitalFilter_Config¨Ú)P!HAL_FMPI2CEx_AnalogFilter_Config-Ú*P"HAL_FMPI2CEx_DigitalFilter_Config¿Ú"PHAL_I2CFastModePlusConfigÚ.P&HAL_I2C_Master_Sequential_Transmit_ITÚ-P%HAL_I2C_Master_Sequential_Receive_IT.Ú-P%HAL_I2C_Slave_Sequential_Transmit_ITÚ,P$HAL_I2C_Slave_Sequential_Receive_IT¡Ú/P'HAL_I2C_Master_Sequential_Transmit_DMAfÚ.P&HAL_I2C_Master_Sequential_Receive_DMA÷Ú.P&HAL_I2C_Slave_Sequential_Transmit_DMAÙÚ-P%HAL_I2C_Slave_Sequential_Receive_DMAjÚPHAL_PWR_PVDConfigÝÚ PHAL_PWR_DisableBkUpRegÏÚ&P HAL_PWR_DisableFlashPowerDown¾Ú%P HAL_PWR_DisableVddio2MonitorCÚ PHAL_PWR_EnableBkUpReg>Ú%P HAL_PWR_EnableFlashPowerDown-Ú$P HAL_PWR_EnableVddio2Monitor²Ú#PHAL_PWR_PVD_PVM_IRQHandlerÆÚ PHAL_PWR_PVDLevelConfigÛÚ)P!HAL_PWR_Vddio2Monitor_IRQHandleræÚ&P HAL_PWR_Vddio2MonitorCallbackèÚ$P HAL_PWREx_ActivateOverDrive
Ú&P HAL_PWREx_DeactivateOverDrive¸Ú%P HAL_PWREx_DisableSDADCAnalogåÚ$P HAL_PWREx_EnableSDADCAnalogTÚ PHAL_PWREx_PVMConfigÚPPWR_MODE_NORMALÚPPWR_MODE_IT_RISINGÚ PPWR_MODE_IT_FALLINGÐÚ#PPWR_MODE_IT_RISING_FALLINGÚ PPWR_MODE_EVENT_RISINGÚ PPWR_MODE_EVENT_FALLINGåÚ&P PWR_MODE_EVENT_RISING_FALLING¬ÚP CR_OFFSET_BBÚPCSR_OFFSET_BBÀÚPPMODE_BIT_NUMBERÐÚP CR_PMODE_BBiÚPDBP_BitNumberôÚPPVDE_BitNumberÚPPMODE_BitNumberQÚPEWUP_BitNumberÚPFPDS_BitNumberÚPODEN_BitNumber¢ÚPODSWEN_BitNumberôÚPMRLVDS_BitNumberìÚPLPLVDS_BitNumberïÚPBRE_BitNumberñÚP PWR_MODE_EVTèÚ"PHAL_SMBUS_Slave_Listen_IT·Ú$P HAL_SMBUS_SlaveAddrCallbackõÚ*P"HAL_SMBUS_SlaveListenCpltCallbackbÚ PHAL_SPI_FlushRxFifoÖÚ"PHAL_TIM_DMADelayPulseCplt¿ÚPHAL_TIM_DMAErrorRÚ PHAL_TIM_DMACaptureCpltéÚ%P HAL_TIMEx_DMACommutationCpltdÚ+P#HAL_TIM_SlaveConfigSynchronizationgÚ.P&HAL_TIM_SlaveConfigSynchronization_ITeÚ&P HAL_TIMEx_CommutationCallbackºÚ)P!HAL_TIMEx_ConfigCommutationEventiÚ,P$HAL_TIMEx_ConfigCommutationEvent_ITgÚ-P%HAL_TIMEx_ConfigCommutationEvent_DMA0Ú PHAL_UART_WakeupCallbackTÚ"PHAL_LTDC_LineEvenCallback¼ÚPHAL_LTDC_RelaodÚ+P#HAL_LTDC_StructInitFromVideoConfigÓÚ4P,HAL_LTDC_StructInitFromAdaptedCommandConfigFÚP
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__HAL_UNFREEZE_TIM16_DBGMCU~Ú"P__HAL_FREEZE_TIM17_DBGMCU$Ú$P __HAL_UNFREEZE_TIM17_DBGMCU}Ú P__HAL_FREEZE_RTC_DBGMCUÚ"P__HAL_UNFREEZE_RTC_DBGMCUêÚ!P__HAL_FREEZE_WWDG_DBGMCU?Ú#P__HAL_UNFREEZE_WWDG_DBGMCUÚ!P__HAL_FREEZE_IWDG_DBGMCUMÚ#P__HAL_UNFREEZE_IWDG_DBGMCU¦Ú)P!__HAL_FREEZE_I2C1_TIMEOUT_DBGMCUóÚ+P#__HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCULÚ)P!__HAL_FREEZE_I2C2_TIMEOUT_DBGMCUòÚ+P#__HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCUKÚ)P!__HAL_FREEZE_I2C3_TIMEOUT_DBGMCUñÚ+P#__HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCUJÚ!P__HAL_FREEZE_CAN1_DBGMCUuÚ#P__HAL_UNFREEZE_CAN1_DBGMCUÎÚ#P__HAL_FREEZE_LPTIM1_DBGMCU½Ú%P __HAL_UNFREEZE_LPTIM1_DBGMCUÚ#P__HAL_FREEZE_LPTIM2_DBGMCU¼Ú%P __HAL_UNFREEZE_LPTIM2_DBGMCUÚ)P!__HAL_COMP_EXTI_RISING_IT_ENABLE¤Ú*P"__HAL_COMP_EXTI_RISING_IT_DISABLEUÚ*P"__HAL_COMP_EXTI_FALLING_IT_ENABLEqÚ+P#__HAL_COMP_EXTI_FALLING_IT_DISABLE"Ú"P__HAL_COMP_EXTI_ENABLE_ITÝÚ#P__HAL_COMP_EXTI_DISABLE_ITÚ!P__HAL_COMP_EXTI_GET_FLAG)Ú#P__HAL_COMP_EXTI_CLEAR_FLAGÚ!P__HAL_COMP_GET_EXTI_LINEÚ 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Ú P__COMP_RELEASE_RESETtÚ P__COMP_CLK_SLEEP_ENABLEÚ!P__COMP_CLK_SLEEP_DISABLEJÚP__CEC_FORCE_RESETpÚ P__CEC_RELEASE_RESETÚÚP__CRC_CLK_DISABLEÚP__CRC_CLK_ENABLEÖÚ P__CRC_CLK_SLEEP_DISABLE£Ú P__CRC_CLK_SLEEP_ENABLEòÚP__CRC_FORCE_RESETcÚ P__CRC_RELEASE_RESETÍÚP__DAC_CLK_DISABLEÚP__DAC_CLK_ENABLEæÚP__DAC_FORCE_RESETsÚ P__DAC_RELEASE_RESETÝÚP__DAC1_CLK_DISABLEdÚP__DAC1_CLK_ENABLE³Ú!P__DAC1_CLK_SLEEP_DISABLEÚ P__DAC1_CLK_SLEEP_ENABLEÏÚP__DAC1_FORCE_RESET@Ú P__DAC1_RELEASE_RESETªÚ P__DBGMCU_CLK_ENABLEöÚ P__DBGMCU_CLK_DISABLE§Ú P__DBGMCU_FORCE_RESETÚ P__DBGMCU_RELEASE_RESETíÚ P__DFSDM_CLK_DISABLEíÚP__DFSDM_CLK_ENABLE<Ú"P__DFSDM_CLK_SLEEP_DISABLE Ú!P__DFSDM_CLK_SLEEP_ENABLEXÚ P__DFSDM_FORCE_RESETÉÚ P__DFSDM_RELEASE_RESET3ÚP__DMA1_CLK_DISABLEZÚP__DMA1_CLK_ENABLE©Ú!P__DMA1_CLK_SLEEP_DISABLEvÚ P__DMA1_CLK_SLEEP_ENABLEÅÚP__DMA1_FORCE_RESET6Ú P__DMA1_RELEASE_RESET ÚP__DMA2_CLK_DISABLEYÚP__DMA2_CLK_ENABLE¨Ú!P__DMA2_CLK_SLEEP_DISABLEuÚ P__DMA2_CLK_SLEEP_ENABLEÄÚP__DMA2_FORCE_RESET5Ú P__DMA2_RELEASE_RESETÚ P__ETHMAC_CLK_DISABLE§Ú P__ETHMAC_CLK_ENABLEöÚ P__ETHMAC_FORCE_RESETÚ P__ETHMAC_RELEASE_RESETíÚ P__ETHMACRX_CLK_DISABLEùÚ P__ETHMACRX_CLK_ENABLEHÚ P__ETHMACTX_CLK_DISABLE÷Ú P__ETHMACTX_CLK_ENABLEFÚ P__FIREWALL_CLK_DISABLEÿÚ P__FIREWALL_CLK_ENABLENÚ P__FLASH_CLK_DISABLEíÚP__FLASH_CLK_ENABLE<Ú"P__FLASH_CLK_SLEEP_DISABLE Ú!P__FLASH_CLK_SLEEP_ENABLEXÚ P__FLASH_FORCE_RESETÉÚ P__FLASH_RELEASE_RESET3Ú P__FLITF_CLK_DISABLEæÚP__FLITF_CLK_ENABLE5Ú P__FLITF_FORCE_RESETÂÚ P__FLITF_RELEASE_RESET,Ú!P__FLITF_CLK_SLEEP_ENABLEQÚ"P__FLITF_CLK_SLEEP_DISABLEÚP__FMC_CLK_DISABLEÚP__FMC_CLK_ENABLEØÚ P__FMC_CLK_SLEEP_DISABLE¥Ú P__FMC_CLK_SLEEP_ENABLEôÚP__FMC_FORCE_RESETeÚ P__FMC_RELEASE_RESETÏÚP__FSMC_CLK_DISABLE4ÚP__FSMC_CLK_ENABLEÚ P__GPIOA_CLK_DISABLEëÚP__GPIOA_CLK_ENABLE:Ú"P__GPIOA_CLK_SLEEP_DISABLEÚ!P__GPIOA_CLK_SLEEP_ENABLEVÚ P__GPIOA_FORCE_RESETÇÚ P__GPIOA_RELEASE_RESET1Ú P__GPIOB_CLK_DISABLEêÚP__GPIOB_CLK_ENABLE9Ú"P__GPIOB_CLK_SLEEP_DISABLEÚ!P__GPIOB_CLK_SLEEP_ENABLEUÚ P__GPIOB_FORCE_RESETÆÚ P__GPIOB_RELEASE_RESET0Ú P__GPIOC_CLK_DISABLEéÚP__GPIOC_CLK_ENABLE8Ú"P__GPIOC_CLK_SLEEP_DISABLEÚ!P__GPIOC_CLK_SLEEP_ENABLETÚ P__GPIOC_FORCE_RESETÅÚ P__GPIOC_RELEASE_RESET/Ú P__GPIOD_CLK_DISABLEèÚP__GPIOD_CLK_ENABLE7Ú"P__GPIOD_CLK_SLEEP_DISABLEÚ!P__GPIOD_CLK_SLEEP_ENABLESÚ P__GPIOD_FORCE_RESETÄÚ P__GPIOD_RELEASE_RESET.Ú P__GPIOE_CLK_DISABLEçÚP__GPIOE_CLK_ENABLE6Ú"P__GPIOE_CLK_SLEEP_DISABLEÚ!P__GPIOE_CLK_SLEEP_ENABLERÚ P__GPIOE_FORCE_RESETÃÚ P__GPIOE_RELEASE_RESET-Ú P__GPIOF_CLK_DISABLEæÚP__GPIOF_CLK_ENABLE5Ú"P__GPIOF_CLK_SLEEP_DISABLEÚ!P__GPIOF_CLK_SLEEP_ENABLEQÚ P__GPIOF_FORCE_RESETÂÚ P__GPIOF_RELEASE_RESET,Ú P__GPIOG_CLK_DISABLEåÚP__GPIOG_CLK_ENABLE4Ú"P__GPIOG_CLK_SLEEP_DISABLEÚ!P__GPIOG_CLK_SLEEP_ENABLEPÚ P__GPIOG_FORCE_RESETÁÚ P__GPIOG_RELEASE_RESET+Ú P__GPIOH_CLK_DISABLEäÚP__GPIOH_CLK_ENABLE3Ú"P__GPIOH_CLK_SLEEP_DISABLEÚ!P__GPIOH_CLK_SLEEP_ENABLEOÚ P__GPIOH_FORCE_RESETÀÚ P__GPIOH_RELEASE_RESET*ÚP__I2C1_CLK_DISABLEnÚP__I2C1_CLK_ENABLE½Ú!P__I2C1_CLK_SLEEP_DISABLEÚ P__I2C1_CLK_SLEEP_ENABLEÙÚP__I2C1_FORCE_RESETJÚ P__I2C1_RELEASE_RESET´ÚP__I2C2_CLK_DISABLEmÚP__I2C2_CLK_ENABLE¼Ú!P__I2C2_CLK_SLEEP_DISABLEÚ P__I2C2_CLK_SLEEP_ENABLEØÚP__I2C2_FORCE_RESETIÚ P__I2C2_RELEASE_RESET³ÚP__I2C3_CLK_DISABLElÚP__I2C3_CLK_ENABLE»Ú!P__I2C3_CLK_SLEEP_DISABLEÚ P__I2C3_CLK_SLEEP_ENABLE×ÚP__I2C3_FORCE_RESETHÚ P__I2C3_RELEASE_RESET²ÚP__LCD_CLK_DISABLEÚP__LCD_CLK_ENABLEÛÚ P__LCD_CLK_SLEEP_DISABLE¨Ú P__LCD_CLK_SLEEP_ENABLE÷ÚP__LCD_FORCE_RESEThÚ P__LCD_RELEASE_RESETÒÚ P__LPTIM1_CLK_DISABLE¢Ú P__LPTIM1_CLK_ENABLEñÚ#P__LPTIM1_CLK_SLEEP_DISABLE¾Ú"P__LPTIM1_CLK_SLEEP_ENABLE Ú P__LPTIM1_FORCE_RESET~Ú P__LPTIM1_RELEASE_RESETèÚ P__LPTIM2_CLK_DISABLE¡Ú P__LPTIM2_CLK_ENABLEðÚ#P__LPTIM2_CLK_SLEEP_DISABLE½Ú"P__LPTIM2_CLK_SLEEP_ENABLE Ú P__LPTIM2_FORCE_RESET}Ú P__LPTIM2_RELEASE_RESETçÚ P__LPUART1_CLK_DISABLENÚ P__LPUART1_CLK_ENABLEÚ$P __LPUART1_CLK_SLEEP_DISABLEjÚ#P__LPUART1_CLK_SLEEP_ENABLE¹Ú P__LPUART1_FORCE_RESET*Ú P__LPUART1_RELEASE_RESETÚ P__OPAMP_CLK_DISABLEÞÚP__OPAMP_CLK_ENABLE-Ú"P__OPAMP_CLK_SLEEP_DISABLEúÚ!P__OPAMP_CLK_SLEEP_ENABLEIÚ P__OPAMP_FORCE_RESETºÚ P__OPAMP_RELEASE_RESET$Ú P__OTGFS_CLK_DISABLEØÚP__OTGFS_CLK_ENABLE'Ú"P__OTGFS_CLK_SLEEP_DISABLEôÚ!P__OTGFS_CLK_SLEEP_ENABLECÚ P__OTGFS_FORCE_RESET´Ú P__OTGFS_RELEASE_RESET ÚP__PWR_CLK_DISABLEfÚP__PWR_CLK_ENABLEµÚ P__PWR_CLK_SLEEP_DISABLEÚ P__PWR_CLK_SLEEP_ENABLEÑÚP__PWR_FORCE_RESETBÚ P__PWR_RELEASE_RESET¬ÚP__QSPI_CLK_DISABLE ÚP__QSPI_CLK_ENABLEoÚ!P__QSPI_CLK_SLEEP_DISABLE<Ú P__QSPI_CLK_SLEEP_ENABLEÚP__QSPI_FORCE_RESETüÚ P__QSPI_RELEASE_RESETfÚP__RNG_CLK_DISABLExÚP__RNG_CLK_ENABLEÇÚ P__RNG_CLK_SLEEP_DISABLEÚ P__RNG_CLK_SLEEP_ENABLEãÚP__RNG_FORCE_RESETTÚ P__RNG_RELEASE_RESET¾ÚP__SAI1_CLK_DISABLEOÚP__SAI1_CLK_ENABLEÚ!P__SAI1_CLK_SLEEP_DISABLEkÚ P__SAI1_CLK_SLEEP_ENABLEºÚP__SAI1_FORCE_RESET+Ú P__SAI1_RELEASE_RESETÚP__SAI2_CLK_DISABLENÚP__SAI2_CLK_ENABLEÚ!P__SAI2_CLK_SLEEP_DISABLEjÚ P__SAI2_CLK_SLEEP_ENABLE¹ÚP__SAI2_FORCE_RESET*Ú P__SAI2_RELEASE_RESETÚP__SDIO_CLK_DISABLE.ÚP__SDIO_CLK_ENABLE}Ú P__SDMMC_CLK_DISABLEçÚP__SDMMC_CLK_ENABLE6Ú"P__SDMMC_CLK_SLEEP_DISABLEÚ!P__SDMMC_CLK_SLEEP_ENABLERÚ P__SDMMC_FORCE_RESETÃÚ P__SDMMC_RELEASE_RESET-ÚP__SPI1_CLK_DISABLE@ÚP__SPI1_CLK_ENABLEÚ!P__SPI1_CLK_SLEEP_DISABLE\Ú P__SPI1_CLK_SLEEP_ENABLE«ÚP__SPI1_FORCE_RESET Ú P__SPI1_RELEASE_RESETÚP__SPI2_CLK_DISABLE?ÚP__SPI2_CLK_ENABLEÚ!P__SPI2_CLK_SLEEP_DISABLE[Ú P__SPI2_CLK_SLEEP_ENABLEªÚP__SPI2_FORCE_RESETÚ P__SPI2_RELEASE_RESET
ÚP__SPI3_CLK_DISABLE>ÚP__SPI3_CLK_ENABLEÚ!P__SPI3_CLK_SLEEP_DISABLEZÚ P__SPI3_CLK_SLEEP_ENABLE©ÚP__SPI3_FORCE_RESETÚ P__SPI3_RELEASE_RESETÚP__SRAM_CLK_DISABLE*ÚP__SRAM_CLK_ENABLEyÚ"P__SRAM1_CLK_SLEEP_DISABLEÚ!P__SRAM1_CLK_SLEEP_ENABLEbÚ"P__SRAM2_CLK_SLEEP_DISABLEÚ!P__SRAM2_CLK_SLEEP_ENABLEaÚ P__SWPMI1_CLK_DISABLEÚ P__SWPMI1_CLK_ENABLEçÚ#P__SWPMI1_CLK_SLEEP_DISABLE´Ú"P__SWPMI1_CLK_SLEEP_ENABLEÚ P__SWPMI1_FORCE_RESETtÚ P__SWPMI1_RELEASE_RESETÞÚ P__SYSCFG_CLK_DISABLEÚ P__SYSCFG_CLK_ENABLEÙÚ#P__SYSCFG_CLK_SLEEP_DISABLE¦Ú"P__SYSCFG_CLK_SLEEP_ENABLEõÚ P__SYSCFG_FORCE_RESETfÚ P__SYSCFG_RELEASE_RESETÐÚP__TIM1_CLK_DISABLEBÚP__TIM1_CLK_ENABLEÚ!P__TIM1_CLK_SLEEP_DISABLE^Ú P__TIM1_CLK_SLEEP_ENABLEÚP__TIM1_FORCE_RESET Ú P__TIM1_RELEASE_RESETÚ P__TIM10_CLK_DISABLEÚP__TIM10_CLK_ENABLE_Ú P__TIM10_FORCE_RESETìÚ P__TIM10_RELEASE_RESETVÚ P__TIM11_CLK_DISABLEÚP__TIM11_CLK_ENABLE^Ú P__TIM11_FORCE_RESETëÚ P__TIM11_RELEASE_RESETUÚ P__TIM12_CLK_DISABLEÚP__TIM12_CLK_ENABLE]Ú P__TIM12_FORCE_RESETêÚ P__TIM12_RELEASE_RESETTÚ P__TIM13_CLK_DISABLE ÚP__TIM13_CLK_ENABLE\Ú P__TIM13_FORCE_RESETéÚ P__TIM13_RELEASE_RESETSÚ P__TIM14_CLK_DISABLE ÚP__TIM14_CLK_ENABLE[Ú P__TIM14_FORCE_RESETèÚ P__TIM14_RELEASE_RESETRÚ P__TIM15_CLK_DISABLE ÚP__TIM15_CLK_ENABLEZÚ"P__TIM15_CLK_SLEEP_DISABLE'Ú!P__TIM15_CLK_SLEEP_ENABLEvÚ P__TIM15_FORCE_RESETçÚ P__TIM15_RELEASE_RESETQÚ P__TIM16_CLK_DISABLE
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ÚP__TIM16_CLK_ENABLEYÚ"P__TIM16_CLK_SLEEP_DISABLE&Ú!P__TIM16_CLK_SLEEP_ENABLEuÚ P__TIM16_FORCE_RESETæÚ P__TIM16_RELEASE_RESETPÚ P__TIM17_CLK_DISABLE ÚP__TIM17_CLK_ENABLEXÚ"P__TIM17_CLK_SLEEP_DISABLE%Ú!P__TIM17_CLK_SLEEP_ENABLEtÚ P__TIM17_FORCE_RESETåÚ P__TIM17_RELEASE_RESETOÚP__TIM2_CLK_DISABLEAÚP__TIM2_CLK_ENABLEÚ!P__TIM2_CLK_SLEEP_DISABLE]Ú P__TIM2_CLK_SLEEP_ENABLE¬ÚP__TIM2_FORCE_RESET Ú P__TIM2_RELEASE_RESETÚP__TIM3_CLK_DISABLE@ÚP__TIM3_CLK_ENABLEÚ!P__TIM3_CLK_SLEEP_DISABLE\Ú P__TIM3_CLK_SLEEP_ENABLE«ÚP__TIM3_FORCE_RESET Ú P__TIM3_RELEASE_RESETÚP__TIM4_CLK_DISABLE?ÚP__TIM4_CLK_ENABLEÚ!P__TIM4_CLK_SLEEP_DISABLE[Ú P__TIM4_CLK_SLEEP_ENABLEªÚP__TIM4_FORCE_RESETÚ P__TIM4_RELEASE_RESET
ÚP__TIM5_CLK_DISABLE>ÚP__TIM5_CLK_ENABLEÚ!P__TIM5_CLK_SLEEP_DISABLEZÚ P__TIM5_CLK_SLEEP_ENABLE©ÚP__TIM5_FORCE_RESETÚ P__TIM5_RELEASE_RESETÚP__TIM6_CLK_DISABLE=ÚP__TIM6_CLK_ENABLEÚ!P__TIM6_CLK_SLEEP_DISABLEYÚ P__TIM6_CLK_SLEEP_ENABLE¨ÚP__TIM6_FORCE_RESETÚ P__TIM6_RELEASE_RESETÚP__TIM7_CLK_DISABLE<ÚP__TIM7_CLK_ENABLEÚ!P__TIM7_CLK_SLEEP_DISABLEXÚ P__TIM7_CLK_SLEEP_ENABLE§ÚP__TIM7_FORCE_RESETÚ P__TIM7_RELEASE_RESETÚP__TIM8_CLK_DISABLE;ÚP__TIM8_CLK_ENABLEÚ!P__TIM8_CLK_SLEEP_DISABLEWÚ P__TIM8_CLK_SLEEP_ENABLE¦ÚP__TIM8_FORCE_RESETÚ P__TIM8_RELEASE_RESETÚP__TIM9_CLK_DISABLE:ÚP__TIM9_CLK_ENABLEÚP__TIM9_FORCE_RESETÚ P__TIM9_RELEASE_RESETÚP__TSC_CLK_DISABLEuÚP__TSC_CLK_ENABLEÄÚ P__TSC_CLK_SLEEP_DISABLEÚ P__TSC_CLK_SLEEP_ENABLEàÚP__TSC_FORCE_RESETQÚ P__TSC_RELEASE_RESET»Ú P__UART4_CLK_DISABLEëÚP__UART4_CLK_ENABLE:Ú"P__UART4_CLK_SLEEP_DISABLEÚ!P__UART4_CLK_SLEEP_ENABLEVÚ P__UART4_FORCE_RESETÇÚ P__UART4_RELEASE_RESET1Ú P__UART5_CLK_DISABLEêÚP__UART5_CLK_ENABLE9Ú"P__UART5_CLK_SLEEP_DISABLEÚ!P__UART5_CLK_SLEEP_ENABLEUÚ P__UART5_FORCE_RESETÆÚ P__UART5_RELEASE_RESET0Ú P__USART1_CLK_DISABLEÚ P__USART1_CLK_ENABLEèÚ#P__USART1_CLK_SLEEP_DISABLEµÚ"P__USART1_CLK_SLEEP_ENABLEÚ P__USART1_FORCE_RESETuÚ P__USART1_RELEASE_RESETßÚ P__USART2_CLK_DISABLEÚ P__USART2_CLK_ENABLEçÚ#P__USART2_CLK_SLEEP_DISABLE´Ú"P__USART2_CLK_SLEEP_ENABLEÚ P__USART2_FORCE_RESETtÚ P__USART2_RELEASE_RESETÞÚ P__USART3_CLK_DISABLEÚ P__USART3_CLK_ENABLEæÚ#P__USART3_CLK_SLEEP_DISABLE³Ú"P__USART3_CLK_SLEEP_ENABLEÚ P__USART3_FORCE_RESETsÚ P__USART3_RELEASE_RESETÝÚ P__USART4_CLK_DISABLEÚ P__USART4_CLK_ENABLEåÚ"P__USART4_CLK_SLEEP_ENABLEÚ#P__USART4_CLK_SLEEP_DISABLE²Ú P__USART4_FORCE_RESETrÚ P__USART4_RELEASE_RESETÜÚ P__USART5_CLK_DISABLEÚ P__USART5_CLK_ENABLEäÚ"P__USART5_CLK_SLEEP_ENABLEÚ#P__USART5_CLK_SLEEP_DISABLE±Ú P__USART5_FORCE_RESETqÚ P__USART5_RELEASE_RESETÛÚ P__USART7_CLK_DISABLEÚ P__USART7_CLK_ENABLEâÚ P__USART7_FORCE_RESEToÚ P__USART7_RELEASE_RESETÙÚ P__USART8_CLK_DISABLEÚ P__USART8_CLK_ENABLEáÚ P__USART8_FORCE_RESETnÚ P__USART8_RELEASE_RESETØÚP__USB_CLK_DISABLEuÚP__USB_CLK_ENABLEÄÚP__USB_FORCE_RESETQÚ P__USB_CLK_SLEEP_ENABLEàÚ P__USB_CLK_SLEEP_DISABLEÚ!P__USB_OTG_FS_CLK_DISABLE&Ú P__USB_OTG_FS_CLK_ENABLEuÚ P__USB_RELEASE_RESET»ÚP__WWDG_CLK_DISABLE$ÚP__WWDG_CLK_ENABLEsÚ!P__WWDG_CLK_SLEEP_DISABLE@Ú P__WWDG_CLK_SLEEP_ENABLEÚP__WWDG_FORCE_RESETÚ P__WWDG_RELEASE_RESETjÚP__TIM21_CLK_ENABLE]Ú P__TIM21_CLK_DISABLEÚ P__TIM21_FORCE_RESETêÚ P__TIM21_RELEASE_RESETTÚ!P__TIM21_CLK_SLEEP_ENABLEyÚ"P__TIM21_CLK_SLEEP_DISABLE*ÚP__TIM22_CLK_ENABLE\Ú P__TIM22_CLK_DISABLE Ú P__TIM22_FORCE_RESETéÚ P__TIM22_RELEASE_RESETSÚ!P__TIM22_CLK_SLEEP_ENABLExÚ"P__TIM22_CLK_SLEEP_DISABLE)ÚP__CRS_CLK_DISABLEwÚP__CRS_CLK_ENABLEÆÚ P__CRS_CLK_SLEEP_DISABLEÚ P__CRS_CLK_SLEEP_ENABLEâÚP__CRS_FORCE_RESETSÚ P__CRS_RELEASE_RESET½Ú P__RCC_BACKUPRESET_FORCE¡Ú"P__RCC_BACKUPRESET_RELEASE Ú!P__USB_OTG_FS_FORCE_RESETÚ#P__USB_OTG_FS_RELEASE_RESETlÚ&P __USB_OTG_FS_CLK_SLEEP_ENABLEÚ'P __USB_OTG_FS_CLK_SLEEP_DISABLEBÚ!P__USB_OTG_HS_CLK_DISABLE$Ú P__USB_OTG_HS_CLK_ENABLEsÚ%P __USB_OTG_HS_ULPI_CLK_ENABLEÐÚ&P __USB_OTG_HS_ULPI_CLK_DISABLEÚ P__TIM9_CLK_SLEEP_ENABLE¥Ú!P__TIM9_CLK_SLEEP_DISABLEVÚ!P__TIM10_CLK_SLEEP_ENABLE{Ú"P__TIM10_CLK_SLEEP_DISABLE,Ú!P__TIM11_CLK_SLEEP_ENABLEzÚ"P__TIM11_CLK_SLEEP_DISABLE+Ú%P __ETHMACPTP_CLK_SLEEP_ENABLEÚ&P __ETHMACPTP_CLK_SLEEP_DISABLEÉÚ P__ETHMACPTP_CLK_ENABLEüÚ P__ETHMACPTP_CLK_DISABLEÚP__HASH_CLK_ENABLEÚP__HASH_FORCE_RESETÚ P__HASH_RELEASE_RESETÚ P__HASH_CLK_SLEEP_ENABLE¤Ú!P__HASH_CLK_SLEEP_DISABLEUÚP__HASH_CLK_DISABLE9ÚP__SPI5_CLK_ENABLEÚP__SPI5_CLK_DISABLE<ÚP__SPI5_FORCE_RESETÚ P__SPI5_RELEASE_RESETÚ P__SPI5_CLK_SLEEP_ENABLE§Ú!P__SPI5_CLK_SLEEP_DISABLEXÚP__SPI6_CLK_ENABLEÚP__SPI6_CLK_DISABLE;ÚP__SPI6_FORCE_RESETÚ P__SPI6_RELEASE_RESETÚ P__SPI6_CLK_SLEEP_ENABLE¦Ú!P__SPI6_CLK_SLEEP_DISABLEWÚP__LTDC_CLK_ENABLE
ÚP__LTDC_CLK_DISABLE6ÚP__LTDC_FORCE_RESETÚ P__LTDC_RELEASE_RESET|Ú P__LTDC_CLK_SLEEP_ENABLE¡Ú"P__ETHMAC_CLK_SLEEP_ENABLEÚ#P__ETHMAC_CLK_SLEEP_DISABLEÃÚ$P __ETHMACTX_CLK_SLEEP_ENABLEbÚ%P __ETHMACTX_CLK_SLEEP_DISABLEÚ$P __ETHMACRX_CLK_SLEEP_ENABLEdÚ%P __ETHMACRX_CLK_SLEEP_DISABLEÚ!P__TIM12_CLK_SLEEP_ENABLEyÚ"P__TIM12_CLK_SLEEP_DISABLE*Ú!P__TIM13_CLK_SLEEP_ENABLExÚ"P__TIM13_CLK_SLEEP_DISABLE)Ú!P__TIM14_CLK_SLEEP_ENABLEwÚ"P__TIM14_CLK_SLEEP_DISABLE(Ú P__BKPSRAM_CLK_ENABLEÚ P__BKPSRAM_CLK_DISABLEGÚ#P__BKPSRAM_CLK_SLEEP_ENABLE²Ú$P __BKPSRAM_CLK_SLEEP_DISABLEcÚ"P__CCMDATARAMEN_CLK_ENABLE<Ú#P__CCMDATARAMEN_CLK_DISABLEíÚ P__USART6_CLK_ENABLEãÚ P__USART6_CLK_DISABLEÚ P__USART6_FORCE_RESETpÚ P__USART6_RELEASE_RESETÚÚ"P__USART6_CLK_SLEEP_ENABLEÿÚ#P__USART6_CLK_SLEEP_DISABLE°ÚP__SPI4_CLK_ENABLEÚP__SPI4_CLK_DISABLE=ÚP__SPI4_FORCE_RESETÚ P__SPI4_RELEASE_RESETÚ P__SPI4_CLK_SLEEP_ENABLE¨Ú!P__SPI4_CLK_SLEEP_DISABLEYÚP__GPIOI_CLK_ENABLE2Ú P__GPIOI_CLK_DISABLEãÚ P__GPIOI_FORCE_RESET¿Ú P__GPIOI_RELEASE_RESET)Ú!P__GPIOI_CLK_SLEEP_ENABLENÚ"P__GPIOI_CLK_SLEEP_DISABLEÿÚP__GPIOJ_CLK_ENABLE1Ú P__GPIOJ_CLK_DISABLEâÚ P__GPIOJ_FORCE_RESET¾Ú P__GPIOJ_RELEASE_RESET(Ú!P__GPIOJ_CLK_SLEEP_ENABLEMÚ"P__GPIOJ_CLK_SLEEP_DISABLEþÚP__GPIOK_CLK_ENABLE0Ú P__GPIOK_CLK_DISABLEáÚ P__GPIOK_RELEASE_RESET'Ú!P__GPIOK_CLK_SLEEP_ENABLELÚ"P__GPIOK_CLK_SLEEP_DISABLEýÚP__ETH_CLK_ENABLEÍÚP__ETH_CLK_DISABLE~ÚP__DCMI_CLK_ENABLEÚP__DCMI_CLK_DISABLE@ÚP__DCMI_FORCE_RESET Ú P__DCMI_RELEASE_RESETÚ P__DCMI_CLK_SLEEP_ENABLE«Ú!P__DCMI_CLK_SLEEP_DISABLE\ÚP__UART7_CLK_ENABLE7Ú P__UART7_CLK_DISABLEèÚ P__UART7_RELEASE_RESET.Ú P__UART7_FORCE_RESETÄÚ!P__UART7_CLK_SLEEP_ENABLESÚ"P__UART7_CLK_SLEEP_DISABLEÚP__UART8_CLK_ENABLE6Ú P__UART8_CLK_DISABLEçÚ P__UART8_FORCE_RESETÃÚ P__UART8_RELEASE_RESET-Ú!P__UART8_CLK_SLEEP_ENABLERÚ"P__UART8_CLK_SLEEP_DISABLEÚ!P__OTGHS_CLK_SLEEP_ENABLEAÚ"P__OTGHS_CLK_SLEEP_DISABLEòÚ P__OTGHS_FORCE_RESET²Ú P__OTGHS_RELEASE_RESET Ú%P __OTGHSULPI_CLK_SLEEP_ENABLEÿÚ&P __OTGHSULPI_CLK_SLEEP_DISABLE°Ú)P!__HAL_RCC_OTGHS_CLK_SLEEP_ENABLEÆÚ*P"__HAL_RCC_OTGHS_CLK_SLEEP_DISABLEwÚ-P%__HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLEDÚ.P&__HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED0Ú$P __HAL_RCC_OTGHS_FORCE_RESET7Ú&P __HAL_RCC_OTGHS_RELEASE_RESET¡Ú-P%__HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLEÚ.P&__HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE5Ú1P)__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED=Ú2P*__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLEDîÚ!P__SRAM3_CLK_SLEEP_ENABLE`Ú P__CAN2_CLK_SLEEP_ENABLEÄÚ!P__CAN2_CLK_SLEEP_DISABLEuÚ P__DAC_CLK_SLEEP_ENABLEÚ P__DAC_CLK_SLEEP_DISABLE³Ú P__ADC2_CLK_SLEEP_ENABLEÎÚ!P__ADC2_CLK_SLEEP_DISABLEÚ P__ADC3_CLK_SLEEP_ENABLEÍÚ!P__ADC3_CLK_SLEEP_DISABLE~ÚP__FSMC_FORCE_RESETÚ P__FSMC_RELEASE_RESETzÚ P__FSMC_CLK_SLEEP_ENABLEÚ!P__FSMC_CLK_SLEEP_DISABLEPÚP__SDIO_FORCE_RESET
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Ú P__SDIO_RELEASE_RESETtÚ!P__SDIO_CLK_SLEEP_DISABLEJÚ P__SDIO_CLK_SLEEP_ENABLEÚP__DMA2D_CLK_ENABLEbÚ P__DMA2D_CLK_DISABLEÚ P__DMA2D_FORCE_RESETïÚ P__DMA2D_RELEASE_RESETYÚ!P__DMA2D_CLK_SLEEP_ENABLE~Ú"P__DMA2D_CLK_SLEEP_DISABLE/Ú$P __HAL_RCC_OTGFS_FORCE_RESET9Ú&P __HAL_RCC_OTGFS_RELEASE_RESET£ÚP__ADC12_CLK_ENABLEÚ P__ADC12_CLK_DISABLE0ÚP__ADC34_CLK_ENABLE{Ú P__ADC34_CLK_DISABLE,ÚP__DAC2_CLK_ENABLE²ÚP__DAC2_CLK_DISABLEcÚP__TIM18_CLK_ENABLEWÚ P__TIM18_CLK_DISABLEÚP__TIM19_CLK_ENABLEVÚ P__TIM19_CLK_DISABLEÚP__TIM20_CLK_ENABLE^Ú P__TIM20_CLK_DISABLEÚ P__HRTIM1_CLK_ENABLEóÚ P__HRTIM1_CLK_DISABLE¤Ú P__SDADC1_CLK_ENABLEÚ P__SDADC2_CLK_ENABLEÚ P__SDADC3_CLK_ENABLEÚ P__SDADC1_CLK_DISABLEÉÚ P__SDADC2_CLK_DISABLEÈÚ P__SDADC3_CLK_DISABLEÇÚ P__ADC12_FORCE_RESET Ú P__ADC12_RELEASE_RESETvÚ P__ADC34_FORCE_RESETÚ P__ADC34_RELEASE_RESETrÚP__DAC2_FORCE_RESET?Ú P__DAC2_RELEASE_RESET©Ú P__TIM18_FORCE_RESETäÚ P__TIM18_RELEASE_RESETNÚ P__TIM19_FORCE_RESETãÚ P__TIM19_RELEASE_RESETMÚ P__TIM20_FORCE_RESETëÚ P__TIM20_RELEASE_RESETUÚ P__HRTIM1_FORCE_RESETÚ P__HRTIM1_RELEASE_RESETêÚ P__SDADC1_FORCE_RESET¥Ú P__SDADC2_FORCE_RESET¤Ú P__SDADC3_FORCE_RESET£Ú P__SDADC1_RELEASE_RESETÚ P__SDADC2_RELEASE_RESETÚ P__SDADC3_RELEASE_RESET Ú P__ADC1_IS_CLK_ENABLEDlÚ P__ADC1_IS_CLK_DISABLED Ú P__ADC12_IS_CLK_ENABLED8Ú P__ADC12_IS_CLK_DISABLEDéÚ P__ADC34_IS_CLK_ENABLED4Ú P__ADC34_IS_CLK_DISABLEDåÚ P__CEC_IS_CLK_ENABLEDÚ P__CEC_IS_CLK_DISABLEDMÚ P__CRC_IS_CLK_ENABLEDÚ P__CRC_IS_CLK_DISABLED@Ú P__DAC1_IS_CLK_ENABLEDlÚ P__DAC1_IS_CLK_DISABLED Ú P__DAC2_IS_CLK_ENABLEDkÚ P__DAC2_IS_CLK_DISABLED Ú P__DMA1_IS_CLK_ENABLEDbÚ P__DMA1_IS_CLK_DISABLEDÚ P__DMA2_IS_CLK_ENABLEDaÚ P__DMA2_IS_CLK_DISABLEDÚ P__FLITF_IS_CLK_ENABLEDîÚ P__FLITF_IS_CLK_DISABLEDÚ P__FMC_IS_CLK_ENABLEDÚ P__FMC_IS_CLK_DISABLEDBÚ P__GPIOA_IS_CLK_ENABLEDóÚ P__GPIOA_IS_CLK_DISABLED¤Ú P__GPIOB_IS_CLK_ENABLEDòÚ P__GPIOB_IS_CLK_DISABLED£Ú P__GPIOC_IS_CLK_ENABLEDñÚ P__GPIOC_IS_CLK_DISABLED¢Ú P__GPIOD_IS_CLK_ENABLEDðÚ P__GPIOD_IS_CLK_DISABLED¡Ú P__GPIOE_IS_CLK_ENABLEDïÚ P__GPIOE_IS_CLK_DISABLED Ú P__GPIOF_IS_CLK_ENABLEDîÚ P__GPIOF_IS_CLK_DISABLEDÚ P__GPIOG_IS_CLK_ENABLEDíÚ P__GPIOG_IS_CLK_DISABLEDÚ P__GPIOH_IS_CLK_ENABLEDìÚ P__GPIOH_IS_CLK_DISABLEDÚ P__HRTIM1_IS_CLK_ENABLED¬Ú!P__HRTIM1_IS_CLK_DISABLED]Ú P__I2C1_IS_CLK_ENABLEDvÚ P__I2C1_IS_CLK_DISABLED'Ú P__I2C2_IS_CLK_ENABLEDuÚ P__I2C2_IS_CLK_DISABLED&Ú P__I2C3_IS_CLK_ENABLEDtÚ P__I2C3_IS_CLK_DISABLED%Ú P__PWR_IS_CLK_ENABLEDnÚ P__PWR_IS_CLK_DISABLED Ú P__SYSCFG_IS_CLK_ENABLEDÚ!P__SYSCFG_IS_CLK_DISABLEDCÚ P__SPI1_IS_CLK_ENABLEDHÚ P__SPI1_IS_CLK_DISABLEDùÚ P__SPI2_IS_CLK_ENABLEDGÚ P__SPI2_IS_CLK_DISABLEDøÚ P__SPI3_IS_CLK_ENABLEDFÚ P__SPI3_IS_CLK_DISABLED÷Ú P__SPI4_IS_CLK_ENABLEDEÚ P__SPI4_IS_CLK_DISABLEDöÚ P__SDADC1_IS_CLK_ENABLEDÑÚ!P__SDADC1_IS_CLK_DISABLEDÚ P__SDADC2_IS_CLK_ENABLEDÐÚ!P__SDADC2_IS_CLK_DISABLEDÚ P__SDADC3_IS_CLK_ENABLEDÏÚ!P__SDADC3_IS_CLK_DISABLEDÚ P__SRAM_IS_CLK_ENABLED2Ú P__SRAM_IS_CLK_DISABLEDãÚ P__TIM1_IS_CLK_ENABLEDJÚ P__TIM1_IS_CLK_DISABLEDûÚ P__TIM2_IS_CLK_ENABLEDIÚ P__TIM2_IS_CLK_DISABLEDúÚ P__TIM3_IS_CLK_ENABLEDHÚ P__TIM3_IS_CLK_DISABLEDùÚ P__TIM4_IS_CLK_ENABLEDGÚ P__TIM4_IS_CLK_DISABLEDøÚ P__TIM5_IS_CLK_ENABLEDFÚ P__TIM5_IS_CLK_DISABLED÷Ú P__TIM6_IS_CLK_ENABLEDEÚ P__TIM6_IS_CLK_DISABLEDöÚ P__TIM7_IS_CLK_ENABLEDDÚ P__TIM7_IS_CLK_DISABLEDõÚ P__TIM8_IS_CLK_ENABLEDCÚ P__TIM8_IS_CLK_DISABLEDôÚ P__TIM12_IS_CLK_ENABLEDÚ P__TIM12_IS_CLK_DISABLEDÇÚ P__TIM13_IS_CLK_ENABLEDÚ P__TIM13_IS_CLK_DISABLEDÆÚ P__TIM14_IS_CLK_ENABLEDÚ P__TIM14_IS_CLK_DISABLEDÅÚ P__TIM15_IS_CLK_ENABLEDÚ P__TIM15_IS_CLK_DISABLEDÄÚ P__TIM16_IS_CLK_ENABLEDÚ P__TIM16_IS_CLK_DISABLEDÃÚ P__TIM17_IS_CLK_ENABLEDÚ P__TIM17_IS_CLK_DISABLEDÂÚ P__TIM18_IS_CLK_ENABLEDÚ P__TIM18_IS_CLK_DISABLEDÁÚ P__TIM19_IS_CLK_ENABLEDÚ P__TIM19_IS_CLK_DISABLEDÀÚ P__TIM20_IS_CLK_ENABLEDÚ P__TIM20_IS_CLK_DISABLEDÈÚ P__TSC_IS_CLK_ENABLED}Ú P__TSC_IS_CLK_DISABLED.Ú P__UART4_IS_CLK_ENABLEDóÚ P__UART4_IS_CLK_DISABLED¤Ú P__UART5_IS_CLK_ENABLEDòÚ P__UART5_IS_CLK_DISABLED£Ú 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">APB2CLKDivider<ÚRCC_ClkInitTypeDefGÚPRCC_PLLSOURCE_HSIvÚPRCC_PLLSOURCE_HSEzÚ PRCC_OSCILLATORTYPE_NONEÚ PRCC_OSCILLATORTYPE_HSEëÚ PRCC_OSCILLATORTYPE_HSIçÚ PRCC_OSCILLATORTYPE_LSEçÚ PRCC_OSCILLATORTYPE_LSIãÚ PRCC_OSCILLATORTYPE_MSIâÚP RCC_HSE_OFFdÚP RCC_HSE_ON¤ÚPRCC_HSE_BYPASSgÚP RCC_LSE_OFF`ÚP RCC_LSE_ON ÚPRCC_LSE_BYPASScÚP RCC_HSI_OFF`ÚP RCC_HSI_ON ÚP RCC_HSI_DIV4"ÚPRCC_HSI_OUTEN¬Ú#PRCC_HSICALIBRATION_DEFAULTðÚPRCC_MSIRANGE_0ÚPRCC_MSIRANGE_1ÚPRCC_MSIRANGE_2ÚPRCC_MSIRANGE_3ÚPRCC_MSIRANGE_4ÚPRCC_MSIRANGE_5ÚPRCC_MSIRANGE_6ÚP RCC_LSI_OFF\ÚP RCC_LSI_ONÚP RCC_MSI_OFF[ÚP RCC_MSI_ONÚ#PRCC_MSICALIBRATION_DEFAULTëÚP RCC_PLL_NONEÚP RCC_PLL_OFF\ÚP RCC_PLL_ONÚ PRCC_CLOCKTYPE_SYSCLKÚPRCC_CLOCKTYPE_HCLKAÚ PRCC_CLOCKTYPE_PCLK1Ú PRCC_CLOCKTYPE_PCLK2Ú PRCC_SYSCLKSOURCE_MSIzÚ PRCC_SYSCLKSOURCE_HSIÚ PRCC_SYSCLKSOURCE_HSEÚ PRCC_SYSCLKSOURCE_PLLCLKÚ$P RCC_SYSCLKSOURCE_STATUS_MSI)Ú$P RCC_SYSCLKSOURCE_STATUS_HSI.Ú$P RCC_SYSCLKSOURCE_STATUS_HSE2Ú'P RCC_SYSCLKSOURCE_STATUS_PLLCLKJÚPRCC_SYSCLK_DIV1*ÚPRCC_SYSCLK_DIV2)ÚPRCC_SYSCLK_DIV4'ÚPRCC_SYSCLK_DIV8#ÚPRCC_SYSCLK_DIV16òÚPRCC_SYSCLK_DIV64ïÚPRCC_SYSCLK_DIV128¼ÚPRCC_SYSCLK_DIV256ºÚPRCC_SYSCLK_DIV512¿ÚPRCC_HCLK_DIV1åÚPRCC_HCLK_DIV2äÚPRCC_HCLK_DIV4âÚPRCC_HCLK_DIV8ÞÚPRCC_HCLK_DIV16ÚPRCC_RTC_HSE_DIV_2wÚPRCC_RTC_HSE_DIV_4uÚPRCC_RTC_HSE_DIV_8qÚPRCC_RTC_HSE_DIV_16@Ú PRCC_RTCCLKSOURCE_NO_CLKÚ PRCC_RTCCLKSOURCE_LSEÚ PRCC_RTCCLKSOURCE_LSIÚ"PRCC_RTCCLKSOURCE_HSE_DIVXõÚ"PRCC_RTCCLKSOURCE_HSE_DIV2Ú"PRCC_RTCCLKSOURCE_HSE_DIV4Ú"PRCC_RTCCLKSOURCE_HSE_DIV8Ú#PRCC_RTCCLKSOURCE_HSE_DIV16äÚP RCC_PLL_DIV2 ÚP RCC_PLL_DIV3 ÚP RCC_PLL_DIV4 ÚP RCC_PLL_MUL3ÚP RCC_PLL_MUL4ÚP RCC_PLL_MUL6ÚP RCC_PLL_MUL8ÚPRCC_PLL_MUL12âÚPRCC_PLL_MUL16ÞÚPRCC_PLL_MUL24ßÚPRCC_PLL_MUL32àÚPRCC_PLL_MUL48ÙÚP RCC_MCO1tÚP RCC_MCO2sÚP RCC_MCO3rÚP MCO3_GPIO_AF-ÚP RCC_MCODIV_1*ÚP RCC_MCODIV_2)ÚP RCC_MCODIV_4'ÚP RCC_MCODIV_8#ÚPRCC_MCODIV_16òÚ PRCC_MCO1SOURCE_NOCLOCK Ú PRCC_MCO1SOURCE_SYSCLKQÚPRCC_MCO1SOURCE_MSIGÚPRCC_MCO1SOURCE_HSILÚPRCC_MCO1SOURCE_LSELÚPRCC_MCO1SOURCE_LSIHÚPRCC_MCO1SOURCE_HSEPÚ PRCC_MCO1SOURCE_PLLCLKhÚPRCC_IT_LSIRDY§ÚPRCC_IT_LSERDY«ÚPRCC_IT_HSIRDY«ÚPRCC_IT_HSERDY¯ÚPRCC_IT_PLLRDY§ÚPRCC_IT_MSIRDY¦ÚPRCC_IT_LSECSS±ÚP RCC_IT_CSSÚPRCC_FLAG_HSIRDY*ÚPRCC_FLAG_HSIDIV6ÚPRCC_FLAG_MSIRDY%ÚPRCC_FLAG_HSERDY.ÚPRCC_FLAG_PLLRDY&ÚPRCC_FLAG_LSIRDY&ÚPRCC_FLAG_LSERDY*ÚPRCC_FLAG_LSECSS0ÚPRCC_FLAG_OBLRST'ÚPRCC_FLAG_PINRST ÚPRCC_FLAG_PORRSTÚPRCC_FLAG_SFTRSTÚPRCC_FLAG_IWDGRST×ÚPRCC_FLAG_WWDGRSTÉÚPRCC_FLAG_LPWRRST½ÚPRCC_FLAG_FWRSTiÚ"P__HAL_RCC_DMA1_CLK_ENABLE.Ú!P__HAL_RCC_MIF_CLK_ENABLEWÚ!P__HAL_RCC_CRC_CLK_ENABLE[Ú#P__HAL_RCC_DMA1_CLK_DISABLEßÚ"P__HAL_RCC_MIF_CLK_DISABLEÚ"P__HAL_RCC_CRC_CLK_DISABLE Ú#P__HAL_RCC_GPIOA_CLK_ENABLE¿Ú#P__HAL_RCC_GPIOB_CLK_ENABLE¾Ú#P__HAL_RCC_GPIOC_CLK_ENABLE½Ú#P__HAL_RCC_GPIOH_CLK_ENABLE¸Ú$P __HAL_RCC_GPIOA_CLK_DISABLEpÚ$P __HAL_RCC_GPIOB_CLK_DISABLEoÚ$P __HAL_RCC_GPIOC_CLK_DISABLEnÚ$P __HAL_RCC_GPIOH_CLK_DISABLEiÚ"P__HAL_RCC_WWDG_CLK_ENABLEøÚ!P__HAL_RCC_PWR_CLK_ENABLE:Ú#P__HAL_RCC_WWDG_CLK_DISABLE©Ú"P__HAL_RCC_PWR_CLK_DISABLEëÚ$P __HAL_RCC_SYSCFG_CLK_ENABLE^Ú$P __HAL_RCC_DBGMCU_CLK_ENABLE{Ú%P __HAL_RCC_SYSCFG_CLK_DISABLEÚ%P __HAL_RCC_DBGMCU_CLK_DISABLE,Ú&P __HAL_RCC_DMA1_IS_CLK_ENABLEDçÚ%P __HAL_RCC_MIF_IS_CLK_ENABLEDÚ%P __HAL_RCC_CRC_IS_CLK_ENABLEDÚ'P __HAL_RCC_DMA1_IS_CLK_DISABLEDÚ&P __HAL_RCC_MIF_IS_CLK_DISABLEDÁÚ&P __HAL_RCC_CRC_IS_CLK_DISABLEDÅÚ'P __HAL_RCC_GPIOA_IS_CLK_ENABLEDxÚ'P __HAL_RCC_GPIOB_IS_CLK_ENABLEDwÚ'P __HAL_RCC_GPIOC_IS_CLK_ENABLEDvÚ'P __HAL_RCC_GPIOH_IS_CLK_ENABLEDqÚ(P __HAL_RCC_GPIOA_IS_CLK_DISABLED)Ú(P __HAL_RCC_GPIOB_IS_CLK_DISABLED(Ú(P __HAL_RCC_GPIOC_IS_CLK_DISABLED'Ú(P __HAL_RCC_GPIOH_IS_CLK_DISABLED"Ú&P __HAL_RCC_WWDG_IS_CLK_ENABLED±Ú%P __HAL_RCC_PWR_IS_CLK_ENABLEDóÚ'P __HAL_RCC_WWDG_IS_CLK_DISABLEDbÚ&P __HAL_RCC_PWR_IS_CLK_DISABLED¤Ú(P __HAL_RCC_SYSCFG_IS_CLK_ENABLEDÚ(P __HAL_RCC_DBGMCU_IS_CLK_ENABLED4Ú)P!__HAL_RCC_SYSCFG_IS_CLK_DISABLEDÈÚ)P!__HAL_RCC_DBGMCU_IS_CLK_DISABLEDåÚ"P__HAL_RCC_AHB_FORCE_RESETõÚ#P__HAL_RCC_DMA1_FORCE_RESET»Ú"P__HAL_RCC_MIF_FORCE_RESETäÚ"P__HAL_RCC_CRC_FORCE_RESETèÚ$P __HAL_RCC_AHB_RELEASE_RESET_Ú$P __HAL_RCC_CRC_RELEASE_RESETRÚ%P __HAL_RCC_DMA1_RELEASE_RESET%Ú$P __HAL_RCC_MIF_RELEASE_RESETNÚ"P__HAL_RCC_IOP_FORCE_RESETØÚ$P __HAL_RCC_GPIOA_FORCE_RESETLÚ$P __HAL_RCC_GPIOB_FORCE_RESETKÚ$P __HAL_RCC_GPIOC_FORCE_RESETJÚ$P __HAL_RCC_GPIOH_FORCE_RESETEÚ$P __HAL_RCC_IOP_RELEASE_RESETBÚ&P __HAL_RCC_GPIOA_RELEASE_RESET¶Ú&P __HAL_RCC_GPIOB_RELEASE_RESETµÚ&P __HAL_RCC_GPIOC_RELEASE_RESET´Ú&P __HAL_RCC_GPIOH_RELEASE_RESET¯Ú#P__HAL_RCC_APB1_FORCE_RESETºÚ#P__HAL_RCC_WWDG_FORCE_RESET
Ú"P__HAL_RCC_PWR_FORCE_RESETÇÚ%P __HAL_RCC_APB1_RELEASE_RESET$Ú%P __HAL_RCC_WWDG_RELEASE_RESETïÚ$P __HAL_RCC_PWR_RELEASE_RESET1Ú#P__HAL_RCC_APB2_FORCE_RESET¹Ú%P __HAL_RCC_DBGMCU_FORCE_RESETÚ%P __HAL_RCC_SYSCFG_FORCE_RESETëÚ%P __HAL_RCC_APB2_RELEASE_RESET#Ú'P __HAL_RCC_DBGMCU_RELEASE_RESETrÚ'P __HAL_RCC_SYSCFG_RELEASE_RESETUÚ'P __HAL_RCC_CRC_CLK_SLEEP_ENABLEwÚ'P __HAL_RCC_MIF_CLK_SLEEP_ENABLEsÚ(P __HAL_RCC_SRAM_CLK_SLEEP_ENABLEÚ(P __HAL_RCC_DMA1_CLK_SLEEP_ENABLEJÚ(P __HAL_RCC_CRC_CLK_SLEEP_DISABLE(Ú(P __HAL_RCC_MIF_CLK_SLEEP_DISABLE$Ú)P!__HAL_RCC_SRAM_CLK_SLEEP_DISABLEËÚ)P!__HAL_RCC_DMA1_CLK_SLEEP_DISABLEûÚ)P!__HAL_RCC_GPIOA_CLK_SLEEP_ENABLEÛÚ)P!__HAL_RCC_GPIOB_CLK_SLEEP_ENABLEÚÚ)P!__HAL_RCC_GPIOC_CLK_SLEEP_ENABLEÙÚ)P!__HAL_RCC_GPIOH_CLK_SLEEP_ENABLEÔÚ*P"__HAL_RCC_GPIOA_CLK_SLEEP_DISABLEÚ*P"__HAL_RCC_GPIOB_CLK_SLEEP_DISABLEÚ*P"__HAL_RCC_GPIOC_CLK_SLEEP_DISABLEÚ*P"__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Ú(P __HAL_RCC_WWDG_CLK_SLEEP_ENABLEÚ'P __HAL_RCC_PWR_CLK_SLEEP_ENABLEVÚ)P!__HAL_RCC_WWDG_CLK_SLEEP_DISABLEÅÚ(P __HAL_RCC_PWR_CLK_SLEEP_DISABLEÚ*P"__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLEzÚ*P"__HAL_RCC_DBGMCU_CLK_SLEEP_ENABLEÚ+P#__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE+Ú+P#__HAL_RCC_DBGMCU_CLK_SLEEP_DISABLEHÚ+P#__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED0Ú+P#__HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED,Ú,P$__HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLEDÓÚ,P$__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLEDÚ,P$__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLEDáÚ,P$__HAL_RCC_MIF_IS_CLK_SLEEP_DISABLEDÝÚ-P%__HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLEDÚ-P%__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED´Ú-P%__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLEDÚ-P%__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLEDÚ-P%__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLEDÚ-P%__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLEDÚ.P&__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLEDEÚ.P&__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLEDDÚ.P&__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLEDCÚ.P&__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED>Ú,P$__HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLEDÍÚ+P#__HAL_RCC_PWR_IS_CLK_SLEEP_ENABLEDÚ-P%__HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED~Ú,P$__HAL_RCC_PWR_IS_CLK_SLEEP_DISABLEDÀÚ.P&__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED3Ú.P&__HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLEDPÚ/P'__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLEDäÚ/P'__HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLEDÚ P__HAL_RCC_HSI_CONFIGÚ P__HAL_RCC_HSI_ENABLEÚ P__HAL_RCC_HSI_DISABLEAÚ.P&__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUSTFÚ P__HAL_RCC_LSI_ENABLEÚ P__HAL_RCC_LSI_DISABLE=Ú P__HAL_RCC_HSE_CONFIG
Ú P__HAL_RCC_LSE_CONFIGÚ P__HAL_RCC_MSI_ENABLEÚ P__HAL_RCC_MSI_DISABLE<Ú.P&__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUSTAÚ#P__HAL_RCC_MSI_RANGE_CONFIG¤Ú P__HAL_RCC_GET_MSI_RANGEÚ P__HAL_RCC_PLL_ENABLEÚ P__HAL_RCC_PLL_DISABLE=Ú P__HAL_RCC_PLL_CONFIG}Ú$P __HAL_RCC_GET_PLL_OSCSOURCE0Ú P__HAL_RCC_SYSCLK_CONFIGÚ$P __HAL_RCC_GET_SYSCLK_SOURCE$Ú P__HAL_RCC_MCO1_CONFIGSÚ#P__HAL_RCC_RTC_CLKPRESCALER«Ú P__HAL_RCC_RTC_CONFIG|Ú!P__HAL_RCC_GET_RTC_SOURCEÚ(P __HAL_RCC_GET_RTC_HSE_PRESCALERýÚ P__HAL_RCC_RTC_ENABLEÚ P__HAL_RCC_RTC_DISABLE<Ú$P __HAL_RCC_BACKUPRESET_FORCEeÚ&P __HAL_RCC_BACKUPRESET_RELEASEÏÚ P__HAL_RCC_ENABLE_ITÙÚ P__HAL_RCC_DISABLE_ITÚP__HAL_RCC_CLEAR_ITÚP__HAL_RCC_GET_IT¦Ú$P __HAL_RCC_CLEAR_RESET_FLAGSWÚP__HAL_RCC_GET_FLAG%Ú!P__STM32L0xx_HAL_RCC_EX_H
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ÚPIS_RCC_PERIPHCLOCKAÚ PIS_RCC_USART1CLKSOURCEÚ PIS_RCC_USART2CLKSOURCEÚ PIS_RCC_LPUART1CLKSOURCE·Ú PIS_RCC_I2C1CLKSOURCE×Ú PIS_RCC_I2C3CLKSOURCEÕÚPIS_RCC_LPTIMCLKÚ PIS_RCC_STOPWAKEUP_CLOCKÚPIS_RCC_LSE_DRIVE¼Ú8
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<unnamed>QÚ
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"·@PeriphClockSelection°Ú
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"·@RTCClockSelection5Ú
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"·@Usart1ClockSelectionØÚ
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"·@Usart2ClockSelection×Ú
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"·@Lpuart1ClockSelectionmÚ
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"·@I2c1ClockSelection Ú
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"·@I2c3ClockSelection Ú
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"·@LptimClockSelectionÚ!RCC_PeriphCLKInitTypeDefÚ PRCC_EXTI_LINE_LSECSSÚ PRCC_PERIPHCLK_USART1«Ú PRCC_PERIPHCLK_USART2ªÚ PRCC_PERIPHCLK_LPUART1`ÚPRCC_PERIPHCLK_I2C1ÚPRCC_PERIPHCLK_I2C2ÚPRCC_PERIPHCLK_RTCÚ PRCC_PERIPHCLK_LPTIM1´ÚPRCC_PERIPHCLK_I2C3~Ú"PRCC_USART1CLKSOURCE_PCLK2<Ú#PRCC_USART1CLKSOURCE_SYSCLK½Ú PRCC_USART1CLKSOURCE_HSI¸Ú PRCC_USART1CLKSOURCE_LSE¸Ú"PRCC_USART2CLKSOURCE_PCLK1<Ú#PRCC_USART2CLKSOURCE_SYSCLK¼Ú PRCC_USART2CLKSOURCE_HSI·Ú PRCC_USART2CLKSOURCE_LSE·Ú#PRCC_LPUART1CLKSOURCE_PCLK1òÚ$P RCC_LPUART1CLKSOURCE_SYSCLKrÚ!PRCC_LPUART1CLKSOURCE_HSImÚ!PRCC_LPUART1CLKSOURCE_LSEmÚ PRCC_I2C1CLKSOURCE_PCLK1Ú!PRCC_I2C1CLKSOURCE_SYSCLKÚ PRCC_I2C1CLKSOURCE_HSIÚ PRCC_I2C3CLKSOURCE_PCLK1Ú!PRCC_I2C3CLKSOURCE_SYSCLKÚ PRCC_I2C3CLKSOURCE_HSIÚ!PRCC_TIMPRES_DESACTIVATEDpÚ PRCC_TIMPRES_ACTIVATEDRÚ"PRCC_LPTIM1CLKSOURCE_PCLK1FÚ PRCC_LPTIM1CLKSOURCE_LSI½Ú PRCC_LPTIM1CLKSOURCE_HSIÁÚ PRCC_LPTIM1CLKSOURCE_LSEÁÚ!PRCC_STOP_WAKEUPCLOCK_MSI>Ú!PRCC_STOP_WAKEUPCLOCK_HSICÚPRCC_LSEDRIVE_LOWÅÚ PRCC_LSEDRIVE_MEDIUMLOWøÚ PRCC_LSEDRIVE_MEDIUMHIGHÈÚPRCC_LSEDRIVE_HIGHÚ#P__HAL_RCC_GPIOE_CLK_ENABLE»Ú$P __HAL_RCC_GPIOE_CLK_DISABLElÚ'P __HAL_RCC_GPIOE_IS_CLK_ENABLEDtÚ(P __HAL_RCC_GPIOE_IS_CLK_DISABLED%Ú#P__HAL_RCC_GPIOD_CLK_ENABLE¼Ú$P __HAL_RCC_GPIOD_CLK_DISABLEmÚ'P __HAL_RCC_GPIOD_IS_CLK_ENABLEDuÚ(P __HAL_RCC_GPIOD_IS_CLK_DISABLED&Ú"P__HAL_RCC_TIM2_CLK_ENABLEÚ"P__HAL_RCC_TIM3_CLK_ENABLEÚ"P__HAL_RCC_TIM6_CLK_ENABLEÚ"P__HAL_RCC_TIM7_CLK_ENABLEÚ"P__HAL_RCC_SPI2_CLK_ENABLEÚ$P __HAL_RCC_USART2_CLK_ENABLElÚ$P __HAL_RCC_USART4_CLK_ENABLEjÚ$P __HAL_RCC_USART5_CLK_ENABLEiÚ%P __HAL_RCC_LPUART1_CLK_ENABLE"Ú"P__HAL_RCC_I2C1_CLK_ENABLEBÚ"P__HAL_RCC_I2C2_CLK_ENABLEAÚ"P__HAL_RCC_I2C3_CLK_ENABLE@Ú!P__HAL_RCC_DAC_CLK_ENABLEkÚ$P __HAL_RCC_LPTIM1_CLK_ENABLEvÚ#P__HAL_RCC_TIM2_CLK_DISABLEÆÚ#P__HAL_RCC_TIM3_CLK_DISABLEÅÚ#P__HAL_RCC_TIM6_CLK_DISABLEÂÚ#P__HAL_RCC_TIM7_CLK_DISABLEÁÚ#P__HAL_RCC_SPI2_CLK_DISABLEÄÚ%P __HAL_RCC_USART2_CLK_DISABLE Ú%P __HAL_RCC_USART4_CLK_DISABLEÚ%P __HAL_RCC_USART5_CLK_DISABLEÚ&P __HAL_RCC_LPUART1_CLK_DISABLEÓÚ#P__HAL_RCC_I2C1_CLK_DISABLEóÚ#P__HAL_RCC_I2C2_CLK_DISABLEòÚ#P__HAL_RCC_I2C3_CLK_DISABLEñÚ"P__HAL_RCC_DAC_CLK_DISABLE Ú%P __HAL_RCC_LPTIM1_CLK_DISABLE'Ú&P __HAL_RCC_TIM2_IS_CLK_ENABLEDÎÚ&P __HAL_RCC_TIM3_IS_CLK_ENABLEDÍÚ&P __HAL_RCC_TIM6_IS_CLK_ENABLEDÊÚ&P __HAL_RCC_TIM7_IS_CLK_ENABLEDÉÚ&P __HAL_RCC_SPI2_IS_CLK_ENABLEDÌÚ(P __HAL_RCC_USART2_IS_CLK_ENABLED%Ú(P __HAL_RCC_USART4_IS_CLK_ENABLED#Ú(P __HAL_RCC_USART5_IS_CLK_ENABLED"Ú)P!__HAL_RCC_LPUART1_IS_CLK_ENABLEDÛÚ&P __HAL_RCC_I2C1_IS_CLK_ENABLEDûÚ&P __HAL_RCC_I2C2_IS_CLK_ENABLEDúÚ&P __HAL_RCC_I2C3_IS_CLK_ENABLEDùÚ%P __HAL_RCC_DAC_IS_CLK_ENABLED$Ú(P __HAL_RCC_LPTIM1_IS_CLK_ENABLED/Ú'P __HAL_RCC_TIM2_IS_CLK_DISABLEDÚ'P __HAL_RCC_TIM3_IS_CLK_DISABLED~Ú'P __HAL_RCC_TIM6_IS_CLK_DISABLED{Ú'P __HAL_RCC_TIM7_IS_CLK_DISABLEDzÚ'P __HAL_RCC_SPI2_IS_CLK_DISABLED}Ú)P!__HAL_RCC_USART2_IS_CLK_DISABLEDÖÚ)P!__HAL_RCC_USART4_IS_CLK_DISABLEDÔÚ)P!__HAL_RCC_USART5_IS_CLK_DISABLEDÓÚ*P"__HAL_RCC_LPUART1_IS_CLK_DISABLEDÚ'P __HAL_RCC_I2C1_IS_CLK_DISABLED¬Ú'P __HAL_RCC_I2C2_IS_CLK_DISABLED«Ú'P __HAL_RCC_I2C3_IS_CLK_DISABLEDªÚ&P __HAL_RCC_DAC_IS_CLK_DISABLEDÕÚ)P!__HAL_RCC_LPTIM1_IS_CLK_DISABLEDàÚ#P__HAL_RCC_TIM21_CLK_ENABLEâÚ#P__HAL_RCC_TIM22_CLK_ENABLEáÚ"P__HAL_RCC_ADC1_CLK_ENABLE8Ú"P__HAL_RCC_SPI1_CLK_ENABLEÚ$P __HAL_RCC_USART1_CLK_ENABLEmÚ$P __HAL_RCC_TIM21_CLK_DISABLEÚ$P __HAL_RCC_TIM22_CLK_DISABLEÚ#P__HAL_RCC_ADC1_CLK_DISABLEéÚ#P__HAL_RCC_SPI1_CLK_DISABLEÅÚ%P __HAL_RCC_USART1_CLK_DISABLE Ú&P __HAL_RCC_FIREWALL_CLK_ENABLEÓÚ'P __HAL_RCC_FIREWALL_CLK_DISABLEÚ'P __HAL_RCC_TIM21_IS_CLK_ENABLEDÚ'P __HAL_RCC_TIM22_IS_CLK_ENABLEDÚ&P __HAL_RCC_ADC1_IS_CLK_ENABLEDñÚ&P __HAL_RCC_SPI1_IS_CLK_ENABLEDÍÚ(P __HAL_RCC_USART1_IS_CLK_ENABLED&Ú(P __HAL_RCC_TIM21_IS_CLK_DISABLEDLÚ(P __HAL_RCC_TIM22_IS_CLK_DISABLEDKÚ'P __HAL_RCC_ADC1_IS_CLK_DISABLED¢Ú'P __HAL_RCC_SPI1_IS_CLK_DISABLED~Ú)P!__HAL_RCC_USART1_IS_CLK_DISABLED×Ú*P"__HAL_RCC_FIREWALL_IS_CLK_ENABLEDÚ+P#__HAL_RCC_FIREWALL_IS_CLK_DISABLED=Ú$P __HAL_RCC_GPIOE_FORCE_RESETHÚ&P __HAL_RCC_GPIOE_RELEASE_RESET²Ú$P __HAL_RCC_GPIOD_FORCE_RESETIÚ&P __HAL_RCC_GPIOD_RELEASE_RESET³Ú#P__HAL_RCC_TIM2_FORCE_RESET¢Ú#P__HAL_RCC_TIM3_FORCE_RESET¡Ú#P__HAL_RCC_TIM6_FORCE_RESETÚ#P__HAL_RCC_TIM7_FORCE_RESETÚ%P __HAL_RCC_LPTIM1_FORCE_RESETÚ#P__HAL_RCC_I2C1_FORCE_RESETÏÚ#P__HAL_RCC_I2C2_FORCE_RESETÎÚ#P__HAL_RCC_I2C3_FORCE_RESETÍÚ%P __HAL_RCC_USART2_FORCE_RESETùÚ%P __HAL_RCC_USART4_FORCE_RESET÷Ú%P __HAL_RCC_USART5_FORCE_RESETöÚ&P __HAL_RCC_LPUART1_FORCE_RESET¯Ú#P__HAL_RCC_SPI2_FORCE_RESET Ú"P__HAL_RCC_DAC_FORCE_RESETøÚ%P __HAL_RCC_TIM2_RELEASE_RESET Ú%P __HAL_RCC_TIM3_RELEASE_RESET Ú%P __HAL_RCC_TIM6_RELEASE_RESETÚ%P __HAL_RCC_TIM7_RELEASE_RESETÚ'P __HAL_RCC_LPTIM1_RELEASE_RESETmÚ%P __HAL_RCC_I2C1_RELEASE_RESET9Ú%P __HAL_RCC_I2C2_RELEASE_RESET8Ú%P __HAL_RCC_I2C3_RELEASE_RESET7Ú'P __HAL_RCC_USART2_RELEASE_RESETcÚ'P __HAL_RCC_USART4_RELEASE_RESETaÚ'P __HAL_RCC_USART5_RELEASE_RESET`Ú(P __HAL_RCC_LPUART1_RELEASE_RESETÚ%P __HAL_RCC_SPI2_RELEASE_RESET
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Ú$P __HAL_RCC_DAC_RELEASE_RESETbÚ%P __HAL_RCC_USART1_FORCE_RESETúÚ#P__HAL_RCC_ADC1_FORCE_RESETÅÚ#P__HAL_RCC_SPI1_FORCE_RESET¡Ú$P __HAL_RCC_TIM21_FORCE_RESEToÚ$P __HAL_RCC_TIM22_FORCE_RESETnÚ'P __HAL_RCC_USART1_RELEASE_RESETdÚ%P __HAL_RCC_ADC1_RELEASE_RESET/Ú%P __HAL_RCC_SPI1_RELEASE_RESET Ú&P __HAL_RCC_TIM21_RELEASE_RESETÙÚ&P __HAL_RCC_TIM22_RELEASE_RESETØÚ)P!__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE×Ú*P"__HAL_RCC_GPIOE_CLK_SLEEP_DISABLEÚ-P%__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLEDÚ.P&__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLEDAÚ)P!__HAL_RCC_GPIOD_CLK_SLEEP_ENABLEØÚ*P"__HAL_RCC_GPIOD_CLK_SLEEP_DISABLEÚ-P%__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLEDÚ.P&__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLEDBÚ(P __HAL_RCC_TIM2_CLK_SLEEP_ENABLE1Ú(P __HAL_RCC_TIM3_CLK_SLEEP_ENABLE0Ú(P __HAL_RCC_TIM6_CLK_SLEEP_ENABLE-Ú(P __HAL_RCC_TIM7_CLK_SLEEP_ENABLE,Ú(P __HAL_RCC_SPI2_CLK_SLEEP_ENABLE/Ú*P"__HAL_RCC_USART2_CLK_SLEEP_ENABLEÚ*P"__HAL_RCC_USART4_CLK_SLEEP_ENABLEÚ*P"__HAL_RCC_USART5_CLK_SLEEP_ENABLE
Ú+P#__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE>Ú(P __HAL_RCC_I2C1_CLK_SLEEP_ENABLE^Ú(P __HAL_RCC_I2C2_CLK_SLEEP_ENABLE]Ú(P __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\Ú'P __HAL_RCC_DAC_CLK_SLEEP_ENABLEÚ*P"__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLEÚ)P!__HAL_RCC_TIM2_CLK_SLEEP_DISABLEâÚ)P!__HAL_RCC_TIM3_CLK_SLEEP_DISABLEáÚ)P!__HAL_RCC_TIM6_CLK_SLEEP_DISABLEÞÚ)P!__HAL_RCC_TIM7_CLK_SLEEP_DISABLEÝÚ)P!__HAL_RCC_SPI2_CLK_SLEEP_DISABLEàÚ+P#__HAL_RCC_USART2_CLK_SLEEP_DISABLE9Ú+P#__HAL_RCC_USART4_CLK_SLEEP_DISABLE7Ú+P#__HAL_RCC_USART5_CLK_SLEEP_DISABLE6Ú,P$__HAL_RCC_LPUART1_CLK_SLEEP_DISABLEïÚ)P!__HAL_RCC_I2C1_CLK_SLEEP_DISABLEÚ)P!__HAL_RCC_I2C2_CLK_SLEEP_DISABLEÚ)P!__HAL_RCC_I2C3_CLK_SLEEP_DISABLE Ú(P __HAL_RCC_DAC_CLK_SLEEP_DISABLE8Ú+P#__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLECÚ,P$__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLEDêÚ,P$__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLEDéÚ,P$__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLEDæÚ,P$__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLEDåÚ,P$__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLEDèÚ.P&__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLEDAÚ.P&__HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED?Ú.P&__HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED>Ú/P'__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED÷Ú,P$__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLEDÚ,P$__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLEDÚ,P$__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLEDÚ+P#__HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED@Ú.P&__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLEDKÚ-P%__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLEDÚ-P%__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLEDÚ-P%__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLEDÚ-P%__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLEDÚ-P%__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLEDÚ/P'__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLEDòÚ/P'__HAL_RCC_USART4_IS_CLK_SLEEP_DISABLEDðÚ/P'__HAL_RCC_USART5_IS_CLK_SLEEP_DISABLEDïÚ0P(__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED¨Ú-P%__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLEDÈÚ-P%__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLEDÇÚ-P%__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLEDÆÚ,P$__HAL_RCC_DAC_IS_CLK_SLEEP_DISABLEDñÚ/P'__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLEDüÚ)P!__HAL_RCC_TIM21_CLK_SLEEP_ENABLEþÚ)P!__HAL_RCC_TIM22_CLK_SLEEP_ENABLEýÚ(P __HAL_RCC_ADC1_CLK_SLEEP_ENABLETÚ(P __HAL_RCC_SPI1_CLK_SLEEP_ENABLE0Ú*P"__HAL_RCC_USART1_CLK_SLEEP_ENABLEÚ*P"__HAL_RCC_TIM21_CLK_SLEEP_DISABLE¯Ú*P"__HAL_RCC_TIM22_CLK_SLEEP_DISABLE®Ú)P!__HAL_RCC_ADC1_CLK_SLEEP_DISABLEÚ)P!__HAL_RCC_SPI1_CLK_SLEEP_DISABLEáÚ+P#__HAL_RCC_USART1_CLK_SLEEP_DISABLE:Ú-P%__HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED·Ú-P%__HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED¶Ú,P$__HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED Ú,P$__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLEDéÚ.P&__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLEDBÚ.P&__HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLEDhÚ.P&__HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLEDgÚ-P%__HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED¾Ú-P%__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLEDÚ/P'__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLEDóÚ(P __HAL_RCC_LSECSS_EXTI_ENABLE_ITüÚ)P!__HAL_RCC_LSECSS_EXTI_DISABLE_ITÚ+P#__HAL_RCC_LSECSS_EXTI_ENABLE_EVENTÚ,P$__HAL_RCC_LSECSS_EXTI_DISABLE_EVENTÂÚ2P*__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGEÚ3P+__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGEÅÚ1P)__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGEGÚ2P*__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGEøÚ9P1__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGEÛÚ:P2__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGEÚ'P __HAL_RCC_LSECSS_EXTI_GET_FLAGHÚ)P!__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG½Ú,P$__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT¦Ú P__HAL_RCC_I2C1_CONFIGtÚ"P__HAL_RCC_GET_I2C1_SOURCEÚ P__HAL_RCC_I2C3_CONFIGrÚ"P__HAL_RCC_GET_I2C3_SOURCEÚ P__HAL_RCC_USART1_CONFIGÚ$P __HAL_RCC_GET_USART1_SOURCE=Ú P__HAL_RCC_USART2_CONFIGÚ$P __HAL_RCC_GET_USART2_SOURCE<Ú!P__HAL_RCC_LPUART1_CONFIGTÚ%P __HAL_RCC_GET_LPUART1_SOURCEòÚ P__HAL_RCC_LPTIM1_CONFIG¨Ú$P __HAL_RCC_GET_LPTIM1_SOURCEFÚ!P__HAL_RCC_HSISTOP_ENABLEBÚ"P__HAL_RCC_HSISTOP_DISABLEóÚ"P__HAL_RCC_LSEDRIVE_CONFIGýÚ(P __HAL_RCC_WAKEUPSTOP_CLK_CONFIGÚ!P__HAL_RCC_HSI_OUT_ENABLE1Ú"P__HAL_RCC_HSI_OUT_DISABLEâÚ,PeriphClkInit¡Ú" HAL_RCCEx_PeriphCLKConfigöÚ,PeriphClkInit¡Ú% HAL_RCCEx_GetPeriphCLKConfigÐÚ,
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PeriphClkKÚ# HAL_RCCEx_GetPeriphCLKFreqÚ HAL_RCCEx_EnableLSECSSÚ HAL_RCCEx_DisableLSECSSÚ" HAL_RCCEx_EnableLSECSS_IT~Ú$ HAL_RCCEx_LSECSS_IRQHandler´Ú" HAL_RCCEx_LSECSS_CallbackUÚ HAL_RCC_DeInit$Ú,RCC_OscInitStruct:Ú HAL_RCC_OscConfigàÚ,RCC_ClkInitStructEÚ,
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FLatency¹Ú HAL_RCC_ClockConfigÚ,
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RCC_MCOxAÚ,
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RCC_MCOSource>Ú,
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RCC_MCODivÚ HAL_RCC_MCOConfig&Ú HAL_RCC_EnableCSS+Ú HAL_RCC_NMI_IRQHandlerdÚ HAL_RCC_CSSCallbackaÚ HAL_RCC_GetSysClockFreqvÚ HAL_RCC_GetHCLKFreqÚ HAL_RCC_GetPCLK1FreqLÚ HAL_RCC_GetPCLK2FreqKÚ,RCC_OscInitStruct:Ú HAL_RCC_GetOscConfigºÚ,RCC_ClkInitStructEÚ,
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pFLatency9Ú HAL_RCC_GetClockConfigïÚ P__STM32L0xx_HAL_EXTI_H¨Ú HAL_EXTI_COMMON_CB_IDmÚ HAL_EXTI_RISING_CB_IDjÚ HAL_EXTI_FALLING_CB_ID7Ú EXTI_CallbackIDTypeDefñÚ8
|
<unnamed>QÚ
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"CLinesÚ "CPendingCallbackÚEXTI_HandleTypeDefGÚ8
|
<unnamed>QÚ
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"CLineoÚ
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"CModerÚ
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"CTrigger Ú
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"CGPIOSelÚEXTI_ConfigTypeDef=ÚP EXTI_LINE_0eÚP EXTI_LINE_1dÚP EXTI_LINE_2cÚP EXTI_LINE_3bÚP EXTI_LINE_4aÚP EXTI_LINE_5`ÚP EXTI_LINE_6_ÚP EXTI_LINE_7^ÚP EXTI_LINE_8]ÚP EXTI_LINE_9\ÚP EXTI_LINE_102ÚP EXTI_LINE_111ÚP EXTI_LINE_120ÚP EXTI_LINE_13/ÚP EXTI_LINE_14.ÚP EXTI_LINE_15-ÚP EXTI_LINE_16,ÚP EXTI_LINE_17+ÚP EXTI_LINE_18*ÚP EXTI_LINE_19)ÚP EXTI_LINE_201ÚP EXTI_LINE_210ÚP EXTI_LINE_22/ÚP EXTI_LINE_23.ÚP EXTI_LINE_24-ÚP EXTI_LINE_25,ÚP EXTI_LINE_26+ÚP EXTI_LINE_27*ÚP EXTI_LINE_28)ÚP EXTI_LINE_29(ÚPEXTI_MODE_NONEbÚ PEXTI_MODE_INTERRUPT»ÚPEXTI_MODE_EVENTÚPEXTI_TRIGGER_NONEmÚ PEXTI_TRIGGER_RISINGÍÚ PEXTI_TRIGGER_FALLINGÚ$P EXTI_TRIGGER_RISING_FALLINGaÚP EXTI_GPIOA®ÚP EXTI_GPIOBÚP EXTI_GPIOC¬ÚP EXTI_GPIOD«ÚP EXTI_GPIOEªÚP EXTI_GPIOH§Ú PEXTI_PROPERTY_SHIFTªÚP EXTI_DIRECTaÚP EXTI_CONFIGfÚP
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EXTI_GPIOñÚPEXTI_RESERVED¸ÚPEXTI_PROPERTY_MASKþÚPEXTI_PIN_MASK¦ÚPEXTI_MODE_MASKfÚPEXTI_TRIGGER_MASKqÚP EXTI_LINE_NBÚP IS_EXTI_LINE÷ÚP IS_EXTI_MODEúÚPIS_EXTI_TRIGGERÚ PIS_EXTI_PENDING_EDGEÚ PIS_EXTI_CONFIG_LINEÔÚPIS_EXTI_GPIO_PORTBÚPIS_EXTI_GPIO_PIN¢Ú,hexti¥Ú, pExtiConfig[Ú HAL_EXTI_SetConfigLineåÚ,hexti¥Ú, pExtiConfig[Ú HAL_EXTI_GetConfigLineñÚ,hexti¥Ú! HAL_EXTI_ClearConfigLine&Ú,hexti¥Ú," CallbackID Ú, pPendingCbfn Ú" HAL_EXTI_RegisterCallbackÚ,hexti¥Ú,
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ExtiLineÚ HAL_EXTI_GetHandleÚ,hexti¥Ú HAL_EXTI_IRQHandlerKÚ,hexti¥Ú ,
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EdgebÚ HAL_EXTI_GetPendingÚ,hexti¥Ú ,
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EdgebÚ HAL_EXTI_ClearPendingEÚ,hexti¥Ú HAL_EXTI_GenerateSWIÕÚ P__STM32L0xx_HAL_GPIO_H³Ú8
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<unnamed>QÚ
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"ãCPinvÚ
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"ãCModeÚ
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"ãCPullþÚ
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"ãCSpeed¨Ú
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"ãC
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AlternateñÚGPIO_InitTypeDefÚ GPIO_PIN_RESETÚ GPIO_PIN_SET%ÚGPIO_PinState1ÚPIS_GPIO_PIN_ACTIONÚP GPIO_PIN_0³ÚP GPIO_PIN_1²ÚP GPIO_PIN_2±ÚP GPIO_PIN_3°ÚP GPIO_PIN_4¯ÚP GPIO_PIN_5®ÚP GPIO_PIN_6ÚP GPIO_PIN_7¬ÚP GPIO_PIN_8«ÚP GPIO_PIN_9ªÚP GPIO_PIN_10ÚP GPIO_PIN_11ÚP GPIO_PIN_12~ÚP GPIO_PIN_13}ÚP GPIO_PIN_14|ÚP GPIO_PIN_15{ÚP GPIO_PIN_AllÆÚPGPIO_PIN_MASK±ÚP IS_GPIO_PINEÚPGPIO_MODE_INPUT Ú PGPIO_MODE_OUTPUT_PP£Ú PGPIO_MODE_OUTPUT_OD°ÚPGPIO_MODE_AF_PPÚPGPIO_MODE_AF_OD"ÚPGPIO_MODE_ANALOGçÚ PGPIO_MODE_IT_RISINGËÚ PGPIO_MODE_IT_FALLINGÚ$P GPIO_MODE_IT_RISING_FALLING_Ú PGPIO_MODE_EVT_RISINGwÚ PGPIO_MODE_EVT_FALLINGDÚ%P GPIO_MODE_EVT_RISING_FALLING ÚP IS_GPIO_MODEÚ PGPIO_SPEED_FREQ_LOWÈÚ PGPIO_SPEED_FREQ_MEDIUMóÚ PGPIO_SPEED_FREQ_HIGHÚ"PGPIO_SPEED_FREQ_VERY_HIGHéÚPIS_GPIO_SPEED·ÚP GPIO_NOPULLMÚP GPIO_PULLUPEÚPGPIO_PULLDOWN®ÚP IS_GPIO_PULLíÚ!P__HAL_GPIO_EXTI_GET_FLAG)Ú#P__HAL_GPIO_EXTI_CLEAR_FLAGÚ P__HAL_GPIO_EXTI_GET_ITªÚ!P__HAL_GPIO_EXTI_CLEAR_IT Ú&P __HAL_GPIO_EXTI_GENERATE_SWITÚ"P__STM32L0xx_HAL_GPIO_EX_H±ÚPGPIO_AF0_EVENTOUTÚPGPIO_AF0_TIM21¾ÚPGPIO_AF0_SPI1ðÚP GPIO_AF0_MCO0ÚPGPIO_AF0_SWDIO
ÚPGPIO_AF0_SWCLKÚPGPIO_AF0_USART1IÚPGPIO_AF0_SPI2ïÚPGPIO_AF0_LPTIM1RÚPGPIO_AF0_TIM22½ÚPGPIO_AF0_LPUART1þÚPGPIO_AF0_USART2HÚPGPIO_AF0_TIM2ñÚPGPIO_AF1_I2C1 ÚPGPIO_AF1_SPI2îÚPGPIO_AF1_TIM21½ÚPGPIO_AF2_TIM2ïÚPGPIO_AF2_TIM3îÚPGPIO_AF2_EVENTOUTÚPGPIO_AF2_LPTIM1PÚPGPIO_AF2_LPUART1üÚP GPIO_AF2_MCO.ÚP GPIO_AF2_RTC$ÚPGPIO_AF2_SPI2íÚPGPIO_AF2_USART5CÚPGPIO_AF2_SPI1îÚPGPIO_AF3_EVENTOUTÚPGPIO_AF3_I2C1ÚPGPIO_AF4_USART2DÚPGPIO_AF4_LPUART1úÚPGPIO_AF4_USART1EÚPGPIO_AF4_EVENTOUTÚPGPIO_AF4_TIM22¹ÚPGPIO_AF4_TIM3ìÚPGPIO_AF4_I2C1ÚPGPIO_AF5_TIM2ìÚPGPIO_AF5_TIM21¹ÚPGPIO_AF5_TIM22¸ÚPGPIO_AF5_USART1DÚPGPIO_AF5_SPI2êÚPGPIO_AF5_I2C2ÚPGPIO_AF6_USART4@ÚPGPIO_AF6_LPUART1øÚPGPIO_AF6_EVENTOUT
ÚPGPIO_AF6_I2C1ÚPGPIO_AF6_I2C2ÚPGPIO_AF6_USART5?ÚPGPIO_AF6_TIM21¸ÚPGPIO_AF7_COMP1¤ÚPGPIO_AF7_COMP2£ÚPGPIO_AF7_I2C3ÚPGPIO_AF7_LPUART1÷ÚP IS_GPIO_AF§Ú PGPIOA_PIN_AVAILABLEÚ PGPIOB_PIN_AVAILABLEÚ PGPIOC_PIN_AVAILABLE Ú PGPIOD_PIN_AVAILABLE Ú PGPIOE_PIN_AVAILABLE Ú PGPIOH_PIN_AVAILABLEÚPGPIO_GET_INDEXjÚ PIS_GPIO_PIN_AVAILABLEQÚ,GPIOx Ú,
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GPIO_InitÚ HAL_GPIO_InitxÚ,GPIOx Ú,
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GPIO_PinÚ HAL_GPIO_DeInitËÚ,GPIOx Ú, GPIO_PinÚ HAL_GPIO_ReadPincÚ,GPIOx Ú, GPIO_PinÚ," PinStateÚ HAL_GPIO_WritePinÒÚ,GPIOx Ú, GPIO_PinÚ HAL_GPIO_TogglePinyÚ,GPIOx Ú, GPIO_PinÚ HAL_GPIO_LockPinVÚ, GPIO_PinÚ! HAL_GPIO_EXTI_IRQHandler³Ú, GPIO_PinÚ HAL_GPIO_EXTI_CallbackTÚPGPIO_MODE_PosmÚP
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GPIO_MODEÚP MODE_INPUT£ÚP MODE_OUTPUT@ÚPMODE_AF²ÚP MODE_ANALOGÚPOUTPUT_TYPE_PosÚP OUTPUT_TYPE#ÚP
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OUTPUT_PPÉÚP
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OUTPUT_ODÖÚPEXTI_MODE_PosbÚP
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EXTI_MODEûÚPEXTI_ITÚP EXTI_EVT3ÚPTRIGGER_MODE_PosÚP TRIGGER_MODEÚPTRIGGER_RISINGpÚPTRIGGER_FALLING=Ú PSTM32L0xx_HAL_DMA_HÔÚ8
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<unnamed>QÚ
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"ERequest Ú
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"E
|
DirectionMÚ
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"E
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PeriphInclÚ
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"EMemInc»Ú
|
"EPeriphDataAlignmentYÚ
|
"EMemDataAlignment¨Ú
|
"EModesÚ
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"E PriorityÚDMA_InitTypeDefmÚ HAL_DMA_STATE_RESETÚ HAL_DMA_STATE_READY Ú HAL_DMA_STATE_BUSYQÚ HAL_DMA_STATE_TIMEOUTgÚ HAL_DMA_StateTypeDefÂÚ HAL_DMA_FULL_TRANSFERwÚ HAL_DMA_HALF_TRANSFERÚ% HAL_DMA_LevelCompleteTypeDefÚ HAL_DMA_XFER_CPLT_CB_IDÓÚ$ HAL_DMA_XFER_HALFCPLT_CB_ID°Ú! HAL_DMA_XFER_ERROR_CB_IDzÚ! HAL_DMA_XFER_ABORT_CB_IDÚ HAL_DMA_XFER_ALL_CB_ID/Ú"HAL_DMA_CallbackIDTypeDef Ú 8 __DMA_HandleTypeDef³Ú "E InstanceÚ " EInit Ú ""ELockBÚ ""EStateÈÚ "EParentdÚ "EXferCpltCallback
Ú "EXferHalfCpltCallbackÚ "EXferErrorCallback Ú "EXferAbortCallback Ú
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"E
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ErrorCodeQÚ "EDmaBaseAddresskÚ
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"E ChannelIndex ÚDMA_HandleTypeDef±ÚPHAL_DMA_ERROR_NONE)ÚPHAL_DMA_ERROR_TEÄÚ PHAL_DMA_ERROR_NO_XFER"Ú PHAL_DMA_ERROR_TIMEOUT,Ú$P HAL_DMA_ERROR_NOT_SUPPORTED1ÚPDMA_REQUEST_0ÈÚPDMA_REQUEST_1ÇÚPDMA_REQUEST_2ÆÚPDMA_REQUEST_3ÅÚPDMA_REQUEST_4ÄÚPDMA_REQUEST_5ÃÚPDMA_REQUEST_6ÂÚPDMA_REQUEST_7ÁÚPDMA_REQUEST_8ÀÚPDMA_REQUEST_9¿ÚPDMA_REQUEST_10ÚPDMA_REQUEST_12ÚPDMA_REQUEST_13ÚPDMA_REQUEST_14ÚPDMA_REQUEST_15ÚPIS_DMA_ALL_REQUESTÚ PDMA_PERIPH_TO_MEMORYpÚ PDMA_MEMORY_TO_PERIPHpÚ PDMA_MEMORY_TO_MEMORY_ÚPDMA_PINC_ENABLELÚPDMA_PINC_DISABLEýÚPDMA_MINC_ENABLEOÚPDMA_MINC_DISABLEÚ PDMA_PDATAALIGN_BYTE Ú PDMA_PDATAALIGN_HALFWORDáÚ PDMA_PDATAALIGN_WORDÚ PDMA_MDATAALIGN_BYTEÚ PDMA_MDATAALIGN_HALFWORDäÚ PDMA_MDATAALIGN_WORDÚP DMA_NORMAL½ÚP DMA_CIRCULAR-ÚPDMA_PRIORITY_LOW§Ú PDMA_PRIORITY_MEDIUMÒÚPDMA_PRIORITY_HIGHwÚ PDMA_PRIORITY_VERY_HIGHÈÚP
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DMA_IT_TCõÚP
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DMA_IT_HTðÚP
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DMA_IT_TEóÚP DMA_FLAG_GL1EÚP DMA_FLAG_TC1AÚP DMA_FLAG_HT1<ÚP DMA_FLAG_TE1?ÚP DMA_FLAG_GL2DÚP DMA_FLAG_TC2@ÚP DMA_FLAG_HT2;ÚP DMA_FLAG_TE2>ÚP DMA_FLAG_GL3CÚP DMA_FLAG_TC3?ÚP DMA_FLAG_HT3:ÚP DMA_FLAG_TE3=ÚP DMA_FLAG_GL4BÚP DMA_FLAG_TC4>ÚP DMA_FLAG_HT49ÚP DMA_FLAG_TE4<ÚP DMA_FLAG_GL5AÚP DMA_FLAG_TC5=ÚP DMA_FLAG_HT58ÚP DMA_FLAG_TE5;ÚP DMA_FLAG_GL6@ÚP DMA_FLAG_TC6<ÚP DMA_FLAG_HT67ÚP DMA_FLAG_TE6:ÚP DMA_FLAG_GL7?ÚP DMA_FLAG_TC7;ÚP DMA_FLAG_HT76ÚP DMA_FLAG_TE79Ú%P __HAL_DMA_RESET_HANDLE_STATEÚP__HAL_DMA_ENABLEáÚP__HAL_DMA_DISABLEÚ$P __HAL_DMA_GET_TC_FLAG_INDEXLÚ$P __HAL_DMA_GET_HT_FLAG_INDEXGÚ$P __HAL_DMA_GET_TE_FLAG_INDEXJÚ$P __HAL_DMA_GET_GI_FLAG_INDEXSÚP__HAL_DMA_GET_FLAG+Ú P__HAL_DMA_CLEAR_FLAG Ú P__HAL_DMA_ENABLE_ITßÚ P__HAL_DMA_DISABLE_ITÚ P__HAL_DMA_GET_IT_SOURCEnÚ P__HAL_DMA_GET_COUNTER Ú ,hdma/Ú HAL_DMA_Init×Ú ,hdma/Ú HAL_DMA_DeInit*Ú ,hdma/Ú,
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SrcAddressÝÚ,
|
DstAddressÚÚ,
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DataLengthïÚ HAL_DMA_Start[Ú ,hdma/Ú,
|
SrcAddressÝÚ,
|
DstAddressÚÚ,
|
DataLengthïÚ HAL_DMA_Start_ITYÚ ,hdma/Ú HAL_DMA_AbortqÚ ,hdma/Ú HAL_DMA_Abort_IToÚ ,hdma/Ú,"CompleteLevelÚ,
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TimeoutêÚ HAL_DMA_PollForTransferRÚ ,hdma/Ú HAL_DMA_IRQHandlerµÚ ,hdma/Ú," CallbackID Ú,
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pCallbackBÚ! HAL_DMA_RegisterCallbackÚ ,hdma/Ú," CallbackID Ú# HAL_DMA_UnRegisterCallback:Ú ,hdma/Ú HAL_DMA_GetStateBÚ ,hdma/Ú HAL_DMA_GetError9ÚPIS_DMA_DIRECTIONÞÚPIS_DMA_BUFFER_SIZE'Ú$P IS_DMA_PERIPHERAL_INC_STATEdÚ PIS_DMA_MEMORY_INC_STATEÚ$P IS_DMA_PERIPHERAL_DATA_SIZEjÚ PIS_DMA_MEMORY_DATA_SIZE
ÚP IS_DMA_MODEdÚPIS_DMA_PRIORITYÿÚ!P__STM32L0xx_HAL_CORTEX_H Ú8
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<unnamed>QÚ
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"ªF BaseAddressÚ "ªFEnableÚ "ªFNumberkÚ "ªFSize=Ú "ªFSubRegionDisable~Ú "ªF TypeExtFieldÚ "ªFAccessPermissionEÚ "ªF DisableExecÚ "ªF IsShareableÚ "ªF IsCacheable¦Ú "ªF IsBufferable Ú MPU_Region_InitTypeDef|Ú$P IS_NVIC_PREEMPTION_PRIORITY'ÚPIS_NVIC_DEVICE_IRQ"Ú$P SYSTICK_CLKSOURCE_HCLK_DIV8fÚ PSYSTICK_CLKSOURCE_HCLKêÚ PIS_SYSTICK_CLK_SOURCEÚ PMPU_HFNMI_PRIVDEF_NONEÞÚPMPU_HARDFAULT_NMIzÚ PMPU_PRIVILEGED_DEFAULTÿÚPMPU_HFNMI_PRIVDEFwÚPMPU_REGION_ENABLEÚPMPU_REGION_DISABLE?Ú&P MPU_INSTRUCTION_ACCESS_ENABLEÇÚ'P MPU_INSTRUCTION_ACCESS_DISABLExÚ PMPU_ACCESS_SHAREABLEºÚ!PMPU_ACCESS_NOT_SHAREABLEbÚ PMPU_ACCESS_CACHEABLEÙÚ!PMPU_ACCESS_NOT_CACHEABLEÚ PMPU_ACCESS_BUFFERABLEqÚ"PMPU_ACCESS_NOT_BUFFERABLEÚ PMPU_REGION_SIZE_32BðÚ PMPU_REGION_SIZE_64BëÚ PMPU_REGION_SIZE_128B¸Ú PMPU_REGION_SIZE_256B¶Ú PMPU_REGION_SIZE_512B»Ú PMPU_REGION_SIZE_1KBÙÚ PMPU_REGION_SIZE_2KBØÚ PMPU_REGION_SIZE_4KBÖÚ PMPU_REGION_SIZE_8KBÒÚ PMPU_REGION_SIZE_16KB¡Ú PMPU_REGION_SIZE_32KB£Ú PMPU_REGION_SIZE_64KBÚ PMPU_REGION_SIZE_128KBkÚ PMPU_REGION_SIZE_256KBiÚ PMPU_REGION_SIZE_512KBnÚ PMPU_REGION_SIZE_1MB×Ú PMPU_REGION_SIZE_2MBÖÚ PMPU_REGION_SIZE_4MBÔÚ PMPU_REGION_SIZE_8MBÐÚ PMPU_REGION_SIZE_16MBÚ PMPU_REGION_SIZE_32MB¡Ú PMPU_REGION_SIZE_64MBÚ PMPU_REGION_SIZE_128MBiÚ PMPU_REGION_SIZE_256MBgÚ PMPU_REGION_SIZE_512MBlÚ PMPU_REGION_SIZE_1GBÝÚ PMPU_REGION_SIZE_2GBÜÚ PMPU_REGION_SIZE_4GBÚÚ PMPU_REGION_NO_ACCESSÚPMPU_REGION_PRIV_RWêÚ PMPU_REGION_PRIV_RW_UROÚ PMPU_REGION_FULL_ACCESSçÚPMPU_REGION_PRIV_ROòÚ PMPU_REGION_PRIV_RO_UROÚPMPU_REGION_NUMBER0:ÚPMPU_REGION_NUMBER19ÚPMPU_REGION_NUMBER28ÚPMPU_REGION_NUMBER37ÚPMPU_REGION_NUMBER46ÚPMPU_REGION_NUMBER55ÚPMPU_REGION_NUMBER64ÚPMPU_REGION_NUMBER73Ú ,"IRQnhÚ,
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PreemptPriorityÚ,
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SubPriority=Ú HAL_NVIC_SetPriorityoÚ ,"IRQnhÚ HAL_NVIC_EnableIRQÎÚ ,"IRQnhÚ HAL_NVIC_DisableIRQ_Ú HAL_NVIC_SystemResetuÚ,
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TicksNumb=Ú HAL_SYSTICK_Config±Ú ,"IRQnhÚ HAL_NVIC_GetPriority{Ú ,"IRQnhÚ HAL_NVIC_GetPendingIRQ(Ú ,"IRQnhÚ HAL_NVIC_SetPendingIRQ Ú ,"IRQnhÚ! HAL_NVIC_ClearPendingIRQ]Ú,
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CLKSourceÚ$ HAL_SYSTICK_CLKSourceConfigTÚ HAL_SYSTICK_IRQHandlerUÚ HAL_SYSTICK_CallbacköÚ,
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MPU_ControlÚ HAL_MPU_EnableÚ HAL_MPU_DisableÚ, MPU_InitÜÚ HAL_MPU_ConfigRegionÚ PIS_MPU_REGION_ENABLEÚ"PIS_MPU_INSTRUCTION_ACCESSÚÚ PIS_MPU_ACCESS_SHAREABLE¹Ú PIS_MPU_ACCESS_CACHEABLEØÚ!PIS_MPU_ACCESS_BUFFERABLEpÚ+P#IS_MPU_REGION_PERMISSION_ATTRIBUTEüÚ PIS_MPU_REGION_NUMBERkÚPIS_MPU_REGION_SIZEýÚ"PIS_MPU_SUB_REGION_DISABLEíÚ P__STM32L0xx_HAL_ADC_H Ú8
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<unnamed>QÚ
|
"GRatioßÚ
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"GRightBitShift³Ú
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"GTriggeredMode¬Ú ADC_OversamplingTypeDefÚ8
|
<unnamed>QÚ
|
"GClockPrescaler:Ú
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"G ResolutionÚ
|
"G
|
DataAlignlÚ
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"G ScanConvMode+Ú
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"G EOCSelectionNÚ
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"GLowPowerAutoWaitVÚ
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"GLowPowerAutoPowerOff»Ú ""GContinuousConvModeXÚ ""GDiscontinuousConvModeÚ
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"GExternalTrigConvTÚ
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"GExternalTrigConvEdge×Ú ""GDMAContinuousRequests?Ú
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"GOverrunäÚ
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"GLowPowerFrequencyModeCÚ
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"G SamplingTimeÚ
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"GOversamplingModeGÚ " G OversampleÚADC_InitTypeDefwÚ8
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<unnamed>QÚ
|
"²GChannel Ú
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"²GRank<Ú ADC_ChannelConfTypeDef¾Ú8
|
<unnamed>QÚ
|
"¶G WatchdogModeþÚ
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"¶GChannelÚ ""¶GITModeÚ
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"¶GHighThreshold
Ú
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"¶G LowThresholdÕÚ!ADC_AnalogWDGConfTypeDef?Ú PHAL_ADC_STATE_RESETçÚ PHAL_ADC_STATE_READYõÚ$P HAL_ADC_STATE_BUSY_INTERNAL[Ú PHAL_ADC_STATE_TIMEOUT?Ú%P HAL_ADC_STATE_ERROR_INTERNALÚ#PHAL_ADC_STATE_ERROR_CONFIG½Ú PHAL_ADC_STATE_ERROR_DMA§Ú PHAL_ADC_STATE_REG_BUSYäÚ PHAL_ADC_STATE_REG_EOCRÚ PHAL_ADC_STATE_REG_OVR2Ú PHAL_ADC_STATE_REG_EOSMP¡Ú PHAL_ADC_STATE_INJ_BUSYáÚ PHAL_ADC_STATE_INJ_EOCOÚ PHAL_ADC_STATE_INJ_JQOVFÚPHAL_ADC_STATE_AWD1_ÚPHAL_ADC_STATE_AWD2^ÚPHAL_ADC_STATE_AWD3]Ú&P HAL_ADC_STATE_MULTIMODE_SLAVEÌÚ 8 __ADC_HandleTypeDef½Ú "ÏG Instance`Ú "HÏGInitÁÚ "ÏG DMA_HandleÚ ""ÏGLock Ú
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"ÏGState¨Ú
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"ÏG
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ErrorCode ÚADC_HandleTypeDef»ÚPHAL_ADC_ERROR_NONE3Ú PHAL_ADC_ERROR_INTERNALþÚPHAL_ADC_ERROR_OVRnÚPHAL_ADC_ERROR_DMAÚPADC_ENABLE_TIMEOUTSÚ PADC_DISABLE_TIMEOUTÚ$P ADC_STOP_CONVERSION_TIMEOUT=Ú&P ADC_DELAY_10US_MIN_CPU_CYCLESçÚ PADC_CLOCK_ASYNC_DIV1ÀÚ PADC_CLOCK_ASYNC_DIV2¿Ú PADC_CLOCK_ASYNC_DIV4½Ú PADC_CLOCK_ASYNC_DIV6»Ú PADC_CLOCK_ASYNC_DIV8¹Ú PADC_CLOCK_ASYNC_DIV10Ú PADC_CLOCK_ASYNC_DIV12Ú PADC_CLOCK_ASYNC_DIV16Ú PADC_CLOCK_ASYNC_DIV32Ú PADC_CLOCK_ASYNC_DIV64
Ú PADC_CLOCK_ASYNC_DIV128RÚ PADC_CLOCK_ASYNC_DIV256PÚ!PADC_CLOCK_SYNC_PCLK_DIV1pÚ!PADC_CLOCK_SYNC_PCLK_DIV2oÚ!PADC_CLOCK_SYNC_PCLK_DIV4mÚPADC_RESOLUTION_12BhÚPADC_RESOLUTION_10BjÚPADC_RESOLUTION_8BÚPADC_RESOLUTION_6BÚ PADC_DATAALIGN_RIGHT ÚPADC_DATAALIGN_LEFTqÚ&P ADC_EXTERNALTRIGCONVEDGE_NONE÷Ú(P ADC_EXTERNALTRIGCONVEDGE_RISINGWÚ)P!ADC_EXTERNALTRIGCONVEDGE_FALLING$Ú/P'ADC_EXTERNALTRIGCONVEDGE_RISINGFALLINGLÚ PADC_EOC_SINGLE_CONVñÚPADC_EOC_SEQ_CONVÐÚ PADC_OVR_DATA_PRESERVEDùÚ!PADC_OVR_DATA_OVERWRITTEN<Ú PADC_RANK_CHANNEL_NUMBERÊÚPADC_RANK_NONEÏÚPADC_CHANNEL_0ÚPADC_CHANNEL_1ÚPADC_CHANNEL_2ÚPADC_CHANNEL_3ÿÚPADC_CHANNEL_4þÚPADC_CHANNEL_5ýÚPADC_CHANNEL_6üÚPADC_CHANNEL_7ûÚPADC_CHANNEL_8úÚPADC_CHANNEL_9ùÚPADC_CHANNEL_10ÏÚPADC_CHANNEL_11ÎÚPADC_CHANNEL_12ÍÚPADC_CHANNEL_13ÌÚPADC_CHANNEL_14ËÚPADC_CHANNEL_15ÊÚPADC_CHANNEL_17ÈÚPADC_CHANNEL_18ÇÚ PADC_CHANNEL_VREFINTÚ PADC_CHANNEL_TEMPSENSORÚPADC_CHANNEL_MASKÚ PADC_CHANNEL_AWD_MASK½Ú PADC_SAMPLETIME_1CYCLE_5ñÚ!PADC_SAMPLETIME_3CYCLES_5Ú!PADC_SAMPLETIME_7CYCLES_5Ú"PADC_SAMPLETIME_12CYCLES_5hÚ"PADC_SAMPLETIME_19CYCLES_5aÚ"PADC_SAMPLETIME_39CYCLES_5_Ú"PADC_SAMPLETIME_79CYCLES_5[Ú#PADC_SAMPLETIME_160CYCLES_52Ú#PADC_SCAN_DIRECTION_FORWARD×Ú$P ADC_SCAN_DIRECTION_BACKWARD«ÚPADC_SCAN_ENABLE[Ú!PADC_OVERSAMPLING_RATIO_2nÚ!PADC_OVERSAMPLING_RATIO_4lÚ!PADC_OVERSAMPLING_RATIO_8hÚ"PADC_OVERSAMPLING_RATIO_167Ú"PADC_OVERSAMPLING_RATIO_329Ú"PADC_OVERSAMPLING_RATIO_644Ú#PADC_OVERSAMPLING_RATIO_128Ú#PADC_OVERSAMPLING_RATIO_256ÿÚ PADC_RIGHTBITSHIFT_NONEÚ PADC_RIGHTBITSHIFT_1Ú PADC_RIGHTBITSHIFT_2Ú PADC_RIGHTBITSHIFT_3Ú PADC_RIGHTBITSHIFT_4Ú PADC_RIGHTBITSHIFT_5Ú PADC_RIGHTBITSHIFT_6Ú PADC_RIGHTBITSHIFT_7 Ú PADC_RIGHTBITSHIFT_8 Ú)P!ADC_TRIGGEREDMODE_SINGLE_TRIGGERÚ(P ADC_TRIGGEREDMODE_MULTI_TRIGGERGÚ PADC_ANALOGWATCHDOG_NONEäÚ&P ADC_ANALOGWATCHDOG_SINGLE_REG Ú#PADC_ANALOGWATCHDOG_ALL_REGøÚPADC_REGULAR_GROUPÚPADC_AWD_EVENTÍÚPADC_OVR_EVENT²ÚP ADC_IT_RDY¥ÚP ADC_IT_EOSMP ÚP ADC_IT_EOC½ÚP ADC_IT_EOSÚP ADC_IT_OVRÚP ADC_IT_AWD¸ÚP ADC_IT_EOCAL,ÚP ADC_FLAG_RDY$ÚPADC_FLAG_EOSMPÚP ADC_FLAG_EOC<ÚP ADC_FLAG_EOS,ÚP ADC_FLAG_OVR ÚP ADC_FLAG_AWD7ÚPADC_FLAG_EOCAL«ÚP ADC_FLAG_ALL:Ú%P __HAL_ADC_RESET_HANDLE_STATE ÚP__HAL_ADC_ENABLEëÚ PADC_ENABLING_CONDITIONSÝÚP__HAL_ADC_DISABLEÚ!PADC_DISABLING_CONDITIONSÚPADC_IS_ENABLEèÚPADC_GET_RESOLUTION-Ú&P ADC_IS_SOFTWARE_START_REGULAR¦Ú*P"ADC_IS_CONVERSION_ONGOING_REGULARÚPADC_CONTINUOUSqÚP ADC_SCANDIRÚ*P"__HAL_ADC_CFGR1_DISCONTINUOUS_NUMxÚPADC_DMACONTREQÚ"P__HAL_ADC_CFGR1_AutoDelayFÚ P__HAL_ADC_CFGR1_AUTOFFÚ PADC_TRX_HIGHTHRESHOLDPÚ#P__HAL_ADC_CCR_LOWFREQUENCY£Ú$P ADC_OFFSET_SHIFT_RESOLUTIONWÚ+P#ADC_AWD1THRESHOLD_SHIFT_RESOLUTIONVÚ#P__HAL_ADC_Value_Shift_leftÚ P__HAL_ADC_ENABLE_ITéÚ P__HAL_ADC_DISABLE_ITÚ P__HAL_ADC_GET_IT_SOURCExÚ P__HAL_ADC_CLEAR_FLAGªÚP__HAL_ADC_GET_FLAG5ÚPADC_STATE_CLR_SETvÚ PADC_CLEAR_ERRORCODEÚ"P__HAL_ADC_CLOCK_PRESCALERÚ PIS_ADC_CLOCKPRESCALERrÚPIS_ADC_RESOLUTIONsÚ#PIS_ADC_RESOLUTION_8_6_BITS¤ÚPIS_ADC_DATA_ALIGN£Ú PIS_ADC_EXTTRIG_EDGEèÚ PIS_ADC_EOC_SELECTION¥ÚPIS_ADC_OVERRUN\ÚP IS_ADC_RANKgÚPIS_ADC_CHANNELÚPIS_ADC_SAMPLE_TIME5ÚPIS_ADC_SCAN_MODEàÚ"PIS_ADC_OVERSAMPLING_RATIOÚ PIS_ADC_RIGHT_BIT_SHIFTäÚ+P#IS_ADC_TRIGGERED_OVERSAMPLING_MODENÚ$P IS_ADC_ANALOG_WATCHDOG_MODEÚ PIS_ADC_CONVERSION_GROUPÚPIS_ADC_EVENT_TYPEdÚP IS_ADC_RANGE$Ú PIS_ADC_REGULAR_NB_CONVçÚ!P__STM32L0xx_HAL_ADC_EX_HÚPADC_SINGLE_ENDEDÚ%P ADC_EXTERNALTRIGCONV_T6_TRGOÚ%P ADC_EXTERNALTRIGCONV_T21_CC2pÚ%P ADC_EXTERNALTRIGCONV_T2_TRGO Ú$P ADC_EXTERNALTRIGCONV_T2_CC4¡Ú&P ADC_EXTERNALTRIGCONV_T22_TRGOéÚ%P ADC_EXTERNALTRIGCONV_T3_TRGO Ú&P ADC_EXTERNALTRIGCONV_EXT_IT11íÚPADC_SOFTWARE_START(Ú&P ADC_EXTERNALTRIGCONV_T21_TRGOêÚ$P ADC_EXTERNALTRIGCONV_T2_CC3¢ÚPADC_FLAG_SENSOR3ÚPADC_FLAG_VREFINTíÚ#PIS_ADC_SINGLE_DIFFERENTIALçÚPIS_ADC_CALFACTÚPIS_ADC_EXTTRIGfÚ ,hadc9Ú,
|
SingleDiffðÚ$ HAL_ADCEx_Calibration_StartÅÚ ,hadc9Ú,
|
SingleDiffðÚ' HAL_ADCEx_Calibration_GetValue°Ú ,hadc9Ú,
|
SingleDiffðÚ,
|
CalibrationFactoröÚ' HAL_ADCEx_Calibration_SetValue¤Ú HAL_ADCEx_EnableVREFINT=Ú! HAL_ADCEx_DisableVREFINTÎÚ* "HAL_ADCEx_EnableVREFINTTempSensorÚ+ #HAL_ADCEx_DisableVREFINTTempSensorªÚ ,hadc9Ú HAL_ADC_InitáÚ ,hadc9Ú HAL_ADC_DeInit4Ú ,hadc9Ú HAL_ADC_MspInit«Ú ,hadc9Ú HAL_ADC_MspDeInitþÚ ,hadc9Ú HAL_ADC_StarteÚ ,hadc9Ú HAL_ADC_StopÏÚ ,hadc9Ú,
|
TimeoutêÚ" HAL_ADC_PollForConversionwÚ ,hadc9Ú,
|
|
EventType)Ú,
|
TimeoutêÚ HAL_ADC_PollForEvent¥Ú ,hadc9Ú HAL_ADC_Start_ITcÚ ,hadc9Ú HAL_ADC_Stop_ITÍÚ ,hadc9Ú,pDataÝÚ,
|
LengthqÚ HAL_ADC_Start_DMA,Ú ,hadc9Ú HAL_ADC_Stop_DMAÚ ,hadc9Ú HAL_ADC_GetValuePÚ ,hadc9Ú HAL_ADC_IRQHandler¿Ú ,hadc9Ú! HAL_ADC_ConvCpltCallback'Ú ,hadc9Ú% HAL_ADC_ConvHalfCpltCallback¤Ú ,hadc9Ú) !HAL_ADC_LevelOutOfWindowCallbackãÚ ,hadc9Ú HAL_ADC_ErrorCallbackLÚ ,hadc9Ú,sConfigúÚ HAL_ADC_ConfigChannelTÚ ,hadc9Ú,AnalogWDGConfig)Ú HAL_ADC_AnalogWDGConfigÕÚ ,hadc9Ú HAL_ADC_GetStateLÚ ,hadc9Ú HAL_ADC_GetErrorCÚ PHAL_COMP_MODULE_ENABLEDÉÚ PHAL_CRC_MODULE_ENABLED"Ú PHAL_CRYP_MODULE_ENABLEDºÚ PHAL_DAC_MODULE_ENABLED2Ú$P HAL_FIREWALL_MODULE_ENABLEDÚ P__STM32L0xx_HAL_FLASH_HrÚ PFLASH_TIMEOUT_VALUEÕÚ!PFLASH_SIZE_DATA_REGISTERVÚ PIS_FLASH_TYPEPROGRAMÚPIS_FLASH_LATENCYÓÚ FLASH_PROC_NONEOÚ FLASH_PROC_PAGEERASEèÚ FLASH_PROC_PROGRAMaÚ FLASH_ProcedureTypeDef®Ú8
|
<unnamed>QÚ ""ÖIProcedureOnGoingÚ
|
"ÖINbPagesToErase;Ú
|
"ÖIAddressÖÚ
|
"ÖIPage%Ú ""ÖILockÚ
|
"ÖI
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ErrorCodeÚ FLASH_ProcessTypeDef|Ú PHAL_FLASH_ERROR_NONEÚ PHAL_FLASH_ERROR_PGAãÚ PHAL_FLASH_ERROR_WRPÂÚ PHAL_FLASH_ERROR_OPTVpÚ PHAL_FLASH_ERROR_SIZE~ÚPHAL_FLASH_ERROR_RD'Ú PHAL_FLASH_ERROR_FWWERRØÚ PHAL_FLASH_ERROR_NOTZEROÚP FLASH_SIZE¯ÚPFLASH_PAGE_SIZE)ÚP
|
FLASH_ENDÚPFLASH_BANK2_BASEÚPFLASH_BANK1_END]ÚPFLASH_BANK2_END\Ú PFLASH_TYPEPROGRAM_WORDÝÚPFLASH_LATENCY_0AÚPFLASH_LATENCY_1@ÚP FLASH_IT_EOPÚP FLASH_IT_ERRÚPFLASH_FLAG_BSY{ÚPFLASH_FLAG_EOP
ÚPFLASH_FLAG_ENDHVðÚPFLASH_FLAG_READYðÚPFLASH_FLAG_WRPERRÚPFLASH_FLAG_PGAERR¢ÚPFLASH_FLAG_SIZERRÚPFLASH_FLAG_OPTVERR/ÚPFLASH_FLAG_RDERRæÚPFLASH_FLAG_FWWERRÚ PFLASH_FLAG_NOTZEROERRAÚP FLASH_PDKEY18ÚP FLASH_PDKEY27ÚP FLASH_PEKEY17ÚP FLASH_PEKEY26ÚPFLASH_PRGKEY1áÚPFLASH_PRGKEY2àÚPFLASH_OPTKEY1×ÚPFLASH_OPTKEY2ÖÚ P__HAL_FLASH_ENABLE_IT?Ú P__HAL_FLASH_DISABLE_ITðÚ P__HAL_FLASH_GET_FLAGÚ P__HAL_FLASH_CLEAR_FLAGÚ#P__STM32L0xx_HAL_FLASH_EX_HpÚPFLASH_NBPAGES_MAXÚP WRP_MASK_LOWÞÚPWRP_MASK_HIGH®ÚPIS_FLASH_TYPEERASE-ÚPIS_OPTIONBYTE©ÚP IS_WRPSTATE@ÚP
|
IS_OB_WRPÕÚP
|
IS_OB_RDPèÚPIS_OB_BOR_LEVELÚPIS_OB_IWDG_SOURCEcÚPIS_OB_STOP_SOURCEHÚPIS_OB_STDBY_SOURCEÚPIS_OBEXÚPIS_PCROPSTATE±ÚP IS_OB_PCROPFÚPIS_OB_BOOT_BANKÚP IS_OB_BOOT1eÚPIS_TYPEPROGRAMDATA8Ú PIS_FLASH_DATA_ADDRESSZÚ$P IS_FLASH_DATA_BANK1_ADDRESS¢Ú$P IS_FLASH_DATA_BANK2_ADDRESS¡Ú!PIS_FLASH_PROGRAM_ADDRESSVÚ'P IS_FLASH_PROGRAM_BANK1_ADDRESSÚ'P IS_FLASH_PROGRAM_BANK2_ADDRESSÚP IS_NBPAGES¼Ú,
|
PageAddressÚ FLASH_PageEraseÚ8
|
<unnamed>QÚ
|
"¤J
|
TypeErase7Ú
|
"¤J PageAddressÚ
|
"¤JNbPages-Ú FLASH_EraseInitTypeDefÓÚ8
|
<unnamed>QÚ
|
"©J OptionType§Ú
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"©J WRPStateÌÚ
|
"©J
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WRPSector[Ú
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"©J WRPSector2'Ú "©J RDPLevelïÚ "©J BORLevelòÚ "©J USERConfig4Ú "©JBOOTBit1ConfigçÚ#FLASH_OBProgramInitTypeDefRÚ8
|
<unnamed>QÚ
|
"³J OptionTypeÚ
|
"³J PCROPState3Ú
|
"³J PCROPSectorÂÚ
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"³J PCROPSector2Ú "³J BootConfigÌÚ& FLASH_AdvOBProgramInitTypeDef1Ú PFLASH_TYPEERASE_PAGESSÚPOPTIONBYTE_WRPJÚPOPTIONBYTE_RDP]ÚPOPTIONBYTE_USERÚPOPTIONBYTE_BOR`Ú POPTIONBYTE_BOOT_BIT1Ú POB_WRPSTATE_DISABLEèÚPOB_WRPSTATE_ENABLE7ÚPOB_WRP_Pages0to31úÚPOB_WRP_Pages32to63¾ÚPOB_WRP_Pages64to95´Ú POB_WRP_Pages96to127Ú POB_WRP_Pages128to159NÚ POB_WRP_Pages160to191VÚ POB_WRP_Pages192to223UÚ POB_WRP_Pages224to255TÚ POB_WRP_Pages256to287JÚ POB_WRP_Pages288to319IÚ POB_WRP_Pages320to351ZÚ POB_WRP_Pages352to383PÚ POB_WRP_Pages384to415OÚ POB_WRP_Pages416to447NÚ POB_WRP_Pages448to479DÚ POB_WRP_Pages480to511UÚ POB_WRP_Pages512to543TÚ POB_WRP_Pages544to575JÚ POB_WRP_Pages576to607IÚ POB_WRP_Pages608to639HÚ POB_WRP_Pages640to671PÚ POB_WRP_Pages672to703OÚ POB_WRP_Pages704to735NÚ POB_WRP_Pages736to767DÚ POB_WRP_Pages768to799:Ú POB_WRP_Pages800to831TÚ POB_WRP_Pages832to863JÚ POB_WRP_Pages864to895@Ú POB_WRP_Pages896to927?Ú POB_WRP_Pages928to959>Ú POB_WRP_Pages960to991FÚ POB_WRP_Pages992to1023 ÚPOB_WRP_AllPages\Ú POB_WRP2_Pages1024to1055¾Ú POB_WRP2_Pages1056to1087´Ú POB_WRP2_Pages1088to1119³Ú POB_WRP2_Pages1120to1151ÄÚ POB_WRP2_Pages1152to1183ºÚ POB_WRP2_Pages1184to1215¹Ú POB_WRP2_Pages1216to1247¸Ú POB_WRP2_Pages1248to1279®Ú POB_WRP2_Pages1280to1311¿Ú POB_WRP2_Pages1312to1343¾Ú POB_WRP2_Pages1344to1375´Ú POB_WRP2_Pages1376to1407³Ú POB_WRP2_Pages1408to1439²Ú POB_WRP2_Pages1440to1471ºÚ POB_WRP2_Pages1472to1503¹Ú POB_WRP2_Pages1504to1535¸ÚPOB_WRP2_AllPages(ÚPOB_RDP_LEVEL_0sÚPOB_RDP_LEVEL_1rÚPOB_RDP_LEVEL_2qÚP OB_BOR_OFFªÚPOB_BOR_LEVEL1ÖÚPOB_BOR_LEVEL2ÕÚPOB_BOR_LEVEL3ÔÚPOB_BOR_LEVEL4ÓÚPOB_BOR_LEVEL5ÒÚP OB_IWDG_SWÚP OB_IWDG_HWÚPOB_STOP_NORSTÚP OB_STOP_RST'ÚPOB_STDBY_NORSTDÚP OB_STDBY_RSTåÚPOPTIONBYTE_PCROP»Ú POPTIONBYTE_BOOTCONFIGKÚ POB_PCROP_STATE_DISABLEøÚ POB_PCROP_STATE_ENABLEGÚ POB_PCROP_DESELECTEDÚPOB_PCROP_SELECTEDÚ POB_PCROP_Pages0to31kÚ POB_PCROP_Pages32to63/Ú POB_PCROP_Pages64to95%Ú POB_PCROP_Pages96to127òÚ POB_PCROP_Pages128to159¿Ú POB_PCROP_Pages160to191ÇÚ POB_PCROP_Pages192to223ÆÚ POB_PCROP_Pages224to255ÅÚ POB_PCROP_Pages256to287»Ú POB_PCROP_Pages288to319ºÚ POB_PCROP_Pages320to351ËÚ POB_PCROP_Pages352to383ÁÚ POB_PCROP_Pages384to415ÀÚ POB_PCROP_Pages416to447¿Ú POB_PCROP_Pages448to479µÚ POB_PCROP_Pages480to511ÆÚ POB_PCROP_Pages512to543ÅÚ POB_PCROP_Pages544to575»Ú POB_PCROP_Pages576to607ºÚ POB_PCROP_Pages608to639¹Ú POB_PCROP_Pages640to671ÁÚ POB_PCROP_Pages672to703ÀÚ POB_PCROP_Pages704to735¿Ú POB_PCROP_Pages736to767µÚ POB_PCROP_Pages768to799«Ú POB_PCROP_Pages800to831ÅÚ POB_PCROP_Pages832to863»Ú POB_PCROP_Pages864to895±Ú POB_PCROP_Pages896to927°Ú POB_PCROP_Pages928to959¯Ú POB_PCROP_Pages960to991·Ú POB_PCROP_Pages992to1023ÚPOB_PCROP_AllPagesÍÚ"POB_PCROP2_Pages1024to1055/Ú"POB_PCROP2_Pages1056to1087%Ú"POB_PCROP2_Pages1088to1119$Ú"POB_PCROP2_Pages1120to11515Ú"POB_PCROP2_Pages1152to1183+Ú"POB_PCROP2_Pages1184to1215*Ú"POB_PCROP2_Pages1216to1247)Ú"POB_PCROP2_Pages1248to1279 Ú"POB_PCROP2_Pages1280to13110Ú"POB_PCROP2_Pages1312to1343/Ú"POB_PCROP2_Pages1344to1375%Ú"POB_PCROP2_Pages1376to1407$Ú"POB_PCROP2_Pages1408to1439#Ú"POB_PCROP2_Pages1440to1471+Ú"POB_PCROP2_Pages1472to1503*Ú"POB_PCROP2_Pages1504to1535)ÚPOB_PCROP2_AllPagesÚPOB_BOOT_BIT1_RESET2ÚPOB_BOOT_BIT1_SETÍÚ#PFLASH_TYPEPROGRAMDATA_BYTEÃÚ'P FLASH_TYPEPROGRAMDATA_HALFWORDÚ#PFLASH_TYPEPROGRAMDATA_WORD»ÚPOB_BOOT_BANK1áÚPOB_BOOT_BANK2àÚ P__HAL_FLASH_SET_LATENCYÚ P__HAL_FLASH_GET_LATENCYÚ+P#__HAL_FLASH_PREFETCH_BUFFER_ENABLEXÚ,P$__HAL_FLASH_PREFETCH_BUFFER_DISABLE Ú(P __HAL_FLASH_BUFFER_CACHE_ENABLE[Ú)P!__HAL_FLASH_BUFFER_CACHE_DISABLE Ú*P"__HAL_FLASH_PREREAD_BUFFER_ENABLE¨Ú+P#__HAL_FLASH_PREREAD_BUFFER_DISABLEYÚ+P#__HAL_FLASH_SLEEP_POWERDOWN_ENABLE%Ú,P$__HAL_FLASH_SLEEP_POWERDOWN_DISABLEÖÚ&P __HAL_FLASH_POWER_DOWN_ENABLE¨Ú'P __HAL_FLASH_POWER_DOWN_DISABLEYÚ, pEraseInitÉÚ,
|
PageError8Ú HAL_FLASHEx_EraseÚ, pEraseInitÉÚ HAL_FLASHEx_Erase_ITÚ,pOBInit.Ú HAL_FLASHEx_OBProgramÚ,pOBInit.Ú HAL_FLASHEx_OBGetConfigõÚ, pAdvOBInit Ú! HAL_FLASHEx_AdvOBProgramvÚ, pAdvOBInit Ú# HAL_FLASHEx_AdvOBGetConfigÔÚ# HAL_FLASHEx_OB_SelectPCROP"Ú% HAL_FLASHEx_OB_DeSelectPCROPuÚ& HAL_FLASHEx_DATAEEPROM_UnlockCÚ$ HAL_FLASHEx_DATAEEPROM_Lock*Ú,
|
Address Ú% HAL_FLASHEx_DATAEEPROM_EraseÁÚ,
|
TypeProgramOÚ,
|
Address Ú ,
|
Data]Ú' HAL_FLASHEx_DATAEEPROM_ProgramÕÚ6 .HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgramñÚ7 /HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgramÚ$P __STM32L0xx_FLASH_RAMFUNC_H3Ú' HAL_FLASHEx_EnableRunPowerDownÍÚ( HAL_FLASHEx_DisableRunPowerDown^Ú,
|
Page_Address1òÚ,
|
Page_Address2ñÚ& HAL_FLASHEx_EraseParallelPageVÚ,
|
Address1ØÚ, pBuffer1ÆÚ,
|
Address2×Ú, pBuffer2ÅÚ, $HAL_FLASHEx_ProgramParallelHalfPageçÚ,
|
Address Ú,pBufferùÚ$ HAL_FLASHEx_HalfPageProgram$Ú,Error½Ú HAL_FLASHEx_GetErrorØÚ,
|
TypeProgramOÚ,
|
Address Ú ,
|
Data]Ú HAL_FLASH_ProgramíÚ,
|
TypeProgramOÚ,
|
Address Ú ,
|
Data]Ú HAL_FLASH_Program_ITëÚ HAL_FLASH_IRQHandlerÚ,
|
ReturnValueLÚ) !HAL_FLASH_EndOfOperationCallback Ú,
|
ReturnValueLÚ) !HAL_FLASH_OperationErrorCallbackßÚ HAL_FLASH_Unlock[Ú HAL_FLASH_LockBÚ HAL_FLASH_OB_UnlockeÚ HAL_FLASH_OB_LockLÚ HAL_FLASH_OB_LaunchvÚ HAL_FLASH_GetErrorÚ pFlashkÚ,
|
TimeoutêÚ# FLASH_WaitForLastOperationæÚ PSTM32L0xx_HAL_I2C_HèÚ8
|
<unnamed>QÚ
|
"LTiming{Ú
|
"L OwnAddress1®Ú
|
"LAddressingModeJÚ
|
"LDualAddressModeÚ
|
"L OwnAddress2Ú
|
"LOwnAddress2Masks¤Ú
|
"LGeneralCallModeÚ
|
"LNoStretchMode¶ÚI2C_InitTypeDefÚ HAL_I2C_STATE_RESET#Ú HAL_I2C_STATE_READY1Ú HAL_I2C_STATE_BUSYeÚ HAL_I2C_STATE_BUSY_TXTÚ HAL_I2C_STATE_BUSY_RXVÚ HAL_I2C_STATE_LISTENÕÚ% HAL_I2C_STATE_BUSY_TX_LISTENÚ% HAL_I2C_STATE_BUSY_RX_LISTENÚ HAL_I2C_STATE_ABORT.Ú HAL_I2C_STATE_TIMEOUT{Ú HAL_I2C_STATE_ERROR Ú HAL_I2C_StateTypeDefÖÚ HAL_I2C_MODE_NONEÖÚ HAL_I2C_MODE_MASTER6Ú HAL_I2C_MODE_SLAVEÚ HAL_I2C_MODE_MEM)Ú HAL_I2C_ModeTypeDefTÚPHAL_I2C_ERROR_NONE=ÚPHAL_I2C_ERROR_BERRBÚPHAL_I2C_ERROR_ARLO?ÚPHAL_I2C_ERROR_AFêÚPHAL_I2C_ERROR_OVRxÚPHAL_I2C_ERROR_DMAÚ PHAL_I2C_ERROR_TIMEOUT@ÚPHAL_I2C_ERROR_SIZE2Ú PHAL_I2C_ERROR_DMA_PARAMÁÚ$P HAL_I2C_ERROR_INVALID_PARAMÚ 8 __I2C_HandleTypeDefÇÚ "³L InstancewÚ " ³LInitÚ "³L pBuffPtrÚ "³L XferSizeÚ "³L
|
XferCountÚ
|
"³L XferOptions3Ú
|
"³LPreviousStateRÚ "³LXferISR+Ú "³Lhdmatx*Ú "³Lhdmarx,Ú ""³LLock$Ú ""³LStateªÚ ""³LMode(Ú
|
"³L
|
ErrorCode3Ú
|
"³LAddrEventCount(Ú
|
"³L Devaddress±Ú
|
"³L Memaddress±ÚI2C_HandleTypeDefÅÚPI2C_FIRST_FRAME>Ú!PI2C_FIRST_AND_NEXT_FRAME\ÚPI2C_NEXT_FRAMEÚ!PI2C_FIRST_AND_LAST_FRAMEgÚPI2C_LAST_FRAMEÚ PI2C_LAST_FRAME_NO_STOPãÚPI2C_OTHER_FRAMEDÚ!PI2C_OTHER_AND_LAST_FRAMEmÚ PI2C_ADDRESSINGMODE_7BITÚ!PI2C_ADDRESSINGMODE_10BITÖÚ PI2C_DUALADDRESS_DISABLEÚ PI2C_DUALADDRESS_ENABLEPÚPI2C_OA2_NOMASK¨ÚPI2C_OA2_MASK01äÚPI2C_OA2_MASK02ãÚPI2C_OA2_MASK03âÚPI2C_OA2_MASK04áÚPI2C_OA2_MASK05àÚPI2C_OA2_MASK06ßÚPI2C_OA2_MASK07ÞÚ PI2C_GENERALCALL_DISABLEÚ PI2C_GENERALCALL_ENABLEbÚ PI2C_NOSTRETCH_DISABLEwÚ PI2C_NOSTRETCH_ENABLEÆÚ PI2C_MEMADD_SIZE_8BITÎÚ PI2C_MEMADD_SIZE_16BITÚ PI2C_DIRECTION_TRANSMITÚ PI2C_DIRECTION_RECEIVEÚPI2C_RELOAD_MODEUÚPI2C_AUTOEND_MODEúÚPI2C_SOFTEND_MODE÷ÚPI2C_NO_STARTSTOP¾ÚPI2C_GENERATE_STOPÚ PI2C_GENERATE_START_READÍÚ!PI2C_GENERATE_START_WRITE\ÚP I2C_IT_ERRIjÚP I2C_IT_TCI¾ÚP I2C_IT_STOPI ÚP I2C_IT_NACKI4ÚP I2C_IT_ADDRI6ÚP I2C_IT_RXI«ÚP I2C_IT_TXI©ÚP I2C_FLAG_TXE,ÚPI2C_FLAG_TXISÓÚPI2C_FLAG_RXNEÞÚPI2C_FLAG_ADDRÚP I2C_FLAG_AFÚPI2C_FLAG_STOPFÚP I2C_FLAG_TCÚP I2C_FLAG_TCR4ÚPI2C_FLAG_BERRðÚPI2C_FLAG_ARLOíÚP I2C_FLAG_OVR&ÚPI2C_FLAG_PECERRVÚPI2C_FLAG_TIMEOUTîÚPI2C_FLAG_ALERT¡ÚPI2C_FLAG_BUSYØÚP I2C_FLAG_DIR>Ú%P __HAL_I2C_RESET_HANDLE_STATEÚ P__HAL_I2C_ENABLE_ITóÚ P__HAL_I2C_DISABLE_IT¤Ú P__HAL_I2C_GET_IT_SOURCEÚPI2C_FLAG_MASKïÚP__HAL_I2C_GET_FLAG?Ú P__HAL_I2C_CLEAR_FLAG´ÚP__HAL_I2C_ENABLEõÚP__HAL_I2C_DISABLE¦Ú P__HAL_I2C_GENERATE_NACKÇÚ PSTM32L0xx_HAL_I2C_EX_HæÚ PI2C_ANALOGFILTER_ENABLEÚ!PI2C_ANALOGFILTER_DISABLE³Ú PI2C_FMP_NOT_SUPPORTED,Ú PI2C_FASTMODEPLUS_PB6ÈÚ PI2C_FASTMODEPLUS_PB7ÇÚ PI2C_FASTMODEPLUS_PB8ÆÚ PI2C_FASTMODEPLUS_PB9ÅÚ PI2C_FASTMODEPLUS_I2C1Ú PI2C_FASTMODEPLUS_I2C2Ú PI2C_FASTMODEPLUS_I2C3Ú ,hi2ccÚ,
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AnalogFilterÚ% HAL_I2CEx_ConfigAnalogFilterÚ ,hi2ccÚ,
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DigitalFilter¡Ú& HAL_I2CEx_ConfigDigitalFilter&Ú ,hi2ccÚ HAL_I2CEx_EnableWakeUpÚ ,hi2ccÚ HAL_I2CEx_DisableWakeUp«Ú,
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ConfigFastModePlus®Ú% HAL_I2CEx_EnableFastModePlus¤Ú,
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ConfigFastModePlus®Ú& HAL_I2CEx_DisableFastModePlus5Ú PIS_I2C_ANALOG_FILTER´Ú PIS_I2C_DIGITAL_FILTERfÚ PIS_I2C_FASTMODEPLUSöÚ ,hi2ccÚ HAL_I2C_InitëÚ ,hi2ccÚ HAL_I2C_DeInit>Ú ,hi2ccÚ HAL_I2C_MspInitµÚ ,hi2ccÚ HAL_I2C_MspDeInitÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_I2C_Master_TransmitLÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_I2C_Master_ReceiveÝÚ ,hi2ccÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_I2C_Slave_Transmit¿Ú ,hi2ccÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_I2C_Slave_ReceivePÚ ,hi2ccÚ, DevAddressäÚ, MemAddressäÚ, MemAddSizeÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_I2C_Mem_WriteìÚ ,hi2ccÚ, DevAddressäÚ, MemAddressäÚ, MemAddSizeÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_I2C_Mem_Read}Ú ,hi2ccÚ, DevAddressäÚ,
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TrialsdÚ,
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TimeoutêÚ HAL_I2C_IsDeviceReadylÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú# HAL_I2C_Master_Transmit_ITJÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú" HAL_I2C_Master_Receive_ITÛÚ ,hi2ccÚ,pDataÝÚ ,Size:Ú" HAL_I2C_Slave_Transmit_IT½Ú ,hi2ccÚ,pDataÝÚ ,Size:Ú! HAL_I2C_Slave_Receive_ITNÚ ,hi2ccÚ, DevAddressäÚ, MemAddressäÚ, MemAddSizeÚ,pDataÝÚ ,Size:Ú HAL_I2C_Mem_Write_ITêÚ ,hi2ccÚ, DevAddressäÚ, MemAddressäÚ, MemAddSizeÚ,pDataÝÚ ,Size:Ú HAL_I2C_Mem_Read_IT{Ú ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ' HAL_I2C_Master_Seq_Transmit_ITºÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ& HAL_I2C_Master_Seq_Receive_ITKÚ ,hi2ccÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ& HAL_I2C_Slave_Seq_Transmit_IT-Ú ,hi2ccÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ% HAL_I2C_Slave_Seq_Receive_IT¾Ú ,hi2ccÚ HAL_I2C_EnableListen_IT·Ú ,hi2ccÚ! HAL_I2C_DisableListen_ITHÚ ,hi2ccÚ, DevAddressäÚ HAL_I2C_Master_Abort_ITªÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú$ HAL_I2C_Master_Transmit_DMAÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú# HAL_I2C_Master_Receive_DMA¤Ú ,hi2ccÚ,pDataÝÚ ,Size:Ú# HAL_I2C_Slave_Transmit_DMAÚ ,hi2ccÚ,pDataÝÚ ,Size:Ú" HAL_I2C_Slave_Receive_DMAÚ ,hi2ccÚ, DevAddressäÚ, MemAddressäÚ, MemAddSizeÚ,pDataÝÚ ,Size:Ú HAL_I2C_Mem_Write_DMA³Ú ,hi2ccÚ, DevAddressäÚ, MemAddressäÚ, MemAddSizeÚ,pDataÝÚ ,Size:Ú HAL_I2C_Mem_Read_DMADÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ( HAL_I2C_Master_Seq_Transmit_DMAÚ ,hi2ccÚ, DevAddressäÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ' HAL_I2C_Master_Seq_Receive_DMAÚ ,hi2ccÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ' HAL_I2C_Slave_Seq_Transmit_DMAöÚ ,hi2ccÚ,pDataÝÚ ,Size:Ú,
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XferOptionsHÚ& HAL_I2C_Slave_Seq_Receive_DMAÚ ,hi2ccÚ HAL_I2C_EV_IRQHandlerÉÚ ,hi2ccÚ HAL_I2C_ER_IRQHandlerÍÚ ,hi2ccÚ% HAL_I2C_MasterTxCpltCallbackÚ ,hi2ccÚ% HAL_I2C_MasterRxCpltCallbackÚ ,hi2ccÚ$ HAL_I2C_SlaveTxCpltCallbackúÚ ,hi2ccÚ$ HAL_I2C_SlaveRxCpltCallbacküÚ ,hi2ccÚ,TransferDirectionÞÚ,AddrMatchCodeàÚ HAL_I2C_AddrCallbackçÚ ,hi2ccÚ# HAL_I2C_ListenCpltCallbackTÚ ,hi2ccÚ" HAL_I2C_MemTxCpltCallbackÚÚ ,hi2ccÚ" HAL_I2C_MemRxCpltCallbackÜÚ ,hi2ccÚ HAL_I2C_ErrorCallbackVÚ ,hi2ccÚ" HAL_I2C_AbortCpltCallbackÍÚ ,hi2ccÚ HAL_I2C_GetStateVÚ ,hi2ccÚ HAL_I2C_GetModeÔÚ ,hi2ccÚ HAL_I2C_GetErrorMÚ PIS_I2C_ADDRESSING_MODE Ú PIS_I2C_DUAL_ADDRESSÚ!PIS_I2C_OWN_ADDRESS2_MASKmÚ PIS_I2C_GENERAL_CALLÚPIS_I2C_NO_STRETCHxÚPIS_I2C_MEMADD_SIZEMÚPIS_TRANSFER_MODEÇÚ PIS_TRANSFER_REQUEST½Ú(P IS_I2C_TRANSFER_OPTIONS_REQUESTýÚ.P&IS_I2C_TRANSFER_OTHER_OPTIONS_REQUESTÚPI2C_RESET_CR2ëÚPI2C_GET_ADDR_MATCHdÚP I2C_GET_DIRzÚPI2C_GET_STOP_MODEÚ PI2C_GET_OWN_ADDRESS1½Ú PI2C_GET_OWN_ADDRESS2¼Ú PIS_I2C_OWN_ADDRESS1Ú PIS_I2C_OWN_ADDRESS2ÚPI2C_MEM_ADD_MSBHÚPI2C_MEM_ADD_LSBIÚPI2C_GENERATE_STARTRÚPI2C_CHECK_FLAG»Ú PI2C_CHECK_IT_SOURCEþÚ PHAL_I2S_MODULE_ENABLED,Ú PSTM32L0xx_HAL_IWDG_HyÚ8
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<unnamed>QÚ
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"
O
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PrescalerBÚ
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"
OReloadÚ
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"
OWindowqÚIWDG_InitTypeDefÚ8
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<unnamed>QÚ "O InstanceÚ " OInit:ÚIWDG_HandleTypeDefVÚPIWDG_PRESCALER_4íÚPIWDG_PRESCALER_8éÚPIWDG_PRESCALER_16¸ÚPIWDG_PRESCALER_32ºÚPIWDG_PRESCALER_64µÚPIWDG_PRESCALER_128ÚPIWDG_PRESCALER_256Ú PIWDG_WINDOW_DISABLEðÚP__HAL_IWDG_START¡Ú"P__HAL_IWDG_RELOAD_COUNTERçÚ,hiwdg´Ú HAL_IWDG_Init|Ú,hiwdg´Ú HAL_IWDG_Refresh;ÚPIWDG_KEY_RELOAD$ÚPIWDG_KEY_ENABLE4Ú%P IWDG_KEY_WRITE_ACCESS_ENABLE Ú&P IWDG_KEY_WRITE_ACCESS_DISABLEÐÚ!PIWDG_ENABLE_WRITE_ACCESSoÚ"PIWDG_DISABLE_WRITE_ACCESS ÚPIS_IWDG_PRESCALERÚPIS_IWDG_RELOADsÚPIS_IWDG_WINDOWRÚ PHAL_LCD_MODULE_ENABLED'Ú PSTM32L0xx_HAL_LPTIM_H Ú*P"LPTIM_EXTI_LINE_WAKEUPTIMER_EVENTUÚ8
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<unnamed>QÚ
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"¨OSourceUÚ
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"¨O
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Prescaler Ú!LPTIM_ClockConfigTypeDefùÚ8
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<unnamed>QÚ
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"¬O PolarityjÚ
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"¬O SampleTimeÉÚ$ LPTIM_ULPClockConfigTypeDefÚ8
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<unnamed>QÚ
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"°OSourceMÚ
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"°O ActiveEdgeåÚ
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"°O SampleTimeÅÚ#LPTIM_TriggerConfigTypeDef Ú8
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<unnamed>QÚ "µOClock¹Ú "µOUltraLowPowerClockXÚ " µOTriggerÉÚ
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"µOOutputPolarityÄÚ
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"µO UpdateModeÉÚ
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"µOCounterSourceZÚLPTIM_InitTypeDefµÚ HAL_LPTIM_STATE_RESETWÚ HAL_LPTIM_STATE_READYeÚ HAL_LPTIM_STATE_BUSYÚ HAL_LPTIM_STATE_TIMEOUT¯Ú HAL_LPTIM_STATE_ERRORPÚ HAL_LPTIM_StateTypeDef
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Ú8
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<unnamed>QÚ "ÃO InstancedÚ "(ÃOInitåÚ ""ÃOStatusÚ ""ÃOLockÚ ""ÃOStateÚ LPTIM_HandleTypeDefùÚ)P!LPTIM_CLOCKSOURCE_APBCLOCK_LPOSCëÚ!PLPTIM_CLOCKSOURCE_ULPTIM?Ú PLPTIM_PRESCALER_DIV1ªÚ PLPTIM_PRESCALER_DIV2©Ú PLPTIM_PRESCALER_DIV4§Ú PLPTIM_PRESCALER_DIV8£Ú PLPTIM_PRESCALER_DIV16rÚ PLPTIM_PRESCALER_DIV32tÚ PLPTIM_PRESCALER_DIV64oÚ PLPTIM_PRESCALER_DIV128<Ú"PLPTIM_OUTPUTPOLARITY_HIGHÐÚ!PLPTIM_OUTPUTPOLARITY_LOWÚ/P'LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITIONÚ+P#LPTIM_CLOCKSAMPLETIME_2TRANSITIONSVÚ+P#LPTIM_CLOCKSAMPLETIME_4TRANSITIONSTÚ+P#LPTIM_CLOCKSAMPLETIME_8TRANSITIONSPÚ#PLPTIM_CLOCKPOLARITY_RISING§Ú$P LPTIM_CLOCKPOLARITY_FALLINGtÚ+P#LPTIM_CLOCKPOLARITY_RISING_FALLING;Ú"PLPTIM_TRIGSOURCE_SOFTWAREãÚPLPTIM_TRIGSOURCE_0,ÚPLPTIM_TRIGSOURCE_1+ÚPLPTIM_TRIGSOURCE_2*ÚPLPTIM_TRIGSOURCE_3)ÚPLPTIM_TRIGSOURCE_4(ÚPLPTIM_TRIGSOURCE_5'ÚPLPTIM_TRIGSOURCE_6&ÚPLPTIM_TRIGSOURCE_7%Ú PLPTIM_ACTIVEEDGE_RISING¼Ú!PLPTIM_ACTIVEEDGE_FALLINGÚ(P LPTIM_ACTIVEEDGE_RISING_FALLINGPÚ.P&LPTIM_TRIGSAMPLETIME_DIRECTTRANSITIONPÚ*P"LPTIM_TRIGSAMPLETIME_2TRANSITIONSÚ*P"LPTIM_TRIGSAMPLETIME_4TRANSITIONSÚ*P"LPTIM_TRIGSAMPLETIME_8TRANSITIONSÚ PLPTIM_UPDATE_IMMEDIATE Ú!PLPTIM_UPDATE_ENDOFPERIODeÚ%P LPTIM_COUNTERSOURCE_INTERNALÚ%P LPTIM_COUNTERSOURCE_EXTERNALûÚPLPTIM_FLAG_DOWNÚPLPTIM_FLAG_UP®ÚPLPTIM_FLAG_ARROKÎÚPLPTIM_FLAG_CMPOKÓÚPLPTIM_FLAG_EXTTRIG"ÚPLPTIM_FLAG_ARRM ÚPLPTIM_FLAG_CMPM"ÚPLPTIM_IT_DOWNÚP LPTIM_IT_UP/ÚPLPTIM_IT_ARROKOÚPLPTIM_IT_CMPOKTÚPLPTIM_IT_EXTTRIG£ÚPLPTIM_IT_ARRMÚPLPTIM_IT_CMPM£Ú'P __HAL_LPTIM_RESET_HANDLE_STATEJÚP__HAL_LPTIM_ENABLE)Ú P__HAL_LPTIM_DISABLEÚÚ%P __HAL_LPTIM_START_CONTINUOUS¸Ú!P__HAL_LPTIM_START_SINGLEÚ#P__HAL_LPTIM_AUTORELOAD_SET
Ú P__HAL_LPTIM_COMPARE_SETtÚ P__HAL_LPTIM_GET_FLAGsÚ P__HAL_LPTIM_CLEAR_FLAGèÚ P__HAL_LPTIM_ENABLE_IT'Ú P__HAL_LPTIM_DISABLE_ITØÚ"P__HAL_LPTIM_GET_IT_SOURCE¶Ú/P'__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT¿Ú0P(__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_ITpÚ2P*__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENTÔÚ3P+__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT
Ú,hlptim7Ú HAL_LPTIM_Init Ú,hlptim7Ú HAL_LPTIM_DeInitrÚ,hlptim7Ú HAL_LPTIM_MspInitéÚ,hlptim7Ú HAL_LPTIM_MspDeInit<Ú,hlptim7Ú,
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PeriodpÚ,
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PulseÌÚ HAL_LPTIM_PWM_StartHÚ,hlptim7Ú HAL_LPTIM_PWM_Stop²Ú,hlptim7Ú,
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PeriodpÚ,
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PulseÌÚ HAL_LPTIM_PWM_Start_ITFÚ,hlptim7Ú HAL_LPTIM_PWM_Stop_IT°Ú,hlptim7Ú,
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PeriodpÚ,
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PulseÌÚ! HAL_LPTIM_OnePulse_StartÚ,hlptim7Ú HAL_LPTIM_OnePulse_StopqÚ,hlptim7Ú,
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PeriodpÚ,
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PulseÌÚ$ HAL_LPTIM_OnePulse_Start_ITÚ,hlptim7Ú# HAL_LPTIM_OnePulse_Stop_IToÚ,hlptim7Ú,
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PeriodpÚ,
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PulseÌÚ HAL_LPTIM_SetOnce_StartÚ,hlptim7Ú HAL_LPTIM_SetOnce_StopíÚ,hlptim7Ú,
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PeriodpÚ,
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PulseÌÚ# HAL_LPTIM_SetOnce_Start_ITÚ,hlptim7Ú" HAL_LPTIM_SetOnce_Stop_ITëÚ,hlptim7Ú,
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PeriodpÚ HAL_LPTIM_Encoder_StarttÚ,hlptim7Ú HAL_LPTIM_Encoder_StopÞÚ,hlptim7Ú,
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PeriodpÚ# HAL_LPTIM_Encoder_Start_ITrÚ,hlptim7Ú" HAL_LPTIM_Encoder_Stop_ITÜÚ,hlptim7Ú,
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PeriodpÚ,
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TimeoutêÚ HAL_LPTIM_TimeOut_StartmÚ,hlptim7Ú HAL_LPTIM_TimeOut_Stop×Ú,hlptim7Ú,
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PeriodpÚ,
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TimeoutêÚ# HAL_LPTIM_TimeOut_Start_ITkÚ,hlptim7Ú" HAL_LPTIM_TimeOut_Stop_ITÕÚ,hlptim7Ú,
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PeriodpÚ HAL_LPTIM_Counter_StartTÚ,hlptim7Ú HAL_LPTIM_Counter_Stop¾Ú,hlptim7Ú,
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PeriodpÚ# HAL_LPTIM_Counter_Start_ITRÚ,hlptim7Ú" HAL_LPTIM_Counter_Stop_IT¼Ú,hlptim7Ú HAL_LPTIM_ReadCounterIÚ,hlptim7Ú! HAL_LPTIM_ReadAutoReload3Ú,hlptim7Ú$ HAL_LPTIM_ReadCapturedValueèÚ,hlptim7Ú HAL_LPTIM_IRQHandlerýÚ,hlptim7Ú' HAL_LPTIM_CompareMatchCallbackÒÚ,hlptim7Ú* "HAL_LPTIM_AutoReloadMatchCallback£Ú,hlptim7Ú" HAL_LPTIM_TriggerCallback¼Ú,hlptim7Ú' HAL_LPTIM_CompareWriteCallback´Ú,hlptim7Ú* "HAL_LPTIM_AutoReloadWriteCallback
Ú,hlptim7Ú& HAL_LPTIM_DirectionUpCallback"Ú,hlptim7Ú( HAL_LPTIM_DirectionDownCallbackKÚ,hlptim7Ú HAL_LPTIM_GetStateÚ PIS_LPTIM_CLOCK_SOURCE%Ú!PIS_LPTIM_CLOCK_PRESCALEROÚ%P IS_LPTIM_CLOCK_PRESCALERDIV13Ú!PIS_LPTIM_OUTPUT_POLARITY÷Ú#PIS_LPTIM_CLOCK_SAMPLE_TIMEÚ PIS_LPTIM_CLOCK_POLARITY~Ú PIS_LPTIM_TRG_SOURCE¨Ú"PIS_LPTIM_EXT_TRG_POLARITY©Ú"PIS_LPTIM_TRIG_SAMPLE_TIMEÔÚ PIS_LPTIM_UPDATE_MODE|Ú PIS_LPTIM_COUNTER_SOURCEmÚ PIS_LPTIM_AUTORELOADÕÚPIS_LPTIM_COMPAREÄÚPIS_LPTIM_PERIOD
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ÚPIS_LPTIM_PULSEFÚ,hlptim7Ú LPTIM_Disable5Ú P__STM32L0xx_HAL_PWR_HëÚ8
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<unnamed>QÚ
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"
Q PVDLevelÚ
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"
QModefÚPWR_PVDTypeDefòÚPPWR_EXTI_LINE_PVDGÚPPWR_WAKEUP_PIN1ÚPPWR_WAKEUP_PIN2ÚPPWR_WAKEUP_PIN3ÚPPWR_PVDLEVEL_0fÚPPWR_PVDLEVEL_1eÚPPWR_PVDLEVEL_2dÚPPWR_PVDLEVEL_3cÚPPWR_PVDLEVEL_4bÚPPWR_PVDLEVEL_5aÚPPWR_PVDLEVEL_6`ÚPPWR_PVDLEVEL_7_Ú PPWR_PVD_MODE_NORMAL·Ú PPWR_PVD_MODE_IT_RISING²Ú PPWR_PVD_MODE_IT_FALLINGÚ'P PWR_PVD_MODE_IT_RISING_FALLINGFÚ"PPWR_PVD_MODE_EVENT_RISINGÇÚ#PPWR_PVD_MODE_EVENT_FALLINGÚ*P"PWR_PVD_MODE_EVENT_RISING_FALLING[Ú PPWR_MAINREGULATOR_ONuÚ!PPWR_LOWPOWERREGULATOR_ONÚPPWR_SLEEPENTRY_WFIÿÚPPWR_SLEEPENTRY_WFEÚPPWR_STOPENTRY_WFI4ÚPPWR_STOPENTRY_WFE8Ú%P PWR_REGULATOR_VOLTAGE_SCALE1 Ú%P PWR_REGULATOR_VOLTAGE_SCALE2 Ú%P PWR_REGULATOR_VOLTAGE_SCALE3Ú%P IS_PWR_VOLTAGE_SCALING_RANGEÚP PWR_FLAG_WU8ÚP PWR_FLAG_SBOÚPPWR_FLAG_PVDO§Ú PPWR_FLAG_VREFINTRDYÇÚP PWR_FLAG_VOSêÚPPWR_FLAG_REGLPdÚ(P __HAL_PWR_VOLTAGESCALING_CONFIGÚP__HAL_PWR_GET_FLAGÚ P__HAL_PWR_CLEAR_FLAGyÚ%P __HAL_PWR_PVD_EXTI_ENABLE_ITÄÚ&P __HAL_PWR_PVD_EXTI_DISABLE_ITuÚ(P __HAL_PWR_PVD_EXTI_ENABLE_EVENTÙÚ)P!__HAL_PWR_PVD_EXTI_DISABLE_EVENTÚ/P'__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGEÜÚ0P(__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGEÚ.P&__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGEÚ/P'__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGEÀÚ6P.__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE£Ú7P/__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGETÚ$P __HAL_PWR_PVD_EXTI_GET_FLAGÚ&P __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Ú)P!__HAL_PWR_PVD_EXTI_GENERATE_SWITnÚPIS_PWR_PVD_LEVELÚPIS_PWR_PVD_MODEìÚPIS_PWR_WAKEUP_PINCÚPIS_PWR_REGULATOR£ÚPIS_PWR_SLEEP_ENTRYêÚPIS_PWR_STOP_ENTRY Ú!P__STM32L0xx_HAL_PWR_EX_HéÚ%P __HAL_PWR_FLASHWAKEUP_ENABLEÚ&P __HAL_PWR_FLASHWAKEUP_DISABLE¹Ú" HAL_PWREx_GetVoltageRangeÚ# HAL_PWREx_EnableFastWakeUpIÚ$ HAL_PWREx_DisableFastWakeUpÚÚ& HAL_PWREx_EnableUltraLowPower×Ú' HAL_PWREx_DisableUltraLowPowerhÚ( HAL_PWREx_EnableLowPowerRunMode!Ú) !HAL_PWREx_DisableLowPowerRunMode²Ú HAL_PWR_DeInitÚ! HAL_PWR_EnableBkUpAccess!Ú" HAL_PWR_DisableBkUpAccess²Ú, sConfigPVD
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Ú HAL_PWR_ConfigPVDúÚ HAL_PWR_EnablePVD Ú HAL_PWR_DisablePVDÚ HAL_PWR_PVD_IRQHandler=Ú HAL_PWR_PVDCallback?Ú,
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WakeUpPinxßÚ HAL_PWR_EnableWakeUpPinsÚ,
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WakeUpPinxßÚ! HAL_PWR_DisableWakeUpPinÚ,
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RegulatorÚ,
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STOPEntry|Ú HAL_PWR_EnterSTOPModeiÚ,
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RegulatorÚ, SLEEPEntryGÚ HAL_PWR_EnterSLEEPMode4Ú! HAL_PWR_EnterSTANDBYModeÚ" HAL_PWR_EnableSleepOnExitÚ# HAL_PWR_DisableSleepOnExit$Ú HAL_PWR_EnableSEVOnPendµÚ! HAL_PWR_DisableSEVOnPendFÚ PHAL_RNG_MODULE_ENABLEDÚ PHAL_RTC_MODULE_ENABLEDÚ PSTM32L0xx_HAL_SPI_HºÚ8
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<unnamed>QÚ
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"çQModeÚ
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"çQ
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DirectionÞÚ
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"çQ DataSizelÚ
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"çQ CLKPolarityMÚ
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"çQ CLKPhase¶Ú
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"çQNSSÚ
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"çQBaudRatePrescalerÆÚ
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"çQ FirstBitZÚ
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"çQTIModecÚ
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"çQCRCCalculation.Ú
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"çQCRCPolynomial{ÚSPI_InitTypeDefSÚ HAL_SPI_STATE_RESETõÚ HAL_SPI_STATE_READYÚ HAL_SPI_STATE_BUSY7Ú HAL_SPI_STATE_BUSY_TX&Ú HAL_SPI_STATE_BUSY_RX(Ú! HAL_SPI_STATE_BUSY_TX_RXÚ HAL_SPI_STATE_ERRORîÚ HAL_SPI_STATE_ABORTÚ HAL_SPI_StateTypeDef¨Ú 8 __SPI_HandleTypeDefÚ "ýQ Instance(Ú ",ýQInit¥Ú "ýQ pTxBuffPtrdÚ "ýQ TxXferSizeiÚ "ýQ TxXferCountùÚ "ýQ pRxBuffPtrfÚ "ýQ RxXferSizekÚ "ýQ RxXferCountûÚ "ýQRxISR«Ú "ýQTxISR©Ú "ýQhdmatxÛÚ "ýQhdmarxÝÚ ""ýQLockÕÚ ""ýQState[Ú
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"ýQ
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ErrorCodeäÚSPI_HandleTypeDefÚPHAL_SPI_ERROR_NONEÚPHAL_SPI_ERROR_MODFÚPHAL_SPI_ERROR_CRCiÚPHAL_SPI_ERROR_OVRJÚPHAL_SPI_ERROR_FREdÚPHAL_SPI_ERROR_DMAoÚPHAL_SPI_ERROR_FLAG%Ú PHAL_SPI_ERROR_ABORTÅÚPSPI_MODE_SLAVEeÚPSPI_MODE_MASTERÚ PSPI_DIRECTION_2LINES«Ú$P SPI_DIRECTION_2LINES_RXONLYRÚ PSPI_DIRECTION_1LINEÚPSPI_DATASIZE_8BITÚPSPI_DATASIZE_16BITbÚPSPI_POLARITY_LOWÚPSPI_POLARITY_HIGHkÚPSPI_PHASE_1EDGELÚPSPI_PHASE_2EDGEKÚP SPI_NSS_SOFTÙÚPSPI_NSS_HARD_INPUTûÚ PSPI_NSS_HARD_OUTPUTÚ PSPI_BAUDRATEPRESCALER_2ØÚ PSPI_BAUDRATEPRESCALER_4ÖÚ PSPI_BAUDRATEPRESCALER_8ÒÚ!PSPI_BAUDRATEPRESCALER_16¡Ú!PSPI_BAUDRATEPRESCALER_32£Ú!PSPI_BAUDRATEPRESCALER_64Ú"PSPI_BAUDRATEPRESCALER_128kÚ"PSPI_BAUDRATEPRESCALER_256iÚPSPI_FIRSTBIT_MSB¸ÚPSPI_FIRSTBIT_LSB¹ÚPSPI_TIMODE_DISABLEGÚPSPI_TIMODE_ENABLEÚ#PSPI_CRCCALCULATION_DISABLEòÚ"PSPI_CRCCALCULATION_ENABLEAÚP SPI_IT_TXEÚP SPI_IT_RXNE1ÚP SPI_IT_ERRÚPSPI_FLAG_RXNE°ÚP SPI_FLAG_TXEþÚP SPI_FLAG_BSYÚPSPI_FLAG_CRCERR(ÚPSPI_FLAG_MODFÇÚP SPI_FLAG_OVRøÚP SPI_FLAG_FREÚPSPI_FLAG_MASKÁÚ%P __HAL_SPI_RESET_HANDLE_STATEèÚ P__HAL_SPI_ENABLE_ITÅÚ P__HAL_SPI_DISABLE_ITvÚ P__HAL_SPI_GET_IT_SOURCETÚP__HAL_SPI_GET_FLAGÚ#P__HAL_SPI_CLEAR_CRCERRFLAG¹Ú!P__HAL_SPI_CLEAR_MODFFLAGXÚ P__HAL_SPI_CLEAR_OVRFLAGÚ P__HAL_SPI_CLEAR_FREFLAG£ÚP__HAL_SPI_ENABLEÇÚP__HAL_SPI_DISABLExÚP SPI_1LINE_TXÚP SPI_1LINE_RXÚPSPI_RESET_CRC¬ÚPSPI_CHECK_FLAGÚ PSPI_CHECK_IT_SOURCEÐÚP IS_SPI_MODEJÚPIS_SPI_DIRECTIONÄÚ PIS_SPI_DIRECTION_2LINESªÚ)P!IS_SPI_DIRECTION_2LINES_OR_1LINEàÚPIS_SPI_DATASIZEÚP IS_SPI_CPOLAÚP IS_SPI_CPHASÚP IS_SPI_NSS}Ú"PIS_SPI_BAUDRATE_PRESCALER ÚPIS_SPI_FIRST_BITÚPIS_SPI_TIMODE©Ú PIS_SPI_CRC_CALCULATIONóÚ PIS_SPI_CRC_POLYNOMIAL ÚPIS_SPI_DMA_HANDLEÚ%P IS_SPI_16BIT_ALIGNED_ADDRESSOÚ ,hspiÚ HAL_SPI_Init½Ú ,hspiÚ HAL_SPI_DeInitÚ ,hspiÚ HAL_SPI_MspInitÚ ,hspiÚ HAL_SPI_MspDeInitÚÚ ,hspiÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_SPI_Transmit÷Ú ,hspiÚ,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_SPI_ReceiveÚ ,hspiÚ,pTxData Ú,pRxDataÚ ,Size:Ú,
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TimeoutêÚ HAL_SPI_TransmitReceive&Ú ,hspiÚ,pDataÝÚ ,Size:Ú HAL_SPI_Transmit_ITõÚ ,hspiÚ,pDataÝÚ ,Size:Ú HAL_SPI_Receive_ITÚ ,hspiÚ,pTxData Ú,pRxDataÚ ,Size:Ú# HAL_SPI_TransmitReceive_IT$Ú ,hspiÚ,pDataÝÚ ,Size:Ú HAL_SPI_Transmit_DMA¾Ú ,hspiÚ,pDataÝÚ ,Size:Ú HAL_SPI_Receive_DMAOÚ ,hspiÚ,pTxData Ú,pRxDataÚ ,Size:Ú$ HAL_SPI_TransmitReceive_DMAíÚ ,hspiÚ HAL_SPI_DMAPauseyÚ ,hspiÚ HAL_SPI_DMAResumeÚ ,hspiÚ HAL_SPI_DMAStopÓÚ ,hspiÚ HAL_SPI_AbortWÚ ,hspiÚ HAL_SPI_Abort_ITUÚ ,hspiÚ HAL_SPI_IRQHandlerÚ ,hspiÚ HAL_SPI_TxCpltCallbackÑÚ ,hspiÚ HAL_SPI_RxCpltCallbackÓÚ ,hspiÚ! HAL_SPI_TxRxCpltCallbackÚ ,hspiÚ# HAL_SPI_TxHalfCpltCallbackNÚ ,hspiÚ# HAL_SPI_RxHalfCpltCallbackPÚ ,hspiÚ% HAL_SPI_TxRxHalfCpltCallbackÚ ,hspiÚ HAL_SPI_ErrorCallback(Ú ,hspiÚ" HAL_SPI_AbortCpltCallbackÚ ,hspiÚ HAL_SPI_GetState(Ú ,hspiÚ HAL_SPI_GetError Ú PSTM32L0xx_HAL_TIM_H¼Ú8
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<unnamed>QÚ
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"¯S
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PrescalerÚ
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"¯S CounterModeLÚ
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"¯SPeriodXÚ
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"¯SClockDivision|Ú
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"¯SAutoReloadPreloadîÚ TIM_Base_InitTypeDefqÚ8
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<unnamed>QÚ
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"¶SOCModeÚ
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"¶SPulseÚ
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"¶S OCPolarityÆÚ
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"¶S OCFastModeÚTIM_OC_InitTypeDef^Ú8
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<unnamed>QÚ
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"¼SOCModeÚ
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"¼SPulse§Ú
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"¼S OCPolarityÀÚ
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"¼S ICPolarityÆÚ
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"¼S ICSelectionrÚ
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"¼S ICFilter¸Ú!TIM_OnePulse_InitTypeDef¹Ú8
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<unnamed>QÚ
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"ÄS ICPolarity¾Ú
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"ÄS ICSelectionjÚ
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"ÄS ICPrescaleroÚ
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"ÄS ICFilter°ÚTIM_IC_InitTypeDefdÚ8
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<unnamed>QÚ
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"ÊS EncoderModeQÚ
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"ÊS IC1Polarity
Ú
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"ÊS IC1Selection1Ú
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"ÊS IC1Prescaler6Ú
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"ÊS
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IC1FilterwÚ
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"ÊS IC2PolarityÚ
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"ÊS IC2Selection0Ú
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"ÊS IC2Prescaler5Ú
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"ÊS
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IC2FiltervÚ TIM_Encoder_InitTypeDef&Ú8
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<unnamed>QÚ
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"ÕS ClockSource.Ú
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"ÕSClockPolarityGÚ
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"ÕSClockPrescalerøÚ
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"ÕS ClockFilter9Ú TIM_ClockConfigTypeDefÚ8
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<unnamed>QÚ
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"ÛSClearInputState
Ú
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"ÛSClearInputSourceÚ
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"ÛSClearInputPolarity,Ú
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"ÛSClearInputPrescalerÝÚ
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"ÛSClearInputFilter Ú$ TIM_ClearInputConfigTypeDefÚ8
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<unnamed>QÚ
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"âSMasterOutputTriggerÚ
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"âSMasterSlaveModeÚ TIM_MasterConfigTypeDefÚ8
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<unnamed>QÚ
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"æS
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SlaveModeþÚ
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"æS InputTriggerÚ
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"æSTriggerPolarityJÚ
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"æSTriggerPrescalerûÚ
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"æSTriggerFilter<Ú TIM_SlaveConfigTypeDefÚ HAL_TIM_STATE_RESET÷Ú HAL_TIM_STATE_READYÚ HAL_TIM_STATE_BUSY9Ú HAL_TIM_STATE_TIMEOUTOÚ HAL_TIM_STATE_ERRORðÚ HAL_TIM_StateTypeDefªÚ$ HAL_TIM_CHANNEL_STATE_RESETÚ$ HAL_TIM_CHANNEL_STATE_READYÚ# HAL_TIM_CHANNEL_STATE_BUSYÑÚ$ HAL_TIM_ChannelStateTypeDefãÚ" HAL_DMA_BURST_STATE_RESETÚ" HAL_DMA_BURST_STATE_READY"Ú! HAL_DMA_BURST_STATE_BUSYVÚ% HAL_TIM_DMABurstStateTypeDef¸Ú! HAL_TIM_ACTIVE_CHANNEL_1¬Ú! HAL_TIM_ACTIVE_CHANNEL_2«Ú! HAL_TIM_ACTIVE_CHANNEL_3ªÚ! HAL_TIM_ACTIVE_CHANNEL_4©Ú' HAL_TIM_ACTIVE_CHANNEL_CLEAREDáÚ HAL_TIM_ActiveChannelEÚ8
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<unnamed>QÚ "T Instance¡Ú "TInit6Ú ""TChannelÚ <" ThdmaÚ ""TLockNÚ ""TStateÔÚ <"T ChannelStateðÚ ""TDMABurstStateâÚTIM_HandleTypeDefÚ"PTIM_CLEARINPUTSOURCE_NONEùÚ!PTIM_CLEARINPUTSOURCE_ETR@ÚPTIM_DMABASE_CR1RÚPTIM_DMABASE_CR2QÚPTIM_DMABASE_SMCRáÚPTIM_DMABASE_DIERòÚPTIM_DMABASE_SRuÚPTIM_DMABASE_EGR:ÚPTIM_DMABASE_CCMR1¾ÚPTIM_DMABASE_CCMR2½ÚPTIM_DMABASE_CCERùÚPTIM_DMABASE_CNT3ÚPTIM_DMABASE_PSC2ÚPTIM_DMABASE_ARR3ÚPTIM_DMABASE_CCR1 ÚPTIM_DMABASE_CCR2 ÚPTIM_DMABASE_CCR3 ÚPTIM_DMABASE_CCR4
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ÚPTIM_DMABASE_DCR?ÚPTIM_DMABASE_DMARòÚPTIM_DMABASE_ORyÚ PTIM_EVENTSOURCE_UPDATEáÚ PTIM_EVENTSOURCE_CC1óÚ PTIM_EVENTSOURCE_CC2òÚ PTIM_EVENTSOURCE_CC3ñÚ PTIM_EVENTSOURCE_CC4ðÚ PTIM_EVENTSOURCE_TRIGGERÚ(P TIM_INPUTCHANNELPOLARITY_RISING Ú)P!TIM_INPUTCHANNELPOLARITY_FALLINGéÚ*P"TIM_INPUTCHANNELPOLARITY_BOTHEDGE¢Ú!PTIM_ETRPOLARITY_INVERTED3Ú$P TIM_ETRPOLARITY_NONINVERTEDBÚ PTIM_ETRPRESCALER_DIV1YÚ PTIM_ETRPRESCALER_DIV2XÚ PTIM_ETRPRESCALER_DIV4VÚ PTIM_ETRPRESCALER_DIV8RÚPTIM_COUNTERMODE_UPÚ PTIM_COUNTERMODE_DOWN~Ú'P TIM_COUNTERMODE_CENTERALIGNED1¼Ú'P TIM_COUNTERMODE_CENTERALIGNED2»Ú'P TIM_COUNTERMODE_CENTERALIGNED3ºÚ PTIM_CLOCKDIVISION_DIV1Ú PTIM_CLOCKDIVISION_DIV2Ú PTIM_CLOCKDIVISION_DIV4Ú PTIM_OUTPUTSTATE_DISABLEÚ PTIM_OUTPUTSTATE_ENABLEÞÚ'P TIM_AUTORELOAD_PRELOAD_DISABLEÚ&P TIM_AUTORELOAD_PRELOAD_ENABLEìÚPTIM_OCFAST_DISABLEKÚPTIM_OCFAST_ENABLEÚ!PTIM_OUTPUTNSTATE_DISABLE?Ú PTIM_OUTPUTNSTATE_ENABLEÚ PTIM_OCPOLARITY_HIGH×ÚPTIM_OCPOLARITY_LOWÚ PTIM_ICPOLARITY_RISING-Ú PTIM_ICPOLARITY_FALLINGúÚ PTIM_ICPOLARITY_BOTHEDGE³Ú(P TIM_ENCODERINPUTPOLARITY_RISINGÚ)P!TIM_ENCODERINPUTPOLARITY_FALLINGâÚ!PTIM_ICSELECTION_DIRECTTIiÚ#PTIM_ICSELECTION_INDIRECTTIÎÚ PTIM_ICSELECTION_TRCâÚPTIM_ICPSC_DIV1ÚPTIM_ICPSC_DIV2ÚPTIM_ICPSC_DIV4~ÚPTIM_ICPSC_DIV8zÚPTIM_OPMODE_SINGLE{Ú PTIM_OPMODE_REPETITIVE4Ú PTIM_ENCODERMODE_TI1
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Ú PTIM_ENCODERMODE_TI2 Ú PTIM_ENCODERMODE_TI12ÖÚPTIM_IT_UPDATE©ÚP TIM_IT_CC1»ÚP TIM_IT_CC2ºÚP TIM_IT_CC3¹ÚP TIM_IT_CC4¸ÚPTIM_IT_TRIGGERVÚPTIM_DMA_UPDATErÚP TIM_DMA_CC1ÚP TIM_DMA_CC2ÚP TIM_DMA_CC3ÚP TIM_DMA_CC4ÚPTIM_DMA_TRIGGER Ú PTIM_CCDMAREQUEST_CCöÚ PTIM_CCDMAREQUEST_UPDATE±ÚPTIM_FLAG_UPDATE(ÚP TIM_FLAG_CC1:ÚP TIM_FLAG_CC29ÚP TIM_FLAG_CC38ÚP TIM_FLAG_CC47ÚPTIM_FLAG_TRIGGERÕÚPTIM_FLAG_CC1OF¡ÚPTIM_FLAG_CC2OF ÚPTIM_FLAG_CC3OFÚPTIM_FLAG_CC4OFÚPTIM_CHANNEL_1ßÚPTIM_CHANNEL_2ÞÚPTIM_CHANNEL_3ÝÚPTIM_CHANNEL_4ÜÚPTIM_CHANNEL_ALL3Ú!PTIM_CLOCKSOURCE_INTERNALYÚ!PTIM_CLOCKSOURCE_ETRMODE1uÚ!PTIM_CLOCKSOURCE_ETRMODE2tÚ PTIM_CLOCKSOURCE_TI1EDeÚ PTIM_CLOCKSOURCE_TI1òÚ PTIM_CLOCKSOURCE_TI2ñÚ PTIM_CLOCKSOURCE_ITR0Ú PTIM_CLOCKSOURCE_ITR1Ú PTIM_CLOCKSOURCE_ITR2Ú PTIM_CLOCKSOURCE_ITR3Ú#PTIM_CLOCKPOLARITY_INVERTED®Ú&P TIM_CLOCKPOLARITY_NONINVERTED½Ú!PTIM_CLOCKPOLARITY_RISINGGÚ"PTIM_CLOCKPOLARITY_FALLINGÚ#PTIM_CLOCKPOLARITY_BOTHEDGEÍÚ PTIM_CLOCKPRESCALER_DIV1ÔÚ PTIM_CLOCKPRESCALER_DIV2ÓÚ PTIM_CLOCKPRESCALER_DIV4ÑÚ PTIM_CLOCKPRESCALER_DIV8ÍÚ(P TIM_CLEARINPUTPOLARITY_INVERTEDÚ+P#TIM_CLEARINPUTPOLARITY_NONINVERTED(Ú%P TIM_CLEARINPUTPRESCALER_DIV1?Ú%P TIM_CLEARINPUTPRESCALER_DIV2>Ú%P TIM_CLEARINPUTPRESCALER_DIV4<Ú%P TIM_CLEARINPUTPRESCALER_DIV88ÚPTIM_TRGO_RESETHÚPTIM_TRGO_ENABLE"ÚPTIM_TRGO_UPDATEÚP TIM_TRGO_OC1 ÚPTIM_TRGO_OC1REF)ÚPTIM_TRGO_OC2REF(ÚPTIM_TRGO_OC3REF'ÚPTIM_TRGO_OC4REF&Ú#PTIM_MASTERSLAVEMODE_ENABLEÜÚ$P TIM_MASTERSLAVEMODE_DISABLEÚ PTIM_SLAVEMODE_DISABLEeÚ PTIM_SLAVEMODE_RESETÚÚ PTIM_SLAVEMODE_GATEDøÚ PTIM_SLAVEMODE_TRIGGEREÚ PTIM_SLAVEMODE_EXTERNAL1ÁÚPTIM_OCMODE_TIMINGÚPTIM_OCMODE_ACTIVEÚ PTIM_OCMODE_INACTIVEóÚPTIM_OCMODE_TOGGLEÚPTIM_OCMODE_PWM1)ÚPTIM_OCMODE_PWM2(Ú!PTIM_OCMODE_FORCED_ACTIVEnÚ#PTIM_OCMODE_FORCED_INACTIVEÓÚP TIM_TS_ITR0GÚP TIM_TS_ITR1FÚP TIM_TS_ITR2EÚP TIM_TS_ITR3DÚPTIM_TS_TI1F_EDdÚPTIM_TS_TI1FP1ÍÚPTIM_TS_TI2FP2ËÚP TIM_TS_ETRF5ÚP TIM_TS_NONE6Ú%P TIM_TRIGGERPOLARITY_INVERTEDÚ(P TIM_TRIGGERPOLARITY_NONINVERTEDÚ#PTIM_TRIGGERPOLARITY_RISINGÚ$P TIM_TRIGGERPOLARITY_FALLINGhÚ%P TIM_TRIGGERPOLARITY_BOTHEDGE!Ú"PTIM_TRIGGERPRESCALER_DIV1(Ú"PTIM_TRIGGERPRESCALER_DIV2'Ú"PTIM_TRIGGERPRESCALER_DIV4%Ú"PTIM_TRIGGERPRESCALER_DIV8!Ú PTIM_TI1SELECTION_CH1ËÚ(P TIM_TI1SELECTION_XORCOMBINATIONEÚ%P TIM_DMABURSTLENGTH_1TRANSFER1Ú&P TIM_DMABURSTLENGTH_2TRANSFERSÛÚ&P TIM_DMABURSTLENGTH_3TRANSFERSÚÚ&P TIM_DMABURSTLENGTH_4TRANSFERSÙÚ&P TIM_DMABURSTLENGTH_5TRANSFERSØÚ&P TIM_DMABURSTLENGTH_6TRANSFERS×Ú&P TIM_DMABURSTLENGTH_7TRANSFERSÖÚ&P TIM_DMABURSTLENGTH_8TRANSFERSÕÚ&P TIM_DMABURSTLENGTH_9TRANSFERSÔÚ'P TIM_DMABURSTLENGTH_10TRANSFERSªÚ'P TIM_DMABURSTLENGTH_11TRANSFERS©Ú'P TIM_DMABURSTLENGTH_12TRANSFERS¨Ú'P TIM_DMABURSTLENGTH_13TRANSFERS§Ú'P TIM_DMABURSTLENGTH_14TRANSFERS¦Ú'P TIM_DMABURSTLENGTH_15TRANSFERS¥Ú'P TIM_DMABURSTLENGTH_16TRANSFERS¤Ú'P TIM_DMABURSTLENGTH_17TRANSFERS£Ú'P TIM_DMABURSTLENGTH_18TRANSFERS¢ÚPTIM_DMA_ID_UPDATEÚPTIM_DMA_ID_CC1ÚPTIM_DMA_ID_CC2ÚPTIM_DMA_ID_CC3ÚPTIM_DMA_ID_CC4ÚPTIM_DMA_ID_TRIGGER-ÚPTIM_CCx_ENABLEbÚPTIM_CCx_DISABLEÚ%P __HAL_TIM_RESET_HANDLE_STATEêÚP__HAL_TIM_ENABLEÉÚP__HAL_TIM_DISABLEzÚ P__HAL_TIM_ENABLE_ITÇÚ P__HAL_TIM_DISABLE_ITxÚ P__HAL_TIM_ENABLE_DMAÚ P__HAL_TIM_DISABLE_DMAAÚP__HAL_TIM_GET_FLAGÚ P__HAL_TIM_CLEAR_FLAGÚ P__HAL_TIM_GET_IT_SOURCEVÚP__HAL_TIM_CLEAR_IT Ú'P __HAL_TIM_IS_TIM_COUNTING_DOWNÚ P__HAL_TIM_SET_PRESCALERvÚ P__HAL_TIM_SET_COUNTERûÚ P__HAL_TIM_GET_COUNTERÚ!P__HAL_TIM_SET_AUTORELOAD%Ú!P__HAL_TIM_GET_AUTORELOAD1Ú$P __HAL_TIM_SET_CLOCKDIVISION>Ú$P __HAL_TIM_GET_CLOCKDIVISIONJÚ"P__HAL_TIM_SET_ICPRESCALERæÚ"P__HAL_TIM_GET_ICPRESCALERòÚ P__HAL_TIM_SET_COMPAREÚ P__HAL_TIM_GET_COMPARE Ú$P __HAL_TIM_ENABLE_OCxPRELOADCÚ%P __HAL_TIM_DISABLE_OCxPRELOADôÚ!P__HAL_TIM_ENABLE_OCxFAST"Ú"P__HAL_TIM_DISABLE_OCxFASTÓÚ P__HAL_TIM_URS_ENABLEhÚ P__HAL_TIM_URS_DISABLEÚ&P __HAL_TIM_SET_CAPTUREPOLARITYÚ&P __HAL_TIM_SELECT_CCDMAREQUEST¶ÚPTIM_CCER_CCxE_MASKÚ!PIS_TIM_CLEARINPUT_SOURCE0ÚPIS_TIM_DMA_BASE Ú PIS_TIM_EVENT_SOURCE¯Ú PIS_TIM_COUNTER_MODE½Ú!PIS_TIM_CLOCKDIVISION_DIVDÚ"PIS_TIM_AUTORELOAD_PRELOADÿÚPIS_TIM_FAST_STATEWÚPIS_TIM_OC_POLARITYþÚ%P IS_TIM_ENCODERINPUT_POLARITYìÚPIS_TIM_IC_POLARITYÚ PIS_TIM_IC_SELECTIONÐÚ PIS_TIM_IC_PRESCALERÕÚPIS_TIM_OPM_MODEùÚ PIS_TIM_ENCODER_MODEÝÚPIS_TIM_DMA_SOURCEcÚPIS_TIM_CHANNELS Ú PIS_TIM_OPM_CHANNELSÊÚPIS_TIM_PERIODªÚPIS_TIM_PRESCALERÆÚPIS_TIM_CLOCKSOURCE&Ú PIS_TIM_CLOCKPOLARITYÚ PIS_TIM_CLOCKPRESCALERPÚPIS_TIM_CLOCKFILTER1Ú#PIS_TIM_CLEARINPUT_POLARITYÚ$P IS_TIM_CLEARINPUT_PRESCALERZÚ!PIS_TIM_CLEARINPUT_FILTER;ÚPIS_TIM_TRGO_SOURCE÷ÚPIS_TIM_MSM_STATEÚPIS_TIM_SLAVE_MODEfÚPIS_TIM_PWM_MODEñÚPIS_TIM_OC_MODEUÚ!PIS_TIM_TRIGGER_SELECTION>Ú/P'IS_TIM_INTERNAL_TRIGGEREVENT_SELECTIONäÚ PIS_TIM_TRIGGERPOLARITYÓÚ PIS_TIM_TRIGGERPRESCALER¤Ú PIS_TIM_TRIGGERFILTER
Ú PIS_TIM_TI1SELECTIONíÚPIS_TIM_DMA_LENGTHrÚ PIS_TIM_DMA_DATA_LENGTHïÚPIS_TIM_IC_FILTER¶Ú)P!IS_TIM_SLAVEMODE_TRIGGER_ENABLEDêÚ!PTIM_SET_ICPRESCALERVALUE]Ú#PTIM_RESET_ICPRESCALERVALUEÂÚ PTIM_SET_CAPTUREPOLARITYÚ"PTIM_RESET_CAPTUREPOLARITYæÚ PTIM_CHANNEL_STATE_GET@Ú PTIM_CHANNEL_STATE_SET4Ú"PTIM_CHANNEL_STATE_SET_ALLôÚ PSTM32L0xx_HAL_TIM_EX_HºÚPTIM2_ETR_GPIO½ÚPTIM2_ETR_HSI16ÚP TIM2_ETR_LSE
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ÚPTIM2_ETR_COMP2_OUT*ÚPTIM2_ETR_COMP1_OUT+ÚPTIM2_TI4_GPIO×ÚPTIM2_TI4_COMP2£ÚPTIM2_TI4_COMP1¤Ú PTIM3_TI4_GPIOC9_AF26ÚPTIM3_TI2_GPIO_DEF¢Ú PTIM3_TI2_GPIOB5_AF4;ÚPTIM3_TI1_GPIOÙÚPTIM3_ETR_GPIO¼ÚP TIM3_ETR_HSI ÚPTIM21_ETR_GPIOÚ PTIM21_ETR_COMP2_OUT÷Ú PTIM21_ETR_COMP1_OUTøÚPTIM21_ETR_LSE×ÚPTIM21_TI1_GPIO§ÚPTIM21_TI1_MCOùÚ PTIM21_TI1_RTC_WKUT_IT9ÚPTIM21_TI1_HSE_RTC¨ÚPTIM21_TI1_MSIïÚPTIM21_TI1_LSEôÚPTIM21_TI1_LSIðÚ PTIM21_TI1_COMP1_OUTÚPTIM21_TI2_GPIO¦Ú PTIM21_TI2_COMP2_OUTÚPTIM22_ETR_GPIOÚ PTIM22_ETR_COMP2_OUTöÚ PTIM22_ETR_COMP1_OUT÷ÚPTIM22_ETR_LSEÖÚPTIM22_TI1_GPIO¦Ú PTIM22_TI1_COMP2_OUTÚ PTIM22_TI1_COMP1_OUTÚP IS_TIM_REMAPúÚ PIS_CHANNEL_AVAILABLEÏÚ ,htimÚ,sMasterConfigÚ. &HAL_TIMEx_MasterConfigSynchronizationPÚ ,htimÚ,
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RemapàÚ HAL_TIMEx_RemapConfig9Ú ,htimÚ HAL_TIM_Base_InitÛÚ ,htimÚ HAL_TIM_Base_DeInit.Ú ,htimÚ HAL_TIM_Base_MspInit¥Ú ,htimÚ HAL_TIM_Base_MspDeInitøÚ ,htimÚ HAL_TIM_Base_Start_Ú ,htimÚ HAL_TIM_Base_StopÉÚ ,htimÚ HAL_TIM_Base_Start_IT]Ú ,htimÚ HAL_TIM_Base_Stop_ITÇÚ ,htimÚ,pDataÝÚ,LengthoÚ HAL_TIM_Base_Start_DMA&Ú ,htimÚ HAL_TIM_Base_Stop_DMAÚ ,htimÚ HAL_TIM_OC_InitÈÚ ,htimÚ HAL_TIM_OC_DeInitÚ ,htimÚ HAL_TIM_OC_MspInitÚ ,htimÚ HAL_TIM_OC_MspDeInitåÚ ,htimÚ,
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ChannelÚ HAL_TIM_OC_StartLÚ ,htimÚ,
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ChannelÚ HAL_TIM_OC_Stop¶Ú ,htimÚ,
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ChannelÚ HAL_TIM_OC_Start_ITJÚ ,htimÚ,
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ChannelÚ HAL_TIM_OC_Stop_IT´Ú ,htimÚ,
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ChannelÚ,pDataÝÚ,LengthoÚ HAL_TIM_OC_Start_DMAÚ ,htimÚ,
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ChannelÚ HAL_TIM_OC_Stop_DMA}Ú ,htimÚ HAL_TIM_PWM_InitdÚ ,htimÚ HAL_TIM_PWM_DeInit·Ú ,htimÚ HAL_TIM_PWM_MspInit.Ú ,htimÚ HAL_TIM_PWM_MspDeInitÚ ,htimÚ,
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ChannelÚ HAL_TIM_PWM_StartèÚ ,htimÚ,
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ChannelÚ HAL_TIM_PWM_StopRÚ ,htimÚ,
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ChannelÚ HAL_TIM_PWM_Start_ITæÚ ,htimÚ,
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ChannelÚ HAL_TIM_PWM_Stop_ITPÚ ,htimÚ,
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ChannelÚ,pDataÝÚ,LengthoÚ HAL_TIM_PWM_Start_DMA¯Ú ,htimÚ,
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ChannelÚ HAL_TIM_PWM_Stop_DMAÚ ,htimÚ HAL_TIM_IC_InitÎÚ ,htimÚ HAL_TIM_IC_DeInit!Ú ,htimÚ HAL_TIM_IC_MspInitÚ ,htimÚ HAL_TIM_IC_MspDeInitëÚ ,htimÚ,
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ChannelÚ HAL_TIM_IC_StartRÚ ,htimÚ,
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ChannelÚ HAL_TIM_IC_Stop¼Ú ,htimÚ,
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ChannelÚ HAL_TIM_IC_Start_ITPÚ ,htimÚ,
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ChannelÚ HAL_TIM_IC_Stop_ITºÚ ,htimÚ,
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ChannelÚ,pDataÝÚ,LengthoÚ HAL_TIM_IC_Start_DMAÚ ,htimÚ,
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ChannelÚ HAL_TIM_IC_Stop_DMAÚ ,htimÚ,
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OnePulseModeÚ HAL_TIM_OnePulse_Init#Ú ,htimÚ HAL_TIM_OnePulse_DeInitvÚ ,htimÚ! HAL_TIM_OnePulse_MspInitíÚ ,htimÚ# HAL_TIM_OnePulse_MspDeInit@Ú ,htimÚ,
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OutputChannel{Ú HAL_TIM_OnePulse_Start§Ú ,htimÚ,
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OutputChannel{Ú HAL_TIM_OnePulse_StopÚ ,htimÚ,
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OutputChannel{Ú" HAL_TIM_OnePulse_Start_IT¥Ú ,htimÚ,
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OutputChannel{Ú! HAL_TIM_OnePulse_Stop_ITÚ ,htimÚ,sConfigúÚ HAL_TIM_Encoder_InitÚ ,htimÚ HAL_TIM_Encoder_DeInitãÚ ,htimÚ HAL_TIM_Encoder_MspInitZÚ ,htimÚ" HAL_TIM_Encoder_MspDeInitÚ ,htimÚ,
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ChannelÚ HAL_TIM_Encoder_StartÚ ,htimÚ,
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ChannelÚ HAL_TIM_Encoder_Stop~Ú ,htimÚ,
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ChannelÚ! HAL_TIM_Encoder_Start_ITÚ ,htimÚ,
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ChannelÚ HAL_TIM_Encoder_Stop_IT|Ú ,htimÚ,
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ChannelÚ,pData1ªÚ,pData2©Ú,LengthoÚ" HAL_TIM_Encoder_Start_DMAÛÚ ,htimÚ,
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ChannelÚ! HAL_TIM_Encoder_Stop_DMAEÚ ,htimÚ HAL_TIM_IRQHandlerÚ ,htimÚ,sConfigúÚ,
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ChannelÚ! HAL_TIM_OC_ConfigChannel;Ú ,htimÚ,sConfigúÚ,
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ChannelÚ" HAL_TIM_PWM_ConfigChannel×Ú ,htimÚ,sConfigúÚ,
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ChannelÚ! HAL_TIM_IC_ConfigChannelAÚ ,htimÚ,sConfigúÚ,
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OutputChannel{Ú,
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InputChannelþÚ' HAL_TIM_OnePulse_ConfigChannelÚ ,htimÚ,sClearInputConfigïÚ,
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ChannelÚ! HAL_TIM_ConfigOCrefClear/Ú ,htimÚ,sClockSourceConfigÚ" HAL_TIM_ConfigClockSourceÚ ,htimÚ,
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TI1_SelectionòÚ HAL_TIM_ConfigTI1Input Ú ,htimÚ, sSlaveConfigõÚ# HAL_TIM_SlaveConfigSynchroÚ ,htimÚ, sSlaveConfigõÚ& HAL_TIM_SlaveConfigSynchro_ITþÚ ,htimÚ,
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BurstBaseAddressnÚ,
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BurstRequestSrc Ú, BurstBufferQÚ,
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BurstLengthWÚ$ HAL_TIM_DMABurst_WriteStartÛÚ ,htimÚ,
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BurstBaseAddressnÚ,
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BurstRequestSrc Ú, BurstBufferQÚ,
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BurstLengthWÚ,
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DataLengthïÚ) !HAL_TIM_DMABurst_MultiWriteStartÆÚ ,htimÚ,
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BurstRequestSrc Ú# HAL_TIM_DMABurst_WriteStopEÚ ,htimÚ,
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BurstBaseAddressnÚ,
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BurstRequestSrc Ú, BurstBufferQÚ,
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BurstLengthWÚ# HAL_TIM_DMABurst_ReadStartlÚ ,htimÚ,
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BurstBaseAddressnÚ,
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BurstRequestSrc Ú, BurstBufferQÚ,
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BurstLengthWÚ,
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DataLengthïÚ( HAL_TIM_DMABurst_MultiReadStartWÚ ,htimÚ,
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BurstRequestSrc Ú" HAL_TIM_DMABurst_ReadStopÖÚ ,htimÚ,
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EventSourceVÚ HAL_TIM_GenerateEventÚ ,htimÚ,
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ChannelÚ" HAL_TIM_ReadCapturedValueÚ ,htimÚ& HAL_TIM_PeriodElapsedCallbackÚ ,htimÚ. &HAL_TIM_PeriodElapsedHalfCpltCallbackåÚ ,htimÚ( HAL_TIM_OC_DelayElapsedCallbackÚ ,htimÚ# HAL_TIM_IC_CaptureCallbackkÚ ,htimÚ+ #HAL_TIM_IC_CaptureHalfCpltCallbackMÚ ,htimÚ* "HAL_TIM_PWM_PulseFinishedCallbackÚ ,htimÚ2 *HAL_TIM_PWM_PulseFinishedHalfCpltCallbackxÚ ,htimÚ HAL_TIM_TriggerCallback\Ú ,htimÚ( HAL_TIM_TriggerHalfCpltCallback>Ú ,htimÚ HAL_TIM_ErrorCallback*Ú ,htimÚ HAL_TIM_Base_GetStateFÚ ,htimÚ HAL_TIM_OC_GetState3Ú ,htimÚ HAL_TIM_PWM_GetStateÏÚ ,htimÚ HAL_TIM_IC_GetState9Ú ,htimÚ" HAL_TIM_OnePulse_GetStateÚ ,htimÚ! HAL_TIM_Encoder_GetStateûÚ ,htimÚ! HAL_TIM_GetActiveChannelÚ ,htimÚ,
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ChannelÚ HAL_TIM_GetChannelStatecÚ ,htimÚ HAL_TIM_DMABurstState^Ú ,hdma/Ú TIM_DMAError«Ú ,hdma/Ú TIM_DMACaptureCpltBÚ ,hdma/Ú TIM_DMACaptureHalfCplt¿Ú PHAL_TSC_MODULE_ENABLEDÚ PSTM32L0xx_HAL_UART_HhÚ8
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<unnamed>QÚ
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"ÞX BaudRate{Ú
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"ÞX WordLengthÚ
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"ÞX StopBitsKÚ
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"ÞXParityÚ
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"ÞXModeÚ
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"ÞX
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HwFlowCtlÚ
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"ÞX OverSampling¤Ú
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"ÞXOneBitSamplingûÚUART_InitTypeDefÚ8
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<unnamed>QÚ
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"èXAdvFeatureInitòÚ
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"èXTxPinLevelInvertÚ
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"èXRxPinLevelInvertÚ
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"èX DataInvertÚ
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"èXSwapæÚ
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"èXOverrunDisableÈÚ
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"èXDMADisableonRxError,Ú
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"èXAutoBaudRateEnable}Ú
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"èXAutoBaudRateModeCÚ
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"èX MSBFirstÚ#UART_AdvFeatureInitTypeDefÚ HAL_UART_StateTypeDefVÚ UART_CLOCKSOURCE_PCLK1?Ú UART_CLOCKSOURCE_PCLK2>Ú UART_CLOCKSOURCE_HSIºÚ UART_CLOCKSOURCE_SYSCLK¿Ú UART_CLOCKSOURCE_LSEºÚ# UART_CLOCKSOURCE_UNDEFINEDÚ UART_ClockSourceTypeDef*Ú HAL_UART_RxTypeTypeDeféÚ$ HAL_UART_RxEventTypeTypeDefÝÚ 8 __UART_HandleTypeDefGÚ "þX Instance Ú " þXInit©Ú "(þX AdvancedInit{Ú "þX pTxBuffPtr\Ú "þX TxXferSizeaÚ "þX TxXferCountñÚ "þX pRxBuffPtr^Ú "þX RxXferSizecÚ "þX RxXferCountóÚ "þXMaskÝÚ
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"þXReceptionTypeÚ
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"þX RxEventTypeïÚ "þXRxISR£Ú "þXTxISR¡Ú "þXhdmatxÓÚ "þXhdmarxÕÚ ""þXLockÍÚ
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"þXgStateÿÚ
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"þXRxStateÚ
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"þX
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ErrorCodeÜÚUART_HandleTypeDefEÚ PHAL_UART_STATE_RESETqÚ PHAL_UART_STATE_READYÚ PHAL_UART_STATE_BUSY³Ú PHAL_UART_STATE_BUSY_TX¢Ú PHAL_UART_STATE_BUSY_RX¤Ú"PHAL_UART_STATE_BUSY_TX_RXÚ PHAL_UART_STATE_TIMEOUTÉÚ PHAL_UART_STATE_ERRORjÚ PHAL_UART_ERROR_NONE½ÚPHAL_UART_ERROR_PE\ÚPHAL_UART_ERROR_NE^ÚPHAL_UART_ERROR_FEfÚPHAL_UART_ERROR_ORE ÚPHAL_UART_ERROR_DMA ÚPHAL_UART_ERROR_RTOúÚPUART_STOPBITS_0_5sÚPUART_STOPBITS_1
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ÚPUART_STOPBITS_1_5rÚPUART_STOPBITS_2 ÚPUART_PARITY_NONE¨ÚPUART_PARITY_EVENªÚPUART_PARITY_ODDÚ PUART_HWCONTROL_NONE»ÚPUART_HWCONTROL_RTSôÚPUART_HWCONTROL_CTSÚ PUART_HWCONTROL_RTS_CTS£ÚP UART_MODE_RXêÚP UART_MODE_TXèÚPUART_MODE_TX_RXÙÚPUART_STATE_DISABLE8ÚPUART_STATE_ENABLEÚ PUART_OVERSAMPLING_16«Ú PUART_OVERSAMPLING_8ÜÚ$P UART_ONE_BIT_SAMPLE_DISABLEfÚ#PUART_ONE_BIT_SAMPLE_ENABLEµÚ0P(UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT²Ú3P+UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGEÚ1P)UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAMEÚ1P)UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAMEÀÚ&P UART_RECEIVER_TIMEOUT_DISABLEÈÚ%P UART_RECEIVER_TIMEOUT_ENABLEÚPUART_LIN_DISABLEÚÚPUART_LIN_ENABLE)Ú&P UART_LINBREAKDETECTLENGTH_10B1Ú&P UART_LINBREAKDETECTLENGTH_11B0Ú PUART_DMA_TX_DISABLEÚÚPUART_DMA_TX_ENABLE)Ú PUART_DMA_RX_DISABLEÜÚPUART_DMA_RX_ENABLE+Ú!PUART_HALF_DUPLEX_DISABLEaÚ PUART_HALF_DUPLEX_ENABLE°Ú#PUART_WAKEUPMETHOD_IDLELINEÉÚ&P UART_WAKEUPMETHOD_ADDRESSMARKØÚ PUART_AUTOBAUD_REQUEST)Ú PUART_SENDBREAK_REQUESTíÚ PUART_MUTE_MODE_REQUEST½Ú"PUART_RXDATA_FLUSH_REQUESTÑÚ"PUART_TXDATA_FLUSH_REQUESTÏÚ PUART_ADVFEATURE_NO_INITÚ&P UART_ADVFEATURE_TXINVERT_INITÚ&P UART_ADVFEATURE_RXINVERT_INITÚ(P UART_ADVFEATURE_DATAINVERT_INIT'Ú"PUART_ADVFEATURE_SWAP_INITêÚ.P&UART_ADVFEATURE_RXOVERRUNDISABLE_INIT>Ú/P'UART_ADVFEATURE_DMADISABLEONERROR_INIT Ú*P"UART_ADVFEATURE_AUTOBAUDRATE_INITÚ&P UART_ADVFEATURE_MSBFIRST_INIT³Ú&P UART_ADVFEATURE_TXINV_DISABLEÄÚ%P UART_ADVFEATURE_TXINV_ENABLEÚ&P UART_ADVFEATURE_RXINV_DISABLEÆÚ%P UART_ADVFEATURE_RXINV_ENABLEÚ(P UART_ADVFEATURE_DATAINV_DISABLERÚ'P UART_ADVFEATURE_DATAINV_ENABLE¡Ú%P UART_ADVFEATURE_SWAP_DISABLE$Ú$P UART_ADVFEATURE_SWAP_ENABLEsÚ'P UART_ADVFEATURE_OVERRUN_ENABLEwÚ(P UART_ADVFEATURE_OVERRUN_DISABLE(Ú-P%UART_ADVFEATURE_AUTOBAUDRATE_DISABLEÎÚ,P$UART_ADVFEATURE_AUTOBAUDRATE_ENABLE Ú,P$UART_ADVFEATURE_DMA_ENABLEONRXERRORûÚ-P%UART_ADVFEATURE_DMA_DISABLEONRXERROR¬Ú)P!UART_ADVFEATURE_MSBFIRST_DISABLEíÚ(P UART_ADVFEATURE_MSBFIRST_ENABLE<Ú)P!UART_ADVFEATURE_STOPMODE_DISABLEìÚ(P UART_ADVFEATURE_STOPMODE_ENABLE;Ú)P!UART_ADVFEATURE_MUTEMODE_DISABLE÷Ú(P UART_ADVFEATURE_MUTEMODE_ENABLEFÚ!PUART_CR2_ADDRESS_LSB_POSCÚ PUART_WAKEUP_ON_ADDRESSÖÚ PUART_WAKEUP_ON_STARTBITmÚ)P!UART_WAKEUP_ON_READDATA_NONEMPTY¹Ú PUART_DE_POLARITY_HIGH+Ú PUART_DE_POLARITY_LOW[Ú&P UART_CR1_DEAT_ADDRESS_LSB_POS½Ú&P UART_CR1_DEDT_ADDRESS_LSB_POSºÚP UART_IT_MASKðÚ PHAL_UART_TIMEOUT_VALUEÍÚPUART_FLAG_REACK3ÚPUART_FLAG_TEACK1ÚPUART_FLAG_WUF«ÚPUART_FLAG_RWUÚPUART_FLAG_SBKFuÚPUART_FLAG_CMFÇÚPUART_FLAG_BUSYXÚPUART_FLAG_ABRFÚPUART_FLAG_ABREÚPUART_FLAG_RTOF`ÚPUART_FLAG_CTS³ÚPUART_FLAG_CTSIF ÚPUART_FLAG_LBDFÚPUART_FLAG_TXE¬ÚP UART_FLAG_TCÚPUART_FLAG_RXNE^ÚPUART_FLAG_IDLE}ÚPUART_FLAG_ORE·ÚP UART_FLAG_NE ÚP UART_FLAG_FEÚP UART_FLAG_PE
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ÚP UART_IT_PEÚP UART_IT_TXE-ÚP UART_IT_TCÚP UART_IT_RXNEßÚP UART_IT_IDLEþÚP UART_IT_LBDLÚP UART_IT_CTS4ÚP UART_IT_CMÚP UART_IT_WUF,ÚP UART_IT_RTO)ÚP UART_IT_ERR5ÚP UART_IT_ORE8ÚP UART_IT_NEÚP UART_IT_FEÚPUART_CLEAR_PEFsÚPUART_CLEAR_FEF}ÚPUART_CLEAR_NEFuÚPUART_CLEAR_OREF ÚPUART_CLEAR_IDLEFæÚPUART_CLEAR_TCFqÚPUART_CLEAR_LBDF4ÚPUART_CLEAR_CTSF ÚPUART_CLEAR_CMFxÚPUART_CLEAR_WUF\ÚPUART_CLEAR_RTOFÚ$P HAL_UART_RECEPTION_STANDARDmÚ"PHAL_UART_RECEPTION_TOIDLEÚ!PHAL_UART_RECEPTION_TORTO,Ú'P HAL_UART_RECEPTION_TOCHARMATCHÚ PHAL_UART_RXEVENT_TC´Ú PHAL_UART_RXEVENT_HT¯Ú PHAL_UART_RXEVENT_IDLE)Ú&P __HAL_UART_RESET_HANDLE_STATEÚ$P __HAL_UART_FLUSH_DRREGISTER,Ú P__HAL_UART_CLEAR_FLAG4Ú P__HAL_UART_CLEAR_PEFLAGÚ P__HAL_UART_CLEAR_FEFLAG¥Ú P__HAL_UART_CLEAR_NEFLAGÚ!P__HAL_UART_CLEAR_OREFLAGHÚ"P__HAL_UART_CLEAR_IDLEFLAGÚ P__HAL_UART_GET_FLAG¿Ú P__HAL_UART_ENABLE_ITsÚ P__HAL_UART_DISABLE_IT$ÚP__HAL_UART_GET_IT@Ú!P__HAL_UART_GET_IT_SOURCEÚ P__HAL_UART_CLEAR_ITµÚ P__HAL_UART_SEND_REQ§Ú)P!__HAL_UART_ONE_BIT_SAMPLE_ENABLE·Ú*P"__HAL_UART_ONE_BIT_SAMPLE_DISABLEhÚP__HAL_UART_ENABLEuÚP__HAL_UART_DISABLE&Ú(P __HAL_UART_HWCONTROL_CTS_ENABLEñÚ)P!__HAL_UART_HWCONTROL_CTS_DISABLE¢Ú(P __HAL_UART_HWCONTROL_RTS_ENABLEâÚ)P!__HAL_UART_HWCONTROL_RTS_DISABLEÚPUART_DIV_LPUARTøÚPUART_DIV_SAMPLING87Ú PUART_DIV_SAMPLING16Ú PUART_INSTANCE_LOWPOWERÑÚPIS_UART_BAUDRATEÍÚ PIS_UART_ASSERTIONTIME$Ú PIS_UART_DEASSERTIONTIMEÚPIS_UART_STOPBITSÚPIS_LPUART_STOPBITSýÚPIS_UART_PARITY@Ú&P IS_UART_HARDWARE_FLOW_CONTROLÚP IS_UART_MODEøÚPIS_UART_STATEÚ PIS_UART_OVERSAMPLINGvÚ PIS_UART_ONE_BIT_SAMPLEÈÚ,P$IS_UART_ADVFEATURE_AUTOBAUDRATEMODEÚ!PIS_UART_RECEIVER_TIMEOUT*Ú'P IS_UART_RECEIVER_TIMEOUT_VALUEBÚP IS_UART_LIN<Ú(P IS_UART_LIN_BREAK_DETECT_LENGTHÚPIS_UART_DMA_TX<ÚPIS_UART_DMA_RX>Ú PIS_UART_HALF_DUPLEXÃÚ PIS_UART_WAKEUPMETHODÚ"PIS_UART_REQUEST_PARAMETERÚÚ PIS_UART_ADVFEATURE_INITÚ!PIS_UART_ADVFEATURE_TXINV&Ú!PIS_UART_ADVFEATURE_RXINV(Ú#PIS_UART_ADVFEATURE_DATAINV´Ú PIS_UART_ADVFEATURE_SWAPÚPIS_UART_OVERRUNæÚ(P IS_UART_ADVFEATURE_AUTOBAUDRATE0Ú(P IS_UART_ADVFEATURE_DMAONRXERRORÚ$P IS_UART_ADVFEATURE_MSBFIRSTOÚ$P IS_UART_ADVFEATURE_STOPMODENÚPIS_UART_MUTE_MODETÚ!PIS_UART_WAKEUP_SELECTION3Ú PIS_UART_DE_POLARITY³Ú PSTM32L0xx_HAL_UART_EX_HfÚ8
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<unnamed>QÚ
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"èZ WakeUpEvent"Ú "èZAddressLengthCÚ "èZAddressºÚUART_WakeUpTypeDefDÚPUART_WORDLENGTH_7B6ÚPUART_WORDLENGTH_8B5ÚPUART_WORDLENGTH_9B4Ú PUART_ADDRESS_DETECT_4BÚ PUART_ADDRESS_DETECT_7BÚ,huart£Ú,
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Polarity{Ú,
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AssertionTime~Ú,
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DeassertionTime±Ú HAL_RS485Ex_InitÚ,huart£Ú" HAL_UARTEx_WakeupCallback°Ú,huart£Ú, WakeUpSelection¸Ú. &HAL_UARTEx_StopModeWakeUpSourceConfigÓÚ,huart£Ú" HAL_UARTEx_EnableStopMode¸Ú,huart£Ú# HAL_UARTEx_DisableStopModeIÚ,huart£Ú' HAL_UARTEx_EnableClockStopModeÂÚ,huart£Ú( HAL_UARTEx_DisableClockStopModeSÚ,huart£Ú,
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AddressLengthÚ/ 'HAL_MultiProcessorEx_AddressLength_SetÎÚ,huart£Ú,pDataÝÚ ,Size:Ú,RxLenÞÚ,
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TimeoutêÚ! HAL_UARTEx_ReceiveToIdle(Ú,huart£Ú,pDataÝÚ ,Size:Ú$ HAL_UARTEx_ReceiveToIdle_IT&Ú,huart£Ú,pDataÝÚ ,Size:Ú% HAL_UARTEx_ReceiveToIdle_DMAïÚ,huart£Ú" HAL_UARTEx_GetRxEventTypeÚ PUART_GETCLOCKSOURCEíÚ PUART_MASK_COMPUTATION(Ú PIS_UART_WORD_LENGTH²Ú%P IS_UART_ADDRESSLENGTH_DETECT Ú,huart£Ú HAL_UART_InitkÚ,huart£Ú HAL_HalfDuplex_Init®Ú,huart£Ú,
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BreakDetectLength Ú HAL_LIN_InitÆÚ,huart£Ú,AddressÚ,
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WakeUpMethodÚ HAL_MultiProcessor_InitÈÚ,huart£Ú HAL_UART_DeInit¾Ú,huart£Ú HAL_UART_MspInit5Ú,huart£Ú HAL_UART_MspDeInitÚ,huart£Ú,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_UART_Transmit¥Ú,huart£Ú,pDataÝÚ ,Size:Ú,
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TimeoutêÚ HAL_UART_Receive6Ú,huart£Ú,pDataÝÚ ,Size:Ú HAL_UART_Transmit_IT£Ú,huart£Ú,pDataÝÚ ,Size:Ú HAL_UART_Receive_IT4Ú,huart£Ú,pDataÝÚ ,Size:Ú HAL_UART_Transmit_DMAlÚ,huart£Ú,pDataÝÚ ,Size:Ú HAL_UART_Receive_DMAýÚ,huart£Ú HAL_UART_DMAPause'Ú,huart£Ú HAL_UART_DMAResume²Ú,huart£Ú HAL_UART_DMAStopÚ,huart£Ú HAL_UART_AbortÚ,huart£Ú HAL_UART_AbortTransmit£Ú,huart£Ú HAL_UART_AbortReceive4Ú,huart£Ú HAL_UART_Abort_ITÚ,huart£Ú" HAL_UART_AbortTransmit_IT¡Ú,huart£Ú! HAL_UART_AbortReceive_IT2Ú,huart£Ú HAL_UART_IRQHandlerIÚ,huart£Ú$ HAL_UART_TxHalfCpltCallbacküÚ,huart£Ú HAL_UART_TxCpltCallbackÚ,huart£Ú$ HAL_UART_RxHalfCpltCallbackþÚ,huart£Ú HAL_UART_RxCpltCallbackÚ,huart£Ú HAL_UART_ErrorCallbackÖÚ,huart£Ú# HAL_UART_AbortCpltCallbackMÚ,huart£Ú+ #HAL_UART_AbortTransmitCpltCallbackëÚ,huart£Ú* "HAL_UART_AbortReceiveCpltCallback|Ú,huart£Ú ,Size:Ú# HAL_UARTEx_RxEventCallbackOÚ,huart£Ú,
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TimeoutValueãÚ( HAL_UART_ReceiverTimeout_Config
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Ú,huart£Ú' HAL_UART_EnableReceiverTimeoutzÚ,huart£Ú( HAL_UART_DisableReceiverTimeout Ú,huart£Ú HAL_LIN_SendBreakáÚ,huart£Ú* "HAL_MultiProcessor_EnableMuteModeáÚ,huart£Ú+ #HAL_MultiProcessor_DisableMuteModerÚ,huart£Ú) !HAL_MultiProcessor_EnterMuteMode,Ú,huart£Ú) !HAL_HalfDuplex_EnableTransmitterDÚ,huart£Ú& HAL_HalfDuplex_EnableReceiver²Ú,huart£Ú HAL_UART_GetStateÖÚ,huart£Ú HAL_UART_GetErrorÍÚ,huart£Ú UART_SetConfig¯Ú,huart£Ú UART_CheckIdleStateÊÚ,huart£Ú ,
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Flag]Ú,"Status:Ú,
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TickstartÚ,
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TimeoutêÚ$ UART_WaitOnFlagUntilTimeoutXÚ,huart£Ú UART_AdvFeatureConfigæÚ,huart£Ú,pDataÝÚ ,Size:Ú UART_Start_Receive_IT÷Ú,huart£Ú,pDataÝÚ ,Size:Ú UART_Start_Receive_DMAÀÚ!PHAL_USART_MODULE_ENABLEDgÚ PHAL_IRDA_MODULE_ENABLEDØÚ%P HAL_SMARTCARD_MODULE_ENABLEDMÚ!PHAL_SMBUS_MODULE_ENABLEDlÚ PHAL_WWDG_MODULE_ENABLED¿Ú PHAL_PCD_MODULE_ENABLED#ÚPUSE_FULL_ASSERTûÚP assert_param±Ú HAL_TICK_FREQ_10HZÚ HAL_TICK_FREQ_100HZYÚ HAL_TICK_FREQ_1KHZpÚ HAL_TICK_FREQ_DEFAULTÚ HAL_TickFreqTypeDefÝÚ PSYSCFG_BOOT_MAINFLASHMÚ PSYSCFG_BOOT_SYSTEMFLASHÚPSYSCFG_BOOT_SRAM·ÚP DBGMCU_SLEEP)ÚP DBGMCU_STOP^ÚPDBGMCU_STANDBYÚPIS_DBGMCU_PERIPH×Ú PSYSCFG_VREFINT_OUT_NONEkÚ PSYSCFG_VREFINT_OUT_PB0ÛÚ PSYSCFG_VREFINT_OUT_PB1ÚÚ#PSYSCFG_VREFINT_OUT_PB0_PB1±Ú%P IS_SYSCFG_VREFINT_OUT_SELECTÖÚ"PSYSCFG_FLAG_VREFINT_READYÚPIS_SYSCFG_FLAGlÚ PSYSCFG_FASTMODEPLUS_PB6±Ú PSYSCFG_FASTMODEPLUS_PB7°Ú PSYSCFG_FASTMODEPLUS_PB8¯Ú PSYSCFG_FASTMODEPLUS_PB9®Ú PIS_SYSCFG_FASTMODEPLUSßÚ!P__HAL_DBGMCU_FREEZE_TIM2\Ú#P__HAL_DBGMCU_UNFREEZE_TIM2µÚ!P__HAL_DBGMCU_FREEZE_TIM3[Ú#P__HAL_DBGMCU_UNFREEZE_TIM3´Ú!P__HAL_DBGMCU_FREEZE_TIM6XÚ#P__HAL_DBGMCU_UNFREEZE_TIM6±Ú!P__HAL_DBGMCU_FREEZE_TIM7WÚ#P__HAL_DBGMCU_UNFREEZE_TIM7°Ú P__HAL_DBGMCU_FREEZE_RTCÚ"P__HAL_DBGMCU_UNFREEZE_RTCêÚ!P__HAL_DBGMCU_FREEZE_WWDG?Ú#P__HAL_DBGMCU_UNFREEZE_WWDGÚ!P__HAL_DBGMCU_FREEZE_IWDGMÚ#P__HAL_DBGMCU_UNFREEZE_IWDG¦Ú)P!__HAL_DBGMCU_FREEZE_I2C1_TIMEOUTóÚ2P*__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU-Ú0P(__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCUÓÚ2P*__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU,Ú)P!__HAL_DBGMCU_FREEZE_I2C3_TIMEOUTñÚ+P#__HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUTJÚ$P __HAL_DBGMCU_FREEZE_LPTIMERUÚ&P __HAL_DBGMCU_UNFREEZE_LPTIMER®Ú"P__HAL_DBGMCU_FREEZE_TIM22(Ú$P __HAL_DBGMCU_UNFREEZE_TIM22Ú"P__HAL_DBGMCU_FREEZE_TIM21)Ú$P __HAL_DBGMCU_UNFREEZE_TIM21Ú'P __HAL_SYSCFG_REMAPMEMORY_FLASHTÚ-P%__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASHcÚ&P __HAL_SYSCFG_REMAPMEMORY_SRAMÚ#P__HAL_SYSCFG_DBG_LP_CONFIGÚ#P__HAL_SYSCFG_GET_BOOT_MODEÚ P__HAL_SYSCFG_GET_FLAG(Ú)P!__HAL_SYSCFG_FASTMODEPLUS_ENABLEÎÚ*P"__HAL_SYSCFG_FASTMODEPLUS_DISABLEÚP IS_TICKFREQaÚ
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uwTickxÚ
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uwTickPrioÖÚ" uwTickFreqÍÚ HAL_InitÚ HAL_DeInitcÚ HAL_MspInitÚÚ HAL_MspDeInit-Ú,
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TickPriorityÚÚ HAL_InitTick}Ú HAL_IncTickùÚ,
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DelayæÚ
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HAL_Delay³Ú HAL_GetTickóÚ HAL_GetTickPrioQÚ ,"Freq4Ú HAL_SetTickFreqQÚ HAL_GetTickFreq]Ú HAL_SuspendTick)Ú HAL_ResumeTickÚ HAL_GetHalVersionwÚ HAL_GetREVIDÚ HAL_GetDEVIDÚ HAL_GetUIDw0óÚ HAL_GetUIDw1òÚ HAL_GetUIDw2ñÚ& HAL_DBGMCU_EnableDBGSleepMode×Ú' HAL_DBGMCU_DisableDBGSleepModehÚ% HAL_DBGMCU_EnableDBGStopMode,Ú& HAL_DBGMCU_DisableDBGStopMode½Ú( HAL_DBGMCU_EnableDBGStandbyMode÷Ú) !HAL_DBGMCU_DisableDBGStandbyModeÚ,
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PeriphkÚ, $HAL_DBGMCU_DBG_EnableLowPowerConfigUÚ,
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PeriphkÚ- %HAL_DBGMCU_DBG_DisableLowPowerConfigæÚ HAL_SYSCFG_GetBootMode!Ú' HAL_SYSCFG_Enable_Lock_VREFINTÚ( HAL_SYSCFG_Disable_Lock_VREFINT/Ú ,
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