WXK
2025-02-05 961c1174bbf1aaae5fa2f672806ed4eaf2f917be
01_SDK/modules/hal/panchip/panplat/pan1070/bsp/device/Source/pan_clktrim.c
@@ -43,9 +43,8 @@
{
   uint32_t hclk,err_range;
   uint32_t calc_cnt,ideal_clk_cnt,calc_clk_cnt;
   extern uint32_t SystemCoreClock;
   hclk = SystemCoreClock;
   hclk = FREQ_32MHZ;
   ideal_clk_cnt = hclk / 32000;
   calc_cnt = TRIM_GetCalCnt(trim);
   calc_clk_cnt = (32000+deviation)*ideal_clk_cnt/32;