01_SDK/modules/hal/panchip/panplat/pan1070/bsp/peripheral/src/pan_hal_spi.c
@@ -15,8 +15,8 @@
{
    {
        .pSpix = SPI0,  
        .initObj = {0},
        .interruptObj = {0},
//        .initObj = {0},
//        .interruptObj = {0},
        .xferStat = SPI_STAT_NULL,
        .pTxBuffPtr = NULL,
        .txXferSize = 0,
@@ -33,8 +33,8 @@
    },
    {
        .pSpix = SPI1,  
        .initObj = {0},
        .interruptObj = {0},
//        .initObj = {0},
//        .interruptObj = {0},
        .xferStat = SPI_STAT_NULL,
        .pTxBuffPtr = NULL,
        .txXferSize = 0,
@@ -246,7 +246,8 @@
    pSpi->rxXferCount =0;
    pSpi->pRxBuffPtr = pBuf;
    pSpi->rxIntCallback = callback;
    SPI_EnableIrq(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL | SPI_IRQ_RX_TIMEOUT);
    SPI_EnableIrq(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL);
    SPI_EnableIrq(pSpi->pSpix, SPI_IRQ_RX_TIMEOUT);
    NVIC_EnableIRQ(pSpi->IRQn);
}
@@ -299,7 +300,7 @@
    /* Condition check */
    uint32_t DataWidthInByteSrc =  DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
    // uint32_t DataWidthInByteSrc = 1 <<  DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
    uint32_t IsNotDivisible = pSpi->txXferSize % DataWidthInByteSrc;
//    uint32_t IsNotDivisible = pSpi->txXferSize % DataWidthInByteSrc;
    uint32_t BlockSize = pSpi->txXferSize / DataWidthInByteSrc;    //BlockSize = DataLen / DataWidthInByteSrc
    /* Start DMA Tx channel */
@@ -337,7 +338,7 @@
    /* Condition check */
    uint32_t RxDataWidthInByteSrc =  DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
    uint32_t RxIsNotDivisible = pSpi->rxXferSize % RxDataWidthInByteSrc;
//    uint32_t RxIsNotDivisible = pSpi->rxXferSize % RxDataWidthInByteSrc;
    uint32_t RxBlockSize = pSpi->rxXferSize / RxDataWidthInByteSrc;    //BlockSize = DataLen / DataWidthInByteSrc
   /*We should clear rx fifo before rx start*/
@@ -428,14 +429,14 @@
    rxChNum = HAL_SPI_ReceiveData_DMA_ForSR(pSpi,pRecvBuf,recvBufSize,recvCallback);
    /* Condition check */
    uint32_t RxDataWidthInByteSrc =  DMAC_Channel_Array[rxChNum].ConfigTmp.DataWidthSrc;
    uint32_t RxIsNotDivisible = pSpi->rxXferSize % RxDataWidthInByteSrc;
//    uint32_t RxIsNotDivisible = pSpi->rxXferSize % RxDataWidthInByteSrc;
    uint32_t RxBlockSize = pSpi->rxXferSize / RxDataWidthInByteSrc;    //BlockSize = DataLen / DataWidthInByteSrc
    /* Condition check */
    uint32_t TxDataWidthInByteSrc =  DMAC_Channel_Array[txChNum].ConfigTmp.DataWidthSrc;
    // uint32_t DataWidthInByteSrc = 1 <<  DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
    uint32_t TxIsNotDivisible = pSpi->txXferSize % TxDataWidthInByteSrc;
//    uint32_t TxIsNotDivisible = pSpi->txXferSize % TxDataWidthInByteSrc;
    uint32_t TxBlockSize = pSpi->txXferSize / TxDataWidthInByteSrc;    //BlockSize = DataLen / DataWidthInByteSrc
    /* Start DMA Rx channel */
@@ -456,7 +457,8 @@
            {
                pSpi->rxIntCallback(SPI_CB_FLAG_INT, pSpi->pRxBuffPtr, pSpi->rxXferCount);
            }
            SPI_DisableIrq(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL|SPI_IRQ_RX_TIMEOUT);
            SPI_DisableIrq(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL);
            SPI_DisableIrq(pSpi->pSpix, SPI_IRQ_RX_TIMEOUT);
            break;
        }
    }
@@ -515,15 +517,30 @@
   }
}
void SPI0_IRQHandler(void)
__WEAK void SPI0_IRQHandlerOverlay(void)
{
    SPI_HandleProc(&spiHandleArray[0]);
}
void SPI1_IRQHandler(void)
__WEAK void SPI1_IRQHandlerOverlay(void)
{
    SPI_HandleProc(&spiHandleArray[1]);
}
void SPI0_IRQHandler(void)
{
    PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_SPI0_IRQ, 1);
    SPI0_IRQHandlerOverlay();
    PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_SPI0_IRQ, 0);
}
void SPI1_IRQHandler(void)
{
    PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_SPI1_IRQ, 1);
    SPI1_IRQHandlerOverlay();
    PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_SPI1_IRQ, 0);
}