| | |
| | | #define NRF_RX_TO_TX_TIME (110) |
| | | #define NRF_TX_TO_RX_TIME (110) |
| | | |
| | | #define PHY_MODED_DEFAULT (0) |
| | | #define PHY_MODED_AGC_0X0F (1) |
| | | #define PHY_MODED_FORCE_GAIN_0X0F (2) |
| | | |
| | | #define PHY_CFG_MODE PHY_MODED_DEFAULT |
| | | |
| | | #define REG_WRITE_BITS(reg, mask, value) (reg) = (((reg) & ~(mask)) | (value)) |
| | | |
| | | #define __nop() __asm("nop") |
| | |
| | | uint8_t prf_init_flag = 0; |
| | | int8_t prf_rssi = 0; |
| | | static uint8_t buck_vout_trim = 0xff; |
| | | static uint32_t raw_phy_config_data[7] = {0xffffffff, }; |
| | | |
| | | __ramfunc void panchip_prf_isr_proc(void) |
| | | { |
| | |
| | | normal_m1 = (uint8_t)((PRI_RF->R04_RX_CTL & R04_RX_CTL_NORMAL_M1_Msk) >> R04_RX_CTL_NORMAL_M1_Pos); |
| | | noack = PRI_RF_IsTxNoAckEn(PRI_RF); |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_TX_IRQ_Msk)) { |
| | | if (((((enhc == 0) && (normal_m1 == 0)) || ((enhc == 1) && noack)) && !ptxprx) || ptxprx) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_TX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | | } |
| | | |
| | | if (isr_cb.tx_cb != NULL) { |
| | | (*isr_cb.tx_cb)(); |
| | | } |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_TX_TIMEOUT_IRQ_Msk)) { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_TX_TIMEOUT_IRQ_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_TX_TIMEOUT_IRQ_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | |
| | | } |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_IRQ_Msk)) { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_IRQ_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_IRQ_MASK_Msk)?(false):(true))) { |
| | | if (((enhc == 0) && (normal_m1 == 0) && ptxprx) || !ptxprx) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | |
| | | } |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_CRC_ERR_Msk)) { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_CRC_ERR_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_CRC_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | |
| | | } |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_LENGTH_ERR_Msk)) |
| | | { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_LENGTH_ERR_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_LENGTH_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | |
| | | } |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_ACCADDR_ERR_Msk)) |
| | | { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_ACCADDR_ERR_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_ACCADDR_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | |
| | | } |
| | | } |
| | | |
| | | if (PRI_RF->R01_INT & R01_INT_RX_PID_ERR_IRQ_FLAG_Msk) { |
| | | if ((PRI_RF->R01_INT & R01_INT_RX_PID_ERR_IRQ_FLAG_Msk) && |
| | | ((PRI_RF->R01_INT & R01_INT_PID_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait rx done */ |
| | | if (ptxprx == 0) { |
| | |
| | | |
| | | if (isr_cb.rx_pid_err_cb != NULL) { |
| | | (*isr_cb.rx_pid_err_cb)(); |
| | | } |
| | | } |
| | | |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_TX_IRQ_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_TX_IRQ_MASK_Msk)?(false):(true))) { |
| | | if (((((enhc == 0) && (normal_m1 == 0)) || ((enhc == 1) && noack)) && !ptxprx) || ptxprx) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_TX_DONE_IRQ_FLAG_Msk)) { |
| | | } /* wait tx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | | } |
| | | |
| | | if (isr_cb.tx_cb != NULL) { |
| | | (*isr_cb.tx_cb)(); |
| | | } |
| | | } |
| | | |
| | |
| | | normal_m1 = (uint8_t)((PRI_RF->R04_RX_CTL & R04_RX_CTL_NORMAL_M1_Msk) >> R04_RX_CTL_NORMAL_M1_Pos); |
| | | noack = PRI_RF_IsTxNoAckEn(PRI_RF); |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_TX_IRQ_Msk)) { |
| | | if (((((enhc == 0) && (normal_m1 == 0)) || ((enhc == 1) && noack)) && !ptxprx) || ptxprx) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_TX_DONE_IRQ_FLAG_Msk)); /* wait tx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | | panchip_prf_ble_resume(); |
| | | } |
| | | |
| | | if (isr_cb.tx_cb != NULL) { |
| | | (*isr_cb.tx_cb)(); |
| | | } |
| | | PRI_RF_ClearAllIrqEn(PRI_RF, ENABLE); |
| | | return 1; |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_TX_TIMEOUT_IRQ_Msk)) { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_TX_TIMEOUT_IRQ_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_TX_TIMEOUT_IRQ_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)); /* wait rx timeout */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | |
| | | return 1; |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_IRQ_Msk)) { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_IRQ_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_IRQ_MASK_Msk)?(false):(true))) { |
| | | if (((enhc == 0) && (normal_m1 == 0) && ptxprx) || !ptxprx) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)); /* wait rx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | |
| | | return 1; |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_CRC_ERR_Msk)) { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_CRC_ERR_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_CRC_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)); /* wait rx crc err */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | |
| | | return 1; |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_LENGTH_ERR_Msk)) |
| | | { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_LENGTH_ERR_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_LENGTH_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)); //wait rx done |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | |
| | | return 1; |
| | | } |
| | | |
| | | if (PRI_RF_IntFlag(PRI_RF, R01_INT_RX_ACCADDR_ERR_Msk)) |
| | | { |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_RX_ACCADDR_ERR_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_RX_ACCADDR_ERR_MASK_Msk)?(false):(true))) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_RX_DONE_IRQ_FLAG_Msk)); //wait rx done |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | |
| | | PRI_RF_ClearAllIrqEn(PRI_RF, ENABLE); |
| | | return 1; |
| | | } |
| | | |
| | | if ((PRI_RF_IntFlag(PRI_RF, R01_INT_TX_IRQ_Msk)) && |
| | | ((PRI_RF->R01_INT & R01_INT_TX_IRQ_MASK_Msk)?(false):(true))) { |
| | | if (((((enhc == 0) && (normal_m1 == 0)) || ((enhc == 1) && noack)) && !ptxprx) || ptxprx) { |
| | | while (!(PRI_RF->R01_INT & R01_INT_TX_DONE_IRQ_FLAG_Msk)); /* wait tx done */ |
| | | PHY_strt_stp(LLHWC_PHY_STOP); |
| | | PRI_RF_SetTrxRamReady(PRI_RF, PRI_RF_MODE_SEL_TRX, 0); |
| | | panchip_prf_ble_resume(); |
| | | } |
| | | |
| | | if (isr_cb.tx_cb != NULL) { |
| | | (*isr_cb.tx_cb)(); |
| | | } |
| | | PRI_RF_ClearAllIrqEn(PRI_RF, ENABLE); |
| | | return 1; |
| | | } |
| | | |
| | | return 0; |
| | | } |
| | | |
| | | __ramfunc uint8_t panchip_prf_ble_handler(void) |
| | | __weak uint8_t panchip_prf_ble_handler(void) |
| | | { |
| | | if (panchip_prf_isr_resume_ble_cb() == 1) { |
| | | return 1; |
| | |
| | | return status; |
| | | } |
| | | |
| | | void panchip_prf_set_phy(prf_phy_t phy) |
| | | __weak void panchip_prf_set_phy(prf_phy_t phy) |
| | | { |
| | | rf_config.phy = phy; |
| | | |
| | |
| | | |
| | | ANA->LP_BUCK_3V = (ANA->LP_BUCK_3V & ~(0xFu << 2)) | ((buck_vout_trim_val & 0x0f) << 2); |
| | | |
| | | rf_config.tx_power = tx_pwr; |
| | | |
| | | if(rf_config.chip_mode != PRF_CHIP_MODE_SEL_BLE) |
| | | { |
| | | // panchip_prf_reset(); |
| | | __disable_irq(); |
| | | } |
| | | |
| | | if(tx_pwr <= 0) |
| | | { |
| | | tx_pwr = tx_pwr - 1; |
| | | } |
| | | |
| | | rf_config.tx_power = tx_pwr; |
| | | PHY_set_tx_pwr(tx_pwr); |
| | | |
| | | if(rf_config.chip_mode != PRF_CHIP_MODE_SEL_BLE) |
| | |
| | | |
| | | if(trans_wait_time == 0) |
| | | { |
| | | panchip_prf_reduce_trx_time(true); //trx 25us,rtx 26us |
| | | panchip_prf_reduce_trx_pre_post_delay_time(p_config, false); //trx 25us,rtx 26us |
| | | } |
| | | } |
| | | } |
| | |
| | | prf_delay_nop(30); |
| | | } |
| | | |
| | | __ramfunc void ana_prf_ldo_dis(void) |
| | | __ramfunc __weak void ana_prf_ldo_dis(void) |
| | | { |
| | | #ifndef CONFIG_PRF_REDUCE_TRX_TRANS_TIME |
| | | REG_WRITE_BITS(ANA->ANA_ADC_LDO, 0x01, 0x00); |
| | |
| | | prf_delay_nop(200); |
| | | #endif |
| | | } |
| | | |
| | | __ramfunc void panchip_prf_reduce_trx_pre_post_delay_time(pan_prf_config_t *p_config, bool restore) |
| | | { |
| | | extern uint32_t* g_phy_post_tx_ptr_prf; |
| | | extern uint32_t* g_phy_pre_tx_1M_ptr_prf; |
| | | extern uint32_t* g_phy_pre_rx_1M_ptr_prf; |
| | | extern uint32_t* g_phy_pre_tx_2M_ptr_prf; |
| | | extern uint32_t* g_phy_pre_rx_2M_ptr_prf; |
| | | |
| | | if (0xffffffff == raw_phy_config_data[0]) { |
| | | raw_phy_config_data[0] = g_phy_post_tx_ptr_prf[2]; |
| | | raw_phy_config_data[1] = g_phy_pre_tx_1M_ptr_prf[3]; |
| | | raw_phy_config_data[2] = g_phy_pre_tx_1M_ptr_prf[6]; |
| | | raw_phy_config_data[3] = g_phy_pre_rx_1M_ptr_prf[6]; |
| | | raw_phy_config_data[4] = g_phy_pre_tx_2M_ptr_prf[3]; |
| | | raw_phy_config_data[5] = g_phy_pre_tx_2M_ptr_prf[6]; |
| | | raw_phy_config_data[6] = g_phy_pre_rx_2M_ptr_prf[6]; |
| | | } |
| | | |
| | | if (p_config->phy == PRF_PHY_1M) { |
| | | if (restore) { |
| | | g_phy_pre_tx_1M_ptr_prf[3] = raw_phy_config_data[1]; |
| | | g_phy_pre_tx_1M_ptr_prf[6] = raw_phy_config_data[2]; |
| | | g_phy_post_tx_ptr_prf[2] = raw_phy_config_data[0]; |
| | | /* 21us */ |
| | | g_phy_pre_rx_1M_ptr_prf[6] = raw_phy_config_data[3]; |
| | | } else { |
| | | /* 24us */ |
| | | g_phy_pre_tx_1M_ptr_prf[3] = (g_phy_pre_tx_1M_ptr_prf[3] & 0x00ffffff); |
| | | g_phy_pre_tx_1M_ptr_prf[6] = (g_phy_pre_tx_1M_ptr_prf[6] & 0x00ffffff) | (0x8 << 24); |
| | | g_phy_post_tx_ptr_prf[2] = g_phy_post_tx_ptr_prf[2] & 0x00ffffff; |
| | | /* 21us */ |
| | | g_phy_pre_rx_1M_ptr_prf[6] = (g_phy_pre_rx_1M_ptr_prf[6] & 0x00ffffff) | (0x0 << 24); |
| | | } |
| | | } else if (p_config->phy == PRF_PHY_2M) { |
| | | |
| | | if (restore) { |
| | | g_phy_pre_tx_2M_ptr_prf[3] = raw_phy_config_data[4]; |
| | | g_phy_pre_tx_2M_ptr_prf[6] = raw_phy_config_data[5]; |
| | | g_phy_post_tx_ptr_prf[2] = raw_phy_config_data[0]; |
| | | /* 21us */ |
| | | g_phy_pre_rx_2M_ptr_prf[6] = raw_phy_config_data[6]; |
| | | } else { |
| | | /* 24us */ |
| | | g_phy_pre_tx_2M_ptr_prf[3] = (g_phy_pre_tx_2M_ptr_prf[3] & 0x00ffffff); |
| | | g_phy_pre_tx_2M_ptr_prf[6] = (g_phy_pre_tx_2M_ptr_prf[6] & 0x00ffffff) | (0x8 << 24); |
| | | g_phy_post_tx_ptr_prf[2] = g_phy_post_tx_ptr_prf[2] & 0x00ffffff; |
| | | /* 21us */ |
| | | g_phy_pre_rx_2M_ptr_prf[6] = (g_phy_pre_rx_2M_ptr_prf[6] & 0x00ffffff) | (0x0 << 24); |
| | | } |
| | | } |
| | | |
| | | extern uint32_t PHY_SeqRamInit(void); |
| | | PHY_SeqRamInit(); |
| | | } |
| | | |
| | | __ramfunc int16_t panchip_prf_set_trx_trans_time(pan_prf_config_t *p_config, |
| | | prf_speed_sel_t speed, |
| | | uint16_t transfer_time) |
| | | { |
| | | int16_t trans_wait_time = 0; |
| | | uint32_t prescale_clk; |
| | | uint32_t write_phy_time = 0, write_phy_delay_time = 0; |
| | | uint32_t legency_time = 0; |
| | | |
| | | if ((speed == PRF_TRANSFER_SPEED_4K) || (speed == PRF_TRANSFER_SPEED_8K)) { |
| | | panchip_prf_reduce_trx_pre_post_delay_time(p_config, false); |
| | | } |
| | | |
| | | prescale_clk = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, IF_CLK_PRESCALE); |
| | | /* calculate phy write time */ |
| | | if (p_config->trx_mode == PRF_TX_MODE) { |
| | | if (p_config->phy == PRF_PHY_1M) { |
| | | write_phy_time = (24 * prescale_clk + 8) * ((post_tx_interpacket_size >> 2)); |
| | | if (p_config->work_mode == PRF_MODE_ENHANCE) { |
| | | write_phy_time += (24 * prescale_clk + 8) * ((pre_rx_interpacket_size >> 2) + 1) + 10; |
| | | /* calculate phy write delay time */ |
| | | write_phy_delay_time = phy_time_cfg(p_config->phy - 1, 1); |
| | | } |
| | | } else if (p_config->phy == PRF_PHY_2M) { |
| | | write_phy_time = (24 * prescale_clk + 8) * ((post_tx_interpacket_size >> 2)); |
| | | if (p_config->work_mode == PRF_MODE_ENHANCE) { |
| | | write_phy_time += (24 * prescale_clk + 8) * ((pre_rx_interpacket_2M_size >> 2) + 1) + 10; |
| | | /* calculate phy write delay time */ |
| | | write_phy_delay_time = phy_time_cfg(p_config->phy - 1, 1); |
| | | } |
| | | } |
| | | } |
| | | if (p_config->trx_mode == PRF_RX_MODE) { |
| | | if (p_config->phy == PRF_PHY_1M) { |
| | | legency_time = RX_LEGENCY_1M; |
| | | write_phy_time = (24 * prescale_clk + 8) * ((post_rx_interpacket_size >> 2)); |
| | | if (p_config->work_mode == PRF_MODE_ENHANCE) { |
| | | write_phy_time += (24 * prescale_clk + 8) * ((pre_tx_interpacket_size >> 2) + 1) + 10; |
| | | /* calculate phy write delay time */ |
| | | write_phy_delay_time = phy_time_cfg(p_config->phy - 1, 0); |
| | | } |
| | | } else if (p_config->phy == PRF_PHY_2M) { |
| | | legency_time = RX_LEGENCY_2M; |
| | | write_phy_time = (24 * prescale_clk + 8) * ((post_rx_interpacket_size >> 2)); |
| | | if (p_config->work_mode == PRF_MODE_ENHANCE) { |
| | | write_phy_time += (24 * prescale_clk + 8) * ((pre_tx_interpacket_2M_size >> 2) + 1) + 10; |
| | | /* calculate phy write delay time */ |
| | | write_phy_delay_time = phy_time_cfg(p_config->phy - 1, 0); |
| | | } |
| | | } |
| | | } |
| | | /* phy clk is 32M, here right shift 5 bit means the time is microsecond */ |
| | | write_phy_time >>= 5; |
| | | if (p_config->trx_mode == PRF_RX_MODE) { |
| | | trans_wait_time = transfer_time - write_phy_time - write_phy_delay_time |
| | | - legency_time - RX_WINDOW; |
| | | } else { |
| | | trans_wait_time = transfer_time - write_phy_time - write_phy_delay_time - TX_WINDOW; |
| | | } |
| | | |
| | | if (trans_wait_time < 0) { |
| | | return trans_wait_time; |
| | | } |
| | | |
| | | if (p_config->work_mode == PRF_MODE_ENHANCE) { |
| | | PRI_RF_SetTrxTransWaitTime(PRI_RF, trans_wait_time); |
| | | } |
| | | |
| | | return trans_wait_time; |
| | | } |
| | | |
| | | void panchip_prf_phy_cfg_mode_set(uint32_t *phy_data, uint16_t len) |
| | | { |
| | | #if(PHY_CFG_MODE == PHY_MODED_AGC_0X0F) |
| | | for(int i = 0; i < len; i++) { |
| | | if(phy_data[i] == 0x00d4a202) { |
| | | phy_data[i] = 0x00dea202; |
| | | } else if(phy_data[i] == 0x002fa202) { |
| | | phy_data[i] = 0x000fa202; |
| | | |
| | | break; |
| | | } |
| | | } |
| | | #elif(PHY_CFG_MODE == PHY_MODED_FORCE_GAIN_0X0F) |
| | | for(int i = 0; i < len; i++) { |
| | | if(phy_data[i] == 0x00d6a202) { |
| | | phy_data[i] = 0x00c2a202; |
| | | } else if(phy_data[i] == 0x00b7a202) { |
| | | phy_data[i] = 0x00c2a202; |
| | | } else if((phy_data[i] == 0x0006a202) && (phy_data[i + 1] == 0x000ca302)) { |
| | | phy_data[i] = 0x00dea202; |
| | | } else if(phy_data[i] == 0x00f2a202) { |
| | | phy_data[i] = 0x00dea202; |
| | | } else if(phy_data[i] == 0x00d4a202) { |
| | | phy_data[i] = 0x00dea202; |
| | | } else if(phy_data[i] == 0x0003a202) { |
| | | phy_data[i] = 0x000fa202; |
| | | } else if(phy_data[i] == 0x0007a202) { |
| | | phy_data[i] = 0x000fa202; |
| | | } else if(phy_data[i] == 0x002fa202) { |
| | | phy_data[i] = 0x000fa202; |
| | | |
| | | break; |
| | | } |
| | | } |
| | | #endif |
| | | } |