BLE_PAN1070.git

			@@ -45,6 +45,7 @@
			// Registers (PAN107X)
			//
			__constant U32 ANA_CPU_ADDR_REMAP_CTRL_REG_ADDR = 0x4007005C; // SoC CPU Remap Ctrl Register
			__constant U32 ANA_LP_FL_CTRL_3V_REG_ADDR = 0x40070004; // SoC Low Power Ctrl Register

			//
			// Registers (ARM)
			@@ -109,6 +110,10 @@
			JLINK_SYS_Report("Reset: Clear CPU Remap Ctrl Register.");
			// Clear CPU Remap ctrl reg before reset triggering
			JLINK_MEM_WriteU32(ANA_CPU_ADDR_REMAP_CTRL_REG_ADDR, 0x0);

			// Reset SoC Low Power ctrl reg (Clear BIT6 to indicate SysReset)
			JLINK_MEM_WriteU32(ANA_LP_FL_CTRL_3V_REG_ADDR, 0x00000008);

			// Make sure that no sticky error bits are set on the DP
			JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_ABORT, 0x1E);