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| | | /* =========================================================================================================================== */ |
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| | | |
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| | | /** Enable trace output */ |
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| | | #define TRACE_EN (0) |
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| | | #define TRACE_EN (1) |
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| | | |
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| | | /** Enable exception reboot */ |
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| | | #ifndef TRACE_REBOOT_EN |
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| | |
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| | | #define TRACE_STD_LIB_EN (0) |
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| | | |
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| | | /** Configure trace level for modules: BOOT | TEST | UCI | UWB | APP | DRIVER | PHY | MAC */ |
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| | | #define TRACE_LVL_CONFIG_0 (0x44444004) |
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| | | #define TRACE_LVL_CONFIG_0 (0x44444004) //yuan #define TRACE_LVL_CONFIG_0 (0x44444444) |
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| | | |
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| | | /** Configure trace level for modules: CCC | FIRA | OS */ |
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| | | #define TRACE_LVL_CONFIG_1 (0x00000444) |
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| | |
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| | | /** Antenna port number for AoA, 2~4 */ |
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| | | #define RX_AOA_ANT_PORTS_NUM (4) |
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| | | |
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| | | /** Antenna ports combination for AoA, @ref enum RX_ANTENNA_MODE_T */ |
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| | | /** Antenna ports c ombination for AoA, @ref enum RX_ANTENNA_MODE_T */ |
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| | | #define RX_AOA_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2) |
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| | | |
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| | | /** Antenna pattern: Linear or Square */ |
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| | |
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| | | /** Maximum PHY payload length */ |
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| | | #define PHY_PAYLOAD_LEN_MAX (127) |
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| | | |
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| | | //#define BOXING |
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| | | //#define BOXING |
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| | | #define LED_PIN IO_PIN_4 |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Simple Selection ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | |
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| | | |
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| | | //#define MK_DS_TWR_RESP_STS |
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| | | |
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| | | //#define MK_SS_TWR_DW_INIT |
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| | | #define MK_SS_TWR_DW_INIT |
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| | | |
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| | | #define MK_SS_TWR_DW_RESP |
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| | | //#define MK_SS_TWR_DW_RESP |
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| | | |
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| | | #define INPUT_5V_Pin IO_PIN_11 |
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| | | #define RSSI_EN (1) |
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| | | #define INPUT_5V_Pin IO_PIN_2 |
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| | | |
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| | | #define ACCLERATE_DETECT_Pin IO_PIN_2 |
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| | | #define SDA_PIN IO_PIN_3 |
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| | | #define SER_PIN IO_PIN_3 |
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| | | #define SCL_PIN IO_PIN_4 |
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| | | #define SRCLK_PIN IO_PIN_8 |
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| | | #define RCLK_PIN IO_PIN_7 |
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| | | #define RSSI_EN (0) |
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| | | /** channel number: 2, 5, 9 */ |
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| | | #define UWB_CH_NUM (5) |
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| | | /** Velocity of propagation (%) */ |
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| | | #define VP_VAL (100) |
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| | | #define RANGING_CORR (0) |
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| | | #define XTAL_AUTO_TUNE_EN (0) |
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| | | //#define STS_MODE |
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| | | //#define MK_MODE |
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| | | #define SLEEP_COUNT 1000 |
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| | | #define DW1000 |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ End ================ */ |
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| | | /* =========================================================================================================================== */ |
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