| | |
| | | * @{ |
| | | */ |
| | | |
| | | /** @defgroup MK8000_UWB UWB Driver */ |
| | | /** @defgroup MK8000_MAC MAC */ |
| | | /** @defgroup MK8000_PHY PHY */ |
| | | /** @defgroup MK8000_RADAR Radar */ |
| | | /** @defgroup MK8000_UWB UWB Driver */ |
| | | |
| | | /** |
| | | * @} |
| | |
| | | UART0_IRQn = 24, /*!< 24 UART0 */ |
| | | UART1_IRQn = 25, /*!< 25 UART1 */ |
| | | CALIB_IRQn = 26, /*!< 26 Calibration */ |
| | | RCO32K_CAL_IRQn = 27, /*!< 27 RCO 32K calibration */ |
| | | CLK32K_CAL_IRQn = 27, /*!< 27 CLK 32K calibration */ |
| | | WAKEUP_IRQn = 28, /*!< 28 wakeup */ |
| | | PHY_TIMER_IRQn = 29, /*!< 29 PHY timer */ |
| | | |
| | |
| | | __IOM uint32_t DATA_SIZE; /*!< (0x108) DMA CH Transcation length Register */ |
| | | __IOM uint32_t ADDR_SRC; /*!< (0x10C) DMA CH Source Address Register */ |
| | | __IOM uint32_t ADDR_DST; /*!< (0x110) DMA CH Destination Address Register */ |
| | | uint32_t RESERVED1[3]; |
| | | __IOM uint32_t CHAIN_PTR; /*!< (0x114) DMA CH Chained Transfer Control Structure Pointer Register */ |
| | | uint32_t RESERVED1[2]; |
| | | } CH[8]; |
| | | } DMA_TypeDef; |
| | | |