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| | | #ifndef USER_CONFIG_H_ |
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| | | #define USER_CONFIG_H_ |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Platform configuration ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | | |
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| | | /** Platform */ |
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| | | // #define CELL_PHONE_EN |
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| | | // #define RPI4_EN |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Silicon configuration ================ */ |
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| | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Board configuration ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | | |
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| | | /** UCI hardware port config: 0 - UART, 1 - SPI */ |
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| | | #define UCI_INTF_PORT (0) |
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| | | |
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| | | /** UCI UART handshake enable, handshake pins configured from board.h */ |
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| | | #define UCI_INTF_UART_HS_EN (0) |
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| | | |
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| | | /** UCI SPI half-duplex or full-duplex mode selection: 0 - half-duplex, 1 - full-duplex */ |
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| | | #define UCI_INTF_SPI_HD_FD (0) |
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| | | |
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| | | /** When the host platform is cell phone or Raspberry Pi, the SPI full-duplex handshake interface is enabled */ |
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| | | #if defined(CELL_PHONE_EN) || defined(RPI4_EN) |
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| | | /** By default, spi full-duplex is used to communicate with cell phone and Raspberry Pi */ |
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| | | #undef UCI_INTF_PORT |
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| | | #define UCI_INTF_PORT (1) |
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| | | |
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| | | #undef UCI_INTF_SPI_HD_FD |
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| | | #define UCI_INTF_SPI_HD_FD (1) |
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| | | #endif |
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| | | |
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| | | #if UCI_INTF_PORT == 1 |
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| | | |
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| | | #if UCI_INTF_SPI_HD_FD |
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| | | /** UCI SPI full-duplex handshake interface, handshake pins configured from board.h */ |
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| | | #define UCI_INTF_SPI_FD_HS (1) |
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| | | #else |
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| | | /** UCI SPI half-duplex handshake interface, handshake pins configured from board.h */ |
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| | | #define UCI_INTF_SPI_HD_HS (1) |
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| | | #endif |
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| | | |
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| | | /** UCI SPI bit rate */ |
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| | | #define UCI_INTF_SPI_SPEED 1000000 |
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| | | |
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| | | #else |
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| | | |
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| | | #if UCI_INTF_UART_HS_EN |
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| | | /** UCI UART interface with handshake */ |
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| | | #define UCI_INTF_UART_HS (1) |
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| | | |
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| | | /** The time for UART delay to send */ |
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| | | #define UCI_INTF_UART_HS_DELAYED_SEND_US (1000) |
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| | | #else |
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| | | /** UCI UART interface without handshake */ |
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| | | #define UCI_INTF_UART (1) |
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| | | #endif |
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| | | |
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| | | /** UART baudrate, @ref enum UART_BAUD_T */ |
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| | | #define UCI_INTF_UART_BAUD BAUD_921600 |
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| | | |
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| | | #endif |
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| | | |
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| | | /** Enable SE check over SPI */ |
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| | | #if defined(CELL_PHONE_EN) |
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| | | #define UCI_CHECK_SE_EN (1) |
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| | | #else |
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| | | #define UCI_CHECK_SE_EN (0) |
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| | | #endif |
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| | | |
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| | | /** UCI handshake timeout */ |
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| | | #define UCI_HS_TIMEOUT_MS (50U) |
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| | | |
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| | | /** Enable antenna delay calibration, golden reference need to set this macro */ |
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| | | #define ANT_DELAY_CAL_EN (1) |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Driver configuration ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | | // ACMP work mode |
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| | | #define ACMP_INT_MODE_EN (0) |
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| | | // ADC work mode |
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| | | #define ADC_INT_MODE_EN (0) |
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| | | #define ADC_DMA_MODE_EN (0) |
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| | | #define ADC_POLL_MODE_EN (1) |
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| | | // AES work mode |
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| | | #define AES_INT_MODE_EN (0) |
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| | | #define AES_DMA_MODE_EN (1) |
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| | | #define AES_POLL_MODE_EN (0) |
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| | | // Flash work mode |
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| | | #define FLASH_INT_MODE_EN (0) |
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| | | #define FLASH_DMA_MODE_EN (0) |
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| | | #if ANT_DELAY_CAL_EN |
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| | | #define FLASH_WRITE_EN (1) |
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| | | #else |
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| | | #define FLASH_WRITE_EN (0) |
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| | | #endif |
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| | | // I2C work mode |
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| | | #define I2C_INT_MODE_EN (0) |
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| | | #define I2C_POLL_MODE_EN (1) |
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| | | // LSP work mode |
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| | | #define LSP_INT_MODE_EN (0) |
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| | | // PWM work mode |
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| | | #define PWM_INT_MODE_EN (0) |
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| | | // RTC work mode |
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| | | #define RTC_FREE_COUNTER_EN (0) |
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| | | // SPI work mode |
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| | | #define SPI_INT_MODE_EN (0) |
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| | | #define SPI_DMA_MODE_EN (1) |
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| | | #define SPI_POLL_MODE_EN (1) |
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| | | // TRNG work mode |
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| | | #define TRNG_INT_MODE_EN (0) |
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| | | #define TRNG_POLL_MODE_EN (1) |
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| | | // UART work mode |
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| | | #define UART_INT_MODE_EN (0) |
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| | | #define UART_DMA_MODE_EN (1) |
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| | | #define UART_POLL_MODE_EN (0) |
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| | | // Dual Timer work mode |
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| | | #define TIMER0_INT_MODE_EN (1) |
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| | | #define TIMER1_INT_MODE_EN (1) |
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| | | // Timer work mode |
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| | | #define TIMER2_INT_MODE_EN (0) |
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| | | #define TIMER3_INT_MODE_EN (1) |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Debug/TRACE configuration ================ */ |
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| | |
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| | | #define TRACE_STD_LIB_EN (0) |
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| | | |
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| | | /** Configure trace level for modules: BOOT | TEST | UCI | UWB | APP | DRIVER | PHY | MAC */ |
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| | | #define TRACE_LVL_CONFIG_0 (0x44444004) |
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| | | #define TRACE_LVL_CONFIG_0 (0x44444444) |
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| | | |
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| | | /** Configure trace level for modules: CCC | FIRA | OS */ |
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| | | #define TRACE_LVL_CONFIG_1 (0x00000444) |
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| | | |
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| | | /** Configure trace buffer size (in bytes) */ |
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| | | #define TRACE_BUF_SIZE (1024) |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Power configuration ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | | |
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| | | /** Enable low power mode */ |
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| | | #ifndef LOW_POWER_EN |
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| | | #if (UCI_INTF_PORT || (UCI_INTF_PORT == 0 && UCI_INTF_UART_HS_EN) || ANT_DELAY_CAL_EN) |
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| | | #define LOW_POWER_EN (1) |
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| | | #else |
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| | | #define LOW_POWER_EN (0) |
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| | | #endif |
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| | | #endif |
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| | | |
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| | | /** Enable 32.768K crystal as low power mode clock source */ |
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| | |
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| | | |
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| | | /** Enable UWB high performance mode, it will increase power consumption */ |
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| | | #ifndef HIGH_PERFORMANCE_MODE_EN |
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| | | #define HIGH_PERFORMANCE_MODE_EN (0) |
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| | | #define HIGH_PERFORMANCE_MODE_EN (1) |
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| | | #endif |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | |
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| | | /* =========================================================================================================================== */ |
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| | | |
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| | | /** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */ |
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| | | #if defined(CELL_PHONE_EN) |
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| | | #define SYS_CLK_SOURCE (CLOCK_62P4M_EXT38P4M_SINE_TO_SYS_CLK) |
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| | | #else |
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| | | #define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK) |
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| | | #endif |
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| | | |
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| | | /** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */ |
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| | | #define AHB_DIV (CLOCK_DIVIDED_BY_1) |
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| | |
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| | | #define APB_DIV (CLOCK_DIVIDED_BY_1) |
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| | | |
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| | | /** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */ |
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| | | #if defined(CELL_PHONE_EN) |
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| | | #define CLK_32K_SOURCE (CLOCK_EXT32K_SQUARE_TO_32K_CLK) |
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| | | #else |
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| | | #if XTAL32K_EN |
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| | | #define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK) |
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| | | #define LOW_POWER_CLOCK_PPM (50) |
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| | | #else |
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| | | #define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK) |
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| | | #define LOW_POWER_CLOCK_PPM (1000) |
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| | | #endif |
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| | | #endif |
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| | | |
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| | | /** Enable system tick timer (period = 10ms), needed by OS */ |
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| | |
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| | | /* ================ UWB configuration ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | | |
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| | | /** Enable Post-process filter */ |
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| | | #define FILTER_EN (0) |
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| | | |
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| | | /** Enable RSSI output */ |
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| | | #define RSSI_EN (1) |
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| | | |
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| | | /** Enable Channel status information output */ |
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| | | #define CSI_EN (0) |
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| | | |
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| | | /** Enable PDoA 3D */ |
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| | | #define PDOA_3D_EN (0) |
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| | | |
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| | | /** Enable AoA */ |
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| | | #define AOA_EN (1) |
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| | | |
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| | | /** Measure angle on 1 (responder side), 2 (initiator side), 3 (both sides), 0 (None) */ |
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| | | #define MEASURE_ANGLE_ON_ROLE (3) |
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| | | |
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| | | /** TX power level: 0 ~ 60 */ |
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| | | #define TX_POWER_LEVEL (55) |
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| | | #define TX_POWER_LEVEL (36) |
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| | | #define RANGING_CORR (0) |
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| | | /** Antenna ports combination, @ref macro definition RX_xPORTS_ANT_xxx */ |
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| | | #define RX_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2) |
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| | | |
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| | | /** Antenna port number for AoA, 2~4 */ |
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| | | #define RX_AOA_ANT_PORTS_NUM (4) |
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| | | /** Dynamic update RX main antenna, can be enabled only when 4 ports are in use */ |
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| | | #define DYNAMIC_UPDATE_MAIN_ANTENNA_EN (0) |
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| | | |
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| | | /** Antenna ports combination for AoA, @ref enum RX_ANTENNA_MODE_T */ |
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| | | #define RX_AOA_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2) |
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| | | #if PDOA_3D_EN |
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| | | /// Antenna pattern |
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| | | #define ANT_PATTERN (ANT_PATTERN_SQUARE) |
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| | | /// Antenna layout, @ref enum ANT_LAYOUT_T |
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| | | #define ANT_LAYOUT (ANT_LAYOUT_HORIZONTAL) |
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| | | #else |
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| | | /// Antenna pattern |
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| | | #define ANT_PATTERN (ANT_PATTERN_LINEAR) |
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| | | #endif |
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| | | //#define MY_MODE |
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| | | /** Enable load cap automatic tuning during ranging procedure */ |
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| | | #define XTAL_AUTO_TUNE_EN (1) |
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| | | |
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| | | /** Antenna pattern: Linear or Square */ |
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| | | #define SQUARE_4ANTS (0) |
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| | | /** Enable kalman filter as post process filter, FILTER_EN should be enabled meanwhile */ |
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| | | #define KF_EN (0) |
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| | | |
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| | | /** Velocity of propagation (%) */ |
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| | | #define VP_VAL (100) |
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| | | |
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| | | /** Maximum PHY payload length */ |
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| | | #define PHY_PAYLOAD_LEN_MAX (127) |
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| | | #define DW1000 |
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| | | /* ========================================== Timing configuration ======================================== */ |
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| | | |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ Simple Selection ================ */ |
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| | | /* =========================================================================================================================== */ |
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| | | //#define MK_SIMPLE_TX |
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| | | |
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| | | //#define MK_SIMPLE_RX |
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| | | |
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| | | //#define MK_DS_TWR_INIT |
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| | | |
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| | | //#define MK_DS_TWR_RESP |
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| | | |
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| | | //#define MK_DS_TWR_INIT_STS |
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| | | |
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| | | //#define MK_DS_TWR_RESP_STS |
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| | | |
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| | | //#define MK_SS_TWR_DW_INIT |
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| | | |
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| | | #define MK_SS_TWR_DW_RESP |
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| | | |
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| | | /// Period prefetch time for event program from wakeup - 400us+ |
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| | | #define UWB_PERIOD_PREFETCH_TIME (US_TO_PHY_TIMER_COUNT(400)) |
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| | | /// Event prefetch time for event program - 300us |
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| | | #define UWB_EVT_PREFETCH_TIME (US_TO_PHY_TIMER_COUNT(300)) |
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| | | /// RX window open in advance time - 10us |
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| | | #define UWB_RX_OPEN_IN_ADVANCE (US_TO_PHY_TIMER_COUNT(10)) |
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| | | /// RX window - 750us |
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| | | #define UWB_RX_WINDOW (US_TO_PHY_TIMER_COUNT(750)) |
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| | | //#define LED_PIN IO_PIN_4 |
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| | | #define INPUT_5V_Pin IO_PIN_11 |
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| | | #define RSSI_EN (1) |
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| | | |
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| | | #define _4G_USART_RX_Pin IO_PIN_6 |
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| | | #define ACCLERATE_DETECT_Pin IO_PIN_2 |
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| | | #define SDA_PIN IO_PIN_3 |
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| | | #define SER_PIN IO_PIN_3 |
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| | | #define SCL_PIN IO_PIN_4 |
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| | | #define SRCLK_PIN IO_PIN_8 |
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| | | #define RCLK_PIN IO_PIN_7 |
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| | | #define MODE_CHANGE_PIN IO_PIN_0 |
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| | | #define LORA_CS IO_PIN_8 |
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| | | #define LORA_MOSI IO_PIN_11 |
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| | | #define LORA_MISO IO_PIN_12 |
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| | | #define LORA_CLK IO_PIN_13 |
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| | | #define LORA_IRQ IO_PIN_7 |
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| | | #define LORA_BUSY IO_PIN_2 |
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| | | #define LORA_NRST IO_PIN_4 |
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| | | #define SOS_PIN IO_PIN_4 //这个未定义 |
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| | | /* =========================================================================================================================== */ |
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| | | /* ================ End ================ */ |
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| | | /* =========================================================================================================================== */ |
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