| | |
| | | { |
| | | switch (irq_type) |
| | | { |
| | | case GPIO_IRQ_TYPE_LOW_LEVEL: |
| | | gpio_handle[0].base->INTPOLCLR = (1U << pin); |
| | | gpio_handle[0].base->INTTYPECLR = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_HIGH_LEVEL: |
| | | gpio_handle[0].base->INTPOLSET = (1U << pin); |
| | | gpio_handle[0].base->INTTYPECLR = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_FALLING_EDGE: |
| | | gpio_handle[0].base->INTPOLCLR = (1U << pin); |
| | | gpio_handle[0].base->INTTYPESET = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_RISING_EDGE: |
| | | gpio_handle[0].base->INTPOLSET = (1U << pin); |
| | | gpio_handle[0].base->INTTYPESET = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_LOW_LEVEL: |
| | | gpio_handle[0].base->INTPOLCLR = (1U << pin); |
| | | gpio_handle[0].base->INTTYPECLR = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_HIGH_LEVEL: |
| | | gpio_handle[0].base->INTPOLSET = (1U << pin); |
| | | gpio_handle[0].base->INTTYPECLR = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_FALLING_EDGE: |
| | | gpio_handle[0].base->INTPOLCLR = (1U << pin); |
| | | gpio_handle[0].base->INTTYPESET = (1U << pin); |
| | | break; |
| | | case GPIO_IRQ_TYPE_RISING_EDGE: |
| | | gpio_handle[0].base->INTPOLSET = (1U << pin); |
| | | gpio_handle[0].base->INTTYPESET = (1U << pin); |
| | | break; |
| | | } |
| | | |
| | | gpio_handle[0].irq_handler[pin] = irq_handler; |