ChinaUWBProject.git

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			/*
			* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
			* its subsidiaries and affiliates (collectly called MKSEMI).
			*
			* All rights reserved.
			*
			* Redistribution and use in source and binary forms, with or without
			* modification, are permitted provided that the following conditions are met:
			*
			* 1. Redistributions of source code must retain the above copyright notice,
			* this list of conditions and the following disclaimer.
			*
			* 2. Redistributions in binary form, except as embedded into an MKSEMI
			* integrated circuit in a product or a software update for such product,
			* must reproduce the above copyright notice, this list of conditions and
			* the following disclaimer in the documentation and/or other materials
			* provided with the distribution.
			*
			* 3. Neither the name of MKSEMI nor the names of its contributors may be used
			* to endorse or promote products derived from this software without
			* specific prior written permission.
			*
			* 4. This software, with or without modification, must only be used with a
			* MKSEMI integrated circuit.
			*
			* 5. Any software provided in binary form under this license must not be
			* reverse engineered, decompiled, modified and/or disassembled.
			*
			* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
			* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
			* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
			* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
			* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
			* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
			* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
			* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
			* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
			* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
			*/

			#ifndef USER_CONFIG_H_
			#define USER_CONFIG_H_

			/* =========================================================================================================================== */
			/* ================ Silicon configuration ================ */
			/* =========================================================================================================================== */

			/** CPU model */
			#define CPU_MK8000

			/* =========================================================================================================================== */
			/* ================ Board configuration ================ */
			/* =========================================================================================================================== */

			/* =========================================================================================================================== */
			/* ================ Debug/TRACE configuration ================ */
			/* =========================================================================================================================== */

			/** Enable trace output */
			#define TRACE_EN (1)

			/** Enable exception reboot */
			#ifndef TRACE_REBOOT_EN
			#define TRACE_REBOOT_EN (1)
			#endif

			/** Enable standard format output */
			#define TRACE_STD_LIB_EN (0)

			/** Configure trace level for modules: BOOT \| TEST \| UCI \| UWB \| APP \| DRIVER \| PHY \| MAC */
			#define TRACE_LVL_CONFIG_0 (0x44444004)

			/** Configure trace level for modules: CCC \| FIRA \| OS */
			#define TRACE_LVL_CONFIG_1 (0x00000444)

			/* =========================================================================================================================== */
			/* ================ Power configuration ================ */
			/* =========================================================================================================================== */
			/** Enable low power mode */
			#ifndef LOW_POWER_EN
			#define LOW_POWER_EN (1)
			#endif

			/** Enable 32.768K crystal as low power mode clock source */
			#ifndef XTAL32K_EN
			#define XTAL32K_EN (1)
			#endif

			/** Enable DC-DC */
			#ifndef DCDC_EN
			#define DCDC_EN (1)
			#endif

			/** Enable BOR */
			#ifndef BOR_EN
			#define BOR_EN (0)
			#endif

			/** Enable BOD */
			#ifndef BOD_EN
			#define BOD_EN (0)
			#endif

			/** Enable UWB high performance mode, it will increase power consumption */
			#ifndef HIGH_PERFORMANCE_MODE_EN
			#define HIGH_PERFORMANCE_MODE_EN (0)
			#endif

			/* =========================================================================================================================== */
			/* ================ Clock configuration ================ */
			/* =========================================================================================================================== */

			/** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */
			#define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK)

			/** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
			#define AHB_DIV (CLOCK_DIVIDED_BY_1)

			/** APBCLK = AHBCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
			#define APB_DIV (CLOCK_DIVIDED_BY_1)

			/** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */
			#if XTAL32K_EN
			#define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK)
			#define LOW_POWER_CLOCK_PPM (50)
			#else
			#define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK)
			#define LOW_POWER_CLOCK_PPM (1000)
			#endif

			/** Enable system tick timer (period = 10ms), needed by OS */
			#define SYS_TICK_EN (1)

			/* =========================================================================================================================== */
			/* ================ UWB configuration ================ */
			/* =========================================================================================================================== */

			/** TX power level: 0 ~ 60 */
			#define TX_POWER_LEVEL (55)

			/** Antenna port number for AoA, 2~4 */
			#define RX_AOA_ANT_PORTS_NUM (4)

			/** Antenna ports combination for AoA, @ref enum RX_ANTENNA_MODE_T */
			#define RX_AOA_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2)

			/** Antenna pattern: Linear or Square */
			#define SQUARE_4ANTS (0)

			#define RANGING_CORR (0)

			/** Velocity of propagation (%) */
			#define VP_VAL (100)

			/** Maximum PHY payload length */
			#define PHY_PAYLOAD_LEN_MAX (127)


			/* =========================================================================================================================== */
			/* ================ Simple Selection ================ */
			/* =========================================================================================================================== */
			//#define MK_SIMPLE_TX

			//#define MK_SIMPLE_RX

			//#define MK_DS_TWR_INIT

			//#define MK_DS_TWR_RESP

			//#define MK_DS_TWR_INIT_STS

			//#define MK_DS_TWR_RESP_STS

			//#define MK_SS_TWR_DW_INIT

			#define MK_SS_TWR_DW_RESP

			#define INPUT_5V_Pin IO_PIN_11
			#define RSSI_EN (1)

			#define _4G_USART_RX_Pin IO_PIN_17
			#define ACCLERATE_DETECT_Pin IO_PIN_2
			#define SDA_PIN IO_PIN_3
			#define SER_PIN IO_PIN_3
			#define SCL_PIN IO_PIN_4
			#define SRCLK_PIN IO_PIN_8
			#define RCLK_PIN IO_PIN_7
			#define ADC_GND_ENABLE IO_PIN_12
			#define GET_USERKEY gpio_pin_get_val(SCL_PIN)
			/* =========================================================================================================================== */
			/* ================ End ================ */
			/* =========================================================================================================================== */

			#endif /* USER_CONFIG_H_ */