对比新文件 |
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| | | /* |
| | | * Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and |
| | | * its subsidiaries and affiliates (collectly called MKSEMI). |
| | | * |
| | | * All rights reserved. |
| | | * |
| | | * Redistribution and use in source and binary forms, with or without |
| | | * modification, are permitted provided that the following conditions are met: |
| | | * |
| | | * 1. Redistributions of source code must retain the above copyright notice, |
| | | * this list of conditions and the following disclaimer. |
| | | * |
| | | * 2. Redistributions in binary form, except as embedded into an MKSEMI |
| | | * integrated circuit in a product or a software update for such product, |
| | | * must reproduce the above copyright notice, this list of conditions and |
| | | * the following disclaimer in the documentation and/or other materials |
| | | * provided with the distribution. |
| | | * |
| | | * 3. Neither the name of MKSEMI nor the names of its contributors may be used |
| | | * to endorse or promote products derived from this software without |
| | | * specific prior written permission. |
| | | * |
| | | * 4. This software, with or without modification, must only be used with a |
| | | * MKSEMI integrated circuit. |
| | | * |
| | | * 5. Any software provided in binary form under this license must not be |
| | | * reverse engineered, decompiled, modified and/or disassembled. |
| | | * |
| | | * THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED |
| | | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| | | * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| | | * DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY |
| | | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| | | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| | | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| | | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| | | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| | | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| | | */ |
| | | |
| | | #include "mk_dual_timer.h" |
| | | #include "mk_clock.h" |
| | | #include "mk_reset.h" |
| | | #include "mk_trace.h" |
| | | |
| | | static struct DUAL_TIMER_HANDLE_T dual_timer_handle[DUAL_TIMER_MAX_NUM] = { |
| | | { |
| | | .base = TIMER2, |
| | | .irq = TIMER2_IRQn, |
| | | }, |
| | | { |
| | | .base = TIMER3, |
| | | .irq = TIMER3_IRQn, |
| | | }, |
| | | }; |
| | | |
| | | int dual_timer_open(enum DUAL_TIMER_DEV_T id, struct DUAL_TIMER_CFG_T *config) |
| | | { |
| | | if ((id >= DUAL_TIMER_MAX_NUM) || (config == NULL)) |
| | | { |
| | | return DRV_ERROR; |
| | | } |
| | | else if (id == DUAL_TIMER_ID0) |
| | | { |
| | | // enable TIMER2 clock |
| | | clock_enable(CLOCK_TIMER2); |
| | | } |
| | | else if (id == DUAL_TIMER_ID1) |
| | | { |
| | | // enable TIMER3 clock |
| | | clock_enable(CLOCK_TIMER3); |
| | | } |
| | | ASSERT((config->width == 0 && config->load < 0x10000) || (config->width == 1), "config is invalid"); |
| | | |
| | | // clear int status |
| | | dual_timer_handle[id].base->INTR_CLR = 0; |
| | | |
| | | // config |
| | | uint32_t val = DTIMER_CTRL_SIZE(config->width) | DTIMER_CTRL_PRESCALE(config->prescale) | DTIMER_CTRL_INT_EN(config->int_en); |
| | | |
| | | if (config->type == DUAL_TIMER_TYPE_ONESHOT) |
| | | { |
| | | val |= DTIMER_CTRL_ONE_SHOT_MSK; |
| | | } |
| | | else if (config->type == DUAL_TIMER_TYPE_PERIODIC) |
| | | { |
| | | val |= DTIMER_CTRL_MODE_MSK; |
| | | } |
| | | |
| | | dual_timer_handle[id].base->CTRL = val; |
| | | |
| | | // load |
| | | dual_timer_handle[id].base->LOAD = config->load; |
| | | |
| | | dual_timer_handle[id].int_en = config->int_en; |
| | | dual_timer_handle[id].callback = config->callback; |
| | | |
| | | #if (TIMER2_INT_MODE_EN || TIMER3_INT_MODE_EN) |
| | | NVIC_SetPriority(dual_timer_handle[id].irq, IRQ_PRIORITY_NORMAL); |
| | | NVIC_ClearPendingIRQ(dual_timer_handle[id].irq); |
| | | NVIC_EnableIRQ(dual_timer_handle[id].irq); |
| | | #endif |
| | | |
| | | return DRV_OK; |
| | | } |
| | | |
| | | int dual_timer_close(enum DUAL_TIMER_DEV_T id) |
| | | { |
| | | if (id >= DUAL_TIMER_MAX_NUM) |
| | | { |
| | | return DRV_ERROR; |
| | | } |
| | | |
| | | // disable |
| | | dual_timer_handle[id].base->CTRL &= ~DTIMER_CTRL_EN_MSK; |
| | | |
| | | #if (TIMER2_INT_MODE_EN || TIMER3_INT_MODE_EN) |
| | | NVIC_DisableIRQ(dual_timer_handle[id].irq); |
| | | NVIC_ClearPendingIRQ(dual_timer_handle[id].irq); |
| | | #endif |
| | | |
| | | if (id == DUAL_TIMER_ID0) |
| | | { |
| | | // disable TIMER2 clock |
| | | clock_disable(CLOCK_TIMER2); |
| | | } |
| | | else if (id == DUAL_TIMER_ID1) |
| | | { |
| | | // disable TIMER3 clock |
| | | clock_disable(CLOCK_TIMER3); |
| | | } |
| | | return DRV_OK; |
| | | } |
| | | |
| | | void dual_timer_start(enum DUAL_TIMER_DEV_T id, uint32_t start) |
| | | { |
| | | dual_timer_handle[id].base->LOAD = start; |
| | | // enable |
| | | dual_timer_handle[id].base->CTRL |= DTIMER_CTRL_EN_MSK; |
| | | } |
| | | |
| | | void dual_timer_stop(enum DUAL_TIMER_DEV_T id) |
| | | { |
| | | // disable |
| | | dual_timer_handle[id].base->CTRL &= ~DTIMER_CTRL_EN_MSK; |
| | | } |
| | | |
| | | void dual_timer_reset(void) |
| | | { |
| | | reset_module(RESET_MODULE_DUAL_TIMER); |
| | | } |
| | | |
| | | // update periodic counter value |
| | | void dual_timer_set(enum DUAL_TIMER_DEV_T id, uint32_t count) |
| | | { |
| | | // load |
| | | dual_timer_handle[id].base->BG_LOAD = count; |
| | | } |
| | | |
| | | uint32_t dual_timer_get(enum DUAL_TIMER_DEV_T id) |
| | | { |
| | | return dual_timer_handle[id].base->VALUE; |
| | | } |
| | | |
| | | // Dual-Timer work at one shot mode, usually disable interrupt |
| | | void dual_timer_delay(enum DUAL_TIMER_DEV_T id, uint32_t count) |
| | | { |
| | | // clear int status |
| | | dual_timer_handle[id].base->INTR_CLR = 0; |
| | | // load |
| | | dual_timer_handle[id].base->LOAD = count; |
| | | while ((dual_timer_handle[id].base->STATUS & DTIMER_STATUS_MSK) == 0) |
| | | { |
| | | } |
| | | } |
| | | |
| | | void TIMER2_IRQHandler(void) |
| | | { |
| | | #if TIMER2_INT_MODE_EN |
| | | enum DUAL_TIMER_DEV_T id = DUAL_TIMER_ID0; |
| | | // clear |
| | | dual_timer_handle[id].base->INTR_CLR = 0; |
| | | if (dual_timer_handle[id].callback) |
| | | { |
| | | dual_timer_handle[id].callback(&id, dual_timer_handle[id].base->LOAD); |
| | | } |
| | | #endif |
| | | } |
| | | |
| | | void TIMER3_IRQHandler(void) |
| | | { |
| | | #if TIMER3_INT_MODE_EN |
| | | enum DUAL_TIMER_DEV_T id = DUAL_TIMER_ID1; |
| | | // clear |
| | | dual_timer_handle[id].base->INTR_CLR = 0; |
| | | if (dual_timer_handle[id].callback) |
| | | { |
| | | dual_timer_handle[id].callback(&id, dual_timer_handle[id].base->LOAD); |
| | | } |
| | | #endif |
| | | } |