| | |
| | | { |
| | | if (uci_validate(recv_buff)) |
| | | { |
| | | uint16_t frame_len = *(recv_buff + 3) + UCI_HEADER_SIZE; |
| | | uint16_t frame_len = (uint16_t)((recv_buff[2] << 8) + recv_buff[3] + UCI_HEADER_SIZE); |
| | | |
| | | if (WsfQueueCount(&g_uci_tl_dev.tl_down_queue) < UCI_MAX_DL_ITEMS) |
| | | { |
| | |
| | | if (!tx_idle) |
| | | { |
| | | gpio_pin_set(SLAVE2HOST_HS_GPIO); |
| | | WsfTimerStop(&g_uci_tl_dev.tl_timer); |
| | | spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL); |
| | | if (tl_up_msg != NULL) |
| | | { |
| | |
| | | memset(send_buff, 0, UCI_TX_BUFF_SIZE); |
| | | spi_open(UCI_PORT, &uci_spi_cfg); |
| | | spi_transfer(UCI_PORT, send_buff, recv_buff, UCI_RX_BUFF_SIZE, NULL); |
| | | WsfTimerStartMs(&g_uci_tl_dev.tl_timer, UCI_HS_TIMEOUT_MS, WSF_TIMER_ONE_SHOT); |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback); |
| | | gpio_pin_clr(SLAVE2HOST_HS_GPIO); |
| | | rx_idle = false; |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback); |
| | | power_mode_request(POWER_UNIT_UCI_RX, POWER_MODE_SLEEP); |
| | | } |
| | | else |
| | | { |
| | | WsfTimerStop(&g_uci_tl_dev.tl_timer); |
| | | spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL); |
| | | rx_over_callback(NULL, 0); |
| | | memset(recv_buff, 0, UCI_RX_BUFF_SIZE); |
| | | memset(send_buff, 0, UCI_TX_BUFF_SIZE); |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback); |
| | | gpio_pin_set(SLAVE2HOST_HS_GPIO); |
| | | rx_idle = true; |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback); |
| | | power_mode_clear(POWER_UNIT_UCI_RX); |
| | | } |
| | | } |
| | |
| | | } |
| | | spi_open(UCI_PORT, &uci_spi_cfg); |
| | | spi_transfer(UCI_PORT, send_buff, recv_buff, UCI_RX_BUFF_SIZE, NULL); |
| | | WsfTimerStartMs(&g_uci_tl_dev.tl_timer, UCI_HS_TIMEOUT_MS, WSF_TIMER_ONE_SHOT); |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback); |
| | | gpio_pin_clr(SLAVE2HOST_HS_GPIO); |
| | | } |
| | | else |
| | | { |
| | | WsfTimerStop(&g_uci_tl_dev.tl_timer); |
| | | } |
| | | |
| | | rx_idle = false; |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback); |
| | | power_mode_request(POWER_UNIT_UCI_RX, POWER_MODE_SLEEP); |
| | | } |
| | | else |
| | | { |
| | | WsfTimerStop(&g_uci_tl_dev.tl_timer); |
| | | spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL); |
| | | rx_over_callback(NULL, 0); |
| | | if (!tx_idle) |
| | |
| | | } |
| | | memset(recv_buff, 0, UCI_RX_BUFF_SIZE); |
| | | memset(send_buff, 0, UCI_TX_BUFF_SIZE); |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback); |
| | | gpio_pin_set(SLAVE2HOST_HS_GPIO); |
| | | rx_idle = true; |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback); |
| | | power_mode_clear(POWER_UNIT_UCI_RX); |
| | | power_mode_clear(POWER_UNIT_UCI_TX); |
| | | } |
| | |
| | | spi_transfer(UCI_PORT, send_buff, recv_buff, tl_up_msg->msg_length, tx_over_callback); |
| | | #else |
| | | spi_transfer(UCI_PORT, send_buff, recv_buff, UCI_RX_BUFF_SIZE, NULL); |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_RISING_EDGE, host2slave_gpio_callback); |
| | | #endif |
| | | gpio_pin_clr(SLAVE2HOST_HS_GPIO); |
| | | WsfTimerStartMs(&g_uci_tl_dev.tl_timer, UCI_HS_TIMEOUT_MS, WSF_TIMER_ONE_SHOT); |
| | |
| | | static void uci_tl_timer_notify(void) |
| | | { |
| | | uint32_t lock = int_lock(); |
| | | |
| | | gpio_enable_irq(HOST2SLAVE_HS_GPIO, GPIO_IRQ_TYPE_FALLING_EDGE, host2slave_gpio_callback); |
| | | gpio_pin_set(SLAVE2HOST_HS_GPIO); |
| | | |
| | | if (!tx_idle) |
| | | { |
| | | LOG_INFO(TRACE_MODULE_UCI, "UCI Host did not ACK in time\n"); |
| | | gpio_pin_set(SLAVE2HOST_HS_GPIO); |
| | | spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL); |
| | | if (rx_idle) |
| | | { |
| | | LOG_INFO(TRACE_MODULE_UCI, "UCI Host did not ACK in time\n"); |
| | | spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL); |
| | | } |
| | | |
| | | if (++retry_cnt > UCI_SEND_RETRY_MAX) |
| | | { |
| | |
| | | |
| | | g_uci_tl_dev.uci_tl_up_done_notify(); |
| | | tx_idle = true; |
| | | power_mode_clear(POWER_UNIT_UCI_TX); |
| | | } |
| | | if (!rx_idle) |
| | | { |
| | | LOG_INFO(TRACE_MODULE_UCI, "UCI Host did not send CMD in time after CMD pin has gone low\n"); |
| | | spi_abort_dma(UCI_PORT, SPI_DMA_ABORT_TX | SPI_DMA_ABORT_RX, NULL, NULL); |
| | | rx_idle = true; |
| | | power_mode_clear(POWER_UNIT_UCI_RX); |
| | | } |
| | | int_unlock(lock); |
| | | |
| | | power_mode_clear(POWER_UNIT_UCI_TX); |
| | | } |
| | | |
| | | #endif |