Merge branch '安邦测距手环' of http://47.108.70.204:60062/r/ChinaUWBProject into ...

yincheng.zhong

2024-08-27 fc78430a35be252a1cd5a29b5b66290a68cd9ca3

 keil/include/drivers/mk_clock.c

@@ -172,17 +172,17 @@

    switch (mux)
    {
        case CLOCK_32K_CLK_SEL:
            clock_32K_clk_config(choice);
            break;
        case CLOCK_SYS_CLK_SEL:
            clock_sys_clk_config(choice);
            break;
        case CLOCK_WDT_CLK_SEL:
            clock_wdt_clk_config(choice);
            break;
        default:
            break;
    case CLOCK_32K_CLK_SEL:
        clock_32K_clk_config(choice);
        break;
    case CLOCK_SYS_CLK_SEL:
        clock_sys_clk_config(choice);
        break;
    case CLOCK_WDT_CLK_SEL:
        clock_wdt_clk_config(choice);
        break;
    default:
        break;
    }
}

@@ -190,21 +190,21 @@
{
    switch (div_name)
    {
        case CLOCK_AHB_DIV:
            SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_HCLK_DIV_MSK) | SYSCON_CLK_DIV_HCLK_DIV(div_value);
            break;
        case CLOCK_APB_DIV:
            SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_PCLK_DIV_MSK) | SYSCON_CLK_DIV_PCLK_DIV(div_value);
            break;
        case CLOCK_FLASH_CTRL_DIV:
            SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK) | SYSCON_CLK_DIV_FLASH_CTRL_DIV(div_value);
            break;
        case CLOCK_UART1_FDIV:
            SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART1_FDIV_MSK) | SYSCON_CLK_DIV_UART1_FDIV(div_value);
            break;
        case CLOCK_UART0_FDIV:
            SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART0_FDIV_MSK) | SYSCON_CLK_DIV_UART0_FDIV(div_value);
            break;
    case CLOCK_AHB_DIV:
        SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_HCLK_DIV_MSK) | SYSCON_CLK_DIV_HCLK_DIV(div_value);
        break;
    case CLOCK_APB_DIV:
        SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_PCLK_DIV_MSK) | SYSCON_CLK_DIV_PCLK_DIV(div_value);
        break;
    case CLOCK_FLASH_CTRL_DIV:
        SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK) | SYSCON_CLK_DIV_FLASH_CTRL_DIV(div_value);
        break;
    case CLOCK_UART1_FDIV:
        SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART1_FDIV_MSK) | SYSCON_CLK_DIV_UART1_FDIV(div_value);
        break;
    case CLOCK_UART0_FDIV:
        SYSCON->CLK_DIV = (SYSCON->CLK_DIV & ~SYSCON_CLK_DIV_UART0_FDIV_MSK) | SYSCON_CLK_DIV_UART0_FDIV(div_value);
        break;
    }
}

@@ -213,24 +213,24 @@
    uint32_t freq = 0;
    switch (clk_name)
    {
        case CLOCK_SYS_CLK:
            freq = clock_get_sys_clk_freq();
            break;
        case CLOCK_AHB_CLK:
            freq = clock_get_ahb_clk_freq();
            break;
        case CLOCK_APB_CLK:
            freq = clock_get_apb_clk_freq();
            break;
        case CLOCK_WDT_CLK:
            freq = clock_get_wdt_clk_freq();
            break;
        case CLOCK_32K_CLK:
            freq = clock_get_32k_clk_freq();
            break;
        case CLOCK_FLASH_CLK:
            freq = clock_get_flash_clk_freq();
            break;
    case CLOCK_SYS_CLK:
        freq = clock_get_sys_clk_freq();
        break;
    case CLOCK_AHB_CLK:
        freq = clock_get_ahb_clk_freq();
        break;
    case CLOCK_APB_CLK:
        freq = clock_get_apb_clk_freq();
        break;
    case CLOCK_WDT_CLK:
        freq = clock_get_wdt_clk_freq();
        break;
    case CLOCK_32K_CLK:
        freq = clock_get_32k_clk_freq();
        break;
    case CLOCK_FLASH_CLK:
        freq = clock_get_flash_clk_freq();
        break;
    }
    return freq;
}