| | |
| | | .dma_wr_ch = DMA_CH2, |
| | | .dma_rd_ch = DMA_CH3, |
| | | .config = |
| | | { |
| | | .timeout = 0xFFFFU, |
| | | .cs_high_time = 0xFU, |
| | | .dual_mode = false, |
| | | .prefetch_dis = false, |
| | | .cache_prefetch_dis = false, |
| | | .feedback_clk_sel = false, |
| | | .spi_sck_high = false, |
| | | .spi_falling_edge_active = true, |
| | | .dma_en = false, |
| | | .int_en = false, |
| | | .start_addr = FLASH_BASE, |
| | | .total_size = FLASH_SIZE, |
| | | .block_size = FLASH_BLOCK_SIZE, |
| | | .sector_size = FLASH_SECTOR_SIZE, |
| | | .page_size = FLASH_PAGE_SIZE, |
| | | }, |
| | | { |
| | | .timeout = 0xFFFFU, |
| | | .cs_high_time = 0xFU, |
| | | .dual_mode = false, |
| | | .prefetch_dis = false, |
| | | .cache_prefetch_dis = false, |
| | | .feedback_clk_sel = false, |
| | | .spi_sck_high = false, |
| | | .spi_falling_edge_active = true, |
| | | .dma_en = false, |
| | | .int_en = false, |
| | | .start_addr = FLASH_BASE, |
| | | .total_size = FLASH_SIZE, |
| | | .block_size = FLASH_BLOCK_SIZE, |
| | | .sector_size = FLASH_SECTOR_SIZE, |
| | | .page_size = FLASH_PAGE_SIZE, |
| | | }, |
| | | .callback = NULL, |
| | | .flash_type = 0, |
| | | .wrsr_type = 0, // MXIC automotive flash type need set to 1 |
| | |
| | | // update state |
| | | switch (flash_handle[id].state) |
| | | { |
| | | case FLASH_STATE_READY: |
| | | flash_handle[id].state = new_state; |
| | | break; |
| | | case FLASH_STATE_BUSY_READ: |
| | | case FLASH_STATE_BUSY_ERASE: |
| | | case FLASH_STATE_BUSY_WRITE: |
| | | ret = DRV_BUSY; |
| | | break; |
| | | case FLASH_STATE_RESET: |
| | | case FLASH_STATE_TIMEOUT: |
| | | case FLASH_STATE_ERROR: |
| | | ret = DRV_ERROR; |
| | | break; |
| | | case FLASH_STATE_READY: |
| | | flash_handle[id].state = new_state; |
| | | break; |
| | | case FLASH_STATE_BUSY_READ: |
| | | case FLASH_STATE_BUSY_ERASE: |
| | | case FLASH_STATE_BUSY_WRITE: |
| | | ret = DRV_BUSY; |
| | | break; |
| | | case FLASH_STATE_RESET: |
| | | case FLASH_STATE_TIMEOUT: |
| | | case FLASH_STATE_ERROR: |
| | | ret = DRV_ERROR; |
| | | break; |
| | | } |
| | | int_unlock(lock); |
| | | |
| | |
| | | else |
| | | { |
| | | for (flash_handle[id].wr_nbyte_cfg.write_count = 0x01U; flash_handle[id].wr_nbyte_cfg.write_count <= flash_handle[id].wr_nbyte_cfg.write_num; |
| | | flash_handle[id].wr_nbyte_cfg.write_count++) |
| | | flash_handle[id].wr_nbyte_cfg.write_count++) |
| | | { |
| | | switch (flash_handle[id].wr_nbyte_cfg.page_count) |
| | | { |
| | | case WRITE_ONE_PAGES: |
| | | case WRITE_ONE_PAGES: |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len); |
| | | break; |
| | | |
| | | case WRITE_TWO_PAGES: |
| | | if (0x01U == flash_handle[id].wr_nbyte_cfg.write_count) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len); |
| | | break; |
| | | flash_handle[id].wr_nbyte_cfg.dest_tmp_addr += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | } |
| | | else if (flash_handle[id].wr_nbyte_cfg.write_count == flash_handle[id].wr_nbyte_cfg.write_num) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.end_page_inc_data_len); |
| | | } |
| | | break; |
| | | |
| | | case WRITE_TWO_PAGES: |
| | | if (0x01U == flash_handle[id].wr_nbyte_cfg.write_count) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len); |
| | | flash_handle[id].wr_nbyte_cfg.dest_tmp_addr += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | } |
| | | else if (flash_handle[id].wr_nbyte_cfg.write_count == flash_handle[id].wr_nbyte_cfg.write_num) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.end_page_inc_data_len); |
| | | } |
| | | break; |
| | | |
| | | default: |
| | | if (0x01U == flash_handle[id].wr_nbyte_cfg.write_count) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len); |
| | | flash_handle[id].wr_nbyte_cfg.dest_tmp_addr += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | } |
| | | else if (flash_handle[id].wr_nbyte_cfg.write_count == flash_handle[id].wr_nbyte_cfg.write_num) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.end_page_inc_data_len); |
| | | } |
| | | else |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].config.page_size); |
| | | flash_handle[id].wr_nbyte_cfg.dest_tmp_addr += flash_handle[id].config.page_size; |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].config.page_size; |
| | | } |
| | | break; |
| | | default: |
| | | if (0x01U == flash_handle[id].wr_nbyte_cfg.write_count) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len); |
| | | flash_handle[id].wr_nbyte_cfg.dest_tmp_addr += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].wr_nbyte_cfg.start_page_inc_data_len; |
| | | } |
| | | else if (flash_handle[id].wr_nbyte_cfg.write_count == flash_handle[id].wr_nbyte_cfg.write_num) |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].wr_nbyte_cfg.end_page_inc_data_len); |
| | | } |
| | | else |
| | | { |
| | | flash_page_write_nbytes(id, flash_handle[id].wr_nbyte_cfg.dest_tmp_addr, &buf[flash_handle[id].wr_nbyte_cfg.src_buf_pos], |
| | | flash_handle[id].config.page_size); |
| | | flash_handle[id].wr_nbyte_cfg.dest_tmp_addr += flash_handle[id].config.page_size; |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].config.page_size; |
| | | } |
| | | break; |
| | | } |
| | | } |
| | | |
| | |
| | | // wait until the flash writing operation is complete |
| | | delay_us(350); |
| | | if ((flash_handle[id].wr_nbyte_cfg.write_count == flash_handle[id].wr_nbyte_cfg.write_num) && |
| | | (flash_handle[id].wr_nbyte_cfg.write_count > 0x01U)) |
| | | (flash_handle[id].wr_nbyte_cfg.write_count > 0x01U)) |
| | | { |
| | | flash_handle[id].wr_nbyte_cfg.src_buf_pos += flash_handle[id].config.page_size; |
| | | // Write enable |