ChinaUWBProject.git

			@@ -53,17 +53,17 @@
			.base = I2C0,
			.irq = I2C0_IRQn,
			.config =
			{
			.mode = I2C_MASTER,
			.speed_mode = I2C_SPEED_STANDARD,
			.addr_mode = I2C_7BIT_ADDR,
			.local_addr = MK_DEV_ADDRESS,
			.target_addr = 0x33,
			.rx_level = I2C_RXFIFO_CHAR_1,
			.tx_level = I2C_TXFIFO_CHAR_1,
			.int_rx = false,
			.int_tx = false,
			},
			{
			.mode = I2C_MASTER,
			.speed_mode = I2C_SPEED_STANDARD,
			.addr_mode = I2C_7BIT_ADDR,
			.local_addr = MK_DEV_ADDRESS,
			.target_addr = 0x33,
			.rx_level = I2C_RXFIFO_CHAR_1,
			.tx_level = I2C_TXFIFO_CHAR_1,
			.int_rx = false,
			.int_tx = false,
			},
			},
			};

			@@ -170,19 +170,19 @@
			// update state
			switch (i2c_handle[id].state)
			{
			case I2C_STATE_READY:
			i2c_handle[id].state = state;
			break;
			case I2C_STATE_BUSY_TX:
			case I2C_STATE_BUSY_RX:
			case I2C_STATE_BUSY_TX_RX:
			ret = DRV_BUSY;
			break;
			case I2C_STATE_RESET:
			case I2C_STATE_TIMEOUT:
			case I2C_STATE_ERROR:
			ret = DRV_ERROR;
			break;
			case I2C_STATE_READY:
			i2c_handle[id].state = state;
			break;
			case I2C_STATE_BUSY_TX:
			case I2C_STATE_BUSY_RX:
			case I2C_STATE_BUSY_TX_RX:
			ret = DRV_BUSY;
			break;
			case I2C_STATE_RESET:
			case I2C_STATE_TIMEOUT:
			case I2C_STATE_ERROR:
			ret = DRV_ERROR;
			break;
			}
			int_unlock(lock);

			@@ -621,7 +621,7 @@
			i2c_handle[id].rx_buff[i2c_handle[id].rx_count++] = (uint8_t)i2c_handle[id].base->DATA;
			}

			_i2c_exit:
			_i2c_exit:
			// update state
			i2c_handle[id].state = I2C_STATE_READY;

			@@ -832,7 +832,7 @@

			uint8_t rx_level = GET_BIT_FIELD(i2c_handle[id].base->FIFO_TH, I2C_FIFO_TH_RX_TL_MSK, I2C_FIFO_TH_RX_TL_POS);
			if (i2c_handle[id].rx_count == i2c_handle[id].rx_size)
			{ // RX done
			{ // RX done
			usr_callback = i2c_handle[id].rx_callback;
			// restore rx threshold
			i2c_handle[id].base->FIFO_TH =
			@@ -851,7 +851,7 @@
			{
			// set rx fifo threshold if necessary
			i2c_handle[id].base->FIFO_TH = SET_BIT_FIELD(i2c_handle[id].base->FIFO_TH, I2C_FIFO_TH_RX_TL_MSK, I2C_FIFO_TH_RX_TL_POS,
			(i2c_handle[id].rx_size - i2c_handle[id].rx_count - 1));
			(i2c_handle[id].rx_size - i2c_handle[id].rx_count - 1));
			}
			}
			}
			@@ -878,7 +878,7 @@
			// tx buffer has all been sent in bulk mode yet the
			// master is still requesting more data.
			if (i2c_handle[id].tx_count == i2c_handle[id].tx_size)
			{ // TX done
			{ // TX done
			usr_callback = i2c_handle[id].tx_callback;

			// update state
			@@ -891,7 +891,7 @@
			int_stat = 0;
			}
			else
			{ // TX continue
			{ // TX continue
			// write data to FIFO
			while ((i2c_handle[id].tx_count < i2c_handle[id].tx_size) && (i2c_handle[id].base->STATUS1 & I2C_STATUS1_TFNF_MSK))
			{
			@@ -907,7 +907,7 @@
			if (i2c_handle[id].state & I2C_STATE_BUSY_TX)
			{
			if (i2c_handle[id].tx_count == i2c_handle[id].tx_size)
			{ // TX done
			{ // TX done
			usr_callback = i2c_handle[id].tx_callback;

			// update state
			@@ -929,7 +929,7 @@
			int_stat = 0;
			}
			else
			{ // TX continue
			{ // TX continue
			uint32_t restart = 0;
			uint32_t stop = 0;
			// write data to FIFO
			@@ -961,12 +961,12 @@
			else if (i2c_handle[id].state & I2C_STATE_BUSY_RX)
			{
			if (i2c_handle[id].tx_count == i2c_handle[id].rx_size)
			{ // TX done
			{ // TX done
			// mask tx empty interrupt
			i2c_handle[id].base->INTR_EN &= ~I2C_INTR_TX_EMPTY_MSK;
			}
			else
			{ // TX continue
			{ // TX continue
			uint32_t restart = 0;
			uint32_t stop = 0;

			@@ -995,7 +995,7 @@
			}

			if (i2c_handle[id].tx_count == i2c_handle[id].rx_size)
			{ // TX done
			{ // TX done
			// mask tx empty interrupt
			i2c_handle[id].base->INTR_EN &= ~I2C_INTR_TX_EMPTY_MSK;
			}