| | |
| | | // update state |
| | | switch (spi_handle[id].state) |
| | | { |
| | | case SPI_STATE_READY: |
| | | spi_handle[id].state = state; |
| | | break; |
| | | case SPI_STATE_BUSY_RX: |
| | | if (state == SPI_STATE_BUSY_TX) |
| | | { |
| | | spi_handle[id].state = SPI_STATE_BUSY_TX_RX; |
| | | } |
| | | else |
| | | { |
| | | ret = DRV_BUSY; |
| | | } |
| | | break; |
| | | case SPI_STATE_BUSY_TX: |
| | | if (state == SPI_STATE_BUSY_RX) |
| | | { |
| | | spi_handle[id].state = SPI_STATE_BUSY_TX_RX; |
| | | } |
| | | else |
| | | { |
| | | ret = DRV_BUSY; |
| | | } |
| | | break; |
| | | case SPI_STATE_BUSY_TX_RX: |
| | | case SPI_STATE_READY: |
| | | spi_handle[id].state = state; |
| | | break; |
| | | case SPI_STATE_BUSY_RX: |
| | | if (state == SPI_STATE_BUSY_TX) |
| | | { |
| | | spi_handle[id].state = SPI_STATE_BUSY_TX_RX; |
| | | } |
| | | else |
| | | { |
| | | ret = DRV_BUSY; |
| | | break; |
| | | case SPI_STATE_RESET: |
| | | case SPI_STATE_TIMEOUT: |
| | | case SPI_STATE_ERROR: |
| | | ret = DRV_ERROR; |
| | | break; |
| | | } |
| | | break; |
| | | case SPI_STATE_BUSY_TX: |
| | | if (state == SPI_STATE_BUSY_RX) |
| | | { |
| | | spi_handle[id].state = SPI_STATE_BUSY_TX_RX; |
| | | } |
| | | else |
| | | { |
| | | ret = DRV_BUSY; |
| | | } |
| | | break; |
| | | case SPI_STATE_BUSY_TX_RX: |
| | | ret = DRV_BUSY; |
| | | break; |
| | | case SPI_STATE_RESET: |
| | | case SPI_STATE_TIMEOUT: |
| | | case SPI_STATE_ERROR: |
| | | ret = DRV_ERROR; |
| | | break; |
| | | } |
| | | int_unlock(lock); |
| | | |