| | |
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| | | #define VBAT_ADDRESS (0x08) |
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| | | #define VTEMP_ADDRESS (0x09) |
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| | | #define XTRIM_ADDRESS (0x1E) |
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| | | |
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| | | u8 module_power; |
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| | | int dwt_initialise(uint16_t config) |
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| | | { |
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| | | u32 power_temp,power_input; |
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| | | uint8_t plllockdetect = EC_CTRL_PLLLCK; |
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| | | uint16_t otp_addr = 0; |
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| | | uint32_t ldo_tune = 0; |
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| | |
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| | | } |
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| | | |
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| | | _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable |
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| | | |
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| | | dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f); |
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| | | if(module_power>67) |
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| | | {module_power=67;} |
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| | | if(module_power<0) |
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| | | {module_power=0;} |
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| | | if(module_power>36) |
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| | | { |
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| | | power_temp =(module_power-36); |
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| | | }else{ |
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| | | power_temp = ((6-(module_power/6))<<5)|(module_power%6); |
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| | | } |
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| | | power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp; |
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| | | dwt_write32bitreg(TX_POWER_ID, power_input); |
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| | | // Configure the CPLL lock detect |
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| | | dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect); |
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| | | |
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| | |
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| | | |
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| | | // Read system register / store local copy |
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| | | dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register |
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| | | |
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| | | { |
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| | | uint32_t reg; |
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| | | reg = dwt_read32bitreg(GPIO_CTRL_ID); |
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| | | reg |= 0x00014000; |
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| | | reg |= 0x00050000; |
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| | | dwt_write32bitreg(GPIO_CTRL_ID,reg); |
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| | | dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK); |
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| | | |
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| | | } |
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| | | return DWT_SUCCESS ; |
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| | | |
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| | | } // end dwt_initialise() |
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