UWB_SmallModule_F103.git

			@@ -10,12 +10,11 @@
			*
			*/

			#include "deca_types.h"
			#include <stddef.h>
			#include "deca_param_types.h"
			#include "deca_regs.h"
			#include "deca_device_api.h"
			#include "deca_sleep.h"
			#include "port.h"
			#include "dw_driver.h"

			// Defines for enable_clocks function
			#define FORCE_SYS_XTI 0
			@@ -42,9 +41,9 @@
			// Load ucode from OTP/ROM
			void _dwt_loaducodefromrom(void);
			// Read non-volatile memory
			uint32 _dwt_otpread(uint32 address);
			uint32_t _dwt_otpread(uint32_t address);
			// Program the non-volatile memory
			uint32 _dwt_otpprogword32(uint32 data, uint16 address);
			uint32_t _dwt_otpprogword32(uint32_t data, uint16_t address);
			// Upload the device configuration into always on memory
			void _dwt_aonarrayupload(void);
			// -------------------------------------------------------------------------------------------------------------------
			@@ -57,21 +56,21 @@
			// Structure to hold device data
			typedef struct
			{
			uint32 deviceID ;
			uint32 partID ;
			uint32 lotID ;
			uint8 chan; // Added channel here - used in the reading of accumulator
			uint8 longFrames ; // Flag in non-standard long frame mode
			uint8 otprev ; // OTP revision number (read during initialisation)
			uint32 txFCTRL ; // Keep TX_FCTRL register config
			uint8 xtrim; // XTAL trim value read from OTP
			uint8 dblbuffon; // Double RX buffer mode flag
			uint32 sysCFGreg ; // Local copy of system config register
			uint16 sleep_mode; // Used for automatic reloading of LDO tune and microcode at wake-up
			uint32_t deviceID ;
			uint32_t partID ;
			uint32_t lotID ;
			uint8_t chan; // Added channel here - used in the reading of accumulator
			uint8_t longFrames ; // Flag in non-standard long frame mode
			uint8_t otprev ; // OTP revision number (read during initialisation)
			uint32_t txFCTRL ; // Keep TX_FCTRL register config
			uint8_t xtrim; // XTAL trim value read from OTP
			uint8_t dblbuffon; // Double RX buffer mode flag
			uint32_t sysCFGreg ; // Local copy of system config register
			uint16_t sleep_mode; // Used for automatic reloading of LDO tune and microcode at wake-up

			dwt_callback_data_t cdata; // Callback data structure

			uint8 wait4resp ; // wait4response was set with last TX start command
			uint8_t wait4resp ; // wait4response was set with last TX start command
			int prfIndex ;

			void (dwt_txcallback)(const dwt_callback_data_t txd);
			@@ -104,18 +103,64 @@
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			// OTP addresses definitions
			#define CPUID_OTP_ADRESS 0x1d

			uint32_t ReadUniqueID(void)
			{
			uint8_t m_UIDAdd[4];
			uint32_t cpuID_add;
			//è·åCPUå¯ä¸ID
			// m_CpuID.Data32[0] = (vu32)(0x1ffff7e8);
			// m_CpuID.Data32[1] = (vu32)(0x1ffff7ec);
			// m_CpuID.Data32[2] = (vu32)(0x1ffff7f0);
			//è¿éæ¯é²æ¢åæ±ç¼è½çå°å¨åªéè¯»åçUIDï¼å°UIDçå°ååè§£åå¨RAMä¸
			//å å¯ç®æ³,å¾ç®åçå å¯ç®æ³
			m_UIDAdd[0] = 0xE8;
			m_UIDAdd[1] = m_UIDAdd[0]+0x0F; //f7 = e8 + 0f
			m_UIDAdd[2] = m_UIDAdd[1]+0x08; //ff = f7 + 08
			m_UIDAdd[3] = m_UIDAdd[2]-0xe0; //1f = ff - e0
			memcpy(&cpuID_add, (uint8_t*)m_UIDAdd, 4);

			return (uint32_t)(cpuID_add);
			}

			uint8_t UID_ERROR=0;
			void CheckCPUID(void)
			{ uint32_t cpuID = 0;
			uint32_t key_ID = 0;
			uint8_t i=10;
			cpuID = ReadUniqueID();
			Spi_ChangePrescaler(SPI_BaudRatePrescaler_256);
			while(i--)
			{
			dwt_otpread(CPUID_OTP_ADRESS,&key_ID,1);
			if(cpuID != key_ID)
			{
			UID_ERROR = 1;
			}
			else
			{
			UID_ERROR = 0;
			break;
			}
			}

			Spi_ChangePrescaler(SPI_BaudRatePrescaler_8);
			}
			#define LDOTUNE_ADDRESS (0x04)
			#define PARTID_ADDRESS (0x06)
			#define LOTID_ADDRESS (0x07)
			#define VBAT_ADDRESS (0x08)
			#define VTEMP_ADDRESS (0x09)
			#define XTRIM_ADDRESS (0x1E)

			int dwt_initialise(uint16 config)
			u8 module_power;
			int dwt_initialise(uint16_t config)
			{
			uint8 plllockdetect = EC_CTRL_PLLLCK;
			uint16 otp_addr = 0;
			uint32 ldo_tune = 0;

			u32 power_temp,power_input;
			uint8_t plllockdetect = EC_CTRL_PLLLCK;
			uint16_t otp_addr = 0;
			uint32_t ldo_tune = 0;

			dw1000local.dblbuffon = 0; // Double buffer mode off by default
			dw1000local.prfIndex = 0; // 16MHz
			@@ -128,30 +173,42 @@

			// Read and validate device ID return -1 if not recognised
			dw1000local.deviceID = dwt_readdevid() ;
			if (DWT_DEVICE_ID != dw1000local.deviceID) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
			while (DWT_DEVICE_ID != dw1000local.deviceID) // MP IC ONLY (i.e. DW1000) FOR THIS CODE
			{
			return DWT_ERROR ;
			dw1000local.deviceID = dwt_readdevid() ;
			}

			_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
			if(module_power>67)
			{module_power=67;}
			if(module_power<0)
			{module_power=0;}
			if(module_power>36)
			{
			power_temp =(module_power-36);
			}else{
			power_temp = ((6-(module_power/6))<<5)\|(module_power%6);
			}
			power_input= power_temp<<24\|power_temp<<16\|power_temp<<8\|power_temp;
			dwt_write32bitreg(TX_POWER_ID, power_input);

			//dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
			// Configure the CPLL lock detect
			dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);

			dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f);
			// Configure the CPLL lock detect
			dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect);

			// Read OTP revision number
			otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
			dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte
			// Read OTP revision number
			otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits)
			dw1000local.otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte

			// Load LDO tune from OTP and kick it if there is a value actually programmed.
			ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS);
			if((ldo_tune & 0xFF) != 0)
			{
			uint8 ldok = OTP_SF_LDO_KICK;
			// Kick LDO tune
			dwt_writetodevice(OTP_IF_ID, OTP_SF, 1, &ldok); // Set load LDE kick bit
			dw1000local.sleep_mode \|= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
			}
			if((ldo_tune & 0xFF) != 0)
			{
			uint8_t ldok = OTP_SF_LDO_KICK;
			// Kick LDO tune
			dwt_writetodevice(OTP_IF_ID, OTP_SF, 1, &ldok); // Set load LDE kick bit
			dw1000local.sleep_mode \|= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
			}

			// Load Part and Lot ID from OTP
			dw1000local.partID = _dwt_otpread(PARTID_ADDRESS);
			@@ -168,22 +225,31 @@

			// Load leading edge detect code
			if(config & DWT_LOADUCODE)
			{
			{
			_dwt_loaducodefromrom();
			dw1000local.sleep_mode \|= AON_WCFG_ONW_LLDE; // microcode must be loaded at wake-up
			}
			else // Should disable the LDERUN enable bit in 0x36, 0x4
			{
			uint16 rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1) ;
			rega &= 0xFDFF ; // Clear LDERUN bit
			dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1, rega) ;
			}
			}
			else // Should disable the LDERUN enable bit in 0x36, 0x4
			{
			uint16_t rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1) ;
			rega &= 0xFDFF ; // Clear LDERUN bit
			dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET + 1, rega) ;
			}

			_dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing

			// Read system register / store local copy
			dw1000local.sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register

			{
			uint32_t reg;
			reg = dwt_read32bitreg(GPIO_CTRL_ID);
			reg \|= 0x00014000;
			reg \|= 0x00050000;
			dwt_write32bitreg(GPIO_CTRL_ID,reg);
			dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK);

			}
			CheckCPUID();
			return DWT_SUCCESS ;

			} // end dwt_initialise()
			@@ -199,9 +265,9 @@
			*
			* returns the read OTP revision value
			*/
			uint8 dwt_otprevision(void)
			uint8_t dwt_otprevision(void)
			{
			return dw1000local.otprev ;
			return dw1000local.otprev ;
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -217,7 +283,7 @@
			*/
			void dwt_setGPIOforEXTTRX(void)
			{
			uint8 buf[GPIO_MODE_LEN];
			uint8_t buf[GPIO_MODE_LEN];

			// Set the GPIO to control external PA/LNA
			dwt_readfromdevice(GPIO_CTRL_ID, GPIO_MODE_OFFSET, GPIO_MODE_LEN, buf);
			@@ -241,16 +307,16 @@
			*
			* no return value
			*/
			void dwt_setGPIOdirection(uint32 gpioNum, uint32 direction)
			void dwt_setGPIOdirection(uint32_t gpioNum, uint32_t direction)
			{
			uint8 buf[GPIO_DIR_LEN];
			uint32 command = direction \| gpioNum;
			uint8_t buf[GPIO_DIR_LEN];
			uint32_t command = direction \| gpioNum;

			buf[0] = command & 0xff;
			buf[1] = (command >> 8) & 0xff;
			buf[2] = (command >> 16) & 0xff;
			buf[0] = command & 0xff;
			buf[1] = (command >> 8) & 0xff;
			buf[2] = (command >> 16) & 0xff;

			dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf);
			dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf);
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -266,16 +332,16 @@
			*
			* no return value
			*/
			void dwt_setGPIOvalue(uint32 gpioNum, uint32 value)
			void dwt_setGPIOvalue(uint32_t gpioNum, uint32_t value)
			{
			uint8 buf[GPIO_DOUT_LEN];
			uint32 command = value \| gpioNum;
			uint8_t buf[GPIO_DOUT_LEN];
			uint32_t command = value \| gpioNum;

			buf[0] = command & 0xff;
			buf[1] = (command >> 8) & 0xff;
			buf[2] = (command >> 16) & 0xff;
			buf[0] = command & 0xff;
			buf[1] = (command >> 8) & 0xff;
			buf[2] = (command >> 16) & 0xff;

			dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf);
			dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf);
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -289,7 +355,7 @@
			*
			* returns the 32 bit part ID value as programmed in the factory
			*/
			uint32 dwt_getpartid(void)
			uint32_t dwt_getpartid(void)
			{
			return dw1000local.partID;
			}
			@@ -305,7 +371,7 @@
			*
			* returns the 32 bit lot ID value as programmed in the factory
			*/
			uint32 dwt_getlotid(void)
			uint32_t dwt_getlotid(void)
			{
			return dw1000local.lotID;
			}
			@@ -321,9 +387,9 @@
			*
			* returns the read value which for DW1000 is 0xDECA0130
			*/
			uint32 dwt_readdevid(void)
			uint32_t dwt_readdevid(void)
			{
			return dwt_read32bitoffsetreg(DEV_ID_ID,0);
			return dwt_read32bitoffsetreg(DEV_ID_ID, 0);
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -368,32 +434,32 @@
			*/
			int dwt_configure(dwt_config_t *config)
			{
			uint8 nsSfd_result = 0;
			uint8 useDWnsSFD = 0;
			uint8 chan = config->chan ;
			uint32 regval ;
			uint16 reg16 = lde_replicaCoeff[config->rxCode];
			uint8 prfIndex = dw1000local.prfIndex = config->prf - DWT_PRF_16M;
			uint8 bw = ((chan == 4) \|\| (chan == 7)) ? 1 : 0 ; // Select wide or narrow band
			uint8_t nsSfd_result = 0;
			uint8_t useDWnsSFD = 0;
			uint8_t chan = config->chan ;
			uint32_t regval ;
			uint16_t reg16 = lde_replicaCoeff[config->rxCode];
			uint8_t prfIndex = dw1000local.prfIndex = config->prf - DWT_PRF_16M;
			uint8_t bw = ((chan == 4) \|\| (chan == 7)) ? 1 : 0 ; // Select wide or narrow band

			dw1000local.chan = config->chan ;

			#ifdef DWT_API_ERROR_CHECK
			if (config->dataRate > DWT_BR_6M8)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}// validate datarate parameter
			if ((config->prf > DWT_PRF_64M) \|\| (config->prf < DWT_PRF_16M))
			{
			return DWT_ERROR ; // validate Pulse Repetition Frequency
			return DWT_ERROR ; // validate Pulse Repetition Frequency
			}
			if (config->rxPAC > DWT_PAC64)
			{
			return DWT_ERROR ; // validate PAC size
			return DWT_ERROR ; // validate PAC size
			}
			if ((chan < 1) \|\| (chan > 7) \|\| (6 == chan))
			{
			return DWT_ERROR ; // validate channel number parameter
			return DWT_ERROR ; // validate channel number parameter
			}

			// validate TX and TX pre-amble codes selections
			@@ -416,8 +482,10 @@
			case DWT_PLEN_512 :
			case DWT_PLEN_256 :
			case DWT_PLEN_128 :
			case DWT_PLEN_64 : break ; // all okay
			default : return DWT_ERROR ; // not a good preamble length parameter
			case DWT_PLEN_64 :
			break ; // all okay
			default :
			return DWT_ERROR ; // not a good preamble length parameter
			}

			if(config->phrMode > DWT_PHRMODE_EXT)
			@@ -441,7 +509,7 @@

			dw1000local.sysCFGreg \|= (SYS_CFG_PHR_MODE_11 & (config->phrMode << 16)) ;

			dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
			dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
			// Set the lde_replicaCoeff
			dwt_write16bitoffsetreg(LDE_IF_ID, LDE_REPC_OFFSET, reg16) ;

			@@ -472,13 +540,13 @@
			{
			if(config->txPreambLength == DWT_PLEN_64)
			{
			uint8 temp = 0x10;
			uint8_t temp = 0x10;
			dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, 0x10);
			dwt_writetodevice(DRX_CONF_ID, 0x26, 1, &temp);
			}
			else
			{
			uint8 temp = 0x28;
			uint8_t temp = 0x28;
			dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, 0x20);
			dwt_writetodevice(DRX_CONF_ID, 0x26, 1, &temp);
			}
			@@ -502,26 +570,26 @@
			// Set (non-standard) user SFD for improved performance,
			if(config->nsSFD)
			{
			// Write non standard (DW) SFD length
			dwt_writetodevice(USR_SFD_ID,0x00,1,&dwnsSFDlen[config->dataRate]);
			nsSfd_result = 3 ;
			useDWnsSFD = 1 ;
			// Write non standard (DW) SFD length
			dwt_writetodevice(USR_SFD_ID, 0x00, 1, &dwnsSFDlen[config->dataRate]);
			nsSfd_result = 3 ;
			useDWnsSFD = 1 ;
			}
			regval = (CHAN_CTRL_TX_CHAN_MASK & (chan << CHAN_CTRL_TX_CHAN_SHIFT)) \| // Transmit Channel
			(CHAN_CTRL_RX_CHAN_MASK & (chan << CHAN_CTRL_RX_CHAN_SHIFT)) \| // Receive Channel
			(CHAN_CTRL_RXFPRF_MASK & (config->prf << CHAN_CTRL_RXFPRF_SHIFT)) \| // RX PRF
			((CHAN_CTRL_TNSSFD\|CHAN_CTRL_RNSSFD) & (nsSfd_result << CHAN_CTRL_TNSSFD_SHIFT)) \| // nsSFD enable RX&TX
			((CHAN_CTRL_TNSSFD \| CHAN_CTRL_RNSSFD) & (nsSfd_result << CHAN_CTRL_TNSSFD_SHIFT)) \| // nsSFD enable RX&TX
			(CHAN_CTRL_DWSFD & (useDWnsSFD << CHAN_CTRL_DWSFD_SHIFT)) \| // Use DW nsSFD
			(CHAN_CTRL_TX_PCOD_MASK & (config->txCode << CHAN_CTRL_TX_PCOD_SHIFT)) \| // TX Preamble Code
			(CHAN_CTRL_RX_PCOD_MASK & (config->rxCode << CHAN_CTRL_RX_PCOD_SHIFT)) ; // RX Preamble Code

			dwt_write32bitreg(CHAN_CTRL_ID,regval) ;
			dwt_write32bitreg(CHAN_CTRL_ID, regval) ;

			// Set up TX Preamble Size and TX PRF
			// Set up TX Ranging Bit and Data Rate
			dw1000local.txFCTRL = (config->txPreambLength \| config->prf) << 16;
			dw1000local.txFCTRL \|= (config->dataRate << TX_FCTRL_TXBR_SHFT) \| TX_FCTRL_TR; // Always set ranging bit !!!
			dwt_write32bitoffsetreg(TX_FCTRL_ID,0,dw1000local.txFCTRL) ;
			dwt_write32bitoffsetreg(TX_FCTRL_ID, 0, dw1000local.txFCTRL) ;

			return DWT_SUCCESS ;

			@@ -540,7 +608,7 @@
			*
			* no return value
			*/
			void dwt_setrxantennadelay(uint16 rxDelay)
			void dwt_setrxantennadelay(uint16_t rxDelay)
			{
			// Set the RX antenna delay for auto TX timestamp adjustment
			dwt_write16bitoffsetreg(LDE_IF_ID, LDE_RXANTD_OFFSET, rxDelay);
			@@ -559,7 +627,7 @@
			*
			* no return value
			*/
			void dwt_settxantennadelay(uint16 txDelay)
			void dwt_settxantennadelay(uint16_t txDelay)
			{
			// Set the TX antenna delay for auto TX timestamp adjustment
			dwt_write16bitoffsetreg(TX_ANTD_ID, 0x0, txDelay);
			@@ -585,26 +653,26 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			int dwt_writetxdata(uint16 txFrameLength, uint8 *txFrameBytes, uint16 txBufferOffset)
			int dwt_writetxdata(uint16_t txFrameLength, uint8_t *txFrameBytes, uint16_t txBufferOffset)
			{
			#ifdef DWT_API_ERROR_CHECK
			if (dw1000local.longFrames)
			{
			if (txFrameLength > 1023)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}
			}
			else
			{
			if (txFrameLength > 127)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}
			}
			if (txFrameLength < 2)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}
			#endif

			@@ -613,7 +681,7 @@
			return DWT_ERROR ;
			}
			// Write the data to the IC TX buffer, (-2 bytes for auto generated CRC)
			dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength-2, txFrameBytes) ;
			dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength - 2, txFrameBytes) ;


			return DWT_SUCCESS ;
			@@ -635,7 +703,7 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			int dwt_writetxfctrl(uint16 txFrameLength, uint16 txBufferOffset)
			int dwt_writetxfctrl(uint16_t txFrameLength, uint16_t txBufferOffset)
			{

			#ifdef DWT_API_ERROR_CHECK
			@@ -643,26 +711,26 @@
			{
			if (txFrameLength > 1023)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}
			}
			else
			{
			if (txFrameLength > 127)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}
			}
			if (txFrameLength < 2)
			{
			return DWT_ERROR ;
			return DWT_ERROR ;
			}
			#endif

			// Write the frame length to the TX frame control register
			// dw1000local.txFCTRL has kept configured bit rate information
			uint32 reg32 = dw1000local.txFCTRL \| txFrameLength \| (txBufferOffset << 22);
			dwt_write32bitoffsetreg(TX_FCTRL_ID,0,reg32) ;
			uint32_t reg32 = dw1000local.txFCTRL \| txFrameLength \| (txBufferOffset << 22);
			dwt_write32bitoffsetreg(TX_FCTRL_ID, 0, reg32) ;

			return DWT_SUCCESS ;

			@@ -683,9 +751,9 @@
			*
			* no return value
			*/
			void dwt_readrxdata(uint8 *buffer, uint16 length, uint16 rxBufferOffset)
			void dwt_readrxdata(uint8_t *buffer, uint16_t length, uint16_t rxBufferOffset)
			{
			dwt_readfromdevice(RX_BUFFER_ID,rxBufferOffset,length,buffer) ;
			dwt_readfromdevice(RX_BUFFER_ID, rxBufferOffset, length, buffer) ;
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -702,12 +770,12 @@
			*
			* no return value
			*/
			void dwt_readaccdata(uint8 *buffer, uint16 len, uint16 accOffset)
			void dwt_readaccdata(uint8_t *buffer, uint16_t len, uint16_t accOffset)
			{
			// Force on the ACC clocks if we are sequenced
			_dwt_enableclocks(READ_ACC_ON);

			dwt_readfromdevice(ACC_MEM_ID,accOffset,len,buffer) ;
			dwt_readfromdevice(ACC_MEM_ID, accOffset, len, buffer) ;

			_dwt_enableclocks(READ_ACC_OFF); // Revert clocks back
			}
			@@ -733,7 +801,7 @@
			diagnostics->maxNoise = dwt_read16bitoffsetreg(LDE_IF_ID, LDE_THRESH_OFFSET);

			// Read all 8 bytes in one SPI transaction
			dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8*)&diagnostics->stdNoise);
			dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8_t *)&diagnostics->stdNoise);
			//diagnostics->stdNoise = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x0) ;
			//diagnostics->firstPathAmp2 = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x2) ;
			//diagnostics->firstPathAmp3 = dwt_read16bitoffsetreg(RX_FQUAL_ID, 0x4) ;
			@@ -760,7 +828,7 @@
			*
			* no return value
			*/
			void dwt_readtxtimestamp(uint8 * timestamp)
			void dwt_readtxtimestamp(uint8_t *timestamp)
			{
			dwt_readfromdevice(TX_TIME_ID, 0, TX_TIME_TX_STAMP_LEN, timestamp) ; // Read bytes directly into buffer
			}
			@@ -776,7 +844,7 @@
			*
			* returns high 32-bits of TX timestamp
			*/
			uint32 dwt_readtxtimestamphi32(void)
			uint32_t dwt_readtxtimestamphi32(void)
			{
			return dwt_read32bitoffsetreg(TX_TIME_ID, 1);
			}
			@@ -792,7 +860,7 @@
			*
			* returns low 32-bits of TX timestamp
			*/
			uint32 dwt_readtxtimestamplo32(void)
			uint32_t dwt_readtxtimestamplo32(void)
			{
			return dwt_read32bitoffsetreg(TX_TIME_ID, 0);
			}
			@@ -809,7 +877,7 @@
			*
			* no return value
			*/
			void dwt_readrxtimestamp(uint8 * timestamp)
			void dwt_readrxtimestamp(uint8_t *timestamp)
			{
			dwt_readfromdevice(RX_TIME_ID, 0, RX_TIME_RX_STAMP_LEN, timestamp) ; // Get the adjusted time of arrival
			}
			@@ -825,7 +893,7 @@
			*
			* returns high 32-bits of RX timestamp
			*/
			uint32 dwt_readrxtimestamphi32(void)
			uint32_t dwt_readrxtimestamphi32(void)
			{
			return dwt_read32bitoffsetreg(RX_TIME_ID, 1);
			}
			@@ -841,7 +909,7 @@
			*
			* returns low 32-bits of RX timestamp
			*/
			uint32 dwt_readrxtimestamplo32(void)
			uint32_t dwt_readrxtimestamplo32(void)
			{
			return dwt_read32bitoffsetreg(RX_TIME_ID, 0);
			}
			@@ -857,7 +925,7 @@
			*
			* returns high 32-bits of system time timestamp
			*/
			uint32 dwt_readsystimestamphi32(void)
			uint32_t dwt_readsystimestamphi32(void)
			{
			return dwt_read32bitoffsetreg(SYS_TIME_ID, 1);
			}
			@@ -875,7 +943,7 @@
			*
			* no return value
			*/
			void dwt_readsystime(uint8 * timestamp)
			void dwt_readsystime(uint8_t *timestamp)
			{
			dwt_readfromdevice(SYS_TIME_ID, 0, SYS_TIME_LEN, timestamp) ;
			}
			@@ -906,13 +974,13 @@
			*/
			int dwt_writetodevice
			(
			uint16 recordNumber,
			uint16 index,
			uint32 length,
			const uint8 *buffer
			uint16_t recordNumber,
			uint16_t index,
			uint32_t length,
			const uint8_t *buffer
			)
			{
			uint8 header[3] ; // Buffer to compose header in
			uint8_t header[3] ; // Buffer to compose header in
			int cnt = 0; // Counter for length of header
			#ifdef DWT_API_ERROR_CHECK
			if (recordNumber > 0x3F)
			@@ -933,7 +1001,7 @@
			{
			return DWT_ERROR ; // Index is limited to 15-bits.
			}
			if ((index + length)> 0x7FFF)
			if ((index + length) > 0x7FFF)
			{
			return DWT_ERROR ; // Sub-addressable area is limited to 15-bits.
			}
			@@ -942,17 +1010,17 @@

			if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
			{
			header[cnt++] = (uint8)index ; // Bit-7 zero means no extension, bits 6-0 is index.
			header[cnt++] = (uint8_t)index ; // Bit-7 zero means no extension, bits 6-0 is index.
			}
			else
			{
			header[cnt++] = 0x80 \| (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
			header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
			header[cnt++] = 0x80 \| (uint8_t)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
			header[cnt++] = (uint8_t) (index >> 7) ; // 8-bit value = high eight bits of index.
			}
			}

			// Write it to the SPI
			return writetospi(cnt,header,length,buffer);
			return writetospi(cnt, header, length, buffer);

			} // end dwt_writetodevice()

			@@ -981,13 +1049,13 @@
			*/
			int dwt_readfromdevice
			(
			uint16 recordNumber,
			uint16 index,
			uint32 length,
			uint8 *buffer
			uint16_t recordNumber,
			uint16_t index,
			uint32_t length,
			uint8_t *buffer
			)
			{
			uint8 header[3] ; // Buffer to compose header in
			uint8_t header[3] ; // Buffer to compose header in
			int cnt = 0; // Counter for length of header
			#ifdef DWT_API_ERROR_CHECK
			if (recordNumber > 0x3F)
			@@ -999,7 +1067,7 @@
			// Write message header selecting READ operation and addresses as appropriate (this is one to three bytes long)
			if (index == 0) // For index of 0, no sub-index is required
			{
			header[cnt++] = (uint8) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
			header[cnt++] = (uint8_t) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
			}
			else
			{
			@@ -1008,21 +1076,21 @@
			{
			return DWT_ERROR ; // Index is limited to 15-bits.
			}
			if ((index + length)> 0x7FFF)
			if ((index + length) > 0x7FFF)
			{
			return DWT_ERROR ; // Sub-addressable area is limited to 15-bits.
			}
			#endif
			header[cnt++] = (uint8)(0x40 \| recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id
			header[cnt++] = (uint8_t)(0x40 \| recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id

			if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required
			{
			header[cnt++] = (uint8) index ; // Bit-7 zero means no extension, bits 6-0 is index.
			header[cnt++] = (uint8_t) index ; // Bit-7 zero means no extension, bits 6-0 is index.
			}
			else
			{
			header[cnt++] = 0x80 \| (uint8)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
			header[cnt++] = (uint8) (index >> 7) ; // 8-bit value = high eight bits of index.
			header[cnt++] = 0x80 \| (uint8_t)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index.
			header[cnt++] = (uint8_t) (index >> 7) ; // 8-bit value = high eight bits of index.
			}
			}

			@@ -1046,13 +1114,13 @@
			*
			* returns 32 bit register value (success), or DWT_ERROR for error
			*/
			uint32 dwt_read32bitoffsetreg(int regFileID,int regOffset)
			uint32_t dwt_read32bitoffsetreg(int regFileID, int regOffset)
			{
			uint32 regval = DWT_ERROR ;
			uint32_t regval = (uint32_t)DWT_ERROR ;
			int j ;
			uint8 buffer[4] ;
			uint8_t buffer[4] ;

			int result = dwt_readfromdevice(regFileID,regOffset,4,buffer); // Read 4 bytes (32-bits) register into buffer
			int result = dwt_readfromdevice(regFileID, regOffset, 4, buffer); // Read 4 bytes (32-bits) register into buffer

			if(result == DWT_SUCCESS)
			{
			@@ -1078,12 +1146,12 @@
			*
			* returns 16 bit register value (success), or DWT_ERROR for error
			*/
			uint16 dwt_read16bitoffsetreg(int regFileID,int regOffset)
			uint16_t dwt_read16bitoffsetreg(int regFileID, int regOffset)
			{
			uint16 regval = DWT_ERROR ;
			uint8 buffer[2] ;
			uint16_t regval = (uint16_t)DWT_ERROR ;
			uint8_t buffer[2] ;

			int result = dwt_readfromdevice(regFileID,regOffset,2,buffer); // Read 2 bytes (16-bits) register into buffer
			int result = dwt_readfromdevice(regFileID, regOffset, 2, buffer); // Read 2 bytes (16-bits) register into buffer

			if(result == DWT_SUCCESS)
			{
			@@ -1107,15 +1175,15 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			int dwt_write16bitoffsetreg(int regFileID,int regOffset,uint16 regval)
			int dwt_write16bitoffsetreg(int regFileID, int regOffset, uint16_t regval)
			{
			int reg;
			uint8 buffer[2] ;
			uint8_t buffer[2] ;

			buffer[0] = regval & 0xFF;
			buffer[1] = regval >> 8 ;

			reg = dwt_writetodevice(regFileID,regOffset,2,buffer);
			reg = dwt_writetodevice(regFileID, regOffset, 2, buffer);

			return reg;

			@@ -1135,11 +1203,11 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			int dwt_write32bitoffsetreg(int regFileID,int regOffset,uint32 regval)
			int dwt_write32bitoffsetreg(int regFileID, int regOffset, uint32_t regval)
			{
			int j ;
			int reg;
			uint8 buffer[4] ;
			uint8_t buffer[4] ;

			for ( j = 0 ; j < 4 ; j++ )
			{
			@@ -1147,7 +1215,7 @@
			regval >>= 8 ;
			}

			reg = dwt_writetodevice(regFileID,regOffset,4,buffer);
			reg = dwt_writetodevice(regFileID, regOffset, 4, buffer);

			return reg;

			@@ -1173,9 +1241,9 @@
			*
			* no return value
			*/
			void dwt_enableframefilter(uint16 enable)
			void dwt_enableframefilter(uint16_t enable)
			{
			uint32 sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
			uint32_t sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register

			if(enable)
			{
			@@ -1189,7 +1257,7 @@
			}

			dw1000local.sysCFGreg = sysconfig ;
			dwt_write32bitreg(SYS_CFG_ID,sysconfig) ;
			dwt_write32bitreg(SYS_CFG_ID, sysconfig) ;
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -1204,7 +1272,7 @@
			*
			* no return value
			*/
			void dwt_setpanid(uint16 panID)
			void dwt_setpanid(uint16_t panID)
			{
			// PAN ID is high 16 bits of register
			dwt_write16bitoffsetreg(PANADR_ID, 2, panID) ;
			@@ -1222,7 +1290,7 @@
			*
			* no return value
			*/
			void dwt_setaddress16(uint16 shortAddress)
			void dwt_setaddress16(uint16_t shortAddress)
			{
			// Short address into low 16 bits
			dwt_write16bitoffsetreg(PANADR_ID, 0, shortAddress) ;
			@@ -1240,7 +1308,7 @@
			*
			* no return value
			*/
			void dwt_seteui(uint8 *eui64)
			void dwt_seteui(uint8_t *eui64)
			{
			dwt_writetodevice(EUI_64_ID, 0x0, 8, eui64);
			}
			@@ -1257,7 +1325,7 @@
			*
			* no return value
			*/
			void dwt_geteui(uint8 *eui64)
			void dwt_geteui(uint8_t *eui64)
			{
			dwt_readfromdevice(EUI_64_ID, 0x0, 8, eui64);
			}
			@@ -1276,13 +1344,13 @@
			*
			* no return value
			*/
			void dwt_otpread(uint32 address, uint32 *array, uint8 length)
			void dwt_otpread(uint32_t address, uint32_t *array, uint8_t length)
			{
			int i;

			_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: Set system clock to XTAL - this is necessary to make sure the values read by _dwt_otpread are reliable

			for(i=0; i<length; i++)
			for(i = 0; i < length; i++)
			{
			array[i] = _dwt_otpread(address + i) ;
			}
			@@ -1304,25 +1372,25 @@
			*
			* returns the 32bit of read data
			*/
			uint32 _dwt_otpread(uint32 address)
			uint32_t _dwt_otpread(uint32_t address)
			{
			uint8 buf[4];
			uint32 ret_data;
			uint8_t buf[4];
			uint32_t ret_data;

			buf[1] = (address>>8) & 0xff;
			buf[1] = (address >> 8) & 0xff;
			buf[0] = address & 0xff;

			// Write the address
			dwt_writetodevice(OTP_IF_ID,OTP_ADDR,2,buf);
			dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, buf);

			// Assert OTP Read (self clearing)
			buf[0] = 0x03; // 0x03 for manual drive of OTP_READ
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL,1,buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, buf);
			buf[0] = 0x00; // Bit0 is not autoclearing, so clear it (Bit 1 is but we clear it anyway).
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL,1,buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, buf);

			// Read read data, available 40ns after rising edge of OTP_READ
			ret_data=dwt_read32bitoffsetreg(OTP_IF_ID,OTP_RDAT);
			ret_data = dwt_read32bitoffsetreg(OTP_IF_ID, OTP_RDAT);

			// Return the 32bit of read data
			return (ret_data);
			@@ -1348,155 +1416,156 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			uint32 _dwt_otpsetmrregs(int mode)
			uint32_t _dwt_otpsetmrregs(int mode)
			{
			uint8 rd_buf[4];
			uint8 wr_buf[4];
			uint32 mra=0,mrb=0,mr=0;
			uint8_t rd_buf[4];
			uint8_t wr_buf[4];
			uint32_t mra = 0, mrb = 0, mr = 0;
			//printf("OTP SET MR: Setting MR,MRa,MRb for mode %2x\n",mode);

			// PROGRAMME MRA
			// Set MRA, MODE_SEL
			wr_buf[0] = 0x03;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);

			// Load data
			switch(mode&0x0f) {
			switch(mode & 0x0f)
			{
			case 0x0 :
			mr =0x0000;
			mra=0x0000;
			mrb=0x0000;
			mr = 0x0000;
			mra = 0x0000;
			mrb = 0x0000;
			break;
			case 0x1 :
			mr =0x1024;
			mra=0x9220; // Enable CPP mon
			mrb=0x000e;
			mr = 0x1024;
			mra = 0x9220; // Enable CPP mon
			mrb = 0x000e;
			break;
			case 0x2 :
			mr =0x1824;
			mra=0x9220;
			mrb=0x0003;
			mr = 0x1824;
			mra = 0x9220;
			mrb = 0x0003;
			break;
			case 0x3 :
			mr =0x1824;
			mra=0x9220;
			mrb=0x004e;
			mr = 0x1824;
			mra = 0x9220;
			mrb = 0x004e;
			break;
			case 0x4 :
			mr =0x0000;
			mra=0x0000;
			mrb=0x0003;
			mr = 0x0000;
			mra = 0x0000;
			mrb = 0x0003;
			break;
			case 0x5 :
			mr =0x0024;
			mra=0x0000;
			mrb=0x0003;
			mr = 0x0024;
			mra = 0x0000;
			mrb = 0x0003;
			break;
			default :
			// printf("OTP SET MR: ERROR : Invalid mode selected\n",mode);
			return DWT_ERROR;
			// printf("OTP SET MR: ERROR : Invalid mode selected\n",mode);
			return (uint32_t)DWT_ERROR;
			}

			wr_buf[0] = mra & 0x00ff;
			wr_buf[1] = (mra & 0xff00)>>8;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
			wr_buf[1] = (mra & 0xff00) >> 8;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 2, wr_buf);


			// Set WRITE_MR
			wr_buf[0] = 0x08;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);

			// Wait?

			// Set Clear Mode sel
			wr_buf[0] = 0x02;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);

			// Set AUX update, write MR
			wr_buf[0] = 0x88;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
			// Clear write MR
			wr_buf[0] = 0x80;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
			// Clear AUX update
			wr_buf[0] = 0x00;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);

			///////////////////////////////////////////
			// PROGRAM MRB
			// Set SLOW, MRB, MODE_SEL
			wr_buf[0] = 0x05;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);

			wr_buf[0] = mrb & 0x00ff;
			wr_buf[1] = (mrb & 0xff00)>>8;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
			wr_buf[1] = (mrb & 0xff00) >> 8;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 2, wr_buf);

			// Set WRITE_MR
			wr_buf[0] = 0x08;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);

			// Wait?

			// Set Clear Mode sel
			wr_buf[0] = 0x04;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);

			// Set AUX update, write MR
			wr_buf[0] = 0x88;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
			// Clear write MR
			wr_buf[0] = 0x80;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
			// Clear AUX update
			wr_buf[0] = 0x00;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);

			///////////////////////////////////////////
			// PROGRAM MR
			// Set SLOW, MODE_SEL
			wr_buf[0] = 0x01;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
			// Load data

			wr_buf[0] = mr & 0x00ff;
			wr_buf[1] = (mr & 0xff00)>>8;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
			wr_buf[1] = (mr & 0xff00) >> 8;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 2, wr_buf);

			// Set WRITE_MR
			wr_buf[0] = 0x08;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);

			// Wait?
			deca_sleep(10);
			// Set Clear Mode sel
			wr_buf[0] = 0x00;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);

			// Read confirm mode writes.
			// Set man override, MRA_SEL
			wr_buf[0] = OTP_CTRL_OTPRDEN;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
			wr_buf[0] = 0x02;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
			// MRB_SEL
			wr_buf[0] = 0x04;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
			deca_sleep(100);

			// Clear mode sel
			wr_buf[0] = 0x00;
			dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL + 1, 1, wr_buf);
			// Clear MAN_OVERRIDE
			wr_buf[0] = 0x00;
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
			dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);

			deca_sleep(10);

			if (((mode&0x0f) == 0x1)\|\|((mode&0x0f) == 0x2))
			{
			if (((mode & 0x0f) == 0x1) \|\| ((mode & 0x0f) == 0x2))
			{
			// Read status register
			dwt_readfromdevice(OTP_IF_ID, OTP_STAT,1,rd_buf);
			dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
			}

			return DWT_SUCCESS;
			@@ -1516,30 +1585,30 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			uint32 _dwt_otpprogword32(uint32 data, uint16 address)
			uint32_t _dwt_otpprogword32(uint32_t data, uint16_t address)
			{
			uint8 rd_buf[1];
			uint8 wr_buf[4];
			uint8 otp_done;
			uint8_t rd_buf[1];
			uint8_t wr_buf[4];
			uint8_t otp_done;

			// Read status register
			dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);

			if((rd_buf[0] & 0x02) != 0x02)
			{
			// printf("OTP PROG 32: ERROR VPP NOT OK, programming will fail. Are MR/MRA/MRB set?\n");
			return DWT_ERROR;
			// printf("OTP PROG 32: ERROR VPP NOT OK, programming will fail. Are MR/MRA/MRB set?\n");
			return (uint32_t)DWT_ERROR;
			}

			// Write the data
			wr_buf[3] = (data>>24) & 0xff;
			wr_buf[2] = (data>>16) & 0xff;
			wr_buf[1] = (data>>8) & 0xff;
			wr_buf[3] = (data >> 24) & 0xff;
			wr_buf[2] = (data >> 16) & 0xff;
			wr_buf[1] = (data >> 8) & 0xff;
			wr_buf[0] = data & 0xff;
			dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 4, wr_buf);

			// Write the address [10:0]
			wr_buf[1] = (address>>8) & 0x07;
			wr_buf[1] = (address >> 8) & 0x07;
			wr_buf[0] = address & 0xff;
			dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, wr_buf);

			@@ -1578,7 +1647,7 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			uint32 dwt_otpwriteandverify(uint32 value, uint16 address)
			uint32_t dwt_otpwriteandverify(uint32_t value, uint16_t address)
			{
			int prog_ok = DWT_SUCCESS;
			int retry = 0;
			@@ -1602,7 +1671,7 @@
			break;
			}
			retry++;
			if(retry==5)
			if(retry == 5)
			{
			break;
			}
			@@ -1635,12 +1704,12 @@
			*/
			void _dwt_aonconfigupload(void)
			{
			uint8 buf[1];
			uint8_t buf[1];

			buf[0] = 0x04;
			dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
			buf[0] = 0x00;
			dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -1657,12 +1726,12 @@
			*/
			void _dwt_aonarrayupload(void)
			{
			uint8 buf[1];
			uint8_t buf[1];

			buf[0] = 0x00;
			dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
			buf[0] = 0x02;
			dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -1697,12 +1766,12 @@
			*
			* no return value
			*/
			void dwt_configuresleepcnt(uint16 sleepcnt)
			void dwt_configuresleepcnt(uint16_t sleepcnt)
			{
			uint8 buf[2];
			uint8_t buf[2];

			buf[0] = 0x01;
			dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
			dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);

			buf[0] = 0;
			dwt_writetodevice(AON_ID, AON_CFG0_OFFSET, 1, buf); // To make sure we don't accidentaly go to sleep
			@@ -1715,7 +1784,7 @@
			// Set new value
			buf[0] = sleepcnt & 0xFF;
			buf[1] = (sleepcnt >> 8) & 0xFF;
			dwt_writetodevice(AON_ID, (AON_CFG0_OFFSET+2) , 2, buf);
			dwt_writetodevice(AON_ID, (AON_CFG0_OFFSET + 2) , 2, buf);
			_dwt_aonconfigupload();

			// Enable the sleep counter
			@@ -1724,7 +1793,7 @@
			_dwt_aonconfigupload();

			buf[0] = 0x00;
			dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
			dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
			}


			@@ -1741,10 +1810,10 @@
			*
			* returns the number of XTAL/2 cycles per low-power oscillator cycle. LP OSC frequency = 19.2 MHz/return value
			*/
			uint16 dwt_calibratesleepcnt(void)
			uint16_t dwt_calibratesleepcnt(void)
			{
			uint8 buf[2];
			uint16 result;
			uint8_t buf[2];
			uint16_t result;

			// Enable cal of the sleep counter
			buf[0] = 4;
			@@ -1757,48 +1826,48 @@
			_dwt_aonconfigupload();

			buf[0] = 0x01;
			dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
			dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);
			deca_sleep(1);

			// Read the number of XTAL/2 cycles one lposc cycle took.
			// Set up address
			buf[0] = 118;
			dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1,buf);
			dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1, buf);

			// Enable manual override
			buf[0] = 0x80; // OVR EN
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);

			// Read confirm data that was written
			buf[0] = 0x88; // OVR EN, OVR_RD
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);

			// Read back byte from AON
			dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1,buf);
			dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1, buf);
			result = buf[0];
			result = result << 8;

			// Set up address
			buf[0] = 117;
			dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1,buf);
			dwt_writetodevice(AON_ID, AON_ADDR_OFFSET, 1, buf);

			// Enable manual override
			buf[0] = 0x80; // OVR EN
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);

			// Read confirm data that was written
			buf[0] = 0x88; // OVR EN, OVR_RD
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);

			// Read back byte from AON
			dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1,buf);
			dwt_readfromdevice(AON_ID, AON_RDAT_OFFSET, 1, buf);
			result \|= buf[0];

			buf[0] = 0x00; // Disable OVR EN
			dwt_writetodevice(AON_ID,AON_CTRL_OFFSET,1,buf);
			dwt_writetodevice(AON_ID, AON_CTRL_OFFSET, 1, buf);

			buf[0] = 0x00;
			dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,buf);
			dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, buf);

			// Returns the number of XTAL/2 cycles per one LP OSC cycle
			// This can be converted into LP OSC frequency by 19.2 MHz/result
			@@ -1838,9 +1907,9 @@
			*
			* no return value
			*/
			void dwt_configuresleep(uint16 mode, uint8 wake)
			void dwt_configuresleep(uint16_t mode, uint8_t wake)
			{
			uint8 buf[1];
			uint8_t buf[1];

			// Add predefined sleep settings before writing the mode
			mode \|= dw1000local.sleep_mode;
			@@ -1869,7 +1938,7 @@
			*/
			void dwt_entersleepaftertx(int enable)
			{
			uint32 reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
			uint32_t reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET);
			// Set the auto TX -> sleep bit
			if(enable)
			{
			@@ -1906,7 +1975,7 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			int dwt_spicswakeup(uint8 *buff, uint16 length)
			int dwt_spicswakeup(uint8_t *buff, uint16_t length)
			{
			if(dwt_readdevid() != DWT_DEVICE_ID) // Device was in deep sleep (the first read fails)
			{
			@@ -1944,17 +2013,17 @@
			*/
			void _dwt_configlde(int prfIndex)
			{
			uint8 x = LDE_PARAM1;
			uint8_t x = LDE_PARAM1;

			dwt_writetodevice( LDE_IF_ID, LDE_CFG1_OFFSET, 1, &x ); // 8-bit configuration register

			if(prfIndex)
			{
			dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
			dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16_t) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
			}
			else
			{
			dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16) LDE_PARAM3_16);
			dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16_t) LDE_PARAM3_16);
			}
			}

			@@ -1972,7 +2041,7 @@
			*/
			void _dwt_loaducodefromrom(void)
			{
			uint8 wr_buf[2];
			uint8_t wr_buf[2];

			// Set up clocks
			wr_buf[1] = 0x03;
			@@ -2002,10 +2071,10 @@
			*
			* no return value
			*/
			void dwt_loadopsettabfromotp(uint8 gtab_sel)
			void dwt_loadopsettabfromotp(uint8_t gtab_sel)
			{
			uint8 wr_buf[2];
			uint16 reg = (((gtab_sel & 0x3) << 5) \| 0x1);
			uint8_t wr_buf[2];
			uint16_t reg = (((gtab_sel & 0x3) << 5) \| 0x1);
			// Set up clocks
			wr_buf[1] = 0x03;
			wr_buf[0] = 0x01;
			@@ -2045,7 +2114,7 @@
			dw1000local.sysCFGreg \|= SYS_CFG_DIS_STXP ;
			}

			dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
			dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
			}


			@@ -2063,13 +2132,13 @@
			*
			* no return value
			*/
			void dwt_enableautoack(uint8 responseDelayTime)
			void dwt_enableautoack(uint8_t responseDelayTime)
			{
			// Set auto ACK reply delay
			dwt_write16bitoffsetreg(ACK_RESP_T_ID, 0x2, (responseDelayTime << 8) ) ; //in symbols
			// Enable auto ACK
			dw1000local.sysCFGreg \|= SYS_CFG_AUTOACK;
			dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
			dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -2099,7 +2168,7 @@
			dw1000local.dblbuffon = 0;
			}

			dwt_write32bitreg(SYS_CFG_ID,dw1000local.sysCFGreg) ;
			dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ;
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -2116,12 +2185,12 @@
			*/
			void dwt_setautorxreenable(int enable)
			{
			uint8 byte = 0;
			uint8_t byte = 0;

			if(enable)
			{
			// Enable auto re-enable of the receiver
			dw1000local.sysCFGreg \|= SYS_CFG_RXAUTR;
			dw1000local.sysCFGreg \|= SYS_CFG_RXAUTR;
			}
			else
			{
			@@ -2129,7 +2198,7 @@
			dw1000local.sysCFGreg &= ~SYS_CFG_RXAUTR;
			}

			byte = dw1000local.sysCFGreg >> 24;
			byte = dw1000local.sysCFGreg >> 24;

			dwt_writetodevice(SYS_CFG_ID, 3, 1, &byte) ;
			}
			@@ -2146,9 +2215,9 @@
			*
			* no return value
			*/
			void dwt_setrxaftertxdelay(uint32 rxDelayTime)
			void dwt_setrxaftertxdelay(uint32_t rxDelayTime)
			{
			uint32 val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register
			uint32_t val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register

			val &= ~(ACK_RESP_T_W4R_TIM_MASK) ; // Clear the timer (19:0)

			@@ -2188,13 +2257,13 @@
			*
			* return value is 1 if the IRQS bit is set and 0 otherwise
			*/
			uint8 dwt_checkIRQ(void)
			uint8_t dwt_checkIRQ(void)
			{
			uint8 temp;
			uint8_t temp;

			dwt_readfromdevice(SYS_STATUS_ID, 0, 1, &temp);
			dwt_readfromdevice(SYS_STATUS_ID, 0, 1, &temp);

			return (temp & 0x1) ;
			return (temp & 0x1) ;
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -2215,13 +2284,13 @@
			*/
			void dwt_isr(void) // Assume interrupt can supply context
			{
			uint32 status = 0;
			uint32 clear = 0; // Will clear any events seen
			uint32_t status = 0;
			uint32_t clear = 0; // Will clear any events seen

			dw1000local.cdata.event = 0;
			dw1000local.cdata.dblbuff = dw1000local.dblbuffon ;
			dw1000local.cdata.dblbuff = dw1000local.dblbuffon ;

			status = dw1000local.cdata.status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register low 32bits
			status = dw1000local.cdata.status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register low 32bits

			//NOTES:
			//1. TX Event - if DWT_INT_TFRS is enabled, then when the frame has completed transmission the interrupt will be triggered.
			@@ -2234,81 +2303,81 @@
			// This function will clear the rx event and call the dwt_rxcallback function, notifying the application that ACK req is set.
			// If using auto-ACK, the AAT indicates that ACK frame transmission is in progress. Once the ACK has been sent the TXFRS bit will be set and TX event triggered.
			// If the auto-ACK is not enabled, the application can format/configure and start transmission of its own ACK frame.
			//
			//

			// Fix for bug 622 - LDE done flag gets latched on a bad frame
			if((status & SYS_STATUS_LDEDONE) && (dw1000local.dblbuffon == 0))
			{
			if((status & (SYS_STATUS_LDEDONE \| SYS_STATUS_RXPHD \| SYS_STATUS_RXSFDD)) != (SYS_STATUS_LDEDONE \| SYS_STATUS_RXPHD \| SYS_STATUS_RXSFDD))
			{
			// Fix for bug 622 - LDE done flag gets latched on a bad frame
			if((status & SYS_STATUS_LDEDONE) && (dw1000local.dblbuffon == 0))
			{
			if((status & (SYS_STATUS_LDEDONE \| SYS_STATUS_RXPHD \| SYS_STATUS_RXSFDD)) != (SYS_STATUS_LDEDONE \| SYS_STATUS_RXPHD \| SYS_STATUS_RXSFDD))
			{

			// Got LDE done but other flags SFD and PHR are clear - this is a bad frame - reset the transceiver
			dwt_forcetrxoff(); //this will clear all events
			// Got LDE done but other flags SFD and PHR are clear - this is a bad frame - reset the transceiver
			dwt_forcetrxoff(); //this will clear all events

			dwt_rxreset();
			// Leave any TX events for processing (e.g. if we TX a frame, and then enable RX,
			// We can get into here before the TX frame done has been processed, when we are polling (i.e. slow to process the TX)
			status &= SYS_STATUS_ALL_TX;
			// Re-enable the receiver - if auto RX re-enable set
			if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR)
			{
			dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
			}
			else
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			dwt_rxreset();
			// Leave any TX events for processing (e.g. if we TX a frame, and then enable RX,
			// We can get into here before the TX frame done has been processed, when we are polling (i.e. slow to process the TX)
			status &= SYS_STATUS_ALL_TX;
			// Re-enable the receiver - if auto RX re-enable set
			if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR)
			{
			dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
			}
			else
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;

			if(dw1000local.dwt_rxcallback != NULL)
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			}
			}
			if(dw1000local.dwt_rxcallback != NULL)
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			}
			}


			//
			// 1st check for RX frame received or RX timeout and if so call the rx callback function
			//
			if(status & SYS_STATUS_RXFCG) // Receiver FCS Good
			{
			if(status & SYS_STATUS_LDEDONE) // LDE done/finished
			{
			// Bug 634 - overrun overwrites the frame info data... so both frames should be discarded
			// Read frame info and other registers and check for overflow again
			// If overflow set then discard both frames...
			{
			if(status & SYS_STATUS_LDEDONE) // LDE done/finished
			{
			// Bug 634 - overrun overwrites the frame info data... so both frames should be discarded
			// Read frame info and other registers and check for overflow again
			// If overflow set then discard both frames...

			uint16 len = 0;
			uint16_t len = 0;

			if (status & SYS_STATUS_RXOVRR) // NOTE when overrun both HS and RS pointers point to the same buffer
			{
			// When the overrun happens the frame info data of the buffer A (which contains the older frame e.g. seq. num = x)
			// will be corrupted with the latest frame (seq. num = x + 2) data, both the host and IC are pointing to buffer A
			// We are going to discard this frame - turn off transceiver and reset receiver
			dwt_forcetrxoff();
			if (status & SYS_STATUS_RXOVRR) // NOTE when overrun both HS and RS pointers point to the same buffer
			{
			// When the overrun happens the frame info data of the buffer A (which contains the older frame e.g. seq. num = x)
			// will be corrupted with the latest frame (seq. num = x + 2) data, both the host and IC are pointing to buffer A
			// We are going to discard this frame - turn off transceiver and reset receiver
			dwt_forcetrxoff();

			dwt_rxreset();
			dwt_rxreset();

			if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here (ignore error)
			{
			dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
			}
			else // The RX will be re-enabled by the application, report an error
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here (ignore error)
			{
			dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
			}
			else // The RX will be re-enabled by the application, report an error
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;

			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			}
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			}

			return;
			}
			else // No overrun condition - proceed to process the frame
			{
			return;
			}
			else // No overrun condition - proceed to process the frame
			{

			len = dwt_read16bitoffsetreg(RX_FINFO_ID, 0) & 0x3FF;
			dwt_readfromdevice(RX_BUFFER_ID,0,2,dw1000local.cdata.fctrl) ;
			if (dw1000local.longFrames==0)
			dwt_readfromdevice(RX_BUFFER_ID, 0, 2, dw1000local.cdata.fctrl) ;
			if (dw1000local.longFrames == 0)
			{
			len &= 0x7F ;
			}
			@@ -2318,8 +2387,8 @@

			// Bug 627 workaround - clear the AAT bit if the ACK request bit in the FC is not set
			if((status & SYS_STATUS_AAT) // AAT bit is set (ACK has been requested)
			&& (((dw1000local.cdata.fctrl[0] & 0x20) == 0) \|\| (dw1000local.cdata.fctrl[0] == 0x02)) // But the data frame has it clear or it is an ACK frame
			)
			&& (((dw1000local.cdata.fctrl[0] & 0x20) == 0) \|\| (dw1000local.cdata.fctrl[0] == 0x02)) // But the data frame has it clear or it is an ACK frame
			)
			{
			clear \|= SYS_STATUS_AAT ;
			dw1000local.cdata.aatset = 0 ; // ACK request is not set
			@@ -2336,7 +2405,7 @@
			{
			// Clear all receive status bits (as we are finished with this receive event)
			clear \|= status & SYS_STATUS_ALL_RX_GOOD ;
			dwt_write32bitreg(SYS_STATUS_ID,clear) ; // Write status register to clear event bits we have seen
			dwt_write32bitreg(SYS_STATUS_ID, clear) ; // Write status register to clear event bits we have seen

			// NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
			// New events can trigger and give rise to new interrupts
			@@ -2348,25 +2417,25 @@
			}
			else // Double buffer
			{
			uint8 buff ;
			uint8 hsrb = 0x01 ;
			uint8_t buff ;
			uint8_t hsrb = 0x01 ;

			// Need to make sure that the host/IC buffer pointers are aligned before starting RX
			// Read again because the status could have changed since the interrupt was triggered
			dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &buff);
			// If ICRBP is equal to HSRBP this means we've received another frame (both buffers have frames)
			if((buff & (SYS_STATUS_ICRBP >> 24)) == // IC side Receive Buffer Pointer
			((buff & (SYS_STATUS_HSRBP >> 24)) << 1)) // Host Side Receive Buffer Pointer
			((buff & (SYS_STATUS_HSRBP >> 24)) << 1)) // Host Side Receive Buffer Pointer
			{
			// Clear all receive status bits (as we are finished with this receive event)
			clear \|= status & SYS_STATUS_ALL_DBLBUFF;
			dwt_write32bitreg(SYS_STATUS_ID,clear); // Write status register to clear event bits we have seen
			dwt_write32bitreg(SYS_STATUS_ID, clear); // Write status register to clear event bits we have seen
			}
			// If they are not aligned then there is a new frame in the other buffer, so we just need to toggle...

			if((dw1000local.sysCFGreg & SYS_CFG_RXAUTR) == 0) // Double buffer is on but no auto RX re-enable RX
			{
			dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
			dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
			}

			// Call the RX call-back function to process the RX event
			@@ -2391,122 +2460,122 @@

			if(dw1000local.sysCFGreg & SYS_CFG_RXAUTR) // Re-enable of RX is ON, then re-enable here
			{
			dwt_write16bitoffsetreg(SYS_CTRL_ID,0,(uint16)SYS_CTRL_RXENAB) ;
			dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, (uint16_t)SYS_CTRL_RXENAB) ;
			}
			}
			} // end of else double buffer

			}// end of no overrun
			} // If LDE_DONE is set (this means we have both SYS_STATUS_RXFCG and SYS_STATUS_LDEDONE)
			else // No LDE_DONE ?
			{
			//printf("NO LDE done or LDE error\n");
			if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
			{
			dwt_forcetrxoff();
			}
			dwt_rxreset(); // Reset the RX
			dw1000local.wait4resp = 0;
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			}
			} // end if CRC is good
			else
			//
			// Check for TX frame sent event and signal to upper layer.
			//
			if (status & SYS_STATUS_TXFRS) // Transmit Frame Sent
			{
			clear \|= SYS_STATUS_ALL_TX; //clear TX event bits
			dwt_write32bitreg(SYS_STATUS_ID,clear); // Write status register to clear event bits we have seen
			// NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
			// New events can trigger and give rise to new interrupts
			if(dw1000local.cdata.aatset)
			}// end of no overrun
			} // If LDE_DONE is set (this means we have both SYS_STATUS_RXFCG and SYS_STATUS_LDEDONE)
			else // No LDE_DONE ?
			{
			dw1000local.cdata.aatset = 0; // The ACK has been sent
			if(dw1000local.dblbuffon == 0) // If not double buffered
			//printf("NO LDE done or LDE error\n");
			if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
			{
			if(dw1000local.wait4resp) // wait4response was set with the last TX start command
			{
			// If using wait4response and the ACK has been sent as the response requested it
			// the receiver will be re-enabled, so issue a TRXOFF command to disable and prevent any
			// unexpected interrupts
			dwt_forcetrxoff();
			}
			dwt_forcetrxoff();
			}
			dwt_rxreset(); // Reset the RX
			dw1000local.wait4resp = 0;
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			}
			} // end if CRC is good
			else
			//
			// Check for TX frame sent event and signal to upper layer.
			//
			if (status & SYS_STATUS_TXFRS) // Transmit Frame Sent
			{
			clear \|= SYS_STATUS_ALL_TX; //clear TX event bits
			dwt_write32bitreg(SYS_STATUS_ID, clear); // Write status register to clear event bits we have seen
			// NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
			// New events can trigger and give rise to new interrupts
			if(dw1000local.cdata.aatset)
			{
			dw1000local.cdata.aatset = 0; // The ACK has been sent
			if(dw1000local.dblbuffon == 0) // If not double buffered
			{
			if(dw1000local.wait4resp) // wait4response was set with the last TX start command
			{
			// If using wait4response and the ACK has been sent as the response requested it
			// the receiver will be re-enabled, so issue a TRXOFF command to disable and prevent any
			// unexpected interrupts
			dwt_forcetrxoff();
			}
			}
			}

			dw1000local.cdata.event = DWT_SIG_TX_DONE ; // Signal TX completed
			dw1000local.cdata.event = DWT_SIG_TX_DONE ; // Signal TX completed

			// Call the TX call-back function to process the TX event
			if(dw1000local.dwt_txcallback != NULL)
			{
			dw1000local.dwt_txcallback(&dw1000local.cdata);
			}
			// Call the TX call-back function to process the TX event
			if(dw1000local.dwt_txcallback != NULL)
			{
			dw1000local.dwt_txcallback(&dw1000local.cdata);
			}

			}
			else if (status & SYS_STATUS_RXRFTO) // Receiver Frame Wait timeout
			{
			clear \|= status & SYS_STATUS_RXRFTO ;
			dwt_write32bitreg(SYS_STATUS_ID,clear) ; // Write status register to clear event bits we have seen
			dw1000local.cdata.event = DWT_SIG_RX_TIMEOUT ;
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			dw1000local.wait4resp = 0;
			else if (status & SYS_STATUS_RXRFTO) // Receiver Frame Wait timeout
			{
			clear \|= status & SYS_STATUS_RXRFTO ;
			dwt_write32bitreg(SYS_STATUS_ID, clear) ; // Write status register to clear event bits we have seen
			dw1000local.cdata.event = DWT_SIG_RX_TIMEOUT ;
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			dw1000local.wait4resp = 0;

			}
			else if(status & SYS_STATUS_ALL_RX_ERR) // Catches all other error events
			{
			clear \|= status & SYS_STATUS_ALL_RX_ERR;
			dwt_write32bitreg(SYS_STATUS_ID,clear) ; // Write status register to clear event bits we have seen
			}
			else if(status & SYS_STATUS_ALL_RX_ERR) // Catches all other error events
			{
			clear \|= status & SYS_STATUS_ALL_RX_ERR;
			dwt_write32bitreg(SYS_STATUS_ID, clear) ; // Write status register to clear event bits we have seen

			dw1000local.wait4resp = 0;
			// NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
			// New events can trigger and give rise to new interrupts
			dw1000local.wait4resp = 0;
			// NOTE: clear the event which caused interrupt means once the RX is enabled or TX is started
			// New events can trigger and give rise to new interrupts

			// Fix for bug 622 - LDE done flag gets latched on a bad frame / reset receiver
			if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
			{
			dwt_forcetrxoff(); // This will clear all events
			}
			dwt_rxreset(); // Reset the RX
			// End of fix for bug 622 - LDE done flag gets latched on a bad frame
			// Fix for bug 622 - LDE done flag gets latched on a bad frame / reset receiver
			if(!(dw1000local.sysCFGreg & SYS_CFG_RXAUTR))
			{
			dwt_forcetrxoff(); // This will clear all events
			}
			dwt_rxreset(); // Reset the RX
			// End of fix for bug 622 - LDE done flag gets latched on a bad frame

			if(status & SYS_STATUS_RXPHE)
			{
			dw1000local.cdata.event = DWT_SIG_RX_PHR_ERROR ;
			if(status & SYS_STATUS_RXPHE)
			{
			dw1000local.cdata.event = DWT_SIG_RX_PHR_ERROR ;
			}
			else if(status & SYS_STATUS_RXFCE)
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			}
			else if(status & SYS_STATUS_RXRFSL)
			{
			dw1000local.cdata.event = DWT_SIG_RX_SYNCLOSS ;
			}
			else if(status & SYS_STATUS_RXSFDTO)
			{
			dw1000local.cdata.event = DWT_SIG_RX_SFDTIMEOUT ;
			}
			else if(status & SYS_STATUS_RXPTO)
			{
			dw1000local.cdata.event = DWT_SIG_RX_PTOTIMEOUT ;
			}
			else
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			}
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			status &= SYS_STATUS_ALL_TX;
			}
			else if(status & SYS_STATUS_RXFCE)
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			}
			else if(status & SYS_STATUS_RXRFSL)
			{
			dw1000local.cdata.event = DWT_SIG_RX_SYNCLOSS ;
			}
			else if(status & SYS_STATUS_RXSFDTO)
			{
			dw1000local.cdata.event = DWT_SIG_RX_SFDTIMEOUT ;
			}
			else if(status & SYS_STATUS_RXPTO)
			{
			dw1000local.cdata.event = DWT_SIG_RX_PTOTIMEOUT ;
			}
			else
			{
			dw1000local.cdata.event = DWT_SIG_RX_ERROR ;
			}
			if(dw1000local.dwt_rxcallback != NULL)
			{
			dw1000local.dwt_rxcallback(&dw1000local.cdata);
			}
			status &= SYS_STATUS_ALL_TX;
			}
			} // end dwt_isr()

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -2524,44 +2593,44 @@
			*
			* no return value
			*/
			void dwt_setleds(uint8 test)
			void dwt_setleds(uint8_t test)
			{
			uint8 buf[2];
			uint8_t buf[2];

			if(test & 0x1)
			{
			// Set up MFIO for LED output
			dwt_readfromdevice(GPIO_CTRL_ID,0x00,2,buf);
			dwt_readfromdevice(GPIO_CTRL_ID, 0x00, 2, buf);
			buf[1] &= ~0x3C; //clear the bits
			buf[1] \|= 0x14;
			dwt_writetodevice(GPIO_CTRL_ID,0x01,1,&buf[1]);
			dwt_writetodevice(GPIO_CTRL_ID, 0x01, 1, &buf[1]);

			// Enable LP Oscillator to run from counter, turn on debounce clock
			dwt_readfromdevice(PMSC_ID,0x02,1,buf);
			dwt_readfromdevice(PMSC_ID, 0x02, 1, buf);
			buf[0] \|= 0x84; //
			dwt_writetodevice(PMSC_ID,0x02,1,buf);
			dwt_writetodevice(PMSC_ID, 0x02, 1, buf);

			// Enable LEDs to blink
			buf[0] = 0x10; // Blink period.
			buf[1] = 0x01; // Enable blink counter
			dwt_writetodevice(PMSC_ID,PMSC_LEDC_OFFSET,2,buf);
			dwt_writetodevice(PMSC_ID, PMSC_LEDC_OFFSET, 2, buf);

			}
			else if ((test & 0x1)== 0)
			else if ((test & 0x1) == 0)
			{
			// Clear the GPIO bits that are used for LED control
			dwt_readfromdevice(GPIO_CTRL_ID,0x00,2,buf);
			dwt_readfromdevice(GPIO_CTRL_ID, 0x00, 2, buf);
			buf[1] &= ~(0x14);
			dwt_writetodevice(GPIO_CTRL_ID,0x00,2,buf);
			dwt_writetodevice(GPIO_CTRL_ID, 0x00, 2, buf);
			}

			// Test LEDs
			if(test & 0x2)
			{
			buf[0] = 0x0f; // Fire a LED blink trigger
			dwt_writetodevice(PMSC_ID,0x2a,1,buf);
			dwt_writetodevice(PMSC_ID, 0x2a, 1, buf);
			buf[0] = 0x00; // Clear forced trigger bits
			dwt_writetodevice(PMSC_ID,0x2a,1,buf);
			dwt_writetodevice(PMSC_ID, 0x2a, 1, buf);
			}

			} // end _dwt_enableleds()
			@@ -2580,58 +2649,58 @@
			*/
			void _dwt_enableclocks(int clocks)
			{
			uint8 reg[2];
			uint8_t reg[2];

			dwt_readfromdevice(PMSC_ID, PMSC_CTRL0_OFFSET, 2, reg);
			switch(clocks)
			{
			case ENABLE_ALL_SEQ:
			{
			reg[0] = 0x00 ;
			reg[1] = reg[1] & 0xfe;
			}
			break;
			case FORCE_SYS_XTI:
			{
			// System and RX
			reg[0] = 0x01 \| (reg[0] & 0xfc);
			}
			break;
			case FORCE_SYS_PLL:
			{
			// System
			reg[0] = 0x02 \| (reg[0] & 0xfc);
			}
			break;
			case READ_ACC_ON:
			{
			reg[0] = 0x48 \| (reg[0] & 0xb3);
			reg[1] = 0x80 \| reg[1];
			}
			break;
			case READ_ACC_OFF:
			{
			reg[0] = reg[0] & 0xb3;
			reg[1] = 0x7f & reg[1];
			case ENABLE_ALL_SEQ:
			{
			reg[0] = 0x00 ;
			reg[1] = reg[1] & 0xfe;
			}
			break;
			case FORCE_SYS_XTI:
			{
			// System and RX
			reg[0] = 0x01 \| (reg[0] & 0xfc);
			}
			break;
			case FORCE_SYS_PLL:
			{
			// System
			reg[0] = 0x02 \| (reg[0] & 0xfc);
			}
			break;
			case READ_ACC_ON:
			{
			reg[0] = 0x48 \| (reg[0] & 0xb3);
			reg[1] = 0x80 \| reg[1];
			}
			break;
			case READ_ACC_OFF:
			{
			reg[0] = reg[0] & 0xb3;
			reg[1] = 0x7f & reg[1];

			}
			break;
			case FORCE_OTP_ON:
			{
			reg[1] = 0x02 \| reg[1];
			}
			break;
			case FORCE_OTP_OFF:
			{
			reg[1] = reg[1] & 0xfd;
			}
			break;
			case FORCE_TX_PLL:
			{
			reg[0] = 0x20\| (reg[0] & 0xcf);
			}
			break;
			default:
			}
			break;
			case FORCE_OTP_ON:
			{
			reg[1] = 0x02 \| reg[1];
			}
			break;
			case FORCE_OTP_OFF:
			{
			reg[1] = reg[1] & 0xfd;
			}
			break;
			case FORCE_TX_PLL:
			{
			reg[0] = 0x20 \| (reg[0] & 0xcf);
			}
			break;
			default:
			break;
			}

			@@ -2673,7 +2742,7 @@
			*
			* no return value
			*/
			void dwt_setdelayedtrxtime(uint32 starttime)
			void dwt_setdelayedtrxtime(uint32_t starttime)
			{
			dwt_write32bitoffsetreg(DX_TIME_ID, 1, starttime) ;

			@@ -2694,27 +2763,27 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed transmission will fail if the delayed time has passed)
			*/
			int dwt_starttx(uint8 mode)
			int dwt_starttx(uint8_t mode)
			{
			int retval = DWT_SUCCESS ;
			uint8 temp = 0x00;
			uint16 checkTxOK = 0 ;
			uint8_t temp = 0x00;
			uint16_t checkTxOK = 0 ;

			if(mode & DWT_RESPONSE_EXPECTED)
			{
			temp = (uint8)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
			dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
			temp = (uint8_t)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
			dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
			dw1000local.wait4resp = 1;
			}

			if (mode & DWT_START_TX_DELAYED)
			{
			//uint32 status ;
			//uint32_t status ;

			// Both SYS_CTRL_TXSTRT and SYS_CTRL_TXDLYS to correctly enable TX
			temp \|= (uint8)(SYS_CTRL_TXDLYS \| SYS_CTRL_TXSTRT) ;
			dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
			checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID,3) ;
			temp \|= (uint8_t)(SYS_CTRL_TXDLYS \| SYS_CTRL_TXSTRT) ;
			dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
			checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID, 3) ;
			//status = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
			if ((checkTxOK & SYS_STATUS_TXERR) == 0) // Transmit Delayed Send set over Half a Period away or Power Up error (there is enough time to send but not to power up individual blocks).
			{
			@@ -2725,8 +2794,8 @@
			{
			// I am taking DSHP set to Indicate that the TXDLYS was set too late for the specified DX_TIME.
			// Remedial Action - (a) cancel delayed send
			temp = (uint8)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
			dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
			temp = (uint8_t)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
			dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
			// Note event Delayed TX Time too Late
			// Could fall through to start a normal send (below) just sending late.....
			// ... instead return and assume return value of 1 will be used to detect and recover from the issue.
			@@ -2740,8 +2809,8 @@
			}
			else
			{
			temp \|= (uint8)SYS_CTRL_TXSTRT ;
			dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ;
			temp \|= (uint8_t)SYS_CTRL_TXSTRT ;
			dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ;
			}

			return retval;
			@@ -2777,33 +2846,33 @@
			*/
			void dwt_forcetrxoff(void)
			{
			decaIrqStatus_t stat ;
			uint8 temp ;
			uint32 mask;
			decaIrqStatus_t stat ;
			uint8_t temp ;
			uint32_t mask;

			temp = (uint8)SYS_CTRL_TRXOFF ; // This assumes the bit is in the lowest byte
			temp = (uint8_t)SYS_CTRL_TRXOFF ; // This assumes the bit is in the lowest byte

			mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
			mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask

			// Need to beware of interrupts occurring in the middle of following read modify write cycle
			// We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
			// event has just happened before the radio was disabled)
			// thus we need to disable interrupt during this operation
			// Need to beware of interrupts occurring in the middle of following read modify write cycle
			// We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
			// event has just happened before the radio was disabled)
			// thus we need to disable interrupt during this operation
			stat = decamutexon() ;

			dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events
			dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events

			dwt_writetodevice(SYS_CTRL_ID,0,1,&temp) ; // Disable the radio
			dwt_writetodevice(SYS_CTRL_ID, 0, 1, &temp) ; // Disable the radio

			// Forcing Transceiver off - so we do not want to see any new events that may have happened
			dwt_write32bitreg(SYS_STATUS_ID,(SYS_STATUS_ALL_TX \| SYS_STATUS_ALL_RX_ERR \| SYS_STATUS_ALL_RX_GOOD)) ;
			dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX \| SYS_STATUS_ALL_RX_ERR \| SYS_STATUS_ALL_RX_GOOD)) ;

			dwt_syncrxbufptrs();

			dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was
			dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was

			// Enable/restore interrupts again...
			decamutexoff(stat) ;
			// Enable/restore interrupts again...
			decamutexoff(stat) ;
			dw1000local.wait4resp = 0;

			} // end deviceforcetrxoff()
			@@ -2822,14 +2891,14 @@
			*/
			void dwt_syncrxbufptrs(void)
			{
			uint8 buff ;
			uint8_t buff ;
			// Need to make sure that the host/IC buffer pointers are aligned before starting RX
			dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &buff);

			if((buff & (SYS_STATUS_ICRBP >> 24)) != // IC side Receive Buffer Pointer
			((buff & (SYS_STATUS_HSRBP>>24)) << 1) ) // Host Side Receive Buffer Pointer
			((buff & (SYS_STATUS_HSRBP >> 24)) << 1) ) // Host Side Receive Buffer Pointer
			{
			uint8 hsrb = 0x01;
			uint8_t hsrb = 0x01;
			dwt_writetodevice(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET , 1, &hsrb) ; // We need to swap RX buffer status reg (write one to toggle internally)
			}
			}
			@@ -2851,9 +2920,9 @@
			*
			* no return value
			*/
			void dwt_setrxmode(int mode, uint8 rxON, uint8 rxOFF)
			void dwt_setrxmode(int mode, uint8_t rxON, uint8_t rxOFF)
			{
			uint16 reg16 = RX_SNIFF_MASK & ((rxOFF << 8) \| rxON);
			uint16_t reg16 = RX_SNIFF_MASK & ((rxOFF << 8) \| rxON);

			if(mode & DWT_RX_SNIFF)
			{
			@@ -2881,30 +2950,30 @@
			*/
			int dwt_rxenable(int delayed)
			{
			uint16 temp ;
			uint8 temp1 = 0;
			uint16_t temp ;
			uint8_t temp1 = 0;
			dwt_syncrxbufptrs();

			temp = (uint16)SYS_CTRL_RXENAB ;
			temp = (uint16_t)SYS_CTRL_RXENAB ;

			if (delayed)
			{
			temp \|= (uint16)SYS_CTRL_RXDLYE ;
			temp \|= (uint16_t)SYS_CTRL_RXDLYE ;
			}

			dwt_write16bitoffsetreg(SYS_CTRL_ID,0,temp) ;
			dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, temp) ;

			if (delayed) // Check for errors
			{
			//uint32 status1 = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register
			//uint32_t status1 = dwt_read32bitreg(SYS_STATUS_ID) ; // Read status register

			dwt_readfromdevice(SYS_STATUS_ID,3,1,&temp1) ;
			dwt_readfromdevice(SYS_STATUS_ID, 3, 1, &temp1) ;

			if (temp1 & (SYS_STATUS_HPDWARN >> 24)) // If delay has not passed do delayed else immediate RX on
			{
			dwt_forcetrxoff(); // Turn the delayed receive off, and do immediate receive, return warning indication
			temp = (uint16)SYS_CTRL_RXENAB; // Clear the delay bit
			dwt_write16bitoffsetreg(SYS_CTRL_ID,0,temp) ;
			temp = (uint16_t)SYS_CTRL_RXENAB; // Clear the delay bit
			dwt_write16bitoffsetreg(SYS_CTRL_ID, 0, temp) ;
			return DWT_ERROR;
			}
			}
			@@ -2926,29 +2995,29 @@
			*
			* no return value
			*/
			void dwt_setrxtimeout(uint16 time)
			void dwt_setrxtimeout(uint16_t time)
			{
			uint8 temp ;
			uint8_t temp ;

			dwt_readfromdevice(SYS_CFG_ID,3,1,&temp) ; // Read register
			dwt_readfromdevice(SYS_CFG_ID, 3, 1, &temp) ; // Read register

			if(time > 0)
			{
			dwt_write16bitoffsetreg(RX_FWTO_ID, 0x0, time) ;

			temp \|= (uint8)(SYS_CFG_RXWTOE>>24);
			temp \|= (uint8_t)(SYS_CFG_RXWTOE >> 24);
			// OR in 32bit value (1 bit set), I know this is in high byte.
			dw1000local.sysCFGreg \|= SYS_CFG_RXWTOE;

			dwt_writetodevice(SYS_CFG_ID,3,1,&temp) ;
			dwt_writetodevice(SYS_CFG_ID, 3, 1, &temp) ;
			}
			else
			{
			temp &= ~((uint8)(SYS_CFG_RXWTOE>>24));
			temp &= ~((uint8_t)(SYS_CFG_RXWTOE >> 24));
			// AND in inverted 32bit value (1 bit clear), I know this is in high byte.
			dw1000local.sysCFGreg &= ~(SYS_CFG_RXWTOE);

			dwt_writetodevice(SYS_CFG_ID,3,1,&temp) ;
			dwt_writetodevice(SYS_CFG_ID, 3, 1, &temp) ;

			//dwt_write16bitoffsetreg(RX_FWTO_ID,0,0) ; // Clearing the time is not needed
			}
			@@ -2968,7 +3037,7 @@
			*
			* no return value
			*/
			void dwt_setpreambledetecttimeout(uint16 timeout)
			void dwt_setpreambledetecttimeout(uint16_t timeout)
			{
			dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_PRETOC_OFFSET, timeout);
			}
			@@ -2997,10 +3066,10 @@
			*
			* no return value
			*/
			void dwt_setinterrupt(uint32 bitmask, uint8 enable)
			void dwt_setinterrupt(uint32_t bitmask, uint8_t enable)
			{
			decaIrqStatus_t stat ;
			uint32 mask ;
			uint32_t mask ;

			// Need to beware of interrupts occurring in the middle of following read modify write cycle
			stat = decamutexon() ;
			@@ -3015,7 +3084,7 @@
			{
			mask &= ~bitmask ; // Clear the bit
			}
			dwt_write32bitreg(SYS_MASK_ID,mask) ; // New value
			dwt_write32bitreg(SYS_MASK_ID, mask) ; // New value

			decamutexoff(stat) ;
			}
			@@ -3033,14 +3102,14 @@
			*/
			void dwt_configeventcounters(int enable)
			{
			uint8 temp = 0x0; //disable
			uint8_t temp = 0x0; //disable
			// Need to clear and disable, can't just clear
			temp = (uint8)(EVC_CLR); // Clear and disable
			temp = (uint8_t)(EVC_CLR); // Clear and disable
			dwt_writetodevice(DIG_DIAG_ID, EVC_CTRL_OFFSET, 1, &temp) ;

			if(enable)
			{
			temp = (uint8)(EVC_EN); // Enable
			temp = (uint8_t)(EVC_EN); // Enable
			dwt_writetodevice(DIG_DIAG_ID, EVC_CTRL_OFFSET, 1, &temp) ;
			}
			}
			@@ -3059,9 +3128,9 @@
			*/
			void dwt_readeventcounters(dwt_deviceentcnts_t *counters)
			{
			uint32 temp;
			uint32_t temp;

			temp= dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
			temp = dwt_read32bitoffsetreg(DIG_DIAG_ID, EVC_PHE_OFFSET); // Read sync loss (31-16), PHE (15-0)
			counters->PHE = temp & 0xFFF;
			counters->RSL = (temp >> 16) & 0xFFF;

			@@ -3100,12 +3169,12 @@
			*/
			void dwt_rxreset(void)
			{
			uint8 resetrx = 0xe0;
			// Set RX reset
			dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
			uint8_t resetrx = 0xe0;
			// Set RX reset
			dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);

			resetrx = 0xf0; // Clear RX reset
			dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
			resetrx = 0xf0; // Clear RX reset
			dwt_writetodevice(PMSC_ID, 0x3, 1, &resetrx);
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -3121,7 +3190,7 @@
			*/
			void dwt_softreset(void)
			{
			uint8 temp[1] = {0};
			uint8_t temp[1] = {0};

			_dwt_disablesequencing();
			//_dwt_enableclocks(FORCE_SYS_XTI); // Set system clock to XTI
			@@ -3162,17 +3231,17 @@
			*
			* no return value
			*/
			void dwt_xtaltrim(uint8 value)
			void dwt_xtaltrim(uint8_t value)
			{
			uint8 write_buf;
			uint8_t write_buf;

			dwt_readfromdevice(FS_CTRL_ID,FS_XTALT_OFFSET,1,&write_buf);
			dwt_readfromdevice(FS_CTRL_ID, FS_XTALT_OFFSET, 1, &write_buf);

			write_buf &= ~FS_XTALT_MASK ;

			write_buf \|= (FS_XTALT_MASK & value) ; // We should not change high bits, cause it will cause malfunction

			dwt_writetodevice(FS_CTRL_ID,FS_XTALT_OFFSET,1,&write_buf);
			dwt_writetodevice(FS_CTRL_ID, FS_XTALT_OFFSET, 1, &write_buf);
			}


			@@ -3188,14 +3257,14 @@
			*
			* returns DWT_SUCCESS for success, or DWT_ERROR for error
			*/
			int dwt_configcwmode(uint8 chan)
			int dwt_configcwmode(uint8_t chan)
			{
			uint8 write_buf[1];
			uint8_t write_buf[1];
			#ifdef DWT_API_ERROR_CHECK
			if ((chan < 1) \|\| (chan > 7) \|\| (6 == chan))
			{
			return DWT_ERROR ; // validate channel number parameter
			}
			return DWT_ERROR ; // validate channel number parameter
			}
			#endif

			//
			@@ -3222,15 +3291,15 @@
			// Configure TX clocks
			//
			write_buf[0] = 0x22;
			dwt_writetodevice(PMSC_ID,PMSC_CTRL0_OFFSET,1,write_buf);
			dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, write_buf);
			write_buf[0] = 0x07;
			dwt_writetodevice(PMSC_ID,0x1,1,write_buf);
			dwt_writetodevice(PMSC_ID, 0x1, 1, write_buf);

			// Disable fine grain TX seq
			dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_DIS_MASK);


			write_buf[0] = TC_PGTEST_CW;
			write_buf[0] = TC_PGTEST_CW;

			// Configure CW mode
			dwt_writetodevice(TX_CAL_ID, TC_PGTEST_OFFSET, TC_PGTEST_LEN, write_buf);
			@@ -3252,9 +3321,9 @@
			*
			* no return value
			*/
			void dwt_configcontinuousframemode(uint32 framerepetitionrate)
			void dwt_configcontinuousframemode(uint32_t framerepetitionrate)
			{
			uint8 write_buf[4];
			uint8_t write_buf[4];

			//
			// Disable TX/RX RF block sequencing (needed for continuous frame mode)
			@@ -3282,8 +3351,8 @@
			//
			// Configure continuous frame TX
			//
			write_buf[0] = (uint8)(DIAG_TMC_TX_PSTM) ;
			dwt_writetodevice(DIG_DIAG_ID, DIAG_TMC_OFFSET, 1,write_buf); // Turn the tx power spectrum test mode - continuous sending of frames
			write_buf[0] = (uint8_t)(DIAG_TMC_TX_PSTM) ;
			dwt_writetodevice(DIG_DIAG_ID, DIAG_TMC_OFFSET, 1, write_buf); // Turn the tx power spectrum test mode - continuous sending of frames
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -3307,39 +3376,39 @@
			*
			* returns (temp_raw<<8)\|(vbat_raw)
			*/
			uint16 dwt_readtempvbat(uint8 fastSPI)
			uint16_t dwt_readtempvbat(uint8_t fastSPI)
			{
			uint8 wr_buf[2];
			uint8 vbat_raw;
			uint8 temp_raw;
			uint8_t wr_buf[2];
			uint8_t vbat_raw;
			uint8_t temp_raw;

			// These writes should be single writes and in sequence
			wr_buf[0] = 0x80; // Enable TLD Bias
			dwt_writetodevice(RF_CONF_ID,0x11,1,wr_buf);
			dwt_writetodevice(RF_CONF_ID, 0x11, 1, wr_buf);

			wr_buf[0] = 0x0A; // Enable TLD Bias and ADC Bias
			dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf);
			dwt_writetodevice(RF_CONF_ID, 0x12, 1, wr_buf);

			wr_buf[0] = 0x0f; // Enable Outputs (only after Biases are up and running)
			dwt_writetodevice(RF_CONF_ID,0x12,1,wr_buf); //
			dwt_writetodevice(RF_CONF_ID, 0x12, 1, wr_buf); //

			// Reading All SAR inputs
			wr_buf[0] = 0x00;
			dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
			dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C, 1, wr_buf);
			wr_buf[0] = 0x01; // Set SAR enable
			dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
			dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C, 1, wr_buf);

			if(fastSPI == 1)
			{
			deca_sleep(1); // If using PLL clocks(and fast SPI rate) then this sleep is needed
			// Read voltage and temperature.
			dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
			dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 2, wr_buf);
			}
			else //change to a slow clock
			{
			_dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read are reliable
			// Read voltage and temperature.
			dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET,2,wr_buf);
			dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 2, wr_buf);
			// Default clocks (ENABLE_ALL_SEQ)
			_dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
			}
			@@ -3348,9 +3417,9 @@
			temp_raw = wr_buf[1];

			wr_buf[0] = 0x00; // Clear SAR enable
			dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C,1,wr_buf);
			dwt_writetodevice(TX_CAL_ID, TC_SARL_SAR_C, 1, wr_buf);

			return ((temp_raw<<8)\|(vbat_raw));
			return ((temp_raw << 8) \| (vbat_raw));
			}

			/*! ------------------------------------------------------------------------------------------------------------------
			@@ -3366,10 +3435,10 @@
			*
			* returns: 8-bit raw temperature sensor value
			*/
			uint8 dwt_readwakeuptemp(void)
			uint8_t dwt_readwakeuptemp(void)
			{
			uint8 temp_raw;
			dwt_readfromdevice(TX_CAL_ID,TC_SARL_SAR_LTEMP_OFFSET,1,&temp_raw);
			uint8_t temp_raw;
			dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LTEMP_OFFSET, 1, &temp_raw);
			return (temp_raw);
			}

			@@ -3386,10 +3455,10 @@
			*
			* returns: 8-bit raw battery voltage sensor value
			*/
			uint8 dwt_readwakeupvbat(void)
			uint8_t dwt_readwakeupvbat(void)
			{
			uint8 vbat_raw;
			dwt_readfromdevice(TX_CAL_ID,TC_SARL_SAR_LVBAT_OFFSET,1,&vbat_raw);
			uint8_t vbat_raw;
			dwt_readfromdevice(TX_CAL_ID, TC_SARL_SAR_LVBAT_OFFSET, 1, &vbat_raw);
			return (vbat_raw);
			}