| | |
| | | * returns DWT_SUCCESS for success, or DWT_ERROR for error |
| | | */ |
| | | // OTP addresses definitions |
| | | #define CPUID_OTP_ADRESS 0x1d |
| | | |
| | | uint32_t ReadUniqueID(void) |
| | | { |
| | | uint8_t m_UIDAdd[4]; |
| | | uint32_t cpuID_add; |
| | | //è·åCPUå¯ä¸ID |
| | | // m_CpuID.Data32[0] = *(vu32*)(0x1ffff7e8); |
| | | // m_CpuID.Data32[1] = *(vu32*)(0x1ffff7ec); |
| | | // m_CpuID.Data32[2] = *(vu32*)(0x1ffff7f0); |
| | | //è¿éæ¯é²æ¢åæ±ç¼è½çå°å¨åªé读åçUIDï¼å°UIDçå°ååè§£åå¨RAMä¸ |
| | | //å å¯ç®æ³,å¾ç®åçå å¯ç®æ³ |
| | | m_UIDAdd[0] = 0xE8; |
| | | m_UIDAdd[1] = m_UIDAdd[0]+0x0F; //f7 = e8 + 0f |
| | | m_UIDAdd[2] = m_UIDAdd[1]+0x08; //ff = f7 + 08 |
| | | m_UIDAdd[3] = m_UIDAdd[2]-0xe0; //1f = ff - e0 |
| | | memcpy(&cpuID_add, (uint8_t*)m_UIDAdd, 4); |
| | | |
| | | return *(uint32_t*)(cpuID_add); |
| | | } |
| | | |
| | | uint8_t UID_ERROR=0; |
| | | void CheckCPUID(void) |
| | | { uint32_t cpuID = 0; |
| | | uint32_t key_ID = 0; |
| | | uint8_t i=10; |
| | | cpuID = ReadUniqueID(); |
| | | Spi_ChangePrescaler(SPI_BaudRatePrescaler_256); |
| | | while(i--) |
| | | { |
| | | dwt_otpread(CPUID_OTP_ADRESS,&key_ID,1); |
| | | if(cpuID != key_ID) |
| | | { |
| | | UID_ERROR = 1; |
| | | } |
| | | else |
| | | { |
| | | UID_ERROR = 0; |
| | | break; |
| | | } |
| | | } |
| | | |
| | | Spi_ChangePrescaler(SPI_BaudRatePrescaler_8); |
| | | } |
| | | #define LDOTUNE_ADDRESS (0x04) |
| | | #define PARTID_ADDRESS (0x06) |
| | | #define LOTID_ADDRESS (0x07) |
| | |
| | | dwt_write16bitoffsetreg(PMSC_ID,PMSC_TXFINESEQ_OFFSET ,PMSC_TXFINESEQ_DIS_MASK); |
| | | |
| | | } |
| | | CheckCPUID(); |
| | | return DWT_SUCCESS ; |
| | | |
| | | } // end dwt_initialise() |