XRange_Tag.git - Gitblit

			@@ -48,15 +48,15 @@
			#include "stm32l0xx.h"

			#if !defined (HSE_VALUE)
			#define HSE_VALUE ((uint32_t)8000000U) /!< Value of the External oscillator in Hz /
			#define HSE_VALUE ((uint32_t)8000000U) /!< Value of the External oscillator in Hz /
			#endif /* HSE_VALUE */

			#if !defined (MSI_VALUE)
			#define MSI_VALUE ((uint32_t)2097152U) /!< Value of the Internal oscillator in Hz/
			#define MSI_VALUE ((uint32_t)2097152U) /!< Value of the Internal oscillator in Hz/
			#endif /* MSI_VALUE */

			#if !defined (HSI_VALUE)
			#define HSI_VALUE ((uint32_t)16000000U) /!< Value of the Internal oscillator in Hz/
			#define HSI_VALUE ((uint32_t)16000000U) /!< Value of the Internal oscillator in Hz/
			#endif /* HSI_VALUE */


			@@ -81,7 +81,7 @@
			Internal SRAM. */
			/* #define VECT_TAB_SRAM */
			#define VECT_TAB_OFFSET 0x5000U /*!< Vector Table base offset field.
			This value must be a multiple of 0x100. */
			This value must be a multiple of 0x100. */
			/******************************************************************************/
			/**
			* @}
			@@ -98,18 +98,18 @@
			/** @addtogroup STM32L0xx_System_Private_Variables
			* @{
			*/
			/* This variable is updated in three ways:
			1) by calling CMSIS function SystemCoreClockUpdate()
			2) by calling HAL API function HAL_RCC_GetHCLKFreq()
			3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
			Note: If you use this function to configure the system clock; then there
			is no need to call the 2 first functions listed above, since SystemCoreClock
			variable is updated automatically.
			*/
			uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
			const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
			const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
			const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
			/* This variable is updated in three ways:
			1) by calling CMSIS function SystemCoreClockUpdate()
			2) by calling HAL API function HAL_RCC_GetHCLKFreq()
			3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
			Note: If you use this function to configure the system clock; then there
			is no need to call the 2 first functions listed above, since SystemCoreClock
			variable is updated automatically.
			*/
			uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
			const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
			const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
			const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};

			/**
			* @}
			@@ -134,32 +134,32 @@
			*/
			void SystemInit (void)
			{
			/!< Set MSION bit /
			RCC->CR \|= (uint32_t)0x00000100U;
			/!< Set MSION bit /
			RCC->CR \|= (uint32_t)0x00000100U;

			/!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits /
			RCC->CFGR &= (uint32_t) 0x88FF400CU;
			/!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits /
			RCC->CFGR &= (uint32_t) 0x88FF400CU;

			/!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits /
			RCC->CR &= (uint32_t)0xFEF6FFF6U;
			/!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits /
			RCC->CR &= (uint32_t)0xFEF6FFF6U;

			/!< Reset HSI48ON bit /
			RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
			/!< Reset HSI48ON bit /
			RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;

			/!< Reset HSEBYP bit /
			RCC->CR &= (uint32_t)0xFFFBFFFFU;
			/!< Reset HSEBYP bit /
			RCC->CR &= (uint32_t)0xFFFBFFFFU;

			/!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits /
			RCC->CFGR &= (uint32_t)0xFF02FFFFU;
			/!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits /
			RCC->CFGR &= (uint32_t)0xFF02FFFFU;

			/!< Disable all interrupts /
			RCC->CIER = 0x00000000U;
			/!< Disable all interrupts /
			RCC->CIER = 0x00000000U;

			/* Configure the Vector Table location add offset address ------------------*/
			/* Configure the Vector Table location add offset address ------------------*/
			#ifdef VECT_TAB_SRAM
			SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
			SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
			#else
			SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
			SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
			#endif
			}

			@@ -203,63 +203,63 @@
			*/
			void SystemCoreClockUpdate (void)
			{
			uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
			uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;

			/* Get SYSCLK source -------------------------------------------------------*/
			tmp = RCC->CFGR & RCC_CFGR_SWS;
			/* Get SYSCLK source -------------------------------------------------------*/
			tmp = RCC->CFGR & RCC_CFGR_SWS;

			switch (tmp)
			{
			switch (tmp)
			{
			case 0x00U: /* MSI used as system clock */
			msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
			SystemCoreClock = (32768U * (1U << (msirange + 1U)));
			break;
			msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
			SystemCoreClock = (32768U * (1U << (msirange + 1U)));
			break;
			case 0x04U: /* HSI used as system clock */
			if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
			{
			SystemCoreClock = HSI_VALUE / 4U;
			}
			else
			{
			SystemCoreClock = HSI_VALUE;
			}
			break;
			case 0x08U: /* HSE used as system clock */
			SystemCoreClock = HSE_VALUE;
			break;
			default: /* PLL used as system clock */
			/* Get PLL clock source and multiplication factor ----------------------*/
			pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
			plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
			pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
			plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;

			pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

			if (pllsource == 0x00U)
			{
			/* HSI oscillator clock selected as PLL clock entry */
			if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
			{
			SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
			SystemCoreClock = HSI_VALUE / 4U;
			}
			else
			{
			SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
			SystemCoreClock = HSI_VALUE;
			}
			}
			else
			{
			/* HSE selected as PLL clock entry */
			SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
			}
			break;
			}
			/* Compute HCLK clock frequency --------------------------------------------*/
			/* Get HCLK prescaler */
			tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
			/* HCLK clock frequency */
			SystemCoreClock >>= tmp;
			break;
			case 0x08U: /* HSE used as system clock */
			SystemCoreClock = HSE_VALUE;
			break;
			default: /* PLL used as system clock */
			/* Get PLL clock source and multiplication factor ----------------------*/
			pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
			plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
			pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
			plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;

			pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

			if (pllsource == 0x00U)
			{
			/* HSI oscillator clock selected as PLL clock entry */
			if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
			{
			SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
			}
			else
			{
			SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
			}
			}
			else
			{
			/* HSE selected as PLL clock entry */
			SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
			}
			break;
			}
			/* Compute HCLK clock frequency --------------------------------------------*/
			/* Get HCLK prescaler */
			tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
			/* HCLK clock frequency */
			SystemCoreClock >>= tmp;
			}