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| | | //----------------------------------------- |
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| | | const uint32_t tx_config[NUM_CH] = |
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| | | { |
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| | | RF_TXCTRL_CH1, /* Tx value match UM */ |
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| | | RF_TXCTRL_CH2, |
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| | | RF_TXCTRL_CH3, |
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| | | RF_TXCTRL_CH4, |
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| | | // RF_TXCTRL_CH1, /* Tx value match UM */ |
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| | | // RF_TXCTRL_CH2, |
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| | | // RF_TXCTRL_CH3, |
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| | | // RF_TXCTRL_CH4, |
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| | | RF_TXCTRL_CH5, |
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| | | RF_TXCTRL_CH7, |
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| | | // RF_TXCTRL_CH7, |
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| | | }; |
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| | | |
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| | | //RF -> Channel_Specific_Cfg -> Channel_Cfg -> RF_PLL -> RF PLL2 |
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| | |
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| | | 0xBC //WBW |
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| | | }; |
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| | | |
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| | | |
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| | | /* offset from AGC_CTRL_ID in bytes */ |
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| | | /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */ |
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| | | #define AGC_TUNE1_OFFSET (0x04) |
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| | | #define AGC_TUNE1_LEN (2) |
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| | | #define AGC_TUNE1_MASK 0xFFFF /* It is a 16-bit tuning register for the AGC. */ |
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| | | #define AGC_TUNE1_16M 0x8870 |
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| | | #define AGC_TUNE1_64M 0x889B |
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| | | /* offset from AGC_CTRL_ID in bytes */ |
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| | | /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */ |
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| | | #define AGC_TUNE2_OFFSET (0x0C) |
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| | | #define AGC_TUNE2_LEN (4) |
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| | | #define AGC_TUNE2_MASK 0xFFFFFFFFUL |
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| | | #define AGC_TUNE2_VAL 0X2502A907UL |
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| | | const agc_cfg_struct agc_config = |
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| | | { |
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| | | AGC_TUNE2_VAL, |
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