| | |
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| | | #define VBAT_ADDRESS (0x08) |
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| | | #define VTEMP_ADDRESS (0x09) |
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| | | #define XTRIM_ADDRESS (0x1E) |
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| | | |
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| | | uint8_t module_power; |
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| | | int dwt_initialise(uint16_t config) |
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| | | { |
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| | | uint32_t power_temp,power_input; |
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| | | uint8_t plllockdetect = EC_CTRL_PLLLCK; |
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| | | uint16_t otp_addr = 0; |
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| | | uint32_t ldo_tune = 0; |
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| | |
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| | | } |
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| | | |
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| | | _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable |
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| | | dwt_write32bitreg(TX_POWER_ID, 0x1f1f1f1f); |
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| | | if(module_power>36) |
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| | | { |
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| | | power_temp =(module_power-36); |
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| | | }else{ |
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| | | power_temp = ((6-(module_power/6))<<5)|(module_power%6); |
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| | | } |
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| | | power_input= power_temp<<24|power_temp<<16|power_temp<<8|power_temp; |
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| | | dwt_write32bitreg(TX_POWER_ID, power_input); |
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| | | // Configure the CPLL lock detect |
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| | | dwt_writetodevice(EXT_SYNC_ID, EC_CTRL_OFFSET, 1, &plllockdetect); |
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| | | // Read OTP revision number |
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| | |
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| | | dw1000local.sysCFGreg |= SYS_CFG_AUTOACK; |
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| | | dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ; |
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| | | } |
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| | | |
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| | | void dwt_enableautorxeanble(uint8_t enable) |
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| | | { |
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| | | // Set auto ACK reply delay |
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| | | |
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| | | // Enable auto ACK |
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| | | if(enable) |
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| | | { |
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| | | dw1000local.sysCFGreg |= SYS_CFG_RXAUTR; |
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| | | }else{ |
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| | | dw1000local.sysCFGreg&=0xDFFFFFFF; |
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| | | } |
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| | | dwt_write32bitreg(SYS_CFG_ID, dw1000local.sysCFGreg) ; |
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| | | } |
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| | | /*! ------------------------------------------------------------------------------------------------------------------ |
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| | | * @fn dwt_setdblrxbuffmode() |
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| | | * |
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