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| | | /* Reset and Clock Control */ |
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| | | /* */ |
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| | | /******************************************************************************/ |
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| | | |
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| | | /* |
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| | | * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) |
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| | | */ |
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| | | #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ |
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| | | #define RCC_MCO3_SUPPORT /*!<Support MCO3 */ |
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| | | #define RCC_MCO3_AF2_SUPPORT /*!<Support MCO3 on Alternate Function AF0 */ |
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| | | |
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| | | /******************** Bit definition for RCC_CR register ********************/ |
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| | | #define RCC_CR_HSION_Pos (0U) |
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| | |
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| | | /* |
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| | | * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) |
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| | | */ |
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| | | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
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| | | || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
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| | | #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */ |
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| | | #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */ |
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| | | #else |
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| | | #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */ |
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| | | #endif |
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| | | |
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| | | /******************* Bit definition for TIM_CR1 register ********************/ |
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| | | #define TIM_CR1_CEN_Pos (0U) |
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| | |
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| | | #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
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| | | ((INSTANCE) == TIM21) || \ |
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| | | ((INSTANCE) == TIM22)) |
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| | | |
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| | | /****************** TIM Instances : supporting synchronization ****************/ |
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| | | #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) |
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| | | |
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| | | /******************* TIM Instances : output(s) OCXEC register *****************/ |
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| | | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) |
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