XRange_Tag.git - Gitblit

			@@ -14,13 +14,12 @@
			******************************************************************************
			* @attention
			*
			* <h2><center>© Copyright(c) 2016 STMicroelectronics.
			* All rights reserved.</center></h2>
			* Copyright (c) 2016 STMicroelectronics.
			* All rights reserved.
			*
			* This software component is licensed by ST under BSD 3-Clause license,
			* the "License"; You may not use this file except in compliance with the
			* License. You may obtain a copy of the License at:
			* opensource.org/licenses/BSD-3-Clause
			* This software is licensed under terms that can be found in the LICENSE file
			* in the root directory of this software component.
			* If no LICENSE file comes with this software, it is provided AS-IS.
			*
			******************************************************************************
			*/
			@@ -72,7 +71,7 @@
			/**** Cortex-M0 Processor Exceptions Numbers ****************************************************/
			NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
			HardFault_IRQn = -13, /!< 3 Cortex-M0+ Hard Fault Interrupt /
			SVC_IRQn = -5, /!< 11 Cortex-M0+ SV Call Interrupt /
			SVCall_IRQn = -5, /!< 11 Cortex-M0+ SV Call Interrupt /
			PendSV_IRQn = -2, /!< 14 Cortex-M0+ Pend SV Interrupt /
			SysTick_IRQn = -1, /!< 15 Cortex-M0+ System Tick Interrupt /

			@@ -766,6 +765,15 @@
			* @{
			*/

			/** @addtogroup Hardware_Constant_Definition
			* @{
			*/
			#define LSI_STARTUP_TIME 200U /!< LSI Maximum startup time in us /

			/**
			* @}
			*/

			/** @addtogroup Peripheral_Registers_Bits_Definition
			* @{
			*/
			@@ -1455,7 +1463,7 @@
			#define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /!< Division Identifier /
			#define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
			#define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /!< 0x00006000 /
			#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /!< MCD divsion ID is 6 /
			#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /!< MCD division ID is 6 /
			#define DBGMCU_IDCODE_REV_ID_Pos (16U)
			#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
			#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
			@@ -3659,9 +3667,13 @@
			/* Reset and Clock Control */
			/* */
			/******************************************************************************/

			/*
			* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
			*/
			#define RCC_HSI48_SUPPORT /!< HSI48 feature support /
			#define RCC_HSECSS_SUPPORT /!< HSE CSS feature activation support /
			#define RCC_MCO3_SUPPORT /!<Support MCO3 /
			#define RCC_MCO3_AF2_SUPPORT /!<Support MCO3 on Alternate Function AF0 /

			/****************** Bit definition for RCC_CR register ******************/
			#define RCC_CR_HSION_Pos (0U)
			@@ -4521,7 +4533,7 @@
			#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /!< 0x00004000 /
			#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /!< External Low Speed oscillator CSS Detected /

			/!< RTC congiguration /
			/!< RTC configuration /
			#define RCC_CSR_RTCSEL_Pos (16U)
			#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /!< 0x00030000 /
			#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
			@@ -5726,13 +5738,8 @@
			/*
			* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
			*/
			#if defined (STM32L071xx) \|\| defined (STM32L072xx) \|\| defined (STM32L073xx) \
			\|\| defined (STM32L081xx) \|\| defined (STM32L082xx) \|\| defined (STM32L083xx)
			#define TIM_TIM2_REMAP_HSI_SUPPORT /!<Support remap HSI on TIM2 /
			#define TIM_TIM2_REMAP_HSI48_SUPPORT /!<Support remap HSI48 on TIM2 /
			#else
			#define TIM_TIM2_REMAP_HSI48_SUPPORT /!<Support remap HSI48 on TIM2 /
			#endif

			/***************** Bit definition for TIM_CR1 register ******************/
			#define TIM_CR1_CEN_Pos (0U)
			@@ -7525,7 +7532,7 @@
			((INSTANCE) == TIM21) \|\| \
			((INSTANCE) == TIM22))

			/*************** TIM Instances : external trigger input availabe **********/
			/*************** TIM Instances : external trigger input available **********/
			#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
			((INSTANCE) == TIM3) \|\| \
			((INSTANCE) == TIM21) \|\| \
			@@ -7550,9 +7557,6 @@
			((INSTANCE) == TIM3) \|\| \
			((INSTANCE) == TIM21) \|\| \
			((INSTANCE) == TIM22))

			/**************** TIM Instances : supporting synchronization **************/
			#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

			/***************** TIM Instances : output(s) OCXEC register ***************/
			#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
			@@ -7654,6 +7658,7 @@
			#define RCC_IRQn RCC_CRS_IRQn
			#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
			#define ADC1_IRQn ADC1_COMP_IRQn
			#define SVC_IRQn SVCall_IRQn

			/* Aliases for __IRQHandler */
			#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
			@@ -7680,4 +7685,4 @@



			/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/