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| | | ****************************************************************************** |
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| | | * @attention |
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| | | * |
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| | | * <h2><center>© Copyright(c) 2016 STMicroelectronics. |
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| | | * All rights reserved.</center></h2> |
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| | | * Copyright (c) 2016 STMicroelectronics. |
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| | | * All rights reserved. |
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| | | * |
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| | | * This software component is licensed by ST under BSD 3-Clause license, |
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| | | * the "License"; You may not use this file except in compliance with the |
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| | | * License. You may obtain a copy of the License at: |
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| | | * opensource.org/licenses/BSD-3-Clause |
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| | | * This software is licensed under terms that can be found in the LICENSE file |
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| | | * in the root directory of this software component. |
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| | | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| | | * |
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| | | ****************************************************************************** |
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| | | */ |
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| | |
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| | | /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ |
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| | | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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| | | HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ |
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| | | SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ |
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| | | SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ |
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| | | PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ |
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| | | SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ |
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| | | /** @addtogroup Exported_constants |
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| | | * @{ |
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| | | */ |
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| | | |
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| | | /** @addtogroup Hardware_Constant_Definition |
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| | | * @{ |
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| | | */ |
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| | | #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ |
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| | | |
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| | | /** |
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| | | * @} |
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| | | */ |
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| | | |
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| | | /** @addtogroup Peripheral_Registers_Bits_Definition |
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| | | * @{ |
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| | | #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */ |
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| | | #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U) |
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| | | #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */ |
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| | | #define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */ |
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| | | #define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD division ID is 6 */ |
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| | | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
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| | | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
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| | | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
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| | | #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ |
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| | | #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ |
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| | | /*!< RTC congiguration */ |
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| | | /*!< RTC configuration */ |
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| | | #define RCC_CSR_RTCSEL_Pos (16U) |
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| | | #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ |
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| | | #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
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| | | ((INSTANCE) == TIM21) || \ |
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| | | ((INSTANCE) == TIM22)) |
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| | | |
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| | | /***************** TIM Instances : external trigger input availabe ************/ |
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| | | /***************** TIM Instances : external trigger input available ************/ |
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| | | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
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| | | ((INSTANCE) == TIM3) || \ |
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| | | ((INSTANCE) == TIM21) || \ |
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| | | #define RCC_IRQn RCC_CRS_IRQn |
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| | | #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn |
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| | | #define ADC1_IRQn ADC1_COMP_IRQn |
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| | | #define SVC_IRQn SVCall_IRQn |
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| | | |
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| | | /* Aliases for __IRQHandler */ |
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| | | #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler |
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| | | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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