From 13e0fafc140c16539691d26afafaca417e7e2fbc Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期四, 16 一月 2025 09:43:45 +0800
Subject: [PATCH] 更新为sdk0.7.0版本
---
01_SDK/nimble/os/freertos/portable/RVDS/ARM_CM0/pan107x/os_setup.c | 232 +++++++++++++++++++++++++++++++++------------------------
1 files changed, 134 insertions(+), 98 deletions(-)
diff --git a/01_SDK/nimble/os/freertos/portable/RVDS/ARM_CM0/pan107x/os_setup.c b/01_SDK/nimble/os/freertos/portable/RVDS/ARM_CM0/pan107x/os_setup.c
index db749c2..a3b2bc2 100644
--- a/01_SDK/nimble/os/freertos/portable/RVDS/ARM_CM0/pan107x/os_setup.c
+++ b/01_SDK/nimble/os/freertos/portable/RVDS/ARM_CM0/pan107x/os_setup.c
@@ -1,13 +1,14 @@
#include "FreeRTOS.h"
#include "task.h"
-#ifdef NIMBLE_SPARK_SUP
-#include "app_config_spark.h"
-#endif
+#include "ble_config.h"
#include "pan_clktrim.h"
#include "nimble/nimble_port.h"
#include "pan_svc_call.h"
#ifdef NIMBLE_SPARK_SUP
#include "nimble/pan107x/nimble_glue_spark.h"
+#endif
+#if CONFIG_RTT_LOG_ENABLE
+#include "SEGGER_RTT.h"
#endif
#include "pan_power.h"
@@ -24,7 +25,7 @@
extern uint32_t lp_int_ctrl_reg;
extern uint32_t rst_status_reg;
-extern void app_main(void);
+extern void app_init(void);
static uint8_t m_chip_mac[6];
@@ -59,8 +60,28 @@
temp_check_start(TEMP_CHECK_INTERVAL_MS);
- if (HAL_ADC_GetValue(&adc_temperature, &temp) == PAN_HAL_SUCCESS)
+ if (HAL_ADC_GetValue(&adc_temperature, &temp) == PAN_HAL_SUCCESS) {
PW_AutoOptimizeParams((int)temp);
+
+ /* Update SCA */
+ static uint8_t config = 0xFF;
+ uint16_t SCA = CONFIG_BT_CTLR_SCA;
+ if(temp > 15 && temp < 30){
+ if(config == 0)
+ return;
+ config = 0;
+ SCA = CONFIG_BT_CTLR_SCA;
+ }
+ else{
+ if(config == 1)
+ return;
+ config = 1;
+ SCA = (CONFIG_LOW_SPEED_CLOCK_SRC==0 ? 1000:500);
+ }
+ pan_misc_upd_local_sca(SCA);
+
+ //printf("update SCA:%d\n", SCA);
+ }
#endif
}
@@ -70,8 +91,8 @@
//register timer
ble_npl_callout_init(&temp_check_timer, (struct ble_npl_eventq *)nimble_port_get_dflt_eventq(), temp_check_cb, NULL);
- //start timer
- temp_check_start(1000);
+ //start timer right after os shedulingk
+ temp_check_start(0);
#endif
}
@@ -161,44 +182,64 @@
}
#endif /* CONFIG_FORCE_CALIB_RCL_CLK */
-#if CONFIG_LOG_ENABLE
+#if CONFIG_UART_LOG_ENABLE
void debug_uart_init(void)
{
- /* Unlock protected registers */
- SYS_UnlockReg();
+ UART_InitTypeDef Init_Struct = {
+ .UART_BaudRate = CONFIG_LOG_UART_BAUDRATE,
+ .UART_LineCtrl = Uart_Line_8n1,
+ };
+#if (CONFIG_LOG_UART_PIN == 0)
CLK_APB1PeriphClockCmd(CLK_APB1Periph_UART0, ENABLE);
-
-#ifdef IP_101x
- /* Init I/O Multi-function */
- SYS_SET_MFP(P1, 1, UART0_TX);
- SYS_SET_MFP(P1, 2, UART0_RX);
- GPIO_EnableDigitalPath(P1, BIT2);
-#else
- /* Init I/O Multi-function */
- SYS_SET_MFP(P1, 6, UART0_TX);
- SYS_SET_MFP(P1, 7, UART0_RX);
- GPIO_EnableDigitalPath(P1, BIT7);
-#endif
-
- /* Relock protected registers */
-// SYS_LockReg();
-
- UART_InitTypeDef Init_Struct;
-
- Init_Struct.UART_BaudRate = 921600;
-
- #ifdef CONFIG_APP_REDEFINE_BAUDRATE
- Init_Struct.UART_BaudRate = CONFIG_APP_REDEFINE_BAUDRATE;
- #endif
-
- Init_Struct.UART_LineCtrl = Uart_Line_8n1;
-
- /* Init UART0 for printf */
+ SYS_SET_MFP(P0, 5, UART0_TX);
UART_Init(UART0, &Init_Struct);
UART_EnableFifo(UART0);
+#endif
+#if (CONFIG_LOG_UART_PIN == 1)
+ CLK_APB1PeriphClockCmd(CLK_APB1Periph_UART0, ENABLE);
+ SYS_SET_MFP(P1, 1, UART0_TX);
+ UART_Init(UART0, &Init_Struct);
+ UART_EnableFifo(UART0);
+#endif
+#if (CONFIG_LOG_UART_PIN == 2)
+ CLK_APB1PeriphClockCmd(CLK_APB1Periph_UART0, ENABLE);
+ SYS_SET_MFP(P1, 6, UART0_TX);
+ UART_Init(UART0, &Init_Struct);
+ UART_EnableFifo(UART0);
+#endif
+#if (CONFIG_LOG_UART_PIN == 3)
+ CLK_APB2PeriphClockCmd(CLK_APB2Periph_UART1, ENABLE);
+ SYS_SET_MFP(P0, 1, UART1_TX);
+ UART_Init(UART1, &Init_Struct);
+ UART_EnableFifo(UART1);
+#endif
+#if (CONFIG_LOG_UART_PIN == 4)
+ CLK_APB2PeriphClockCmd(CLK_APB2Periph_UART1, ENABLE);
+ SYS_SET_MFP(P1, 0, UART1_TX);
+ UART_Init(UART1, &Init_Struct);
+ UART_EnableFifo(UART1);
+#endif
+#if (CONFIG_LOG_UART_PIN == 5)
+ CLK_APB2PeriphClockCmd(CLK_APB2Periph_UART1, ENABLE);
+ SYS_SET_MFP(P1, 2, UART1_TX);
+ UART_Init(UART1, &Init_Struct);
+ UART_EnableFifo(UART1);
+#endif
+#if (CONFIG_LOG_UART_PIN == 6)
+ CLK_APB2PeriphClockCmd(CLK_APB2Periph_UART1, ENABLE);
+ SYS_SET_MFP(P2, 5, UART1_TX);
+ UART_Init(UART1, &Init_Struct);
+ UART_EnableFifo(UART1);
+#endif
+#if (CONFIG_LOG_UART_PIN == 7)
+ CLK_APB2PeriphClockCmd(CLK_APB2Periph_UART1, ENABLE);
+ SYS_SET_MFP(P3, 1, UART1_TX);
+ UART_Init(UART1, &Init_Struct);
+ UART_EnableFifo(UART1);
+#endif
}
-#endif //CONFIG_LOG_ENABLE
+#endif //CONFIG_UART_LOG_ENABLE
void track_pin_init(void)
{
@@ -274,8 +315,8 @@
CLK->RCH_CTRL &= ~BIT(0);
- CLK_PCLK1Config(CONFIG_PERIPH_DIVIDE / 2);
- CLK_PCLK2Config(CONFIG_PERIPH_DIVIDE / 2);
+ CLK_PCLK1Config(CONFIG_APB1_CLOCK_DIVISOR >> 1);
+ CLK_PCLK2Config(CONFIG_APB2_CLOCK_DIVISOR >> 1);
/*
* Note that all clocks on APB are disabled by default after SoC power up, and
* the default AHB clocks enabled after SoC power up are:
@@ -308,6 +349,24 @@
#endif
}
+#define APP_POWER_TEST_EN 0
+#if APP_POWER_TEST_EN
+void app_power_test(OTP_STRUCT_T *otp)
+{
+ //buck out(DCDC):default:8; FT-2
+ uint32_t tmp = ANA->LP_BUCK_3V;
+ tmp &= ~(0xFul<<2);
+ tmp |= (((otp->m.buck_out_trim >> 1) - 2) << 2);
+ //tmp |= (((otp->m.buck_out_trim >> 1) - 3) << 2);
+ ANA->LP_BUCK_3V = tmp;
+
+ //HPLDO(DVDD) default - 1/2; default:8
+ tmp = ANA->LP_HP_LDO;
+ tmp &= ~(0xFul <<3);
+ tmp |= ((otp->m.hp_ldo_trim - 2)<<3); //~1.12V
+ ANA->LP_HP_LDO = tmp;
+}
+#endif
static int pan10xx_hw_calib_init(void)
{
@@ -332,25 +391,9 @@
}
printf("- Chip UID : %02X%02X%02X%02X%02X%02X%02X%02X%02X\n", otp.m.uid[0], otp.m.uid[1],
otp.m.uid[2], otp.m.uid[3], otp.m.uid[4], otp.m.uid[5], otp.m.uid[6], otp.m.uid[7], otp.m.uid[8]);
-
- //buck out(DCDC):default - 2; default:8
- uint32_t tmp = ANA->LP_BUCK_3V;
- tmp &= ~(0xFul<<2);
- tmp |= (((otp.m.buck_out_trim >> 1) - 2) << 2);
- ANA->LP_BUCK_3V = tmp;
-
- #if CONFIG_DVDD_VOL_OPTIMIZE_EN
- //HPLDO(DVDD) default - 1/2; default:8
- tmp = ANA->LP_HP_LDO;
- tmp &= ~(0xFul <<3);
- tmp |= ((otp.m.hp_ldo_trim - 2)<<3); //~1.12V
- ANA->LP_HP_LDO = tmp;
- #else
- //HPLDO(DVDD) default - 1/2; default:8
- tmp = ANA->LP_HP_LDO;
- tmp &= ~(0xFul <<3);
- tmp |= ((otp.m.hp_ldo_trim - 1)<<3); //~1.16V
- ANA->LP_HP_LDO = tmp;
+
+ #if APP_POWER_TEST_EN
+ app_power_test(&otp);
#endif
}
printf("- Chip Flash UID : ");
@@ -358,16 +401,6 @@
printf("%02X", flash_ids.uid[i]);
}
printf("\n- Chip Flash Size : %ld KB\n", BIT(flash_ids.memory_density_id) >> 10);
-
-#if CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE
- /* Temporarily get and increase LPLDOH calibrate code */
- uint32_t i = ((ANA->LP_LP_LDO_3V & (0xFu << 17)) >> 17) + CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE;
- /* Handle code overflow */
- if (i > 15) {
- i = 15;
- }
- ANA->LP_LP_LDO_3V = (ANA->LP_LP_LDO_3V & ~(0xFu << 17)) | (i << 17);
-#endif /* CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE */
return 0;
}
@@ -377,6 +410,7 @@
uint8_t addr_null[6] = {0, 0, 0, 0, 0, 0};
if (memcmp(m_chip_mac, addr_null, 6) == 0) {
+ printf("Warnning: No chip mac addr\n");
return 1;
} else {
memcpy(mac, m_chip_mac, 6);
@@ -384,11 +418,26 @@
}
}
+
+uint8_t pan10x_roll_mac_addr_get(uint8_t *mac)
+{
+ uint8_t addr_temp[6];
+ uint8_t addr_null[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+ FMC_ReadInfoArea(FLCTL, 0x100, CMD_DREAD, addr_temp, sizeof(addr_temp));
+
+ if (memcmp(addr_temp, addr_null, 6) == 0) {
+ printf("Warnning: No chip roll mac addr\n");
+ return 1;
+ } else {
+ memcpy(mac, addr_temp, 6);
+ return 0;
+ }
+}
+
+
void pan10x_init()
{
-#if CONFIG_RF_CALIB
- CLK->XTH_CTRL = (CLK->XTH_CTRL & ~CLK_XTHCTL_XO_CAP_SEL_Msk) | (0x16 << CLK_XTHCTL_XO_CAP_SEL_Pos);
-#endif
#if CONFIG_VECTOR_REMAP_TO_RAM
static ALIGN(256) uint32_t ram_vector[64] = {0};
@@ -400,10 +449,6 @@
pan10xx_hw_calib_init();
#if CONFIG_FLASH_LDO_EN
-#if CONFIG_FLASH_LDO_VOL < 8
- ANA->LP_HP_LDO &= ~(BIT(22)|BIT(21)|BIT(20));
- ANA->LP_HP_LDO |= (CONFIG_FLASH_LDO_VOL<<20);
-#endif /* CONFIG_FLASH_LDO_VOL */
ANA->LP_HP_LDO &= ~ANAC_HPLDO_FLASHLDO_BP_Msk_3v;
#else
ANA->LP_HP_LDO |= ANAC_HPLDO_FLASHLDO_BP_Msk_3v;
@@ -493,7 +538,7 @@
void setup_thread(void *param)
{
- app_main();
+ app_init();
}
CONFIG_RAM_CODE void soc_busy_wait(uint32_t us)
@@ -519,15 +564,23 @@
extern void app_init_early(void);
app_init_early();
-#if CONFIG_LOG_ENABLE
- /* log uart initialize */
+#if CONFIG_UART_LOG_ENABLE
debug_uart_init();
-#endif /* CONFIG_LOG_ENABLE */
+#endif
+
+#if CONFIG_RTT_LOG_ENABLE
+ SEGGER_RTT_Init();
+#endif
+
+#if NIMBLE_CFG_CONTROLLER
+#if (CONFIG_UART_LOG_ENABLE || CONFIG_RTT_LOG_ENABLE)
+ pan_misc_register_print(vprintf);
+#endif
+#endif /* NIMBLE_CFG_CONTROLLER */
/* Track Init */
#if CONFIG_BT_CTLR_LINK_LAYER_DEBUG
track_pin_init();
- pan_misc_register_print(vprintf);
#endif
/* system configure */
@@ -537,7 +590,6 @@
/* Init low power flow */
extern void deepsleep_init(void);
deepsleep_init();
-
#endif
#ifdef NIMBLE_SPARK_SUP
@@ -558,11 +610,6 @@
/* get clock frequence, no matter rcl or xtl */
clktrim_measure_32k_clk(1000);
#endif
-
-#if CONFIG_SYSTEM_WATCH_DOG_ENABLE
- extern void system_watch_dog_init(void);
- system_watch_dog_init();
-#endif
setup_thread(NULL);
@@ -577,17 +624,6 @@
void vApplicationMallocFailedHook(void)
{
printf("pvPortMalloc failed\n");
-}
-#endif
-
-#if (CONFIG_LOG_ENABLE == 0)
-void SendChar(int ch)
-{
-}
-
-char GetChar(void)
-{
- return (char)0;
}
#endif
--
Gitblit v1.9.3