From 255c51174a0571340ef470184064a5c75d261d27 Mon Sep 17 00:00:00 2001
From: WXK <287788329@qq.com>
Date: 星期三, 22 一月 2025 15:06:27 +0800
Subject: [PATCH] 加入一开始不广播升级 中断触发gpio后广播升级 10分钟自动退出
---
01_SDK/nimble/controller/pan107x_spark/include/stack/controller/bb_def.h | 18 ++++++++++++++----
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/01_SDK/nimble/controller/pan107x_spark/include/stack/controller/bb_def.h b/01_SDK/nimble/controller/pan107x_spark/include/stack/controller/bb_def.h
index a6c2447..d77b148 100644
--- a/01_SDK/nimble/controller/pan107x_spark/include/stack/controller/bb_def.h
+++ b/01_SDK/nimble/controller/pan107x_spark/include/stack/controller/bb_def.h
@@ -3,14 +3,14 @@
* @FileName : bb_def.h
* @Author : GaoQiu
* @CreateDate: 2020-09-10
- * @Copyright : Copyright(C) GaoQiu
+ * @Copyright : Copyright(C) PanChip
* All Rights Reserved.
*
*******************************************************************************
*
* The information contained herein is confidential and proprietary property of
- * GaoQiu and is available under the terms of Commercial License Agreement
- * between GaoQiu and the licensee in separate contract or the terms described
+ * PanChip and is available under the terms of Commercial License Agreement
+ * between PanChip and the licensee in separate contract or the terms described
* here-in.
*
* This heading MUST NOT be removed from this file.
@@ -33,7 +33,7 @@
#define BB_SEQ_RAM_BASE (BB_BASE + 0x1000)
#define BB_LIST_RAM_BASE (BB_BASE + 0x8000) /* 512B */
//#define BB_TX_RX_BUF_BASE (BB_BASE + 0x8200) /* 7.5K + 8K for BB TX/RX Buffer */
-#define BB_TX_RX_BUF_BASE (BB_BASE + 0x8100) /* 7.5K + 8K for BB TX/RX Buffer */
+//#define BB_TX_RX_BUF_BASE (BB_BASE + 0x8100) /* 7.5K + 8K for BB TX/RX Buffer */
#define BB_REG32(addr) (*((volatile uint32_t *)(BB_BASE + addr)))
#define RCC_REG32(addr) (*((volatile uint32_t *)(RCC_BASE + addr)))
@@ -519,6 +519,16 @@
// For BLE ADV PDU filter module
#define BB_ADV_PDU_FLTR_CTRL_ADDR 0x940
+enum{
+ BB_ADV_TYPE_FLTR_EN_Pos = 17,
+ #define BB_ADV_TYPE_FLTR_EN_Mask (1ul << BB_ADV_TYPE_FLTR_EN_Pos)
+
+ BB_ADV_PDU_FLTR_EN_Pos = 16,
+ #define BB_ADV_PDU_FLTR_EN_Mask (1ul << BB_ADV_PDU_FLTR_EN_Pos)
+
+ BB_ADV_PDU_FLTR_MSK_Pos = 0,
+ #define BB_ADV_PDU_FLTR_MSK_Mask (0xFFFF)
+};
#define BB_ADV_PDU_FLTR0_ADDR 0x944 // Format: ADV Data Type | AD Length
#define BB_ADV_PDU_FLTR1_ADDR 0x948 // Format: ADV Data Type | AD Length
#define BB_ADV_PDU_FLTR2_ADDR 0x94C // Format: ADV Data Type | AD Length
--
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